* [hch-misc:dma_direct_set_offset-export 11/11] drivers/gpu/drm/sun4i/sun4i_backend.c:818:9: error: implicit declaration of function 'dma_direct_set_offset'
@ 2020-11-11 1:03 kernel test robot
0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2020-11-11 1:03 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 16545 bytes --]
tree: git://git.infradead.org/users/hch/misc.git dma_direct_set_offset-export
head: 5963f88d365367fe74d477b8420d34562d684406
commit: 5963f88d365367fe74d477b8420d34562d684406 [11/11] dma-mapping: remove the dma_direct_set_offset export
config: arm-defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git remote add hch-misc git://git.infradead.org/users/hch/misc.git
git fetch --no-tags hch-misc dma_direct_set_offset-export
git checkout 5963f88d365367fe74d477b8420d34562d684406
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/gpu/drm/sun4i/sun4i_backend.c: In function 'sun4i_backend_bind':
>> drivers/gpu/drm/sun4i/sun4i_backend.c:818:9: error: implicit declaration of function 'dma_direct_set_offset' [-Werror=implicit-function-declaration]
818 | ret = dma_direct_set_offset(drm->dev, PHYS_OFFSET, 0, SZ_4G);
| ^~~~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/dma_direct_set_offset +818 drivers/gpu/drm/sun4i/sun4i_backend.c
9026e0d122ac87d Maxime Ripard 2015-10-29 778
9026e0d122ac87d Maxime Ripard 2015-10-29 779 static int sun4i_backend_bind(struct device *dev, struct device *master,
9026e0d122ac87d Maxime Ripard 2015-10-29 780 void *data)
9026e0d122ac87d Maxime Ripard 2015-10-29 781 {
9026e0d122ac87d Maxime Ripard 2015-10-29 782 struct platform_device *pdev = to_platform_device(dev);
9026e0d122ac87d Maxime Ripard 2015-10-29 783 struct drm_device *drm = data;
9026e0d122ac87d Maxime Ripard 2015-10-29 784 struct sun4i_drv *drv = drm->dev_private;
9026e0d122ac87d Maxime Ripard 2015-10-29 785 struct sun4i_backend *backend;
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 786 const struct sun4i_backend_quirks *quirks;
9026e0d122ac87d Maxime Ripard 2015-10-29 787 struct resource *res;
9026e0d122ac87d Maxime Ripard 2015-10-29 788 void __iomem *regs;
9026e0d122ac87d Maxime Ripard 2015-10-29 789 int i, ret;
9026e0d122ac87d Maxime Ripard 2015-10-29 790
9026e0d122ac87d Maxime Ripard 2015-10-29 791 backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
9026e0d122ac87d Maxime Ripard 2015-10-29 792 if (!backend)
9026e0d122ac87d Maxime Ripard 2015-10-29 793 return -ENOMEM;
9026e0d122ac87d Maxime Ripard 2015-10-29 794 dev_set_drvdata(dev, backend);
ca07b210bc5c124 Maxime Ripard 2018-01-22 795 spin_lock_init(&backend->frontend_lock);
9026e0d122ac87d Maxime Ripard 2015-10-29 796
564d6fd611f9c66 Maxime Ripard 2019-04-01 797 if (of_find_property(dev->of_node, "interconnects", NULL)) {
564d6fd611f9c66 Maxime Ripard 2019-04-01 798 /*
564d6fd611f9c66 Maxime Ripard 2019-04-01 799 * This assume we have the same DMA constraints for all our the
564d6fd611f9c66 Maxime Ripard 2019-04-01 800 * devices in our pipeline (all the backends, but also the
564d6fd611f9c66 Maxime Ripard 2019-04-01 801 * frontends). This sounds bad, but it has always been the case
564d6fd611f9c66 Maxime Ripard 2019-04-01 802 * for us, and DRM doesn't do per-device allocation either, so
564d6fd611f9c66 Maxime Ripard 2019-04-01 803 * we would need to fix DRM first...
564d6fd611f9c66 Maxime Ripard 2019-04-01 804 */
564d6fd611f9c66 Maxime Ripard 2019-04-01 805 ret = of_dma_configure(drm->dev, dev->of_node, true);
564d6fd611f9c66 Maxime Ripard 2019-04-01 806 if (ret)
564d6fd611f9c66 Maxime Ripard 2019-04-01 807 return ret;
564d6fd611f9c66 Maxime Ripard 2019-04-01 808 } else {
564d6fd611f9c66 Maxime Ripard 2019-04-01 809 /*
564d6fd611f9c66 Maxime Ripard 2019-04-01 810 * If we don't have the interconnect property, most likely
564d6fd611f9c66 Maxime Ripard 2019-04-01 811 * because of an old DT, we need to set the DMA offset by hand
564d6fd611f9c66 Maxime Ripard 2019-04-01 812 * on our device since the RAM mapping is at 0 for the DMA bus,
564d6fd611f9c66 Maxime Ripard 2019-04-01 813 * unlike the CPU.
e0d072782c734d2 Jim Quinlan 2020-09-17 814 *
e0d072782c734d2 Jim Quinlan 2020-09-17 815 * XXX(hch): this has no business in a driver and needs to move
e0d072782c734d2 Jim Quinlan 2020-09-17 816 * to the device tree.
564d6fd611f9c66 Maxime Ripard 2019-04-01 817 */
e0d072782c734d2 Jim Quinlan 2020-09-17 @818 ret = dma_direct_set_offset(drm->dev, PHYS_OFFSET, 0, SZ_4G);
e0d072782c734d2 Jim Quinlan 2020-09-17 819 if (ret)
e0d072782c734d2 Jim Quinlan 2020-09-17 820 return ret;
564d6fd611f9c66 Maxime Ripard 2019-04-01 821 }
564d6fd611f9c66 Maxime Ripard 2019-04-01 822
879693384367106 Icenowy Zheng 2017-05-17 823 backend->engine.node = dev->of_node;
879693384367106 Icenowy Zheng 2017-05-17 824 backend->engine.ops = &sun4i_backend_engine_ops;
879693384367106 Icenowy Zheng 2017-05-17 825 backend->engine.id = sun4i_backend_of_get_id(dev->of_node);
879693384367106 Icenowy Zheng 2017-05-17 826 if (backend->engine.id < 0)
879693384367106 Icenowy Zheng 2017-05-17 827 return backend->engine.id;
da3a1c30dc10858 Chen-Yu Tsai 2017-04-21 828
ca07b210bc5c124 Maxime Ripard 2018-01-22 829 backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node);
ca07b210bc5c124 Maxime Ripard 2018-01-22 830 if (IS_ERR(backend->frontend))
ca07b210bc5c124 Maxime Ripard 2018-01-22 831 dev_warn(dev, "Couldn't find matching frontend, frontend features disabled\n");
ca07b210bc5c124 Maxime Ripard 2018-01-22 832
9026e0d122ac87d Maxime Ripard 2015-10-29 833 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9026e0d122ac87d Maxime Ripard 2015-10-29 834 regs = devm_ioremap_resource(dev, res);
9a8aa939ba33998 Wei Yongjun 2016-09-15 835 if (IS_ERR(regs))
9026e0d122ac87d Maxime Ripard 2015-10-29 836 return PTR_ERR(regs);
9026e0d122ac87d Maxime Ripard 2015-10-29 837
9026e0d122ac87d Maxime Ripard 2015-10-29 838 backend->reset = devm_reset_control_get(dev, NULL);
9026e0d122ac87d Maxime Ripard 2015-10-29 839 if (IS_ERR(backend->reset)) {
9026e0d122ac87d Maxime Ripard 2015-10-29 840 dev_err(dev, "Couldn't get our reset line\n");
9026e0d122ac87d Maxime Ripard 2015-10-29 841 return PTR_ERR(backend->reset);
9026e0d122ac87d Maxime Ripard 2015-10-29 842 }
9026e0d122ac87d Maxime Ripard 2015-10-29 843
9026e0d122ac87d Maxime Ripard 2015-10-29 844 ret = reset_control_deassert(backend->reset);
9026e0d122ac87d Maxime Ripard 2015-10-29 845 if (ret) {
9026e0d122ac87d Maxime Ripard 2015-10-29 846 dev_err(dev, "Couldn't deassert our reset line\n");
9026e0d122ac87d Maxime Ripard 2015-10-29 847 return ret;
9026e0d122ac87d Maxime Ripard 2015-10-29 848 }
9026e0d122ac87d Maxime Ripard 2015-10-29 849
9026e0d122ac87d Maxime Ripard 2015-10-29 850 backend->bus_clk = devm_clk_get(dev, "ahb");
9026e0d122ac87d Maxime Ripard 2015-10-29 851 if (IS_ERR(backend->bus_clk)) {
9026e0d122ac87d Maxime Ripard 2015-10-29 852 dev_err(dev, "Couldn't get the backend bus clock\n");
9026e0d122ac87d Maxime Ripard 2015-10-29 853 ret = PTR_ERR(backend->bus_clk);
9026e0d122ac87d Maxime Ripard 2015-10-29 854 goto err_assert_reset;
9026e0d122ac87d Maxime Ripard 2015-10-29 855 }
9026e0d122ac87d Maxime Ripard 2015-10-29 856 clk_prepare_enable(backend->bus_clk);
9026e0d122ac87d Maxime Ripard 2015-10-29 857
9026e0d122ac87d Maxime Ripard 2015-10-29 858 backend->mod_clk = devm_clk_get(dev, "mod");
9026e0d122ac87d Maxime Ripard 2015-10-29 859 if (IS_ERR(backend->mod_clk)) {
9026e0d122ac87d Maxime Ripard 2015-10-29 860 dev_err(dev, "Couldn't get the backend module clock\n");
9026e0d122ac87d Maxime Ripard 2015-10-29 861 ret = PTR_ERR(backend->mod_clk);
9026e0d122ac87d Maxime Ripard 2015-10-29 862 goto err_disable_bus_clk;
9026e0d122ac87d Maxime Ripard 2015-10-29 863 }
451debe55715aca Maxime Ripard 2020-01-07 864
451debe55715aca Maxime Ripard 2020-01-07 865 ret = clk_set_rate_exclusive(backend->mod_clk, 300000000);
451debe55715aca Maxime Ripard 2020-01-07 866 if (ret) {
451debe55715aca Maxime Ripard 2020-01-07 867 dev_err(dev, "Couldn't set the module clock frequency\n");
451debe55715aca Maxime Ripard 2020-01-07 868 goto err_disable_bus_clk;
451debe55715aca Maxime Ripard 2020-01-07 869 }
451debe55715aca Maxime Ripard 2020-01-07 870
9026e0d122ac87d Maxime Ripard 2015-10-29 871 clk_prepare_enable(backend->mod_clk);
9026e0d122ac87d Maxime Ripard 2015-10-29 872
9026e0d122ac87d Maxime Ripard 2015-10-29 873 backend->ram_clk = devm_clk_get(dev, "ram");
9026e0d122ac87d Maxime Ripard 2015-10-29 874 if (IS_ERR(backend->ram_clk)) {
9026e0d122ac87d Maxime Ripard 2015-10-29 875 dev_err(dev, "Couldn't get the backend RAM clock\n");
9026e0d122ac87d Maxime Ripard 2015-10-29 876 ret = PTR_ERR(backend->ram_clk);
9026e0d122ac87d Maxime Ripard 2015-10-29 877 goto err_disable_mod_clk;
9026e0d122ac87d Maxime Ripard 2015-10-29 878 }
9026e0d122ac87d Maxime Ripard 2015-10-29 879 clk_prepare_enable(backend->ram_clk);
9026e0d122ac87d Maxime Ripard 2015-10-29 880
440d2c7b127a8b3 Maxime Ripard 2016-09-06 881 if (of_device_is_compatible(dev->of_node,
440d2c7b127a8b3 Maxime Ripard 2016-09-06 882 "allwinner,sun8i-a33-display-backend")) {
440d2c7b127a8b3 Maxime Ripard 2016-09-06 883 ret = sun4i_backend_init_sat(dev);
440d2c7b127a8b3 Maxime Ripard 2016-09-06 884 if (ret) {
440d2c7b127a8b3 Maxime Ripard 2016-09-06 885 dev_err(dev, "Couldn't init SAT resources\n");
440d2c7b127a8b3 Maxime Ripard 2016-09-06 886 goto err_disable_ram_clk;
440d2c7b127a8b3 Maxime Ripard 2016-09-06 887 }
440d2c7b127a8b3 Maxime Ripard 2016-09-06 888 }
440d2c7b127a8b3 Maxime Ripard 2016-09-06 889
8270249fbeaf0a3 Chen-Yu Tsai 2017-10-14 890 backend->engine.regs = devm_regmap_init_mmio(dev, regs,
8270249fbeaf0a3 Chen-Yu Tsai 2017-10-14 891 &sun4i_backend_regmap_config);
8270249fbeaf0a3 Chen-Yu Tsai 2017-10-14 892 if (IS_ERR(backend->engine.regs)) {
8270249fbeaf0a3 Chen-Yu Tsai 2017-10-14 893 dev_err(dev, "Couldn't create the backend regmap\n");
8270249fbeaf0a3 Chen-Yu Tsai 2017-10-14 894 return PTR_ERR(backend->engine.regs);
8270249fbeaf0a3 Chen-Yu Tsai 2017-10-14 895 }
8270249fbeaf0a3 Chen-Yu Tsai 2017-10-14 896
879693384367106 Icenowy Zheng 2017-05-17 897 list_add_tail(&backend->engine.list, &drv->engine_list);
80a58240efef576 Chen-Yu Tsai 2017-04-21 898
936598d16e9111e Chen-Yu Tsai 2017-10-14 899 /*
936598d16e9111e Chen-Yu Tsai 2017-10-14 900 * Many of the backend's layer configuration registers have
936598d16e9111e Chen-Yu Tsai 2017-10-14 901 * undefined default values. This poses a risk as we use
936598d16e9111e Chen-Yu Tsai 2017-10-14 902 * regmap_update_bits in some places, and don't overwrite
936598d16e9111e Chen-Yu Tsai 2017-10-14 903 * the whole register.
936598d16e9111e Chen-Yu Tsai 2017-10-14 904 *
936598d16e9111e Chen-Yu Tsai 2017-10-14 905 * Clear the registers here to have something predictable.
936598d16e9111e Chen-Yu Tsai 2017-10-14 906 */
9026e0d122ac87d Maxime Ripard 2015-10-29 907 for (i = 0x800; i < 0x1000; i += 4)
879693384367106 Icenowy Zheng 2017-05-17 908 regmap_write(backend->engine.regs, i, 0);
9026e0d122ac87d Maxime Ripard 2015-10-29 909
9026e0d122ac87d Maxime Ripard 2015-10-29 910 /* Disable registers autoloading */
879693384367106 Icenowy Zheng 2017-05-17 911 regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG,
9026e0d122ac87d Maxime Ripard 2015-10-29 912 SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
9026e0d122ac87d Maxime Ripard 2015-10-29 913
9026e0d122ac87d Maxime Ripard 2015-10-29 914 /* Enable the backend */
879693384367106 Icenowy Zheng 2017-05-17 915 regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
9026e0d122ac87d Maxime Ripard 2015-10-29 916 SUN4I_BACKEND_MODCTL_DEBE_EN |
9026e0d122ac87d Maxime Ripard 2015-10-29 917 SUN4I_BACKEND_MODCTL_START_CTL);
9026e0d122ac87d Maxime Ripard 2015-10-29 918
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 919 /* Set output selection if needed */
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 920 quirks = of_device_get_match_data(dev);
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 921 if (quirks->needs_output_muxing) {
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 922 /*
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 923 * We assume there is no dynamic muxing of backends
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 924 * and TCONs, so we select the backend with same ID.
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 925 *
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 926 * While dynamic selection might be interesting, since
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 927 * the CRTC is tied to the TCON, while the layers are
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 928 * tied to the backends, this means, we will need to
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 929 * switch between groups of layers. There might not be
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 930 * a way to represent this constraint in DRM.
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 931 */
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 932 regmap_update_bits(backend->engine.regs,
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 933 SUN4I_BACKEND_MODCTL_REG,
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 934 SUN4I_BACKEND_MODCTL_OUT_SEL,
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 935 (backend->engine.id
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 936 ? SUN4I_BACKEND_MODCTL_OUT_LCD1
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 937 : SUN4I_BACKEND_MODCTL_OUT_LCD0));
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 938 }
f55c83d37b85de4 Chen-Yu Tsai 2017-10-17 939
e527cd9e48e33e8 Paul Kocialkowski 2018-07-19 940 backend->quirks = quirks;
e527cd9e48e33e8 Paul Kocialkowski 2018-07-19 941
9026e0d122ac87d Maxime Ripard 2015-10-29 942 return 0;
9026e0d122ac87d Maxime Ripard 2015-10-29 943
440d2c7b127a8b3 Maxime Ripard 2016-09-06 944 err_disable_ram_clk:
440d2c7b127a8b3 Maxime Ripard 2016-09-06 945 clk_disable_unprepare(backend->ram_clk);
9026e0d122ac87d Maxime Ripard 2015-10-29 946 err_disable_mod_clk:
451debe55715aca Maxime Ripard 2020-01-07 947 clk_rate_exclusive_put(backend->mod_clk);
9026e0d122ac87d Maxime Ripard 2015-10-29 948 clk_disable_unprepare(backend->mod_clk);
9026e0d122ac87d Maxime Ripard 2015-10-29 949 err_disable_bus_clk:
9026e0d122ac87d Maxime Ripard 2015-10-29 950 clk_disable_unprepare(backend->bus_clk);
9026e0d122ac87d Maxime Ripard 2015-10-29 951 err_assert_reset:
9026e0d122ac87d Maxime Ripard 2015-10-29 952 reset_control_assert(backend->reset);
9026e0d122ac87d Maxime Ripard 2015-10-29 953 return ret;
9026e0d122ac87d Maxime Ripard 2015-10-29 954 }
9026e0d122ac87d Maxime Ripard 2015-10-29 955
:::::: The code at line 818 was first introduced by commit
:::::: e0d072782c734d27f5af062c62266f2598f68542 dma-mapping: introduce DMA range map, supplanting dma_pfn_offset
:::::: TO: Jim Quinlan <james.quinlan@broadcom.com>
:::::: CC: Christoph Hellwig <hch@lst.de>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 53747 bytes --]
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2020-11-11 1:03 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-11 1:03 [hch-misc:dma_direct_set_offset-export 11/11] drivers/gpu/drm/sun4i/sun4i_backend.c:818:9: error: implicit declaration of function 'dma_direct_set_offset' kernel test robot
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.