* [PATCH 0/4] pinctrl: renesas: Add vin{4,5}_g8 pins
@ 2020-11-10 23:47 Niklas Söderlund
2020-11-10 23:47 ` [PATCH 1/4] pinctrl: renesas: r8a77951: " Niklas Söderlund
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Niklas Söderlund @ 2020-11-10 23:47 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-renesas-soc, Niklas Söderlund
Hello,
This series adds support for the vin{4,5}_g8 pins to R-Car r8a77951 (H3)
r8a7796 (M3-W), r8a77990 (E3) and r8a77965 (M3-N).
It is based on-top of v5.10-rc3.
Niklas Söderlund (4):
pinctrl: renesas: r8a77951: Add vin{4,5}_g8 pins
pinctrl: renesas: r8a7796: Add vin{4,5}_g8 pins
pinctrl: renesas: r8a77990: Add vin{4,5}_g8 pins
pinctrl: renesas: r8a77965: Add vin{4,5}_g8 pins
drivers/pinctrl/renesas/pfc-r8a77951.c | 30 ++++++++++++++++++++++-
drivers/pinctrl/renesas/pfc-r8a7796.c | 30 ++++++++++++++++++++++-
drivers/pinctrl/renesas/pfc-r8a77965.c | 34 +++++++++++++++++++++++++-
drivers/pinctrl/renesas/pfc-r8a77990.c | 34 +++++++++++++++++++++++++-
4 files changed, 124 insertions(+), 4 deletions(-)
--
2.29.2
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/4] pinctrl: renesas: r8a77951: Add vin{4,5}_g8 pins
2020-11-10 23:47 [PATCH 0/4] pinctrl: renesas: Add vin{4,5}_g8 pins Niklas Söderlund
@ 2020-11-10 23:47 ` Niklas Söderlund
2020-11-11 11:55 ` Jacopo Mondi
2020-11-11 11:57 ` Jacopo Mondi
2020-11-10 23:47 ` [PATCH 2/4] pinctrl: renesas: r8a7796: " Niklas Söderlund
` (2 subsequent siblings)
3 siblings, 2 replies; 11+ messages in thread
From: Niklas Söderlund @ 2020-11-10 23:47 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-renesas-soc, Niklas Söderlund
This patch adds VIN{4,5}_g8 support to the R8A77951 SoC.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/pinctrl/renesas/pfc-r8a77951.c | 30 +++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c
index a94ebe0bf5d06127..21864223c880b3ec 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77951.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
@@ -4074,6 +4074,18 @@ static const union vin_data vin4_data_b_mux = {
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
+static const unsigned int vin4_g8_pins[] = {
+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int vin4_g8_mux[] = {
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
@@ -4128,6 +4140,18 @@ static const union vin_data16 vin5_data_mux = {
VI5_DATA14_MARK, VI5_DATA15_MARK,
},
};
+static const unsigned int vin5_g8_pins[] = {
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int vin5_g8_mux[] = {
+ VI5_DATA8_MARK, VI5_DATA9_MARK,
+ VI5_DATA10_MARK, VI5_DATA11_MARK,
+ VI5_DATA12_MARK, VI5_DATA13_MARK,
+ VI5_DATA14_MARK, VI5_DATA15_MARK,
+};
static const unsigned int vin5_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
@@ -4158,7 +4182,7 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[320];
+ struct sh_pfc_pin_group common[322];
struct sh_pfc_pin_group automotive[30];
} pinmux_groups = {
.common = {
@@ -4470,6 +4494,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
+ SH_PFC_PIN_GROUP(vin4_g8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
@@ -4478,6 +4503,7 @@ static const struct {
VIN_DATA_PIN_GROUP(vin5_data, 10),
VIN_DATA_PIN_GROUP(vin5_data, 12),
VIN_DATA_PIN_GROUP(vin5_data, 16),
+ SH_PFC_PIN_GROUP(vin5_g8),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
@@ -5022,6 +5048,7 @@ static const char * const vin4_groups[] = {
"vin4_data18_b",
"vin4_data20_b",
"vin4_data24_b",
+ "vin4_g8",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
@@ -5033,6 +5060,7 @@ static const char * const vin5_groups[] = {
"vin5_data10",
"vin5_data12",
"vin5_data16",
+ "vin5_g8",
"vin5_sync",
"vin5_field",
"vin5_clkenb",
--
2.29.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/4] pinctrl: renesas: r8a7796: Add vin{4,5}_g8 pins
2020-11-10 23:47 [PATCH 0/4] pinctrl: renesas: Add vin{4,5}_g8 pins Niklas Söderlund
2020-11-10 23:47 ` [PATCH 1/4] pinctrl: renesas: r8a77951: " Niklas Söderlund
@ 2020-11-10 23:47 ` Niklas Söderlund
2020-11-11 12:00 ` Jacopo Mondi
2020-11-10 23:47 ` [PATCH 3/4] pinctrl: renesas: r8a77990: " Niklas Söderlund
2020-11-10 23:47 ` [PATCH 4/4] pinctrl: renesas: r8a77965: " Niklas Söderlund
3 siblings, 1 reply; 11+ messages in thread
From: Niklas Söderlund @ 2020-11-10 23:47 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-renesas-soc, Niklas Söderlund
This patch adds VIN{4,5}_g8 support to the R8A7796 SoC.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/pinctrl/renesas/pfc-r8a7796.c | 30 ++++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 55f0344a3d3e9af6..91591fbcec86c3f8 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -4048,6 +4048,18 @@ static const union vin_data vin4_data_b_mux = {
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
+static const unsigned int vin4_g8_pins[] = {
+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int vin4_g8_mux[] = {
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
@@ -4102,6 +4114,18 @@ static const union vin_data16 vin5_data_mux = {
VI5_DATA14_MARK, VI5_DATA15_MARK,
},
};
+static const unsigned int vin5_g8_pins[] = {
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int vin5_g8_mux[] = {
+ VI5_DATA8_MARK, VI5_DATA9_MARK,
+ VI5_DATA10_MARK, VI5_DATA11_MARK,
+ VI5_DATA12_MARK, VI5_DATA13_MARK,
+ VI5_DATA14_MARK, VI5_DATA15_MARK,
+};
static const unsigned int vin5_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
@@ -4132,7 +4156,7 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[316];
+ struct sh_pfc_pin_group common[318];
struct sh_pfc_pin_group automotive[30];
} pinmux_groups = {
.common = {
@@ -4440,6 +4464,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
+ SH_PFC_PIN_GROUP(vin4_g8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
@@ -4448,6 +4473,7 @@ static const struct {
VIN_DATA_PIN_GROUP(vin5_data, 10),
VIN_DATA_PIN_GROUP(vin5_data, 12),
VIN_DATA_PIN_GROUP(vin5_data, 16),
+ SH_PFC_PIN_GROUP(vin5_g8),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
@@ -4978,6 +5004,7 @@ static const char * const vin4_groups[] = {
"vin4_data18_b",
"vin4_data20_b",
"vin4_data24_b",
+ "vin4_g8",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
@@ -4989,6 +5016,7 @@ static const char * const vin5_groups[] = {
"vin5_data10",
"vin5_data12",
"vin5_data16",
+ "vin5_g8",
"vin5_sync",
"vin5_field",
"vin5_clkenb",
--
2.29.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/4] pinctrl: renesas: r8a77990: Add vin{4,5}_g8 pins
2020-11-10 23:47 [PATCH 0/4] pinctrl: renesas: Add vin{4,5}_g8 pins Niklas Söderlund
2020-11-10 23:47 ` [PATCH 1/4] pinctrl: renesas: r8a77951: " Niklas Söderlund
2020-11-10 23:47 ` [PATCH 2/4] pinctrl: renesas: r8a7796: " Niklas Söderlund
@ 2020-11-10 23:47 ` Niklas Söderlund
2020-11-11 12:05 ` Jacopo Mondi
2020-11-10 23:47 ` [PATCH 4/4] pinctrl: renesas: r8a77965: " Niklas Söderlund
3 siblings, 1 reply; 11+ messages in thread
From: Niklas Söderlund @ 2020-11-10 23:47 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-renesas-soc, Niklas Söderlund
This patch adds VIN{4,5}_g8 support to the R8A77990 SoC.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/pinctrl/renesas/pfc-r8a77990.c | 34 +++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index aed04a4c61163cb2..e2cf6061dba1b0d5 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -3644,6 +3644,20 @@ static const union vin_data vin4_data_b_mux = {
},
};
+static const unsigned int vin4_g8_pins[] = {
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
+};
+
+static const unsigned int vin4_g8_mux[] = {
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+};
+
static const unsigned int vin4_sync_pins[] = {
/* HSYNC, VSYNC */
RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
@@ -3718,6 +3732,20 @@ static const unsigned int vin5_data8_b_mux[] = {
VI5_DATA6_B_MARK, VI5_DATA7_B_MARK,
};
+static const unsigned int vin5_g8_pins[] = {
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+};
+
+static const unsigned int vin5_g8_mux[] = {
+ VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
+ VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
+ VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
+ VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
+};
+
static const unsigned int vin5_sync_a_pins[] = {
/* HSYNC_N, VSYNC_N */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
@@ -3760,7 +3788,7 @@ static const unsigned int vin5_clk_b_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[247];
+ struct sh_pfc_pin_group common[249];
struct sh_pfc_pin_group automotive[21];
} pinmux_groups = {
.common = {
@@ -3997,6 +4025,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
+ SH_PFC_PIN_GROUP(vin4_g8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
@@ -4006,6 +4035,7 @@ static const struct {
VIN_DATA_PIN_GROUP(vin5_data, 12, _a),
VIN_DATA_PIN_GROUP(vin5_data, 16, _a),
SH_PFC_PIN_GROUP(vin5_data8_b),
+ SH_PFC_PIN_GROUP(vin5_g8),
SH_PFC_PIN_GROUP(vin5_sync_a),
SH_PFC_PIN_GROUP(vin5_field_a),
SH_PFC_PIN_GROUP(vin5_clkenb_a),
@@ -4439,6 +4469,7 @@ static const char * const vin4_groups[] = {
"vin4_data18_b",
"vin4_data20_b",
"vin4_data24_b",
+ "vin4_g8",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
@@ -4451,6 +4482,7 @@ static const char * const vin5_groups[] = {
"vin5_data12_a",
"vin5_data16_a",
"vin5_data8_b",
+ "vin5_g8",
"vin5_sync_a",
"vin5_field_a",
"vin5_clkenb_a",
--
2.29.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/4] pinctrl: renesas: r8a77965: Add vin{4,5}_g8 pins
2020-11-10 23:47 [PATCH 0/4] pinctrl: renesas: Add vin{4,5}_g8 pins Niklas Söderlund
` (2 preceding siblings ...)
2020-11-10 23:47 ` [PATCH 3/4] pinctrl: renesas: r8a77990: " Niklas Söderlund
@ 2020-11-10 23:47 ` Niklas Söderlund
2020-11-11 12:07 ` Jacopo Mondi
3 siblings, 1 reply; 11+ messages in thread
From: Niklas Söderlund @ 2020-11-10 23:47 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-renesas-soc, Niklas Söderlund
This patch adds VIN{4,5}_g8 support to the R8A77965 SoC.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/pinctrl/renesas/pfc-r8a77965.c | 34 +++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c
index 7a50b9b69a7dc4e3..20198e3b50191665 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -4285,6 +4285,20 @@ static const union vin_data vin4_data_b_mux = {
},
};
+static const unsigned int vin4_g8_pins[] = {
+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+
+static const unsigned int vin4_g8_mux[] = {
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+};
+
static const unsigned int vin4_sync_pins[] = {
/* VSYNC_N, HSYNC_N */
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
@@ -4345,6 +4359,20 @@ static const union vin_data16 vin5_data_mux = {
},
};
+static const unsigned int vin5_g8_pins[] = {
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+
+static const unsigned int vin5_g8_mux[] = {
+ VI5_DATA8_MARK, VI5_DATA9_MARK,
+ VI5_DATA10_MARK, VI5_DATA11_MARK,
+ VI5_DATA12_MARK, VI5_DATA13_MARK,
+ VI5_DATA14_MARK, VI5_DATA15_MARK,
+};
+
static const unsigned int vin5_sync_pins[] = {
/* VSYNC_N, HSYNC_N */
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
@@ -4379,7 +4407,7 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[318];
+ struct sh_pfc_pin_group common[320];
struct sh_pfc_pin_group automotive[30];
} pinmux_groups = {
.common = {
@@ -4689,6 +4717,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
+ SH_PFC_PIN_GROUP(vin4_g8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
@@ -4697,6 +4726,7 @@ static const struct {
VIN_DATA_PIN_GROUP(vin5_data, 10),
VIN_DATA_PIN_GROUP(vin5_data, 12),
VIN_DATA_PIN_GROUP(vin5_data, 16),
+ SH_PFC_PIN_GROUP(vin5_g8),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
@@ -5231,6 +5261,7 @@ static const char * const vin4_groups[] = {
"vin4_data18_b",
"vin4_data20_b",
"vin4_data24_b",
+ "vin4_g8",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
@@ -5242,6 +5273,7 @@ static const char * const vin5_groups[] = {
"vin5_data10",
"vin5_data12",
"vin5_data16",
+ "vin5_g8",
"vin5_sync",
"vin5_field",
"vin5_clkenb",
--
2.29.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/4] pinctrl: renesas: r8a77951: Add vin{4,5}_g8 pins
2020-11-10 23:47 ` [PATCH 1/4] pinctrl: renesas: r8a77951: " Niklas Söderlund
@ 2020-11-11 11:55 ` Jacopo Mondi
2020-11-16 8:58 ` Geert Uytterhoeven
2020-11-11 11:57 ` Jacopo Mondi
1 sibling, 1 reply; 11+ messages in thread
From: Jacopo Mondi @ 2020-11-11 11:55 UTC (permalink / raw)
To: Niklas Söderlund; +Cc: Geert Uytterhoeven, linux-renesas-soc
Hi Niklas,
On Wed, Nov 11, 2020 at 12:47:49AM +0100, Niklas Söderlund wrote:
> This patch adds VIN{4,5}_g8 support to the R8A77951 SoC.
Now that I've asked offline why the 'g' in the group name I see
the reason which otherwise let me search for a _g group that does not
exists in the documentation.
Can you mention in this and other patches that the groups are 8-pins
groups on VIN4/5 [15:8] pins, named 'g' as when capturing RGB they are
dedicated to the green channel ?
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Patch looks good
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Thanks
j
> ---
> drivers/pinctrl/renesas/pfc-r8a77951.c | 30 +++++++++++++++++++++++++-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c
> index a94ebe0bf5d06127..21864223c880b3ec 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a77951.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
> @@ -4074,6 +4074,18 @@ static const union vin_data vin4_data_b_mux = {
> VI4_DATA22_MARK, VI4_DATA23_MARK,
> },
> };
> +static const unsigned int vin4_g8_pins[] = {
> + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
> + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> +};
> +static const unsigned int vin4_g8_mux[] = {
> + VI4_DATA8_MARK, VI4_DATA9_MARK,
> + VI4_DATA10_MARK, VI4_DATA11_MARK,
> + VI4_DATA12_MARK, VI4_DATA13_MARK,
> + VI4_DATA14_MARK, VI4_DATA15_MARK,
> +};
> static const unsigned int vin4_sync_pins[] = {
> /* HSYNC#, VSYNC# */
> RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
> @@ -4128,6 +4140,18 @@ static const union vin_data16 vin5_data_mux = {
> VI5_DATA14_MARK, VI5_DATA15_MARK,
> },
> };
> +static const unsigned int vin5_g8_pins[] = {
> + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
> + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> +};
> +static const unsigned int vin5_g8_mux[] = {
> + VI5_DATA8_MARK, VI5_DATA9_MARK,
> + VI5_DATA10_MARK, VI5_DATA11_MARK,
> + VI5_DATA12_MARK, VI5_DATA13_MARK,
> + VI5_DATA14_MARK, VI5_DATA15_MARK,
> +};
> static const unsigned int vin5_sync_pins[] = {
> /* HSYNC#, VSYNC# */
> RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
> @@ -4158,7 +4182,7 @@ static const unsigned int vin5_clk_mux[] = {
> };
>
> static const struct {
> - struct sh_pfc_pin_group common[320];
> + struct sh_pfc_pin_group common[322];
> struct sh_pfc_pin_group automotive[30];
> } pinmux_groups = {
> .common = {
> @@ -4470,6 +4494,7 @@ static const struct {
> SH_PFC_PIN_GROUP(vin4_data18_b),
> VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
> VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
> + SH_PFC_PIN_GROUP(vin4_g8),
> SH_PFC_PIN_GROUP(vin4_sync),
> SH_PFC_PIN_GROUP(vin4_field),
> SH_PFC_PIN_GROUP(vin4_clkenb),
> @@ -4478,6 +4503,7 @@ static const struct {
> VIN_DATA_PIN_GROUP(vin5_data, 10),
> VIN_DATA_PIN_GROUP(vin5_data, 12),
> VIN_DATA_PIN_GROUP(vin5_data, 16),
> + SH_PFC_PIN_GROUP(vin5_g8),
> SH_PFC_PIN_GROUP(vin5_sync),
> SH_PFC_PIN_GROUP(vin5_field),
> SH_PFC_PIN_GROUP(vin5_clkenb),
> @@ -5022,6 +5048,7 @@ static const char * const vin4_groups[] = {
> "vin4_data18_b",
> "vin4_data20_b",
> "vin4_data24_b",
> + "vin4_g8",
> "vin4_sync",
> "vin4_field",
> "vin4_clkenb",
> @@ -5033,6 +5060,7 @@ static const char * const vin5_groups[] = {
> "vin5_data10",
> "vin5_data12",
> "vin5_data16",
> + "vin5_g8",
> "vin5_sync",
> "vin5_field",
> "vin5_clkenb",
> --
> 2.29.2
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/4] pinctrl: renesas: r8a77951: Add vin{4,5}_g8 pins
2020-11-10 23:47 ` [PATCH 1/4] pinctrl: renesas: r8a77951: " Niklas Söderlund
2020-11-11 11:55 ` Jacopo Mondi
@ 2020-11-11 11:57 ` Jacopo Mondi
1 sibling, 0 replies; 11+ messages in thread
From: Jacopo Mondi @ 2020-11-11 11:57 UTC (permalink / raw)
To: Niklas Söderlund; +Cc: Geert Uytterhoeven, linux-renesas-soc
An additional note
On Wed, Nov 11, 2020 at 12:47:49AM +0100, Niklas Söderlund wrote:
> This patch adds VIN{4,5}_g8 support to the R8A77951 SoC.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> ---
> drivers/pinctrl/renesas/pfc-r8a77951.c | 30 +++++++++++++++++++++++++-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c
> index a94ebe0bf5d06127..21864223c880b3ec 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a77951.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
> @@ -4074,6 +4074,18 @@ static const union vin_data vin4_data_b_mux = {
> VI4_DATA22_MARK, VI4_DATA23_MARK,
> },
> };
> +static const unsigned int vin4_g8_pins[] = {
> + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
> + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> +};
Existing groups have an empty line here, and also 3/4 and 4/4 do.
Can you add it in 1/4 and 2/4 ?
Thanks
j
> +static const unsigned int vin4_g8_mux[] = {
> + VI4_DATA8_MARK, VI4_DATA9_MARK,
> + VI4_DATA10_MARK, VI4_DATA11_MARK,
> + VI4_DATA12_MARK, VI4_DATA13_MARK,
> + VI4_DATA14_MARK, VI4_DATA15_MARK,
> +};
> static const unsigned int vin4_sync_pins[] = {
> /* HSYNC#, VSYNC# */
> RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
> @@ -4128,6 +4140,18 @@ static const union vin_data16 vin5_data_mux = {
> VI5_DATA14_MARK, VI5_DATA15_MARK,
> },
> };
> +static const unsigned int vin5_g8_pins[] = {
> + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
> + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> +};
> +static const unsigned int vin5_g8_mux[] = {
> + VI5_DATA8_MARK, VI5_DATA9_MARK,
> + VI5_DATA10_MARK, VI5_DATA11_MARK,
> + VI5_DATA12_MARK, VI5_DATA13_MARK,
> + VI5_DATA14_MARK, VI5_DATA15_MARK,
> +};
> static const unsigned int vin5_sync_pins[] = {
> /* HSYNC#, VSYNC# */
> RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
> @@ -4158,7 +4182,7 @@ static const unsigned int vin5_clk_mux[] = {
> };
>
> static const struct {
> - struct sh_pfc_pin_group common[320];
> + struct sh_pfc_pin_group common[322];
> struct sh_pfc_pin_group automotive[30];
> } pinmux_groups = {
> .common = {
> @@ -4470,6 +4494,7 @@ static const struct {
> SH_PFC_PIN_GROUP(vin4_data18_b),
> VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
> VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
> + SH_PFC_PIN_GROUP(vin4_g8),
> SH_PFC_PIN_GROUP(vin4_sync),
> SH_PFC_PIN_GROUP(vin4_field),
> SH_PFC_PIN_GROUP(vin4_clkenb),
> @@ -4478,6 +4503,7 @@ static const struct {
> VIN_DATA_PIN_GROUP(vin5_data, 10),
> VIN_DATA_PIN_GROUP(vin5_data, 12),
> VIN_DATA_PIN_GROUP(vin5_data, 16),
> + SH_PFC_PIN_GROUP(vin5_g8),
> SH_PFC_PIN_GROUP(vin5_sync),
> SH_PFC_PIN_GROUP(vin5_field),
> SH_PFC_PIN_GROUP(vin5_clkenb),
> @@ -5022,6 +5048,7 @@ static const char * const vin4_groups[] = {
> "vin4_data18_b",
> "vin4_data20_b",
> "vin4_data24_b",
> + "vin4_g8",
> "vin4_sync",
> "vin4_field",
> "vin4_clkenb",
> @@ -5033,6 +5060,7 @@ static const char * const vin5_groups[] = {
> "vin5_data10",
> "vin5_data12",
> "vin5_data16",
> + "vin5_g8",
> "vin5_sync",
> "vin5_field",
> "vin5_clkenb",
> --
> 2.29.2
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/4] pinctrl: renesas: r8a7796: Add vin{4,5}_g8 pins
2020-11-10 23:47 ` [PATCH 2/4] pinctrl: renesas: r8a7796: " Niklas Söderlund
@ 2020-11-11 12:00 ` Jacopo Mondi
0 siblings, 0 replies; 11+ messages in thread
From: Jacopo Mondi @ 2020-11-11 12:00 UTC (permalink / raw)
To: Niklas Söderlund; +Cc: Geert Uytterhoeven, linux-renesas-soc
On Wed, Nov 11, 2020 at 12:47:50AM +0100, Niklas Söderlund wrote:
> This patch adds VIN{4,5}_g8 support to the R8A7796 SoC.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> ---
> drivers/pinctrl/renesas/pfc-r8a7796.c | 30 ++++++++++++++++++++++++++-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c
> index 55f0344a3d3e9af6..91591fbcec86c3f8 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a7796.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
> @@ -4048,6 +4048,18 @@ static const union vin_data vin4_data_b_mux = {
> VI4_DATA22_MARK, VI4_DATA23_MARK,
> },
> };
> +static const unsigned int vin4_g8_pins[] = {
> + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
> + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> +};
And to correct myself: r8a77951 and r8a7796 PFC have no empty lines,
others do. So you're patches are consistent with what it's there
already
> +static const unsigned int vin4_g8_mux[] = {
> + VI4_DATA8_MARK, VI4_DATA9_MARK,
> + VI4_DATA10_MARK, VI4_DATA11_MARK,
> + VI4_DATA12_MARK, VI4_DATA13_MARK,
> + VI4_DATA14_MARK, VI4_DATA15_MARK,
> +};
> static const unsigned int vin4_sync_pins[] = {
> /* HSYNC#, VSYNC# */
> RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
> @@ -4102,6 +4114,18 @@ static const union vin_data16 vin5_data_mux = {
> VI5_DATA14_MARK, VI5_DATA15_MARK,
> },
> };
> +static const unsigned int vin5_g8_pins[] = {
> + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
> + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> +};
> +static const unsigned int vin5_g8_mux[] = {
> + VI5_DATA8_MARK, VI5_DATA9_MARK,
> + VI5_DATA10_MARK, VI5_DATA11_MARK,
> + VI5_DATA12_MARK, VI5_DATA13_MARK,
> + VI5_DATA14_MARK, VI5_DATA15_MARK,
> +};
Patch looks good!
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> static const unsigned int vin5_sync_pins[] = {
> /* HSYNC#, VSYNC# */
> RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
> @@ -4132,7 +4156,7 @@ static const unsigned int vin5_clk_mux[] = {
> };
>
> static const struct {
> - struct sh_pfc_pin_group common[316];
> + struct sh_pfc_pin_group common[318];
> struct sh_pfc_pin_group automotive[30];
> } pinmux_groups = {
> .common = {
> @@ -4440,6 +4464,7 @@ static const struct {
> SH_PFC_PIN_GROUP(vin4_data18_b),
> VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
> VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
> + SH_PFC_PIN_GROUP(vin4_g8),
> SH_PFC_PIN_GROUP(vin4_sync),
> SH_PFC_PIN_GROUP(vin4_field),
> SH_PFC_PIN_GROUP(vin4_clkenb),
> @@ -4448,6 +4473,7 @@ static const struct {
> VIN_DATA_PIN_GROUP(vin5_data, 10),
> VIN_DATA_PIN_GROUP(vin5_data, 12),
> VIN_DATA_PIN_GROUP(vin5_data, 16),
> + SH_PFC_PIN_GROUP(vin5_g8),
> SH_PFC_PIN_GROUP(vin5_sync),
> SH_PFC_PIN_GROUP(vin5_field),
> SH_PFC_PIN_GROUP(vin5_clkenb),
> @@ -4978,6 +5004,7 @@ static const char * const vin4_groups[] = {
> "vin4_data18_b",
> "vin4_data20_b",
> "vin4_data24_b",
> + "vin4_g8",
> "vin4_sync",
> "vin4_field",
> "vin4_clkenb",
> @@ -4989,6 +5016,7 @@ static const char * const vin5_groups[] = {
> "vin5_data10",
> "vin5_data12",
> "vin5_data16",
> + "vin5_g8",
> "vin5_sync",
> "vin5_field",
> "vin5_clkenb",
> --
> 2.29.2
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/4] pinctrl: renesas: r8a77990: Add vin{4,5}_g8 pins
2020-11-10 23:47 ` [PATCH 3/4] pinctrl: renesas: r8a77990: " Niklas Söderlund
@ 2020-11-11 12:05 ` Jacopo Mondi
0 siblings, 0 replies; 11+ messages in thread
From: Jacopo Mondi @ 2020-11-11 12:05 UTC (permalink / raw)
To: Niklas Söderlund; +Cc: Geert Uytterhoeven, linux-renesas-soc
Hi Niklas,
weird D3 should have the same but the pinmux tables do not report
it..
On Wed, Nov 11, 2020 at 12:47:51AM +0100, Niklas Söderlund wrote:
> This patch adds VIN{4,5}_g8 support to the R8A77990 SoC.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Looks good
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Thanks
j
> ---
> drivers/pinctrl/renesas/pfc-r8a77990.c | 34 +++++++++++++++++++++++++-
> 1 file changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
> index aed04a4c61163cb2..e2cf6061dba1b0d5 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a77990.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
> @@ -3644,6 +3644,20 @@ static const union vin_data vin4_data_b_mux = {
> },
> };
>
> +static const unsigned int vin4_g8_pins[] = {
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
> + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
> +};
> +
> +static const unsigned int vin4_g8_mux[] = {
> + VI4_DATA8_MARK, VI4_DATA9_MARK,
> + VI4_DATA10_MARK, VI4_DATA11_MARK,
> + VI4_DATA12_MARK, VI4_DATA13_MARK,
> + VI4_DATA14_MARK, VI4_DATA15_MARK,
> +};
> +
> static const unsigned int vin4_sync_pins[] = {
> /* HSYNC, VSYNC */
> RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
> @@ -3718,6 +3732,20 @@ static const unsigned int vin5_data8_b_mux[] = {
> VI5_DATA6_B_MARK, VI5_DATA7_B_MARK,
> };
>
> +static const unsigned int vin5_g8_pins[] = {
> + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
> + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
> + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
> + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
> +};
> +
> +static const unsigned int vin5_g8_mux[] = {
> + VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
> + VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
> + VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
> + VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
> +};
> +
> static const unsigned int vin5_sync_a_pins[] = {
> /* HSYNC_N, VSYNC_N */
> RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
> @@ -3760,7 +3788,7 @@ static const unsigned int vin5_clk_b_mux[] = {
> };
>
> static const struct {
> - struct sh_pfc_pin_group common[247];
> + struct sh_pfc_pin_group common[249];
> struct sh_pfc_pin_group automotive[21];
> } pinmux_groups = {
> .common = {
> @@ -3997,6 +4025,7 @@ static const struct {
> SH_PFC_PIN_GROUP(vin4_data18_b),
> VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
> VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
> + SH_PFC_PIN_GROUP(vin4_g8),
> SH_PFC_PIN_GROUP(vin4_sync),
> SH_PFC_PIN_GROUP(vin4_field),
> SH_PFC_PIN_GROUP(vin4_clkenb),
> @@ -4006,6 +4035,7 @@ static const struct {
> VIN_DATA_PIN_GROUP(vin5_data, 12, _a),
> VIN_DATA_PIN_GROUP(vin5_data, 16, _a),
> SH_PFC_PIN_GROUP(vin5_data8_b),
> + SH_PFC_PIN_GROUP(vin5_g8),
> SH_PFC_PIN_GROUP(vin5_sync_a),
> SH_PFC_PIN_GROUP(vin5_field_a),
> SH_PFC_PIN_GROUP(vin5_clkenb_a),
> @@ -4439,6 +4469,7 @@ static const char * const vin4_groups[] = {
> "vin4_data18_b",
> "vin4_data20_b",
> "vin4_data24_b",
> + "vin4_g8",
> "vin4_sync",
> "vin4_field",
> "vin4_clkenb",
> @@ -4451,6 +4482,7 @@ static const char * const vin5_groups[] = {
> "vin5_data12_a",
> "vin5_data16_a",
> "vin5_data8_b",
> + "vin5_g8",
> "vin5_sync_a",
> "vin5_field_a",
> "vin5_clkenb_a",
> --
> 2.29.2
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 4/4] pinctrl: renesas: r8a77965: Add vin{4,5}_g8 pins
2020-11-10 23:47 ` [PATCH 4/4] pinctrl: renesas: r8a77965: " Niklas Söderlund
@ 2020-11-11 12:07 ` Jacopo Mondi
0 siblings, 0 replies; 11+ messages in thread
From: Jacopo Mondi @ 2020-11-11 12:07 UTC (permalink / raw)
To: Niklas Söderlund; +Cc: Geert Uytterhoeven, linux-renesas-soc
Hi Niklas,
On Wed, Nov 11, 2020 at 12:47:52AM +0100, Niklas Söderlund wrote:
> This patch adds VIN{4,5}_g8 support to the R8A77965 SoC.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Looks good!
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Thanks
j
> ---
> drivers/pinctrl/renesas/pfc-r8a77965.c | 34 +++++++++++++++++++++++++-
> 1 file changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c
> index 7a50b9b69a7dc4e3..20198e3b50191665 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a77965.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
> @@ -4285,6 +4285,20 @@ static const union vin_data vin4_data_b_mux = {
> },
> };
>
> +static const unsigned int vin4_g8_pins[] = {
> + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
> + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> +};
> +
> +static const unsigned int vin4_g8_mux[] = {
> + VI4_DATA8_MARK, VI4_DATA9_MARK,
> + VI4_DATA10_MARK, VI4_DATA11_MARK,
> + VI4_DATA12_MARK, VI4_DATA13_MARK,
> + VI4_DATA14_MARK, VI4_DATA15_MARK,
> +};
> +
> static const unsigned int vin4_sync_pins[] = {
> /* VSYNC_N, HSYNC_N */
> RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
> @@ -4345,6 +4359,20 @@ static const union vin_data16 vin5_data_mux = {
> },
> };
>
> +static const unsigned int vin5_g8_pins[] = {
> + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
> + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> +};
> +
> +static const unsigned int vin5_g8_mux[] = {
> + VI5_DATA8_MARK, VI5_DATA9_MARK,
> + VI5_DATA10_MARK, VI5_DATA11_MARK,
> + VI5_DATA12_MARK, VI5_DATA13_MARK,
> + VI5_DATA14_MARK, VI5_DATA15_MARK,
> +};
> +
> static const unsigned int vin5_sync_pins[] = {
> /* VSYNC_N, HSYNC_N */
> RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
> @@ -4379,7 +4407,7 @@ static const unsigned int vin5_clk_mux[] = {
> };
>
> static const struct {
> - struct sh_pfc_pin_group common[318];
> + struct sh_pfc_pin_group common[320];
> struct sh_pfc_pin_group automotive[30];
> } pinmux_groups = {
> .common = {
> @@ -4689,6 +4717,7 @@ static const struct {
> SH_PFC_PIN_GROUP(vin4_data18_b),
> VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
> VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
> + SH_PFC_PIN_GROUP(vin4_g8),
> SH_PFC_PIN_GROUP(vin4_sync),
> SH_PFC_PIN_GROUP(vin4_field),
> SH_PFC_PIN_GROUP(vin4_clkenb),
> @@ -4697,6 +4726,7 @@ static const struct {
> VIN_DATA_PIN_GROUP(vin5_data, 10),
> VIN_DATA_PIN_GROUP(vin5_data, 12),
> VIN_DATA_PIN_GROUP(vin5_data, 16),
> + SH_PFC_PIN_GROUP(vin5_g8),
> SH_PFC_PIN_GROUP(vin5_sync),
> SH_PFC_PIN_GROUP(vin5_field),
> SH_PFC_PIN_GROUP(vin5_clkenb),
> @@ -5231,6 +5261,7 @@ static const char * const vin4_groups[] = {
> "vin4_data18_b",
> "vin4_data20_b",
> "vin4_data24_b",
> + "vin4_g8",
> "vin4_sync",
> "vin4_field",
> "vin4_clkenb",
> @@ -5242,6 +5273,7 @@ static const char * const vin5_groups[] = {
> "vin5_data10",
> "vin5_data12",
> "vin5_data16",
> + "vin5_g8",
> "vin5_sync",
> "vin5_field",
> "vin5_clkenb",
> --
> 2.29.2
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/4] pinctrl: renesas: r8a77951: Add vin{4,5}_g8 pins
2020-11-11 11:55 ` Jacopo Mondi
@ 2020-11-16 8:58 ` Geert Uytterhoeven
0 siblings, 0 replies; 11+ messages in thread
From: Geert Uytterhoeven @ 2020-11-16 8:58 UTC (permalink / raw)
To: Jacopo Mondi, Niklas Söderlund; +Cc: Linux-Renesas
Hi Jacopo, Niklas,
On Wed, Nov 11, 2020 at 12:55 PM Jacopo Mondi <jacopo@jmondi.org> wrote:
> On Wed, Nov 11, 2020 at 12:47:49AM +0100, Niklas Söderlund wrote:
> > This patch adds VIN{4,5}_g8 support to the R8A77951 SoC.
>
> Now that I've asked offline why the 'g' in the group name I see
> the reason which otherwise let me search for a _g group that does not
> exists in the documentation.
>
> Can you mention in this and other patches that the groups are 8-pins
> groups on VIN4/5 [15:8] pins, named 'g' as when capturing RGB they are
g8
> dedicated to the green channel ?
However, that is only true for VIN4: VIN5 does not support 24-bit RGB,
as it is only a 16-bit interface. Hence we need a better name than "g8"
for VIN5. What about "high8" or "msb8"?
Any other suggestions?
The rest looks good to me, but a rebase on renesas-pinctrl wouldn't hurt ;-)
Same comment for the other patches.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-11-16 9:29 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-10 23:47 [PATCH 0/4] pinctrl: renesas: Add vin{4,5}_g8 pins Niklas Söderlund
2020-11-10 23:47 ` [PATCH 1/4] pinctrl: renesas: r8a77951: " Niklas Söderlund
2020-11-11 11:55 ` Jacopo Mondi
2020-11-16 8:58 ` Geert Uytterhoeven
2020-11-11 11:57 ` Jacopo Mondi
2020-11-10 23:47 ` [PATCH 2/4] pinctrl: renesas: r8a7796: " Niklas Söderlund
2020-11-11 12:00 ` Jacopo Mondi
2020-11-10 23:47 ` [PATCH 3/4] pinctrl: renesas: r8a77990: " Niklas Söderlund
2020-11-11 12:05 ` Jacopo Mondi
2020-11-10 23:47 ` [PATCH 4/4] pinctrl: renesas: r8a77965: " Niklas Söderlund
2020-11-11 12:07 ` Jacopo Mondi
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