* [PATCH 01/17] drm/amd/display: Program dpp dto based on actual dpp clk
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 02/17] drm/amd/display: Hook up PSR residency command to DSAT Bindu Ramamurthy
` (15 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Aurabindo.Pillai, Yongqiang Sun,
Bhawanpreet.Lakha, bindu.r
From: Yongqiang Sun <yongqiang.sun@amd.com>
[Why]
dpp dto phase and modulo are programmed with actual dpp global clk
and pipe clk. Need to use actual dpp clk to prgoram dpp dto modulo
to get more accuracy ratio.
[How]
assign actual dpp clk to dccg for dpp modulo programming.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 29 +++++++++++++++++--
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index ec394e3d8367..9e3d8af3895f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -103,6 +103,30 @@ void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
}
+static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
+ struct dc_state *context, bool safe_to_lower)
+{
+ int i;
+
+ clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.actual_dppclk_khz;
+ for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
+ int dpp_inst, dppclk_khz, prev_dppclk_khz;
+
+ /* Loop index will match dpp->inst if resource exists,
+ * and we want to avoid dependency on dpp object
+ */
+ dpp_inst = i;
+ dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
+
+ prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
+
+ if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
+ clk_mgr->dccg->funcs->update_dpp_dto(
+ clk_mgr->dccg, dpp_inst, dppclk_khz);
+ }
+}
+
+
void rn_update_clocks(struct clk_mgr *clk_mgr_base,
struct dc_state *context,
bool safe_to_lower)
@@ -177,7 +201,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
if (dpp_clock_lowered) {
// increase per DPP DTO before lowering global dppclk
- dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+ rn_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
clk_mgr_base->clks.actual_dppclk_khz =
rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
@@ -188,7 +212,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
// always update dtos unless clock is lowered and not safe to lower
if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
- dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+ rn_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
}
if (update_dispclk &&
@@ -199,7 +223,6 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
}
}
-
static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
{
/* get FbMult value */
--
2.25.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 02/17] drm/amd/display: Hook up PSR residency command to DSAT
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 01/17] drm/amd/display: Program dpp dto based on actual dpp clk Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 03/17] drm/amd/display: Populate hostvm parameter before DML calculation Bindu Ramamurthy
` (14 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Aurabindo.Pillai, Wyatt Wood,
Bhawanpreet.Lakha, bindu.r
From: Wyatt Wood <wyatt.wood@amd.com>
[Why]
Use GPINT command to get PSR residency from FW.
[How]
Hook up PSR residency command to DSAT.
Since PSR Count Request is deprecated, we will use this.
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 12 ++++++++++++
drivers/gpu/drm/amd/display/dc/dc_link.h | 2 ++
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 14 ++++++++++++++
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h | 1 +
4 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ee2a51b7a2ee..858acd3df2bc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2783,6 +2783,18 @@ bool dc_link_setup_psr(struct dc_link *link,
}
+void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
+{
+ struct dc *dc = link->ctx->dc;
+ struct dmub_psr *psr = dc->res_pool->psr;
+
+ // PSR residency measurements only supported on DMCUB
+ if (psr != NULL && link->psr_settings.psr_feature_enabled)
+ psr->funcs->psr_get_residency(psr, residency);
+ else
+ *residency = 0;
+}
+
const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
{
return &link->link_status;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 39277aaa3e62..65b083e64131 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -228,6 +228,8 @@ bool dc_link_setup_psr(struct dc_link *dc_link,
const struct dc_stream_state *stream, struct psr_config *psr_config,
struct psr_context *psr_context);
+void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency);
+
/* Request DC to detect if there is a Panel connected.
* boot - If this call is during initial boot.
* Return false for any type of detection failure or MST detection
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index df3879c713c5..0d6fe7c29c20 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -293,12 +293,26 @@ static void dmub_psr_force_static(struct dmub_psr *dmub)
dc_dmub_srv_wait_idle(dc->dmub_srv);
}
+/**
+ * Get PSR residency from firmware.
+ */
+static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency)
+{
+ struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
+
+ // Send gpint command and wait for ack
+ dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, 0, 30);
+
+ dmub_srv_get_gpint_response(srv, residency);
+}
+
static const struct dmub_psr_funcs psr_funcs = {
.psr_copy_settings = dmub_psr_copy_settings,
.psr_enable = dmub_psr_enable,
.psr_get_state = dmub_psr_get_state,
.psr_set_level = dmub_psr_set_level,
.psr_force_static = dmub_psr_force_static,
+ .psr_get_residency = dmub_psr_get_residency,
};
/**
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
index 4e113ac5a56b..fe747c20a0d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
@@ -40,6 +40,7 @@ struct dmub_psr_funcs {
void (*psr_get_state)(struct dmub_psr *dmub, enum dc_psr_state *dc_psr_state);
void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level);
void (*psr_force_static)(struct dmub_psr *dmub);
+ void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency);
};
struct dmub_psr *dmub_psr_create(struct dc_context *ctx);
--
2.25.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 03/17] drm/amd/display: Populate hostvm parameter before DML calculation
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 01/17] drm/amd/display: Program dpp dto based on actual dpp clk Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 02/17] drm/amd/display: Hook up PSR residency command to DSAT Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 04/17] drm/amd/display: Handle Unknown Result for SMU Periodic Retraining on DCN2.1 Bindu Ramamurthy
` (13 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Sung Lee, Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Aurabindo.Pillai, Bhawanpreet.Lakha,
bindu.r
From: Sung Lee <sung.lee@amd.com>
[Why]
If the system does not have hostvm enabled, disabling it for
DML validation will allow more modes to pass at lower voltage
levels.
[How]
When initializing HostVM save state to hubbub and read back
when populating DML pipes from context.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
index 129f0b62f751..42fbb5e6d505 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
@@ -99,6 +99,8 @@ void dcn21_dchvm_init(struct hubbub *hubbub)
//Poll until HOSTVM_PREFETCH_DONE = 1
REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
+
+ hubbub->riommu_active = true;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index ed3f62535301..1c88d2edd381 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1886,7 +1886,7 @@ static int dcn21_populate_dml_pipes_from_context(
for (i = 0; i < pipe_cnt; i++) {
- pipes[i].pipe.src.hostvm = 1;
+ pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
pipes[i].pipe.src.gpuvm = 1;
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index 5425e92efcb8..d9fd28b34f2a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -157,6 +157,7 @@ struct hubbub_funcs {
struct hubbub {
const struct hubbub_funcs *funcs;
struct dc_context *ctx;
+ bool riommu_active;
};
#endif
--
2.25.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 04/17] drm/amd/display: Handle Unknown Result for SMU Periodic Retraining on DCN2.1
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (2 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 03/17] drm/amd/display: Populate hostvm parameter before DML calculation Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 05/17] drm/amd/display: remove unused dml variables Bindu Ramamurthy
` (12 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Sung Lee, Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Aurabindo.Pillai, Bhawanpreet.Lakha,
bindu.r
From: Sung Lee <sung.lee@amd.com>
[WHY & HOW]
Currently if VBIOSSMC_Result_UnknownCmd is returned as result of smu msg
there is no way to know. Put 1 in param so if 1 is returned, this unknown case is handled.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
.../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index ab2b9c61e565..11a7b583d561 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -247,5 +247,6 @@ int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mg
return rn_vbios_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_IsPeriodicRetrainingDisabled,
- 0);
+ 1); // if PMFW doesn't support this message, assume retraining is disabled
+ // so we only use most optimal watermark if we know retraining is enabled.
}
--
2.25.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 05/17] drm/amd/display: remove unused dml variables
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (3 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 04/17] drm/amd/display: Handle Unknown Result for SMU Periodic Retraining on DCN2.1 Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 06/17] drm/amd/display: fix cursor calculation for 1xnY rotated display groups Bindu Ramamurthy
` (11 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Dmytro Laktyushkin, Eryk.Brol, Sunpeng.Li, Harry.Wentland,
Qingqing.Zhuo, Rodrigo.Siqueira, roman.li, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 2 --
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 --
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 -
3 files changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 162464261205..dd0c3b1780d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -334,7 +334,6 @@ struct _vcs_dpi_display_pipe_dest_params_st {
unsigned int vblank_end;
unsigned int htotal;
unsigned int vtotal;
- unsigned int refresh_rate;
unsigned int vfront_porch;
unsigned int vactive;
unsigned int hactive;
@@ -345,7 +344,6 @@ struct _vcs_dpi_display_pipe_dest_params_st {
unsigned char interlaced;
double pixel_rate_mhz;
unsigned char synchronized_vblank_all_planes;
- unsigned char synchronize_timing_if_single_refresh_rate;
unsigned char otg_inst;
unsigned int odm_combine;
unsigned char use_maximum_vstartup;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 3ae72e379402..c9fbb33f05a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -659,10 +659,8 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
// TODO: ODMCombineEnabled => 2 * DPPPerPlane...actually maybe not since all pipes are specified
// Do we want the dscclk to automatically be halved? Guess not since the value is specified
- mode_lib->vba.SynchronizeTimingsIfSingleRefreshRate = pipes[0].pipe.dest.synchronize_timing_if_single_refresh_rate;
mode_lib->vba.SynchronizedVBlank = pipes[0].pipe.dest.synchronized_vblank_all_planes;
for (k = 1; k < mode_lib->vba.cache_num_pipes; ++k) {
- ASSERT(mode_lib->vba.SynchronizeTimingsIfSingleRefreshRate == pipes[k].pipe.dest.synchronize_timing_if_single_refresh_rate);
ASSERT(mode_lib->vba.SynchronizedVBlank == pipes[k].pipe.dest.synchronized_vblank_all_planes);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 4d4ed1287673..3529fedc4c52 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -921,7 +921,6 @@ struct vba_vars_st {
bool UseMinimumRequiredDCFCLK;
bool ClampMinDCFCLK;
bool AllowDramClockChangeOneDisplayVactive;
- bool SynchronizeTimingsIfSingleRefreshRate;
};
--
2.25.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 06/17] drm/amd/display: fix cursor calculation for 1xnY rotated display groups
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (4 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 05/17] drm/amd/display: remove unused dml variables Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 07/17] drm/amd/display: minor restructuring of pbn calculation functions Bindu Ramamurthy
` (10 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Samson Tam, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Samson Tam <Samson.Tam@amd.com>
[Why]
Cursor is missing on displays 2 and up when doing rotated
display groups in 1xnY setup. Calculation puts cursor
out of bounds so it is not enabled.
[How]
In dcn10_set_cursor_position(), add in viewport.y into cursor
calculations for 1xnY rotated display groups.
For pipe split, check viewport.y for both pipes and use lower one
to normalize cursor position before calculations.
Add odm 2:1 support ( using same calculations as pipe split ).
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 64 +++++++++++++++++--
1 file changed, 58 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 8eb88a50af51..1e18f0bb40b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3279,6 +3279,8 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
};
bool pipe_split_on = (pipe_ctx->top_pipe != NULL) ||
(pipe_ctx->bottom_pipe != NULL);
+ bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) ||
+ (pipe_ctx->prev_odm_pipe != NULL);
int x_plane = pipe_ctx->plane_state->dst_rect.x;
int y_plane = pipe_ctx->plane_state->dst_rect.y;
@@ -3362,16 +3364,56 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
uint32_t temp_y = pos_cpy.y;
int viewport_height =
pipe_ctx->plane_res.scl_data.viewport.height;
-
- if (pipe_split_on) {
+ int viewport_y =
+ pipe_ctx->plane_res.scl_data.viewport.y;
+
+ /**
+ * Display groups that are 1xnY, have pos_cpy.x > 2 * viewport.height
+ * For pipe split cases:
+ * - apply offset of viewport.y to normalize pos_cpy.x
+ * - calculate the pos_cpy.y as before
+ * - shift pos_cpy.y back by same offset to get final value
+ * - since we iterate through both pipes, use the lower
+ * viewport.y for offset
+ * For non pipe split cases, use the same calculation for
+ * pos_cpy.y as the 180 degree rotation case below,
+ * but use pos_cpy.x as our input because we are rotating
+ * 270 degrees
+ */
+ if (pipe_split_on || odm_combine_on) {
+ int pos_cpy_x_offset;
+ int other_pipe_viewport_y;
+
+ if (pipe_split_on) {
+ if (pipe_ctx->bottom_pipe) {
+ other_pipe_viewport_y =
+ pipe_ctx->bottom_pipe->plane_res.scl_data.viewport.y;
+ } else {
+ other_pipe_viewport_y =
+ pipe_ctx->top_pipe->plane_res.scl_data.viewport.y;
+ }
+ } else {
+ if (pipe_ctx->next_odm_pipe) {
+ other_pipe_viewport_y =
+ pipe_ctx->next_odm_pipe->plane_res.scl_data.viewport.y;
+ } else {
+ other_pipe_viewport_y =
+ pipe_ctx->prev_odm_pipe->plane_res.scl_data.viewport.y;
+ }
+ }
+ pos_cpy_x_offset = (viewport_y > other_pipe_viewport_y) ?
+ other_pipe_viewport_y : viewport_y;
+ pos_cpy.x -= pos_cpy_x_offset;
if (pos_cpy.x > viewport_height) {
pos_cpy.x = pos_cpy.x - viewport_height;
pos_cpy.y = viewport_height - pos_cpy.x;
} else {
pos_cpy.y = 2 * viewport_height - pos_cpy.x;
}
- } else
- pos_cpy.y = viewport_height - pos_cpy.x;
+ pos_cpy.y += pos_cpy_x_offset;
+ } else {
+ pos_cpy.y = (2 * viewport_y) + viewport_height - pos_cpy.x;
+ }
pos_cpy.x = temp_y;
}
// Mirror horizontally and vertically
@@ -3381,7 +3423,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
int viewport_x =
pipe_ctx->plane_res.scl_data.viewport.x;
- if (pipe_split_on) {
+ if (pipe_split_on || odm_combine_on) {
if (pos_cpy.x >= viewport_width + viewport_x) {
pos_cpy.x = 2 * viewport_width
- pos_cpy.x + 2 * viewport_x;
@@ -3399,7 +3441,17 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
} else {
pos_cpy.x = viewport_width - pos_cpy.x + 2 * viewport_x;
}
- pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;
+
+ /**
+ * Display groups that are 1xnY, have pos_cpy.y > viewport.height
+ * Calculation:
+ * delta_from_bottom = viewport.y + viewport.height - pos_cpy.y
+ * pos_cpy.y_new = viewport.y + delta_from_bottom
+ * Simplify it as:
+ * pos_cpy.y = viewport.y * 2 + viewport.height - pos_cpy.y
+ */
+ pos_cpy.y = (2 * pipe_ctx->plane_res.scl_data.viewport.y) +
+ pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;
}
hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m);
--
2.25.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 07/17] drm/amd/display: minor restructuring of pbn calculation functions
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (5 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 06/17] drm/amd/display: fix cursor calculation for 1xnY rotated display groups Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 08/17] drm/amd/display: Detect dynamic backlight support in eDP sink Bindu Ramamurthy
` (9 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Wenjing Liu, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 858acd3df2bc..165fd2f3c80b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2818,15 +2818,12 @@ static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
return dc_fixpt_div_int(mbytes_per_sec, 54);
}
-static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
+static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
{
- uint64_t kbps;
struct fixed31_32 peak_kbps;
uint32_t numerator;
uint32_t denominator;
- kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
-
/*
* margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
@@ -2846,6 +2843,14 @@ static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
return peak_kbps;
}
+static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
+{
+ uint64_t kbps;
+
+ kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
+ return get_pbn_from_bw_in_kbps(kbps);
+}
+
static void update_mst_stream_alloc_table(
struct dc_link *link,
struct stream_encoder *stream_enc,
@@ -2873,6 +2878,7 @@ static void update_mst_stream_alloc_table(
proposed_table->stream_allocations[i].vcp_id) {
work_table[i] = *dc_alloc;
+ work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
break; /* exit j loop */
}
}
--
2.25.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 08/17] drm/amd/display: Detect dynamic backlight support in eDP sink
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (6 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 07/17] drm/amd/display: minor restructuring of pbn calculation functions Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 09/17] drm/amd/display: Add I2C memory low power support Bindu Ramamurthy
` (8 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Aurabindo.Pillai, Roy Chan,
Bhawanpreet.Lakha, bindu.r
From: Roy Chan <roy.chan@amd.com>
[Why]
Check if the eDP sink supports the dynamic backlight control
[How]
Query the dynamic backlight capability in DPCD (eDP case only)
Signed-off-by: Roy Chan <roy.chan@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +++++++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 6c60c1fdebdc..c9f4f2d3bed6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3740,6 +3740,7 @@ void detect_edp_sink_caps(struct dc_link *link)
uint32_t entry;
uint32_t link_rate_in_khz;
enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
+ uint8_t backlight_adj_cap;
retrieve_link_cap(link);
link->dpcd_caps.edp_supported_link_rates_count = 0;
@@ -3770,6 +3771,12 @@ void detect_edp_sink_caps(struct dc_link *link)
}
link->verified_link_cap = link->reported_link_cap;
+ core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
+ &backlight_adj_cap, sizeof(backlight_adj_cap));
+
+ link->dpcd_caps.dynamic_backlight_capable_edp =
+ (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
+
dc_link_set_default_brightness_aux(link);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 4c57cf099b5e..52e819678ecd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1091,6 +1091,7 @@ struct dpcd_caps {
bool panel_mode_edp;
bool dpcd_display_control_capable;
bool ext_receiver_cap_field_present;
+ bool dynamic_backlight_capable_edp;
union dpcd_fec_capability fec_cap;
struct dpcd_dsc_capabilities dsc_caps;
struct dc_lttpr_caps lttpr_caps;
--
2.25.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 09/17] drm/amd/display: Add I2C memory low power support
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (7 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 08/17] drm/amd/display: Detect dynamic backlight support in eDP sink Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 10/17] drm/amd/display: set dpp dto as per requested clk for lower case Bindu Ramamurthy
` (7 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Aurabindo.Pillai, Jacky Liao,
Bhawanpreet.Lakha, bindu.r
From: Jacky Liao <ziyu.liao@amd.com>
[Why]
The I2C memory blocks should be powered down when they are not in use.
This will reduce power consumption.
[How]
1. Write to I2C_LIGHT_SLEEP_FORCE to put memory in light sleep when
released
2. Added a debug option to allow this behaviour to be turned off
Signed-off-by: Jacky Liao <ziyu.liao@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 12 ++++++++++++
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 16 ++++++++++++++++
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 6 +++---
4 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 52e819678ecd..e282c2211f42 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -419,6 +419,7 @@ struct dc_bw_validation_profile {
union mem_low_power_enable_options {
struct {
+ bool i2c: 1;
bool mpc: 1;
bool optc: 1;
} bits;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 3e34afe8c504..7fbd92fbc63a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -293,6 +293,14 @@ static bool setup_engine(
{
uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
uint32_t reset_length = 0;
+
+ if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {
+ if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL) {
+ REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0);
+ REG_WAIT(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, 0, 0, 5);
+ }
+ }
+
/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
@@ -369,6 +377,10 @@ static void release_engine(
REG_UPDATE_2(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1,
DC_I2C_SW_USE_I2C_REG_REQ, 0);
+ if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {
+ if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL)
+ REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);
+ }
}
struct dce_i2c_hw *acquire_i2c_hw_engine(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
index fb055e6883c0..2309f2bb162c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
@@ -95,6 +95,11 @@ enum {
SR(DC_I2C_DATA),\
SR(MICROSECOND_TIME_BASE_DIV)
+#define I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id)\
+ I2C_HW_ENGINE_COMMON_REG_LIST(id),\
+ SR(DIO_MEM_PWR_CTRL),\
+ SR(DIO_MEM_PWR_STATUS)
+
#define I2C_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -179,6 +184,8 @@ struct dce_i2c_shift {
uint8_t XTAL_REF_DIV;
uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;
uint8_t DC_I2C_REG_RW_CNTL_STATUS;
+ uint8_t I2C_LIGHT_SLEEP_FORCE;
+ uint8_t I2C_MEM_PWR_STATE;
};
struct dce_i2c_mask {
@@ -220,12 +227,19 @@ struct dce_i2c_mask {
uint32_t XTAL_REF_DIV;
uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;
uint32_t DC_I2C_REG_RW_CNTL_STATUS;
+ uint32_t I2C_LIGHT_SLEEP_FORCE;
+ uint32_t I2C_MEM_PWR_STATE;
};
#define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\
I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\
I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh)
+#define I2C_COMMON_MASK_SH_LIST_DCN30(mask_sh)\
+ I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh),\
+ I2C_SF(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh),\
+ I2C_SF(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, mask_sh)
+
struct dce_i2c_registers {
uint32_t SETUP;
uint32_t SPEED;
@@ -239,6 +253,8 @@ struct dce_i2c_registers {
uint32_t DC_I2C_TRANSACTION3;
uint32_t DC_I2C_DATA;
uint32_t MICROSECOND_TIME_BASE_DIV;
+ uint32_t DIO_MEM_PWR_CTRL;
+ uint32_t DIO_MEM_PWR_STATUS;
};
enum dce_i2c_transaction_address_space {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index b379057e669c..eb067034ad45 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -933,7 +933,7 @@ static struct dce_aux *dcn30_aux_engine_create(
return &aux_engine->base;
}
-#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
static const struct dce_i2c_registers i2c_hw_regs[] = {
i2c_inst_regs(1),
@@ -945,11 +945,11 @@ static const struct dce_i2c_registers i2c_hw_regs[] = {
};
static const struct dce_i2c_shift i2c_shifts = {
- I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
+ I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
};
static const struct dce_i2c_mask i2c_masks = {
- I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
+ I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
};
static struct dce_i2c_hw *dcn30_i2c_hw_create(
--
2.25.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 10/17] drm/amd/display: set dpp dto as per requested clk for lower case.
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (8 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 09/17] drm/amd/display: Add I2C memory low power support Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 11/17] drm/amd/display: Add dual edp optimization flag Bindu Ramamurthy
` (6 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Aurabindo.Pillai, Yongqiang Sun,
Bhawanpreet.Lakha, bindu.r
From: Yongqiang Sun <yongqiang.sun@amd.com>
[Why]
Blue screen when PNP with multiple monitor or hotplug external monitor when playing video
due to dpp dto isn't programmed properly.
If lower dpp clock, dpp dto need to be programmed first, and actual dpp clk not avalable yet.
[How]
set dpp dto as per request clk for lower case before dpp clk update, and after dpp clk updated
set dpp dto again with actual dpp clk.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 28 +++++++++++++++----
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 9e3d8af3895f..8d8ee4b9fee1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -104,11 +104,12 @@ void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
}
static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
- struct dc_state *context, bool safe_to_lower)
+ struct dc_state *context, int ref_dpp_clk, bool safe_to_lower)
{
int i;
- clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.actual_dppclk_khz;
+ clk_mgr->dccg->ref_dppclk = ref_dpp_clk;
+
for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
int dpp_inst, dppclk_khz, prev_dppclk_khz;
@@ -200,19 +201,36 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
}
if (dpp_clock_lowered) {
- // increase per DPP DTO before lowering global dppclk
- rn_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+ // increase per DPP DTO before lowering global dppclk with requested dppclk
+ rn_update_clocks_update_dpp_dto(
+ clk_mgr,
+ context,
+ clk_mgr_base->clks.dppclk_khz,
+ safe_to_lower);
+
clk_mgr_base->clks.actual_dppclk_khz =
rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+ //update dpp dto with actual dpp clk.
+ rn_update_clocks_update_dpp_dto(
+ clk_mgr,
+ context,
+ clk_mgr_base->clks.actual_dppclk_khz,
+ safe_to_lower);
+
} else {
// increase global DPPCLK before lowering per DPP DTO
if (update_dppclk || update_dispclk)
clk_mgr_base->clks.actual_dppclk_khz =
rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+
// always update dtos unless clock is lowered and not safe to lower
if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
- rn_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+ rn_update_clocks_update_dpp_dto(
+ clk_mgr,
+ context,
+ clk_mgr_base->clks.actual_dppclk_khz,
+ safe_to_lower);
}
if (update_dispclk &&
--
2.25.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 11/17] drm/amd/display: Add dual edp optimization flag.
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (9 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 10/17] drm/amd/display: set dpp dto as per requested clk for lower case Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 12/17] drm/amd/display: [FW Promotion] Release 0.0.42 Bindu Ramamurthy
` (5 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Aurabindo.Pillai, Yongqiang Sun,
Bhawanpreet.Lakha, bindu.r
From: Yongqiang Sun <yongqiang.sun@amd.com>
[Why & How]
Add a dual edp power optimization flag, so driver will
notify this flag to dmub FW to determine if apply the
power optimization.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 +
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++-
4 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 165fd2f3c80b..f522b664d3c6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2757,6 +2757,7 @@ bool dc_link_setup_psr(struct dc_link *link,
* (Always set for DAL2, did not check ASIC)
*/
psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
+ psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
/* Complete PSR entry before aborting to prevent intermittent
* freezes on certain eDPs
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 86406b42572c..80757a0ea7c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -697,6 +697,7 @@ struct psr_config {
bool psr_frame_capture_indication_req;
unsigned int psr_sdp_transmit_line_num_deadline;
bool allow_smu_optimizations;
+ bool allow_multi_disp_optimizations;
};
union dmcu_psr_level {
@@ -799,6 +800,7 @@ struct psr_context {
*/
unsigned int frame_delay;
bool allow_smu_optimizations;
+ bool allow_multi_disp_optimizations;
};
struct colorspace_transform {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 0d6fe7c29c20..17e84f34ceba 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -261,6 +261,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
// Misc
copy_settings_data->psr_level = psr_context->psr_level.u32all;
copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations;
+ copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations;
copy_settings_data->frame_delay = psr_context->frame_delay;
copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq;
copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline;
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index b0d1347d13f0..9e6a4b4f2f1f 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -612,7 +612,8 @@ struct dmub_cmd_psr_copy_settings_data {
uint8_t smu_optimizations_en;
uint8_t frame_delay;
uint8_t frame_cap_ind;
- uint8_t pad[3];
+ uint8_t pad[2];
+ uint8_t multi_disp_optimizations_en;
uint16_t init_sdp_deadline;
uint16_t pad2;
};
--
2.25.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 12/17] drm/amd/display: [FW Promotion] Release 0.0.42
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (10 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 11/17] drm/amd/display: Add dual edp optimization flag Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 13/17] drm/amd/display: Expose new CRC window property Bindu Ramamurthy
` (4 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Anthony Koo, Eryk.Brol, Sunpeng.Li, Harry.Wentland,
Qingqing.Zhuo, Rodrigo.Siqueira, roman.li, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 9e6a4b4f2f1f..a49641c0f90f 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x821097815
+#define DMUB_FW_VERSION_GIT_HASH 0x52d68b82f
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 41
+#define DMUB_FW_VERSION_REVISION 42
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
--
2.25.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 13/17] drm/amd/display: Expose new CRC window property
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (11 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 12/17] drm/amd/display: [FW Promotion] Release 0.0.42 Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-12-16 22:43 ` Daniel Vetter
2020-11-13 20:56 ` [PATCH 14/17] drm/amd/display: correct data type Bindu Ramamurthy
` (3 subsequent siblings)
16 siblings, 1 reply; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Aurabindo.Pillai, Wayne Lin,
Bhawanpreet.Lakha, bindu.r
From: Wayne Lin <Wayne.Lin@amd.com>
[Why]
Instead of calculating CRC on whole frame, add flexibility to calculate
CRC on specific frame region.
[How]
Add few crc window coordinate properties. By default, CRC is calculated
on whole frame unless user space specifies the CRC calculation window.
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +++++++++++++++++-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 19 +++
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 43 +++++-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 3 +
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +
5 files changed, 201 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 77c06f999040..f81c49f28bc9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -943,6 +943,41 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_
}
#endif
+#ifdef CONFIG_DEBUG_FS
+static int create_crtc_crc_properties(struct amdgpu_display_manager *dm)
+{
+ dm->crc_win_x_start_property =
+ drm_property_create_range(adev_to_drm(dm->adev),
+ DRM_MODE_PROP_ATOMIC,
+ "AMD_CRC_WIN_X_START", 0, U16_MAX);
+ if (!dm->crc_win_x_start_property)
+ return -ENOMEM;
+
+ dm->crc_win_y_start_property =
+ drm_property_create_range(adev_to_drm(dm->adev),
+ DRM_MODE_PROP_ATOMIC,
+ "AMD_CRC_WIN_Y_START", 0, U16_MAX);
+ if (!dm->crc_win_y_start_property)
+ return -ENOMEM;
+
+ dm->crc_win_x_end_property =
+ drm_property_create_range(adev_to_drm(dm->adev),
+ DRM_MODE_PROP_ATOMIC,
+ "AMD_CRC_WIN_X_END", 0, U16_MAX);
+ if (!dm->crc_win_x_end_property)
+ return -ENOMEM;
+
+ dm->crc_win_y_end_property =
+ drm_property_create_range(adev_to_drm(dm->adev),
+ DRM_MODE_PROP_ATOMIC,
+ "AMD_CRC_WIN_Y_END", 0, U16_MAX);
+ if (!dm->crc_win_y_end_property)
+ return -ENOMEM;
+
+ return 0;
+}
+#endif
+
static int amdgpu_dm_init(struct amdgpu_device *adev)
{
struct dc_init_data init_data;
@@ -1084,6 +1119,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
dc_init_callbacks(adev->dm.dc, &init_params);
}
+#endif
+#ifdef CONFIG_DEBUG_FS
+ if (create_crtc_crc_properties(&adev->dm))
+ DRM_ERROR("amdgpu: failed to create crc property.\n");
#endif
if (amdgpu_dm_initialize_drm_device(adev)) {
DRM_ERROR(
@@ -5409,12 +5448,64 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
state->crc_src = cur->crc_src;
state->cm_has_degamma = cur->cm_has_degamma;
state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
-
+#ifdef CONFIG_DEBUG_FS
+ state->crc_window = cur->crc_window;
+#endif
/* TODO Duplicate dc_stream after objects are stream object is flattened */
return &state->base;
}
+#ifdef CONFIG_DEBUG_FS
+int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc,
+ struct drm_crtc_state *crtc_state,
+ struct drm_property *property,
+ uint64_t val)
+{
+ struct drm_device *dev = crtc->dev;
+ struct amdgpu_device *adev = drm_to_adev(dev);
+ struct dm_crtc_state *dm_new_state =
+ to_dm_crtc_state(crtc_state);
+
+ if (property == adev->dm.crc_win_x_start_property)
+ dm_new_state->crc_window.x_start = val;
+ else if (property == adev->dm.crc_win_y_start_property)
+ dm_new_state->crc_window.y_start = val;
+ else if (property == adev->dm.crc_win_x_end_property)
+ dm_new_state->crc_window.x_end = val;
+ else if (property == adev->dm.crc_win_y_end_property)
+ dm_new_state->crc_window.y_end = val;
+ else
+ return -EINVAL;
+
+ return 0;
+}
+
+int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc,
+ const struct drm_crtc_state *state,
+ struct drm_property *property,
+ uint64_t *val)
+{
+ struct drm_device *dev = crtc->dev;
+ struct amdgpu_device *adev = drm_to_adev(dev);
+ struct dm_crtc_state *dm_state =
+ to_dm_crtc_state(state);
+
+ if (property == adev->dm.crc_win_x_start_property)
+ *val = dm_state->crc_window.x_start;
+ else if (property == adev->dm.crc_win_y_start_property)
+ *val = dm_state->crc_window.y_start;
+ else if (property == adev->dm.crc_win_x_end_property)
+ *val = dm_state->crc_window.x_end;
+ else if (property == adev->dm.crc_win_y_end_property)
+ *val = dm_state->crc_window.y_end;
+ else
+ return -EINVAL;
+
+ return 0;
+}
+#endif
+
static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
{
enum dc_irq_source irq_source;
@@ -5481,6 +5572,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
.enable_vblank = dm_enable_vblank,
.disable_vblank = dm_disable_vblank,
.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
+#ifdef CONFIG_DEBUG_FS
+ .atomic_set_property = amdgpu_dm_crtc_atomic_set_property,
+ .atomic_get_property = amdgpu_dm_crtc_atomic_get_property,
+#endif
};
static enum drm_connector_status
@@ -6689,6 +6784,25 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
return 0;
}
+#ifdef CONFIG_DEBUG_FS
+static void attach_crtc_crc_properties(struct amdgpu_display_manager *dm,
+ struct amdgpu_crtc *acrtc)
+{
+ drm_object_attach_property(&acrtc->base.base,
+ dm->crc_win_x_start_property,
+ 0);
+ drm_object_attach_property(&acrtc->base.base,
+ dm->crc_win_y_start_property,
+ 0);
+ drm_object_attach_property(&acrtc->base.base,
+ dm->crc_win_x_end_property,
+ 0);
+ drm_object_attach_property(&acrtc->base.base,
+ dm->crc_win_y_end_property,
+ 0);
+}
+#endif
+
static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
struct drm_plane *plane,
uint32_t crtc_index)
@@ -6736,7 +6850,9 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
true, MAX_COLOR_LUT_ENTRIES);
drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
-
+#ifdef CONFIG_DEBUG_FS
+ attach_crtc_crc_properties(dm, acrtc);
+#endif
return 0;
fail:
@@ -8363,6 +8479,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
*/
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
+ bool configure_crc = false;
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
@@ -8372,21 +8489,30 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
dc_stream_retain(dm_new_crtc_state->stream);
acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
manage_dm_interrupts(adev, acrtc, true);
-
+ }
#ifdef CONFIG_DEBUG_FS
+ if (new_crtc_state->active &&
+ amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
/**
* Frontend may have changed so reapply the CRC capture
* settings for the stream.
*/
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+ dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
- if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
- amdgpu_dm_crtc_configure_crc_source(
- crtc, dm_new_crtc_state,
- dm_new_crtc_state->crc_src);
+ if (amdgpu_dm_crc_window_is_default(dm_new_crtc_state)) {
+ if (!old_crtc_state->active || drm_atomic_crtc_needs_modeset(new_crtc_state))
+ configure_crc = true;
+ } else {
+ if (amdgpu_dm_crc_window_changed(dm_new_crtc_state, dm_old_crtc_state))
+ configure_crc = true;
}
-#endif
+
+ if (configure_crc)
+ amdgpu_dm_crtc_configure_crc_source(
+ crtc, dm_new_crtc_state, dm_new_crtc_state->crc_src);
}
+#endif
}
for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 963a69877455..f2aebbe4d140 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -336,6 +336,13 @@ struct amdgpu_display_manager {
*/
const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
+#ifdef CONFIG_DEBUG_FS
+ /* set the crc calculation window*/
+ struct drm_property *crc_win_x_start_property;
+ struct drm_property *crc_win_y_start_property;
+ struct drm_property *crc_win_x_end_property;
+ struct drm_property *crc_win_y_end_property;
+#endif
/**
* @mst_encoders:
*
@@ -422,6 +429,15 @@ struct dm_plane_state {
struct dc_plane_state *dc_state;
};
+#ifdef CONFIG_DEBUG_FS
+struct crc_rec {
+ uint16_t x_start;
+ uint16_t y_start;
+ uint16_t x_end;
+ uint16_t y_end;
+ };
+#endif
+
struct dm_crtc_state {
struct drm_crtc_state base;
struct dc_stream_state *stream;
@@ -444,6 +460,9 @@ struct dm_crtc_state {
struct dc_info_packet vrr_infopacket;
int abm_level;
+#ifdef CONFIG_DEBUG_FS
+ struct crc_rec crc_window;
+#endif
};
#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index c29dc11619f7..ff6db26626ea 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -81,6 +81,33 @@ const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
return pipe_crc_sources;
}
+bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state)
+{
+ bool ret = true;
+
+ if ((dm_crtc_state->crc_window.x_start != 0) ||
+ (dm_crtc_state->crc_window.y_start != 0) ||
+ (dm_crtc_state->crc_window.x_end != 0) ||
+ (dm_crtc_state->crc_window.y_end != 0))
+ ret = false;
+
+ return ret;
+}
+
+bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
+ struct dm_crtc_state *dm_old_crtc_state)
+{
+ bool ret = false;
+
+ if ((dm_new_crtc_state->crc_window.x_start != dm_old_crtc_state->crc_window.x_start) ||
+ (dm_new_crtc_state->crc_window.y_start != dm_old_crtc_state->crc_window.y_start) ||
+ (dm_new_crtc_state->crc_window.x_end != dm_old_crtc_state->crc_window.x_end) ||
+ (dm_new_crtc_state->crc_window.y_end != dm_old_crtc_state->crc_window.y_end))
+ ret = true;
+
+ return ret;
+}
+
int
amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
size_t *values_cnt)
@@ -105,6 +132,7 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
struct dc_stream_state *stream_state = dm_crtc_state->stream;
bool enable = amdgpu_dm_is_valid_crc_source(source);
int ret = 0;
+ struct crc_params *crc_window = NULL, tmp_window;
/* Configuration will be deferred to stream enable. */
if (!stream_state)
@@ -114,8 +142,21 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
/* Enable CRTC CRC generation if necessary. */
if (dm_is_crc_source_crtc(source)) {
+ if (!amdgpu_dm_crc_window_is_default(dm_crtc_state)) {
+ crc_window = &tmp_window;
+
+ tmp_window.windowa_x_start = dm_crtc_state->crc_window.x_start;
+ tmp_window.windowa_y_start = dm_crtc_state->crc_window.y_start;
+ tmp_window.windowa_x_end = dm_crtc_state->crc_window.x_end;
+ tmp_window.windowa_y_end = dm_crtc_state->crc_window.y_end;
+ tmp_window.windowb_x_start = dm_crtc_state->crc_window.x_start;
+ tmp_window.windowb_y_start = dm_crtc_state->crc_window.y_start;
+ tmp_window.windowb_x_end = dm_crtc_state->crc_window.x_end;
+ tmp_window.windowb_y_end = dm_crtc_state->crc_window.y_end;
+ }
+
if (!dc_stream_configure_crc(stream_state->ctx->dc,
- stream_state, NULL, enable, enable)) {
+ stream_state, crc_window, enable, enable)) {
ret = -EINVAL;
goto unlock;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
index f7d731797d3f..0235bfb246e5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
@@ -47,6 +47,9 @@ static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source
/* amdgpu_dm_crc.c */
#ifdef CONFIG_DEBUG_FS
+bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state);
+bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
+ struct dm_crtc_state *dm_old_crtc_state);
int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
struct dm_crtc_state *dm_crtc_state,
enum amdgpu_dm_pipe_crc_source source);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index f522b664d3c6..5790affc7d61 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3259,6 +3259,9 @@ void core_link_enable_stream(
}
}
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#endif
+
dc->hwss.enable_audio_stream(pipe_ctx);
/* turn off otg test pattern if enable */
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 13/17] drm/amd/display: Expose new CRC window property
2020-11-13 20:56 ` [PATCH 13/17] drm/amd/display: Expose new CRC window property Bindu Ramamurthy
@ 2020-12-16 22:43 ` Daniel Vetter
0 siblings, 0 replies; 20+ messages in thread
From: Daniel Vetter @ 2020-12-16 22:43 UTC (permalink / raw)
To: Bindu Ramamurthy, DRI Development, Dave Airlie
Cc: Eryk.Brol, Sunpeng.Li, Bhawanpreet.Lakha, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, amd-gfx, Aurabindo.Pillai, Wayne Lin
On Fri, Nov 13, 2020 at 03:56:41PM -0500, Bindu Ramamurthy wrote:
> From: Wayne Lin <Wayne.Lin@amd.com>
>
> [Why]
> Instead of calculating CRC on whole frame, add flexibility to calculate
> CRC on specific frame region.
>
> [How]
> Add few crc window coordinate properties. By default, CRC is calculated
> on whole frame unless user space specifies the CRC calculation window.
>
> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
> Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Already pinged Alex on irc, but here also as a mail.
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +++++++++++++++++-
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 19 +++
> .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 43 +++++-
> .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 3 +
> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +
> 5 files changed, 201 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 77c06f999040..f81c49f28bc9 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -943,6 +943,41 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_
> }
> #endif
>
> +#ifdef CONFIG_DEBUG_FS
> +static int create_crtc_crc_properties(struct amdgpu_display_manager *dm)
Yes it's behind a #ifdef but a) most distros enable this anyway and b)
it's still a KMS property, so still uapi, i.e.
- should be discussed on dri-devel
- needs igt testcases and stuff
- and real userspace
Drivers adding random kms properties has brought us into a pretty giant
mess, we need to stop this. That's why we've increased merge criteria for
these to include an igt and have at least some hopes of a cross-driver
standard. Also the crc interface is all in debugfs, that's where this
belongs.
Please fix this before we ship it. Ideally we'd make this a standard part
so it can be used in igt testcase, but quick fix would be to either revert
or at least move into debugfs files (we have per-crtc files, so not hard
to pull off).
If this is for functional safety or whatever the IVI standard for that
was, then it needs real uapi treatment.
Thanks, Daniel
> +{
> + dm->crc_win_x_start_property =
> + drm_property_create_range(adev_to_drm(dm->adev),
> + DRM_MODE_PROP_ATOMIC,
> + "AMD_CRC_WIN_X_START", 0, U16_MAX);
> + if (!dm->crc_win_x_start_property)
> + return -ENOMEM;
> +
> + dm->crc_win_y_start_property =
> + drm_property_create_range(adev_to_drm(dm->adev),
> + DRM_MODE_PROP_ATOMIC,
> + "AMD_CRC_WIN_Y_START", 0, U16_MAX);
> + if (!dm->crc_win_y_start_property)
> + return -ENOMEM;
> +
> + dm->crc_win_x_end_property =
> + drm_property_create_range(adev_to_drm(dm->adev),
> + DRM_MODE_PROP_ATOMIC,
> + "AMD_CRC_WIN_X_END", 0, U16_MAX);
> + if (!dm->crc_win_x_end_property)
> + return -ENOMEM;
> +
> + dm->crc_win_y_end_property =
> + drm_property_create_range(adev_to_drm(dm->adev),
> + DRM_MODE_PROP_ATOMIC,
> + "AMD_CRC_WIN_Y_END", 0, U16_MAX);
> + if (!dm->crc_win_y_end_property)
> + return -ENOMEM;
> +
> + return 0;
> +}
> +#endif
> +
> static int amdgpu_dm_init(struct amdgpu_device *adev)
> {
> struct dc_init_data init_data;
> @@ -1084,6 +1119,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
>
> dc_init_callbacks(adev->dm.dc, &init_params);
> }
> +#endif
> +#ifdef CONFIG_DEBUG_FS
> + if (create_crtc_crc_properties(&adev->dm))
> + DRM_ERROR("amdgpu: failed to create crc property.\n");
> #endif
> if (amdgpu_dm_initialize_drm_device(adev)) {
> DRM_ERROR(
> @@ -5409,12 +5448,64 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
> state->crc_src = cur->crc_src;
> state->cm_has_degamma = cur->cm_has_degamma;
> state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
> -
> +#ifdef CONFIG_DEBUG_FS
> + state->crc_window = cur->crc_window;
> +#endif
> /* TODO Duplicate dc_stream after objects are stream object is flattened */
>
> return &state->base;
> }
>
> +#ifdef CONFIG_DEBUG_FS
> +int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc,
> + struct drm_crtc_state *crtc_state,
> + struct drm_property *property,
> + uint64_t val)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct amdgpu_device *adev = drm_to_adev(dev);
> + struct dm_crtc_state *dm_new_state =
> + to_dm_crtc_state(crtc_state);
> +
> + if (property == adev->dm.crc_win_x_start_property)
> + dm_new_state->crc_window.x_start = val;
> + else if (property == adev->dm.crc_win_y_start_property)
> + dm_new_state->crc_window.y_start = val;
> + else if (property == adev->dm.crc_win_x_end_property)
> + dm_new_state->crc_window.x_end = val;
> + else if (property == adev->dm.crc_win_y_end_property)
> + dm_new_state->crc_window.y_end = val;
> + else
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc,
> + const struct drm_crtc_state *state,
> + struct drm_property *property,
> + uint64_t *val)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct amdgpu_device *adev = drm_to_adev(dev);
> + struct dm_crtc_state *dm_state =
> + to_dm_crtc_state(state);
> +
> + if (property == adev->dm.crc_win_x_start_property)
> + *val = dm_state->crc_window.x_start;
> + else if (property == adev->dm.crc_win_y_start_property)
> + *val = dm_state->crc_window.y_start;
> + else if (property == adev->dm.crc_win_x_end_property)
> + *val = dm_state->crc_window.x_end;
> + else if (property == adev->dm.crc_win_y_end_property)
> + *val = dm_state->crc_window.y_end;
> + else
> + return -EINVAL;
> +
> + return 0;
> +}
> +#endif
> +
> static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
> {
> enum dc_irq_source irq_source;
> @@ -5481,6 +5572,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
> .enable_vblank = dm_enable_vblank,
> .disable_vblank = dm_disable_vblank,
> .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
> +#ifdef CONFIG_DEBUG_FS
> + .atomic_set_property = amdgpu_dm_crtc_atomic_set_property,
> + .atomic_get_property = amdgpu_dm_crtc_atomic_get_property,
> +#endif
> };
>
> static enum drm_connector_status
> @@ -6689,6 +6784,25 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
> return 0;
> }
>
> +#ifdef CONFIG_DEBUG_FS
> +static void attach_crtc_crc_properties(struct amdgpu_display_manager *dm,
> + struct amdgpu_crtc *acrtc)
> +{
> + drm_object_attach_property(&acrtc->base.base,
> + dm->crc_win_x_start_property,
> + 0);
> + drm_object_attach_property(&acrtc->base.base,
> + dm->crc_win_y_start_property,
> + 0);
> + drm_object_attach_property(&acrtc->base.base,
> + dm->crc_win_x_end_property,
> + 0);
> + drm_object_attach_property(&acrtc->base.base,
> + dm->crc_win_y_end_property,
> + 0);
> +}
> +#endif
> +
> static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
> struct drm_plane *plane,
> uint32_t crtc_index)
> @@ -6736,7 +6850,9 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
> drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
> true, MAX_COLOR_LUT_ENTRIES);
> drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
> -
> +#ifdef CONFIG_DEBUG_FS
> + attach_crtc_crc_properties(dm, acrtc);
> +#endif
> return 0;
>
> fail:
> @@ -8363,6 +8479,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
> */
> for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
> + bool configure_crc = false;
>
> dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
>
> @@ -8372,21 +8489,30 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
> dc_stream_retain(dm_new_crtc_state->stream);
> acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
> manage_dm_interrupts(adev, acrtc, true);
> -
> + }
> #ifdef CONFIG_DEBUG_FS
> + if (new_crtc_state->active &&
> + amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
> /**
> * Frontend may have changed so reapply the CRC capture
> * settings for the stream.
> */
> dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
> + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
>
> - if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
> - amdgpu_dm_crtc_configure_crc_source(
> - crtc, dm_new_crtc_state,
> - dm_new_crtc_state->crc_src);
> + if (amdgpu_dm_crc_window_is_default(dm_new_crtc_state)) {
> + if (!old_crtc_state->active || drm_atomic_crtc_needs_modeset(new_crtc_state))
> + configure_crc = true;
> + } else {
> + if (amdgpu_dm_crc_window_changed(dm_new_crtc_state, dm_old_crtc_state))
> + configure_crc = true;
> }
> -#endif
> +
> + if (configure_crc)
> + amdgpu_dm_crtc_configure_crc_source(
> + crtc, dm_new_crtc_state, dm_new_crtc_state->crc_src);
> }
> +#endif
> }
>
> for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> index 963a69877455..f2aebbe4d140 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> @@ -336,6 +336,13 @@ struct amdgpu_display_manager {
> */
> const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
>
> +#ifdef CONFIG_DEBUG_FS
> + /* set the crc calculation window*/
> + struct drm_property *crc_win_x_start_property;
> + struct drm_property *crc_win_y_start_property;
> + struct drm_property *crc_win_x_end_property;
> + struct drm_property *crc_win_y_end_property;
> +#endif
> /**
> * @mst_encoders:
> *
> @@ -422,6 +429,15 @@ struct dm_plane_state {
> struct dc_plane_state *dc_state;
> };
>
> +#ifdef CONFIG_DEBUG_FS
> +struct crc_rec {
> + uint16_t x_start;
> + uint16_t y_start;
> + uint16_t x_end;
> + uint16_t y_end;
> + };
> +#endif
> +
> struct dm_crtc_state {
> struct drm_crtc_state base;
> struct dc_stream_state *stream;
> @@ -444,6 +460,9 @@ struct dm_crtc_state {
> struct dc_info_packet vrr_infopacket;
>
> int abm_level;
> +#ifdef CONFIG_DEBUG_FS
> + struct crc_rec crc_window;
> +#endif
> };
>
> #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
> index c29dc11619f7..ff6db26626ea 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
> @@ -81,6 +81,33 @@ const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
> return pipe_crc_sources;
> }
>
> +bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state)
> +{
> + bool ret = true;
> +
> + if ((dm_crtc_state->crc_window.x_start != 0) ||
> + (dm_crtc_state->crc_window.y_start != 0) ||
> + (dm_crtc_state->crc_window.x_end != 0) ||
> + (dm_crtc_state->crc_window.y_end != 0))
> + ret = false;
> +
> + return ret;
> +}
> +
> +bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
> + struct dm_crtc_state *dm_old_crtc_state)
> +{
> + bool ret = false;
> +
> + if ((dm_new_crtc_state->crc_window.x_start != dm_old_crtc_state->crc_window.x_start) ||
> + (dm_new_crtc_state->crc_window.y_start != dm_old_crtc_state->crc_window.y_start) ||
> + (dm_new_crtc_state->crc_window.x_end != dm_old_crtc_state->crc_window.x_end) ||
> + (dm_new_crtc_state->crc_window.y_end != dm_old_crtc_state->crc_window.y_end))
> + ret = true;
> +
> + return ret;
> +}
> +
> int
> amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
> size_t *values_cnt)
> @@ -105,6 +132,7 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
> struct dc_stream_state *stream_state = dm_crtc_state->stream;
> bool enable = amdgpu_dm_is_valid_crc_source(source);
> int ret = 0;
> + struct crc_params *crc_window = NULL, tmp_window;
>
> /* Configuration will be deferred to stream enable. */
> if (!stream_state)
> @@ -114,8 +142,21 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
>
> /* Enable CRTC CRC generation if necessary. */
> if (dm_is_crc_source_crtc(source)) {
> + if (!amdgpu_dm_crc_window_is_default(dm_crtc_state)) {
> + crc_window = &tmp_window;
> +
> + tmp_window.windowa_x_start = dm_crtc_state->crc_window.x_start;
> + tmp_window.windowa_y_start = dm_crtc_state->crc_window.y_start;
> + tmp_window.windowa_x_end = dm_crtc_state->crc_window.x_end;
> + tmp_window.windowa_y_end = dm_crtc_state->crc_window.y_end;
> + tmp_window.windowb_x_start = dm_crtc_state->crc_window.x_start;
> + tmp_window.windowb_y_start = dm_crtc_state->crc_window.y_start;
> + tmp_window.windowb_x_end = dm_crtc_state->crc_window.x_end;
> + tmp_window.windowb_y_end = dm_crtc_state->crc_window.y_end;
> + }
> +
> if (!dc_stream_configure_crc(stream_state->ctx->dc,
> - stream_state, NULL, enable, enable)) {
> + stream_state, crc_window, enable, enable)) {
> ret = -EINVAL;
> goto unlock;
> }
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
> index f7d731797d3f..0235bfb246e5 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
> @@ -47,6 +47,9 @@ static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source
>
> /* amdgpu_dm_crc.c */
> #ifdef CONFIG_DEBUG_FS
> +bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state);
> +bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
> + struct dm_crtc_state *dm_old_crtc_state);
> int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
> struct dm_crtc_state *dm_crtc_state,
> enum amdgpu_dm_pipe_crc_source source);
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index f522b664d3c6..5790affc7d61 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -3259,6 +3259,9 @@ void core_link_enable_stream(
> }
> }
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
> +#endif
> +
> dc->hwss.enable_audio_stream(pipe_ctx);
>
> /* turn off otg test pattern if enable */
> --
> 2.25.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 13/17] drm/amd/display: Expose new CRC window property
@ 2020-12-16 22:43 ` Daniel Vetter
0 siblings, 0 replies; 20+ messages in thread
From: Daniel Vetter @ 2020-12-16 22:43 UTC (permalink / raw)
To: Bindu Ramamurthy, DRI Development, Dave Airlie
Cc: Eryk.Brol, Sunpeng.Li, Bhawanpreet.Lakha, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, amd-gfx, Aurabindo.Pillai, Wayne Lin,
Harry.Wentland
On Fri, Nov 13, 2020 at 03:56:41PM -0500, Bindu Ramamurthy wrote:
> From: Wayne Lin <Wayne.Lin@amd.com>
>
> [Why]
> Instead of calculating CRC on whole frame, add flexibility to calculate
> CRC on specific frame region.
>
> [How]
> Add few crc window coordinate properties. By default, CRC is calculated
> on whole frame unless user space specifies the CRC calculation window.
>
> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
> Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Already pinged Alex on irc, but here also as a mail.
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +++++++++++++++++-
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 19 +++
> .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 43 +++++-
> .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 3 +
> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +
> 5 files changed, 201 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 77c06f999040..f81c49f28bc9 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -943,6 +943,41 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_
> }
> #endif
>
> +#ifdef CONFIG_DEBUG_FS
> +static int create_crtc_crc_properties(struct amdgpu_display_manager *dm)
Yes it's behind a #ifdef but a) most distros enable this anyway and b)
it's still a KMS property, so still uapi, i.e.
- should be discussed on dri-devel
- needs igt testcases and stuff
- and real userspace
Drivers adding random kms properties has brought us into a pretty giant
mess, we need to stop this. That's why we've increased merge criteria for
these to include an igt and have at least some hopes of a cross-driver
standard. Also the crc interface is all in debugfs, that's where this
belongs.
Please fix this before we ship it. Ideally we'd make this a standard part
so it can be used in igt testcase, but quick fix would be to either revert
or at least move into debugfs files (we have per-crtc files, so not hard
to pull off).
If this is for functional safety or whatever the IVI standard for that
was, then it needs real uapi treatment.
Thanks, Daniel
> +{
> + dm->crc_win_x_start_property =
> + drm_property_create_range(adev_to_drm(dm->adev),
> + DRM_MODE_PROP_ATOMIC,
> + "AMD_CRC_WIN_X_START", 0, U16_MAX);
> + if (!dm->crc_win_x_start_property)
> + return -ENOMEM;
> +
> + dm->crc_win_y_start_property =
> + drm_property_create_range(adev_to_drm(dm->adev),
> + DRM_MODE_PROP_ATOMIC,
> + "AMD_CRC_WIN_Y_START", 0, U16_MAX);
> + if (!dm->crc_win_y_start_property)
> + return -ENOMEM;
> +
> + dm->crc_win_x_end_property =
> + drm_property_create_range(adev_to_drm(dm->adev),
> + DRM_MODE_PROP_ATOMIC,
> + "AMD_CRC_WIN_X_END", 0, U16_MAX);
> + if (!dm->crc_win_x_end_property)
> + return -ENOMEM;
> +
> + dm->crc_win_y_end_property =
> + drm_property_create_range(adev_to_drm(dm->adev),
> + DRM_MODE_PROP_ATOMIC,
> + "AMD_CRC_WIN_Y_END", 0, U16_MAX);
> + if (!dm->crc_win_y_end_property)
> + return -ENOMEM;
> +
> + return 0;
> +}
> +#endif
> +
> static int amdgpu_dm_init(struct amdgpu_device *adev)
> {
> struct dc_init_data init_data;
> @@ -1084,6 +1119,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
>
> dc_init_callbacks(adev->dm.dc, &init_params);
> }
> +#endif
> +#ifdef CONFIG_DEBUG_FS
> + if (create_crtc_crc_properties(&adev->dm))
> + DRM_ERROR("amdgpu: failed to create crc property.\n");
> #endif
> if (amdgpu_dm_initialize_drm_device(adev)) {
> DRM_ERROR(
> @@ -5409,12 +5448,64 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
> state->crc_src = cur->crc_src;
> state->cm_has_degamma = cur->cm_has_degamma;
> state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
> -
> +#ifdef CONFIG_DEBUG_FS
> + state->crc_window = cur->crc_window;
> +#endif
> /* TODO Duplicate dc_stream after objects are stream object is flattened */
>
> return &state->base;
> }
>
> +#ifdef CONFIG_DEBUG_FS
> +int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc,
> + struct drm_crtc_state *crtc_state,
> + struct drm_property *property,
> + uint64_t val)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct amdgpu_device *adev = drm_to_adev(dev);
> + struct dm_crtc_state *dm_new_state =
> + to_dm_crtc_state(crtc_state);
> +
> + if (property == adev->dm.crc_win_x_start_property)
> + dm_new_state->crc_window.x_start = val;
> + else if (property == adev->dm.crc_win_y_start_property)
> + dm_new_state->crc_window.y_start = val;
> + else if (property == adev->dm.crc_win_x_end_property)
> + dm_new_state->crc_window.x_end = val;
> + else if (property == adev->dm.crc_win_y_end_property)
> + dm_new_state->crc_window.y_end = val;
> + else
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc,
> + const struct drm_crtc_state *state,
> + struct drm_property *property,
> + uint64_t *val)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct amdgpu_device *adev = drm_to_adev(dev);
> + struct dm_crtc_state *dm_state =
> + to_dm_crtc_state(state);
> +
> + if (property == adev->dm.crc_win_x_start_property)
> + *val = dm_state->crc_window.x_start;
> + else if (property == adev->dm.crc_win_y_start_property)
> + *val = dm_state->crc_window.y_start;
> + else if (property == adev->dm.crc_win_x_end_property)
> + *val = dm_state->crc_window.x_end;
> + else if (property == adev->dm.crc_win_y_end_property)
> + *val = dm_state->crc_window.y_end;
> + else
> + return -EINVAL;
> +
> + return 0;
> +}
> +#endif
> +
> static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
> {
> enum dc_irq_source irq_source;
> @@ -5481,6 +5572,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
> .enable_vblank = dm_enable_vblank,
> .disable_vblank = dm_disable_vblank,
> .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
> +#ifdef CONFIG_DEBUG_FS
> + .atomic_set_property = amdgpu_dm_crtc_atomic_set_property,
> + .atomic_get_property = amdgpu_dm_crtc_atomic_get_property,
> +#endif
> };
>
> static enum drm_connector_status
> @@ -6689,6 +6784,25 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
> return 0;
> }
>
> +#ifdef CONFIG_DEBUG_FS
> +static void attach_crtc_crc_properties(struct amdgpu_display_manager *dm,
> + struct amdgpu_crtc *acrtc)
> +{
> + drm_object_attach_property(&acrtc->base.base,
> + dm->crc_win_x_start_property,
> + 0);
> + drm_object_attach_property(&acrtc->base.base,
> + dm->crc_win_y_start_property,
> + 0);
> + drm_object_attach_property(&acrtc->base.base,
> + dm->crc_win_x_end_property,
> + 0);
> + drm_object_attach_property(&acrtc->base.base,
> + dm->crc_win_y_end_property,
> + 0);
> +}
> +#endif
> +
> static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
> struct drm_plane *plane,
> uint32_t crtc_index)
> @@ -6736,7 +6850,9 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
> drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
> true, MAX_COLOR_LUT_ENTRIES);
> drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
> -
> +#ifdef CONFIG_DEBUG_FS
> + attach_crtc_crc_properties(dm, acrtc);
> +#endif
> return 0;
>
> fail:
> @@ -8363,6 +8479,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
> */
> for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
> + bool configure_crc = false;
>
> dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
>
> @@ -8372,21 +8489,30 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
> dc_stream_retain(dm_new_crtc_state->stream);
> acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
> manage_dm_interrupts(adev, acrtc, true);
> -
> + }
> #ifdef CONFIG_DEBUG_FS
> + if (new_crtc_state->active &&
> + amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
> /**
> * Frontend may have changed so reapply the CRC capture
> * settings for the stream.
> */
> dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
> + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
>
> - if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
> - amdgpu_dm_crtc_configure_crc_source(
> - crtc, dm_new_crtc_state,
> - dm_new_crtc_state->crc_src);
> + if (amdgpu_dm_crc_window_is_default(dm_new_crtc_state)) {
> + if (!old_crtc_state->active || drm_atomic_crtc_needs_modeset(new_crtc_state))
> + configure_crc = true;
> + } else {
> + if (amdgpu_dm_crc_window_changed(dm_new_crtc_state, dm_old_crtc_state))
> + configure_crc = true;
> }
> -#endif
> +
> + if (configure_crc)
> + amdgpu_dm_crtc_configure_crc_source(
> + crtc, dm_new_crtc_state, dm_new_crtc_state->crc_src);
> }
> +#endif
> }
>
> for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> index 963a69877455..f2aebbe4d140 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> @@ -336,6 +336,13 @@ struct amdgpu_display_manager {
> */
> const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
>
> +#ifdef CONFIG_DEBUG_FS
> + /* set the crc calculation window*/
> + struct drm_property *crc_win_x_start_property;
> + struct drm_property *crc_win_y_start_property;
> + struct drm_property *crc_win_x_end_property;
> + struct drm_property *crc_win_y_end_property;
> +#endif
> /**
> * @mst_encoders:
> *
> @@ -422,6 +429,15 @@ struct dm_plane_state {
> struct dc_plane_state *dc_state;
> };
>
> +#ifdef CONFIG_DEBUG_FS
> +struct crc_rec {
> + uint16_t x_start;
> + uint16_t y_start;
> + uint16_t x_end;
> + uint16_t y_end;
> + };
> +#endif
> +
> struct dm_crtc_state {
> struct drm_crtc_state base;
> struct dc_stream_state *stream;
> @@ -444,6 +460,9 @@ struct dm_crtc_state {
> struct dc_info_packet vrr_infopacket;
>
> int abm_level;
> +#ifdef CONFIG_DEBUG_FS
> + struct crc_rec crc_window;
> +#endif
> };
>
> #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
> index c29dc11619f7..ff6db26626ea 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
> @@ -81,6 +81,33 @@ const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
> return pipe_crc_sources;
> }
>
> +bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state)
> +{
> + bool ret = true;
> +
> + if ((dm_crtc_state->crc_window.x_start != 0) ||
> + (dm_crtc_state->crc_window.y_start != 0) ||
> + (dm_crtc_state->crc_window.x_end != 0) ||
> + (dm_crtc_state->crc_window.y_end != 0))
> + ret = false;
> +
> + return ret;
> +}
> +
> +bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
> + struct dm_crtc_state *dm_old_crtc_state)
> +{
> + bool ret = false;
> +
> + if ((dm_new_crtc_state->crc_window.x_start != dm_old_crtc_state->crc_window.x_start) ||
> + (dm_new_crtc_state->crc_window.y_start != dm_old_crtc_state->crc_window.y_start) ||
> + (dm_new_crtc_state->crc_window.x_end != dm_old_crtc_state->crc_window.x_end) ||
> + (dm_new_crtc_state->crc_window.y_end != dm_old_crtc_state->crc_window.y_end))
> + ret = true;
> +
> + return ret;
> +}
> +
> int
> amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
> size_t *values_cnt)
> @@ -105,6 +132,7 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
> struct dc_stream_state *stream_state = dm_crtc_state->stream;
> bool enable = amdgpu_dm_is_valid_crc_source(source);
> int ret = 0;
> + struct crc_params *crc_window = NULL, tmp_window;
>
> /* Configuration will be deferred to stream enable. */
> if (!stream_state)
> @@ -114,8 +142,21 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
>
> /* Enable CRTC CRC generation if necessary. */
> if (dm_is_crc_source_crtc(source)) {
> + if (!amdgpu_dm_crc_window_is_default(dm_crtc_state)) {
> + crc_window = &tmp_window;
> +
> + tmp_window.windowa_x_start = dm_crtc_state->crc_window.x_start;
> + tmp_window.windowa_y_start = dm_crtc_state->crc_window.y_start;
> + tmp_window.windowa_x_end = dm_crtc_state->crc_window.x_end;
> + tmp_window.windowa_y_end = dm_crtc_state->crc_window.y_end;
> + tmp_window.windowb_x_start = dm_crtc_state->crc_window.x_start;
> + tmp_window.windowb_y_start = dm_crtc_state->crc_window.y_start;
> + tmp_window.windowb_x_end = dm_crtc_state->crc_window.x_end;
> + tmp_window.windowb_y_end = dm_crtc_state->crc_window.y_end;
> + }
> +
> if (!dc_stream_configure_crc(stream_state->ctx->dc,
> - stream_state, NULL, enable, enable)) {
> + stream_state, crc_window, enable, enable)) {
> ret = -EINVAL;
> goto unlock;
> }
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
> index f7d731797d3f..0235bfb246e5 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
> @@ -47,6 +47,9 @@ static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source
>
> /* amdgpu_dm_crc.c */
> #ifdef CONFIG_DEBUG_FS
> +bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state);
> +bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
> + struct dm_crtc_state *dm_old_crtc_state);
> int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
> struct dm_crtc_state *dm_crtc_state,
> enum amdgpu_dm_pipe_crc_source source);
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index f522b664d3c6..5790affc7d61 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -3259,6 +3259,9 @@ void core_link_enable_stream(
> }
> }
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
> +#endif
> +
> dc->hwss.enable_audio_stream(pipe_ctx);
>
> /* turn off otg test pattern if enable */
> --
> 2.25.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 14/17] drm/amd/display: correct data type
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (12 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 13/17] drm/amd/display: Expose new CRC window property Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 15/17] drm/amd/display: 3.2.112 Bindu Ramamurthy
` (2 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Raymond Yang, Sunpeng.Li, Harry.Wentland,
Qingqing.Zhuo, Rodrigo.Siqueira, roman.li, Aurabindo.Pillai,
Bhawanpreet.Lakha, bindu.r
From: Raymond Yang <rayyang@amd.com>
[Why]
We should use int for counting variable
[How]
Change type from bool to uint32_t
Signed-off-by: Raymond Yang <rayyang@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e282c2211f42..96ff556e2567 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -483,7 +483,7 @@ struct dc_debug_options {
bool scl_reset_length10;
bool hdmi20_disable;
bool skip_detection_link_training;
- bool edid_read_retry_times;
+ uint32_t edid_read_retry_times;
bool remove_disconnect_edp;
unsigned int force_odm_combine; //bit vector based on otg inst
#if defined(CONFIG_DRM_AMD_DC_DCN)
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 15/17] drm/amd/display: 3.2.112
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (13 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 14/17] drm/amd/display: correct data type Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 16/17] drm/amd/display: Increase sr enter/exit in rn ddr4 watermark table Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 17/17] drm/amd/display: update vgh bounding box Bindu Ramamurthy
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Aric Cyr, Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Aurabindo.Pillai, Bhawanpreet.Lakha,
bindu.r
From: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 96ff556e2567..443b1f1ad546 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -42,7 +42,7 @@
#include "inc/hw/dmcu.h"
#include "dml/display_mode_lib.h"
-#define DC_VER "3.2.111"
+#define DC_VER "3.2.112"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.25.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 16/17] drm/amd/display: Increase sr enter/exit in rn ddr4 watermark table
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (14 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 15/17] drm/amd/display: 3.2.112 Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 17/17] drm/amd/display: update vgh bounding box Bindu Ramamurthy
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Aurabindo.Pillai, Wyatt Wood,
Bhawanpreet.Lakha, bindu.r
From: Wyatt Wood <wyatt.wood@amd.com>
[Why]
After removing added latency for HostVM by default, DDR4 sr exit
latencies were no longer large enough for some panels and caused
underflow.
[How]
Add 1us to sr enter/exit watermark.
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 8d8ee4b9fee1..458dab9e813b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -618,8 +618,8 @@ static struct wm_table ddr4_wm_table = {
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
- .sr_exit_time_us = 6.09,
- .sr_enter_plus_exit_time_us = 7.14,
+ .sr_exit_time_us = 7.09,
+ .sr_enter_plus_exit_time_us = 8.14,
.valid = true,
},
{
--
2.25.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 17/17] drm/amd/display: update vgh bounding box
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
` (15 preceding siblings ...)
2020-11-13 20:56 ` [PATCH 16/17] drm/amd/display: Increase sr enter/exit in rn ddr4 watermark table Bindu Ramamurthy
@ 2020-11-13 20:56 ` Bindu Ramamurthy
16 siblings, 0 replies; 20+ messages in thread
From: Bindu Ramamurthy @ 2020-11-13 20:56 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, roman.li, Aurabindo.Pillai, Yongqiang Sun,
Bhawanpreet.Lakha, bindu.r
From: Yongqiang Sun <yongqiang.sun@amd.com>
[Why & How]
Update bounding box as per spread sheet.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
---
.../amd/display/dc/dcn301/dcn301_resource.c | 60 +++++++++++++++----
1 file changed, 47 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 8824dbce6f4a..0006d805b3b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -164,29 +164,63 @@ struct _vcs_dpi_ip_params_st dcn3_01_ip = {
struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
.clock_limits = {
- /*TODO: fill out defaults once wm plociy is settled*/
{
.state = 0,
- .dcfclk_mhz = 810.0,
- .fabricclk_mhz = 1200.0,
+ .dram_speed_mts = 2400.0,
+ .fabricclk_mhz = 600,
+ .socclk_mhz = 278.0,
+ .dcfclk_mhz = 400.0,
+ .dscclk_mhz = 206.0,
+ .dppclk_mhz = 1015.0,
+ .dispclk_mhz = 1015.0,
+ .phyclk_mhz = 600.0,
+ },
+ {
+ .state = 1,
+ .dram_speed_mts = 2400.0,
+ .fabricclk_mhz = 688,
+ .socclk_mhz = 278.0,
+ .dcfclk_mhz = 400.0,
+ .dscclk_mhz = 206.0,
+ .dppclk_mhz = 1015.0,
.dispclk_mhz = 1015.0,
+ .phyclk_mhz = 600.0,
+ },
+ {
+ .state = 2,
+ .dram_speed_mts = 4267.0,
+ .fabricclk_mhz = 1067,
+ .socclk_mhz = 278.0,
+ .dcfclk_mhz = 608.0,
+ .dscclk_mhz = 296.0,
.dppclk_mhz = 1015.0,
+ .dispclk_mhz = 1015.0,
.phyclk_mhz = 810.0,
- .socclk_mhz = 1000.0,
+ },
+
+ {
+ .state = 3,
+ .dram_speed_mts = 4267.0,
+ .fabricclk_mhz = 1067,
+ .socclk_mhz = 715.0,
+ .dcfclk_mhz = 676.0,
.dscclk_mhz = 338.0,
- .dram_speed_mts = 4266.0,
+ .dppclk_mhz = 1015.0,
+ .dispclk_mhz = 1015.0,
+ .phyclk_mhz = 810.0,
},
+
{
- .state = 1,
+ .state = 4,
+ .dram_speed_mts = 4267.0,
+ .fabricclk_mhz = 1067,
+ .socclk_mhz = 953.0,
.dcfclk_mhz = 810.0,
- .fabricclk_mhz = 1200.0,
- .dispclk_mhz = 1015.0,
+ .dscclk_mhz = 338.0,
.dppclk_mhz = 1015.0,
+ .dispclk_mhz = 1015.0,
.phyclk_mhz = 810.0,
- .socclk_mhz = 1000.0,
- .dscclk_mhz = 338.0,
- .dram_speed_mts = 4266.0,
- }
+ },
},
.sr_exit_time_us = 9.0,
@@ -226,7 +260,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
.xfc_bus_transport_time_us = 20, // ?
.xfc_xbuf_latency_tolerance_us = 4, // ?
.use_urgent_burst_bw = 1, // ?
- .num_states = 2,
+ .num_states = 5,
.do_urgent_latency_adjustment = false,
.urgent_latency_adjustment_fabric_clock_component_us = 0,
.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
--
2.25.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread