[Intel-gfx] [PATCH 0/9] drm/i915: nuke remaining legacy reg helpers (I915_READ/WRITE etc.)

[Intel-gfx] [PATCH 0/9] drm/i915: nuke remaining legacy reg helpers (I915_READ/WRITE etc.)

[Jani Nikula]

To prevent new code with the old helpers being added, nuke the remaining
legacy reg accessors.

BR,
Jani.

Jani Nikula (9):
  drm/i915: remove last users of I915_READ_FW()
  drm/i915: remove last traces of I915_READ_FW() and I915_WRITE_FW()
  drm/i915/cdclk: prefer intel_de_write() over I915_WRITE()
  drm/i915/debugfs: replace I915_READ()+I915_WRITE() with
    intel_uncore_rmw()
  drm/i915/debugfs: replace I915_READ() with intel_uncore_read()
  drm/i915/suspend: replace I915_READ()/WRITE() with
    intel_de_read()/write()
  drm/i915/pm: replace I915_READ()/WRITE() with
    intel_uncore_read()/write()
  drm/i915/irq: replace I915_READ()/WRITE() with
    intel_uncore_read()/write()
  drm/i915: remove last traces of I915_READ(), I915_WRITE() and
    POSTING_READ()

 drivers/gpu/drm/i915/display/intel_cdclk.c |   4 +-
 drivers/gpu/drm/i915/display/intel_dvo.c   |   4 -
 drivers/gpu/drm/i915/i915_debugfs.c        | 230 +++++----
 drivers/gpu/drm/i915/i915_drv.h            |  37 --
 drivers/gpu/drm/i915/i915_irq.c            | 336 ++++++-------
 drivers/gpu/drm/i915/i915_reg.h            |   6 +-
 drivers/gpu/drm/i915/i915_suspend.c        |  33 +-
 drivers/gpu/drm/i915/intel_pm.c            | 552 ++++++++++-----------
 drivers/gpu/drm/i915/intel_sideband.c      |   4 +-
 drivers/gpu/drm/i915/intel_uncore.c        |   4 +-
 drivers/gpu/drm/i915/intel_uncore.h        |   6 +-
 11 files changed, 587 insertions(+), 629 deletions(-)

-- 
2.20.1

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[Intel-gfx] [PATCH 1/9] drm/i915: remove last users of I915_READ_FW()

[Jani Nikula]

Use the preferred intel_uncore_read_fw() instead.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 77e76b665098..7cbca268cb61 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1238,10 +1238,10 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 		u32 rpdown, rpdownei;
 
 		intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
-		rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
-		rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
-		rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
-		rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
+		rpup = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
+		rpupei = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
+		rpdown = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
+		rpdownei = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
 		intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
 
 		seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
-- 
2.20.1

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[Intel-gfx] [PATCH 2/9] drm/i915: remove last traces of I915_READ_FW() and I915_WRITE_FW()

[Jani Nikula]

Good riddance! Remove the macros and their remaining references in
comments.

intel_uncore_read_fw() and intel_uncore_write_fw() should be used
instead.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h     | 29 -----------------------------
 drivers/gpu/drm/i915/intel_uncore.c |  2 +-
 drivers/gpu/drm/i915/intel_uncore.h |  2 +-
 3 files changed, 2 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 15be8debae54..fecb5899cbac 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1978,35 +1978,6 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data,
 
 #define POSTING_READ(reg__)	__I915_REG_OP(posting_read, dev_priv, (reg__))
 
-/* These are untraced mmio-accessors that are only valid to be used inside
- * critical sections, such as inside IRQ handlers, where forcewake is explicitly
- * controlled.
- *
- * Think twice, and think again, before using these.
- *
- * As an example, these accessors can possibly be used between:
- *
- * spin_lock_irq(&dev_priv->uncore.lock);
- * intel_uncore_forcewake_get__locked();
- *
- * and
- *
- * intel_uncore_forcewake_put__locked();
- * spin_unlock_irq(&dev_priv->uncore.lock);
- *
- *
- * Note: some registers may not need forcewake held, so
- * intel_uncore_forcewake_{get,put} can be omitted, see
- * intel_uncore_forcewake_for_reg().
- *
- * Certain architectures will die if the same cacheline is concurrently accessed
- * by different clients (e.g. on Ivybridge). Access to registers should
- * therefore generally be serialised, by either the dev_priv->uncore.lock or
- * a more localised lock guarding all access to that bank of registers.
- */
-#define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
-#define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
-
 /* i915_mm.c */
 int remap_io_mapping(struct vm_area_struct *vma,
 		     unsigned long addr, unsigned long pfn, unsigned long size,
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 1c14a07eba7d..ef40edfff412 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2070,7 +2070,7 @@ int i915_reg_read_ioctl(struct drm_device *dev,
  * This routine waits until the target register @reg contains the expected
  * @value after applying the @mask, i.e. it waits until ::
  *
- *     (I915_READ_FW(reg) & mask) == value
+ *     (intel_uncore_read_fw(uncore, reg) & mask) == value
  *
  * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
  * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index bd2467284295..5dcb7f4183b2 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -216,7 +216,7 @@ void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
 
 /*
  * Like above but the caller must manage the uncore.lock itself.
- * Must be used with I915_READ_FW and friends.
+ * Must be used with intel_uncore_read_fw() and friends.
  */
 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
 					enum forcewake_domains domains);
-- 
2.20.1

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[Intel-gfx] [PATCH 3/9] drm/i915/cdclk: prefer intel_de_write() over I915_WRITE()

[Jani Nikula]

Let's try to not add new ones while we're phasing out I915_READ() and
I915_WRITE().

Fixes: 27a6bc802bd9 ("drm/i915/dg1: Initialize RAWCLK properly")
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c449d28d0560..088d5908176c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2710,8 +2710,8 @@ static int dg1_rawclk(struct drm_i915_private *dev_priv)
 	 * DG1 always uses a 38.4 MHz rawclk.  The bspec tells us
 	 * "Program Numerator=2, Denominator=4, Divider=37 decimal."
 	 */
-	I915_WRITE(PCH_RAWCLK_FREQ,
-		   CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
+	intel_de_write(dev_priv, PCH_RAWCLK_FREQ,
+		       CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
 
 	return 38400;
 }
-- 
2.20.1

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[Intel-gfx] [PATCH 4/9] drm/i915/debugfs: replace I915_READ()+I915_WRITE() with intel_uncore_rmw()

[Jani Nikula]

Remove the last I915_WRITE() use in i915_debugfs.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7cbca268cb61..151734a1a496 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1562,13 +1562,9 @@ i915_cache_sharing_set(void *data, u64 val)
 	drm_dbg(&dev_priv->drm,
 		"Manually setting uncore sharing to %llu\n", val);
 	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
-		u32 snpcr;
-
 		/* Update the cache sharing policy here as well */
-		snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
-		snpcr &= ~GEN6_MBC_SNPCR_MASK;
-		snpcr |= val << GEN6_MBC_SNPCR_SHIFT;
-		I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
+		intel_uncore_rmw(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR,
+				 GEN6_MBC_SNPCR_MASK, val << GEN6_MBC_SNPCR_SHIFT);
 	}
 
 	return 0;
-- 
2.20.1

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[Intel-gfx] [PATCH 5/9] drm/i915/debugfs: replace I915_READ() with intel_uncore_read()

[Jani Nikula]

Another straggler with I915_READ() uses gone.

Arguably some of these should use intel_de_read(), however not
all. Prioritize I915_READ() removal in general over migrating to the
pedantically correct replacement right away.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 214 ++++++++++++++--------------
 1 file changed, 107 insertions(+), 107 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 151734a1a496..a8b0a67250b5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -397,37 +397,37 @@ static void gen8_display_interrupt_info(struct seq_file *m)
 		}
 		seq_printf(m, "Pipe %c IMR:\t%08x\n",
 			   pipe_name(pipe),
-			   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
+			   intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)));
 		seq_printf(m, "Pipe %c IIR:\t%08x\n",
 			   pipe_name(pipe),
-			   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
+			   intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)));
 		seq_printf(m, "Pipe %c IER:\t%08x\n",
 			   pipe_name(pipe),
-			   I915_READ(GEN8_DE_PIPE_IER(pipe)));
+			   intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IER(pipe)));
 
 		intel_display_power_put(dev_priv, power_domain, wakeref);
 	}
 
 	seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
-		   I915_READ(GEN8_DE_PORT_IMR));
+		   intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR));
 	seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
-		   I915_READ(GEN8_DE_PORT_IIR));
+		   intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR));
 	seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
-		   I915_READ(GEN8_DE_PORT_IER));
+		   intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IER));
 
 	seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
-		   I915_READ(GEN8_DE_MISC_IMR));
+		   intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IMR));
 	seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
-		   I915_READ(GEN8_DE_MISC_IIR));
+		   intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR));
 	seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
-		   I915_READ(GEN8_DE_MISC_IER));
+		   intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IER));
 
 	seq_printf(m, "PCU interrupt mask:\t%08x\n",
-		   I915_READ(GEN8_PCU_IMR));
+		   intel_uncore_read(&dev_priv->uncore, GEN8_PCU_IMR));
 	seq_printf(m, "PCU interrupt identity:\t%08x\n",
-		   I915_READ(GEN8_PCU_IIR));
+		   intel_uncore_read(&dev_priv->uncore, GEN8_PCU_IIR));
 	seq_printf(m, "PCU interrupt enable:\t%08x\n",
-		   I915_READ(GEN8_PCU_IER));
+		   intel_uncore_read(&dev_priv->uncore, GEN8_PCU_IER));
 }
 
 static int i915_interrupt_info(struct seq_file *m, void *data)
@@ -443,16 +443,16 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 		intel_wakeref_t pref;
 
 		seq_printf(m, "Master Interrupt Control:\t%08x\n",
-			   I915_READ(GEN8_MASTER_IRQ));
+			   intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ));
 
 		seq_printf(m, "Display IER:\t%08x\n",
-			   I915_READ(VLV_IER));
+			   intel_uncore_read(&dev_priv->uncore, VLV_IER));
 		seq_printf(m, "Display IIR:\t%08x\n",
-			   I915_READ(VLV_IIR));
+			   intel_uncore_read(&dev_priv->uncore, VLV_IIR));
 		seq_printf(m, "Display IIR_RW:\t%08x\n",
-			   I915_READ(VLV_IIR_RW));
+			   intel_uncore_read(&dev_priv->uncore, VLV_IIR_RW));
 		seq_printf(m, "Display IMR:\t%08x\n",
-			   I915_READ(VLV_IMR));
+			   intel_uncore_read(&dev_priv->uncore, VLV_IMR));
 		for_each_pipe(dev_priv, pipe) {
 			enum intel_display_power_domain power_domain;
 
@@ -467,71 +467,71 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 
 			seq_printf(m, "Pipe %c stat:\t%08x\n",
 				   pipe_name(pipe),
-				   I915_READ(PIPESTAT(pipe)));
+				   intel_uncore_read(&dev_priv->uncore, PIPESTAT(pipe)));
 
 			intel_display_power_put(dev_priv, power_domain, pref);
 		}
 
 		pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 		seq_printf(m, "Port hotplug:\t%08x\n",
-			   I915_READ(PORT_HOTPLUG_EN));
+			   intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN));
 		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
-			   I915_READ(VLV_DPFLIPSTAT));
+			   intel_uncore_read(&dev_priv->uncore, VLV_DPFLIPSTAT));
 		seq_printf(m, "DPINVGTT:\t%08x\n",
-			   I915_READ(DPINVGTT));
+			   intel_uncore_read(&dev_priv->uncore, DPINVGTT));
 		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref);
 
 		for (i = 0; i < 4; i++) {
 			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
-				   i, I915_READ(GEN8_GT_IMR(i)));
+				   i, intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(i)));
 			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
-				   i, I915_READ(GEN8_GT_IIR(i)));
+				   i, intel_uncore_read(&dev_priv->uncore, GEN8_GT_IIR(i)));
 			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
-				   i, I915_READ(GEN8_GT_IER(i)));
+				   i, intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(i)));
 		}
 
 		seq_printf(m, "PCU interrupt mask:\t%08x\n",
-			   I915_READ(GEN8_PCU_IMR));
+			   intel_uncore_read(&dev_priv->uncore, GEN8_PCU_IMR));
 		seq_printf(m, "PCU interrupt identity:\t%08x\n",
-			   I915_READ(GEN8_PCU_IIR));
+			   intel_uncore_read(&dev_priv->uncore, GEN8_PCU_IIR));
 		seq_printf(m, "PCU interrupt enable:\t%08x\n",
-			   I915_READ(GEN8_PCU_IER));
+			   intel_uncore_read(&dev_priv->uncore, GEN8_PCU_IER));
 	} else if (INTEL_GEN(dev_priv) >= 11) {
 		if (HAS_MASTER_UNIT_IRQ(dev_priv))
 			seq_printf(m, "Master Unit Interrupt Control:  %08x\n",
-				   I915_READ(DG1_MSTR_UNIT_INTR));
+				   intel_uncore_read(&dev_priv->uncore, DG1_MSTR_UNIT_INTR));
 
 		seq_printf(m, "Master Interrupt Control:  %08x\n",
-			   I915_READ(GEN11_GFX_MSTR_IRQ));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ));
 
 		seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
-			   I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_RENDER_COPY_INTR_ENABLE));
 		seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
-			   I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_VCS_VECS_INTR_ENABLE));
 		seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
-			   I915_READ(GEN11_GUC_SG_INTR_ENABLE));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_GUC_SG_INTR_ENABLE));
 		seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
-			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE));
 		seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
-			   I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE));
 		seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
-			   I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_GUNIT_CSME_INTR_ENABLE));
 
 		seq_printf(m, "Display Interrupt Control:\t%08x\n",
-			   I915_READ(GEN11_DISPLAY_INT_CTL));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL));
 
 		gen8_display_interrupt_info(m);
 	} else if (INTEL_GEN(dev_priv) >= 8) {
 		seq_printf(m, "Master Interrupt Control:\t%08x\n",
-			   I915_READ(GEN8_MASTER_IRQ));
+			   intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ));
 
 		for (i = 0; i < 4; i++) {
 			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
-				   i, I915_READ(GEN8_GT_IMR(i)));
+				   i, intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(i)));
 			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
-				   i, I915_READ(GEN8_GT_IIR(i)));
+				   i, intel_uncore_read(&dev_priv->uncore, GEN8_GT_IIR(i)));
 			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
-				   i, I915_READ(GEN8_GT_IER(i)));
+				   i, intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(i)));
 		}
 
 		gen8_display_interrupt_info(m);
@@ -539,13 +539,13 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 		intel_wakeref_t pref;
 
 		seq_printf(m, "Display IER:\t%08x\n",
-			   I915_READ(VLV_IER));
+			   intel_uncore_read(&dev_priv->uncore, VLV_IER));
 		seq_printf(m, "Display IIR:\t%08x\n",
-			   I915_READ(VLV_IIR));
+			   intel_uncore_read(&dev_priv->uncore, VLV_IIR));
 		seq_printf(m, "Display IIR_RW:\t%08x\n",
-			   I915_READ(VLV_IIR_RW));
+			   intel_uncore_read(&dev_priv->uncore, VLV_IIR_RW));
 		seq_printf(m, "Display IMR:\t%08x\n",
-			   I915_READ(VLV_IMR));
+			   intel_uncore_read(&dev_priv->uncore, VLV_IMR));
 		for_each_pipe(dev_priv, pipe) {
 			enum intel_display_power_domain power_domain;
 
@@ -560,87 +560,87 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 
 			seq_printf(m, "Pipe %c stat:\t%08x\n",
 				   pipe_name(pipe),
-				   I915_READ(PIPESTAT(pipe)));
+				   intel_uncore_read(&dev_priv->uncore, PIPESTAT(pipe)));
 			intel_display_power_put(dev_priv, power_domain, pref);
 		}
 
 		seq_printf(m, "Master IER:\t%08x\n",
-			   I915_READ(VLV_MASTER_IER));
+			   intel_uncore_read(&dev_priv->uncore, VLV_MASTER_IER));
 
 		seq_printf(m, "Render IER:\t%08x\n",
-			   I915_READ(GTIER));
+			   intel_uncore_read(&dev_priv->uncore, GTIER));
 		seq_printf(m, "Render IIR:\t%08x\n",
-			   I915_READ(GTIIR));
+			   intel_uncore_read(&dev_priv->uncore, GTIIR));
 		seq_printf(m, "Render IMR:\t%08x\n",
-			   I915_READ(GTIMR));
+			   intel_uncore_read(&dev_priv->uncore, GTIMR));
 
 		seq_printf(m, "PM IER:\t\t%08x\n",
-			   I915_READ(GEN6_PMIER));
+			   intel_uncore_read(&dev_priv->uncore, GEN6_PMIER));
 		seq_printf(m, "PM IIR:\t\t%08x\n",
-			   I915_READ(GEN6_PMIIR));
+			   intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR));
 		seq_printf(m, "PM IMR:\t\t%08x\n",
-			   I915_READ(GEN6_PMIMR));
+			   intel_uncore_read(&dev_priv->uncore, GEN6_PMIMR));
 
 		pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 		seq_printf(m, "Port hotplug:\t%08x\n",
-			   I915_READ(PORT_HOTPLUG_EN));
+			   intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN));
 		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
-			   I915_READ(VLV_DPFLIPSTAT));
+			   intel_uncore_read(&dev_priv->uncore, VLV_DPFLIPSTAT));
 		seq_printf(m, "DPINVGTT:\t%08x\n",
-			   I915_READ(DPINVGTT));
+			   intel_uncore_read(&dev_priv->uncore, DPINVGTT));
 		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref);
 
 	} else if (!HAS_PCH_SPLIT(dev_priv)) {
 		seq_printf(m, "Interrupt enable:    %08x\n",
-			   I915_READ(GEN2_IER));
+			   intel_uncore_read(&dev_priv->uncore, GEN2_IER));
 		seq_printf(m, "Interrupt identity:  %08x\n",
-			   I915_READ(GEN2_IIR));
+			   intel_uncore_read(&dev_priv->uncore, GEN2_IIR));
 		seq_printf(m, "Interrupt mask:      %08x\n",
-			   I915_READ(GEN2_IMR));
+			   intel_uncore_read(&dev_priv->uncore, GEN2_IMR));
 		for_each_pipe(dev_priv, pipe)
 			seq_printf(m, "Pipe %c stat:         %08x\n",
 				   pipe_name(pipe),
-				   I915_READ(PIPESTAT(pipe)));
+				   intel_uncore_read(&dev_priv->uncore, PIPESTAT(pipe)));
 	} else {
 		seq_printf(m, "North Display Interrupt enable:		%08x\n",
-			   I915_READ(DEIER));
+			   intel_uncore_read(&dev_priv->uncore, DEIER));
 		seq_printf(m, "North Display Interrupt identity:	%08x\n",
-			   I915_READ(DEIIR));
+			   intel_uncore_read(&dev_priv->uncore, DEIIR));
 		seq_printf(m, "North Display Interrupt mask:		%08x\n",
-			   I915_READ(DEIMR));
+			   intel_uncore_read(&dev_priv->uncore, DEIMR));
 		seq_printf(m, "South Display Interrupt enable:		%08x\n",
-			   I915_READ(SDEIER));
+			   intel_uncore_read(&dev_priv->uncore, SDEIER));
 		seq_printf(m, "South Display Interrupt identity:	%08x\n",
-			   I915_READ(SDEIIR));
+			   intel_uncore_read(&dev_priv->uncore, SDEIIR));
 		seq_printf(m, "South Display Interrupt mask:		%08x\n",
-			   I915_READ(SDEIMR));
+			   intel_uncore_read(&dev_priv->uncore, SDEIMR));
 		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
-			   I915_READ(GTIER));
+			   intel_uncore_read(&dev_priv->uncore, GTIER));
 		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
-			   I915_READ(GTIIR));
+			   intel_uncore_read(&dev_priv->uncore, GTIIR));
 		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
-			   I915_READ(GTIMR));
+			   intel_uncore_read(&dev_priv->uncore, GTIMR));
 	}
 
 	if (INTEL_GEN(dev_priv) >= 11) {
 		seq_printf(m, "RCS Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_RCS0_RSVD_INTR_MASK));
 		seq_printf(m, "BCS Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_BCS_RSVD_INTR_MASK));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_BCS_RSVD_INTR_MASK));
 		seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_VCS0_VCS1_INTR_MASK));
 		seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_VCS2_VCS3_INTR_MASK));
 		seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_VECS0_VECS1_INTR_MASK));
 		seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_GUC_SG_INTR_MASK));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_GUC_SG_INTR_MASK));
 		seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
-			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK));
 		seq_printf(m, "Crypto Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_CRYPTO_RSVD_INTR_MASK));
 		seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
+			   intel_uncore_read(&dev_priv->uncore, GEN11_GUNIT_CSME_INTR_MASK));
 
 	} else if (INTEL_GEN(dev_priv) >= 6) {
 		for_each_uabi_engine(engine, dev_priv) {
@@ -802,7 +802,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		u32 rpmodectl, freq_sts;
 
-		rpmodectl = I915_READ(GEN6_RP_CONTROL);
+		rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL);
 		seq_printf(m, "Video Turbo Mode: %s\n",
 			   yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
 		seq_printf(m, "HW control enabled: %s\n",
@@ -847,19 +847,19 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
 		int max_freq;
 
-		rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
+		rp_state_limits = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_LIMITS);
 		if (IS_GEN9_LP(dev_priv)) {
-			rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
-			gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
+			rp_state_cap = intel_uncore_read(&dev_priv->uncore, BXT_RP_STATE_CAP);
+			gt_perf_status = intel_uncore_read(&dev_priv->uncore, BXT_GT_PERF_STATUS);
 		} else {
-			rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
-			gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
+			rp_state_cap = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_CAP);
+			gt_perf_status = intel_uncore_read(&dev_priv->uncore, GEN6_GT_PERF_STATUS);
 		}
 
 		/* RPSTAT1 is in the GT power well */
 		intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
 
-		reqf = I915_READ(GEN6_RPNSWREQ);
+		reqf = intel_uncore_read(&dev_priv->uncore, GEN6_RPNSWREQ);
 		if (INTEL_GEN(dev_priv) >= 9)
 			reqf >>= 23;
 		else {
@@ -871,24 +871,24 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		}
 		reqf = intel_gpu_freq(rps, reqf);
 
-		rpmodectl = I915_READ(GEN6_RP_CONTROL);
-		rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
-		rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
-
-		rpstat = I915_READ(GEN6_RPSTAT1);
-		rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
-		rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
-		rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
-		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
-		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
-		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
+		rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL);
+		rpinclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_UP_THRESHOLD);
+		rpdeclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_DOWN_THRESHOLD);
+
+		rpstat = intel_uncore_read(&dev_priv->uncore, GEN6_RPSTAT1);
+		rpupei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
+		rpcurup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
+		rpprevup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
+		rpdownei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
+		rpcurdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
+		rpprevdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
 		cagf = intel_rps_read_actual_frequency(rps);
 
 		intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
 
 		if (INTEL_GEN(dev_priv) >= 11) {
-			pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
-			pm_imr = I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK);
+			pm_ier = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
+			pm_imr = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
 			/*
 			 * The equivalent to the PM ISR & IIR cannot be read
 			 * without affecting the current state of the system
@@ -896,17 +896,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 			pm_isr = 0;
 			pm_iir = 0;
 		} else if (INTEL_GEN(dev_priv) >= 8) {
-			pm_ier = I915_READ(GEN8_GT_IER(2));
-			pm_imr = I915_READ(GEN8_GT_IMR(2));
-			pm_isr = I915_READ(GEN8_GT_ISR(2));
-			pm_iir = I915_READ(GEN8_GT_IIR(2));
+			pm_ier = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(2));
+			pm_imr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(2));
+			pm_isr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_ISR(2));
+			pm_iir = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IIR(2));
 		} else {
-			pm_ier = I915_READ(GEN6_PMIER);
-			pm_imr = I915_READ(GEN6_PMIMR);
-			pm_isr = I915_READ(GEN6_PMISR);
-			pm_iir = I915_READ(GEN6_PMIIR);
+			pm_ier = intel_uncore_read(&dev_priv->uncore, GEN6_PMIER);
+			pm_imr = intel_uncore_read(&dev_priv->uncore, GEN6_PMIMR);
+			pm_isr = intel_uncore_read(&dev_priv->uncore, GEN6_PMISR);
+			pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
 		}
-		pm_mask = I915_READ(GEN6_PMINTRMSK);
+		pm_mask = intel_uncore_read(&dev_priv->uncore, GEN6_PMINTRMSK);
 
 		seq_printf(m, "Video Turbo Mode: %s\n",
 			   yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
@@ -1540,7 +1540,7 @@ i915_cache_sharing_get(void *data, u64 *val)
 		return -ENODEV;
 
 	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
-		snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
+		snpcr = intel_uncore_read(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR);
 
 	*val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
 
-- 
2.20.1

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[Intel-gfx] [PATCH 6/9] drm/i915/suspend: replace I915_READ()/WRITE() with intel_de_read()/write()

[Jani Nikula]

Another straggler with I915_READ() and I915_WRITE() uses gone.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_suspend.c | 33 +++++++++++++++--------------
 1 file changed, 17 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index db2111fc809e..63212df33c9e 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -24,6 +24,7 @@
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include "display/intel_de.h"
 #include "display/intel_fbc.h"
 #include "display/intel_gmbus.h"
 #include "display/intel_vga.h"
@@ -39,21 +40,21 @@ static void intel_save_swf(struct drm_i915_private *dev_priv)
 	/* Scratch space */
 	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
 		for (i = 0; i < 7; i++) {
-			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
-			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
+			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i));
+			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
 		}
 		for (i = 0; i < 3; i++)
-			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
+			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
 	} else if (IS_GEN(dev_priv, 2)) {
 		for (i = 0; i < 7; i++)
-			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
+			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
 	} else if (HAS_GMCH(dev_priv)) {
 		for (i = 0; i < 16; i++) {
-			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
-			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
+			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i));
+			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
 		}
 		for (i = 0; i < 3; i++)
-			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
+			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
 	}
 }
 
@@ -64,21 +65,21 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv)
 	/* Scratch space */
 	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
 		for (i = 0; i < 7; i++) {
-			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
-			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
+			intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]);
+			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
 		}
 		for (i = 0; i < 3; i++)
-			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
+			intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
 	} else if (IS_GEN(dev_priv, 2)) {
 		for (i = 0; i < 7; i++)
-			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
+			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
 	} else if (HAS_GMCH(dev_priv)) {
 		for (i = 0; i < 16; i++) {
-			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
-			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
+			intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]);
+			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
 		}
 		for (i = 0; i < 3; i++)
-			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
+			intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
 	}
 }
 
@@ -88,7 +89,7 @@ void i915_save_display(struct drm_i915_private *dev_priv)
 
 	/* Display arbitration control */
 	if (INTEL_GEN(dev_priv) <= 4)
-		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
+		dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB);
 
 	if (IS_GEN(dev_priv, 4))
 		pci_read_config_word(pdev, GCDGMBUS,
@@ -109,7 +110,7 @@ void i915_restore_display(struct drm_i915_private *dev_priv)
 
 	/* Display arbitration */
 	if (INTEL_GEN(dev_priv) <= 4)
-		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
+		intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB);
 
 	/* only restore FBC info on the platform that supports FBC*/
 	intel_fbc_global_disable(dev_priv);
-- 
2.20.1

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[Intel-gfx] [PATCH 7/9] drm/i915/pm: replace I915_READ()/WRITE() with intel_uncore_read()/write()

[Jani Nikula]

Arguably some of these should use intel_de_read() or intel_de_write(),
however not all. Prioritize I915_READ() and I915_WRITE() removal in
general over migrating to the pedantically correct replacements right
away.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 552 ++++++++++++++++----------------
 1 file changed, 276 insertions(+), 276 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bbec56f97832..c0ed82665706 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -81,24 +81,24 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 		 * Must match Sampler, Pixel Back End, and Media. See
 		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
 		 */
-		I915_WRITE(CHICKEN_PAR1_1,
-			   I915_READ(CHICKEN_PAR1_1) |
+		intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
+			   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) |
 			   SKL_DE_COMPRESSED_HASH_MODE);
 	}
 
 	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
-	I915_WRITE(CHICKEN_PAR1_1,
-		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
+	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
+		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
 
 	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
-	I915_WRITE(GEN8_CHICKEN_DCPR_1,
-		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
+	intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
+		   intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
 
 	/*
 	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
 	 * Display WA #0859: skl,bxt,kbl,glk,cfl
 	 */
-	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
 		   DISP_FBC_MEMORY_WAKE);
 }
 
@@ -107,21 +107,21 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
 	gen9_init_clock_gating(dev_priv);
 
 	/* WaDisableSDEUnitClockGating:bxt */
-	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
 	/*
 	 * FIXME:
 	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 	 */
-	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
 		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 
 	/*
 	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
 	 * to stay fully on.
 	 */
-	I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
+	intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
 		   PWM1_GATING_DIS | PWM2_GATING_DIS);
 
 	/*
@@ -130,20 +130,20 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
 	 * is off and a MMIO access is attempted by any privilege
 	 * application, using batch buffers or any other means.
 	 */
-	I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950));
+	intel_uncore_write(&dev_priv->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
 
 	/*
 	 * WaFbcTurnOffFbcWatermark:bxt
 	 * Display WA #0562: bxt
 	 */
-	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
 		   DISP_FBC_WM_DIS);
 
 	/*
 	 * WaFbcHighMemBwCorruptionAvoidance:bxt
 	 * Display WA #0883: bxt
 	 */
-	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_DISABLE_DUMMY0);
 }
 
@@ -156,7 +156,7 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
 	 * Backlight PWM may stop in the asserted state, causing backlight
 	 * to stay fully on.
 	 */
-	I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
+	intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
 		   PWM1_GATING_DIS | PWM2_GATING_DIS);
 }
 
@@ -164,7 +164,7 @@ static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
 {
 	u32 tmp;
 
-	tmp = I915_READ(CLKCFG);
+	tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
 
 	switch (tmp & CLKCFG_FSB_MASK) {
 	case CLKCFG_FSB_533:
@@ -194,7 +194,7 @@ static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
 	}
 
 	/* detect pineview DDR3 setting */
-	tmp = I915_READ(CSHRDDR3CTL);
+	tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL);
 	dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 }
 
@@ -365,39 +365,39 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
 	u32 val;
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-		was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
-		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
-		POSTING_READ(FW_BLC_SELF_VLV);
+		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
+		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
+		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF_VLV);
 	} else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
-		was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
-		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
-		POSTING_READ(FW_BLC_SELF);
+		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
+		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
+		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
 	} else if (IS_PINEVIEW(dev_priv)) {
-		val = I915_READ(DSPFW3);
+		val = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 		was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
 		if (enable)
 			val |= PINEVIEW_SELF_REFRESH_EN;
 		else
 			val &= ~PINEVIEW_SELF_REFRESH_EN;
-		I915_WRITE(DSPFW3, val);
-		POSTING_READ(DSPFW3);
+		intel_uncore_write(&dev_priv->uncore, DSPFW3, val);
+		intel_uncore_posting_read(&dev_priv->uncore, DSPFW3);
 	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
-		was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
+		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
 		val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 			       _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
-		I915_WRITE(FW_BLC_SELF, val);
-		POSTING_READ(FW_BLC_SELF);
+		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, val);
+		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
 	} else if (IS_I915GM(dev_priv)) {
 		/*
 		 * FIXME can't find a bit like this for 915G, and
 		 * and yet it does have the related watermark in
 		 * FW_BLC_SELF. What's going on?
 		 */
-		was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
+		was_enabled = intel_uncore_read(&dev_priv->uncore, INSTPM) & INSTPM_SELF_EN;
 		val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 			       _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
-		I915_WRITE(INSTPM, val);
-		POSTING_READ(INSTPM);
+		intel_uncore_write(&dev_priv->uncore, INSTPM, val);
+		intel_uncore_posting_read(&dev_priv->uncore, INSTPM);
 	} else {
 		return false;
 	}
@@ -493,20 +493,20 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 
 	switch (pipe) {
 	case PIPE_A:
-		dsparb = I915_READ(DSPARB);
-		dsparb2 = I915_READ(DSPARB2);
+		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
 		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 		break;
 	case PIPE_B:
-		dsparb = I915_READ(DSPARB);
-		dsparb2 = I915_READ(DSPARB2);
+		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
 		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 		break;
 	case PIPE_C:
-		dsparb2 = I915_READ(DSPARB2);
-		dsparb3 = I915_READ(DSPARB3);
+		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
+		dsparb3 = intel_uncore_read(&dev_priv->uncore, DSPARB3);
 		sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 		sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 		break;
@@ -524,7 +524,7 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
 			      enum i9xx_plane_id i9xx_plane)
 {
-	u32 dsparb = I915_READ(DSPARB);
+	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
 	int size;
 
 	size = dsparb & 0x7f;
@@ -540,7 +540,7 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
 static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
 			      enum i9xx_plane_id i9xx_plane)
 {
-	u32 dsparb = I915_READ(DSPARB);
+	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
 	int size;
 
 	size = dsparb & 0x1ff;
@@ -557,7 +557,7 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
 static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
 			      enum i9xx_plane_id i9xx_plane)
 {
-	u32 dsparb = I915_READ(DSPARB);
+	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
 	int size;
 
 	size = dsparb & 0x7f;
@@ -910,38 +910,38 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
 		wm = intel_calculate_wm(clock, &pnv_display_wm,
 					pnv_display_wm.fifo_size,
 					cpp, latency->display_sr);
-		reg = I915_READ(DSPFW1);
+		reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
 		reg &= ~DSPFW_SR_MASK;
 		reg |= FW_WM(wm, SR);
-		I915_WRITE(DSPFW1, reg);
+		intel_uncore_write(&dev_priv->uncore, DSPFW1, reg);
 		drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
 
 		/* cursor SR */
 		wm = intel_calculate_wm(clock, &pnv_cursor_wm,
 					pnv_display_wm.fifo_size,
 					4, latency->cursor_sr);
-		reg = I915_READ(DSPFW3);
+		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 		reg &= ~DSPFW_CURSOR_SR_MASK;
 		reg |= FW_WM(wm, CURSOR_SR);
-		I915_WRITE(DSPFW3, reg);
+		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
 
 		/* Display HPLL off SR */
 		wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
 					pnv_display_hplloff_wm.fifo_size,
 					cpp, latency->display_hpll_disable);
-		reg = I915_READ(DSPFW3);
+		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 		reg &= ~DSPFW_HPLL_SR_MASK;
 		reg |= FW_WM(wm, HPLL_SR);
-		I915_WRITE(DSPFW3, reg);
+		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
 
 		/* cursor HPLL off SR */
 		wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
 					pnv_display_hplloff_wm.fifo_size,
 					4, latency->cursor_hpll_disable);
-		reg = I915_READ(DSPFW3);
+		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 		reg &= ~DSPFW_HPLL_CURSOR_MASK;
 		reg |= FW_WM(wm, HPLL_CURSOR);
-		I915_WRITE(DSPFW3, reg);
+		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
 		drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
 
 		intel_set_memory_cxsr(dev_priv, true);
@@ -975,25 +975,25 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
 	for_each_pipe(dev_priv, pipe)
 		trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 
-	I915_WRITE(DSPFW1,
+	intel_uncore_write(&dev_priv->uncore, DSPFW1,
 		   FW_WM(wm->sr.plane, SR) |
 		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
-	I915_WRITE(DSPFW2,
+	intel_uncore_write(&dev_priv->uncore, DSPFW2,
 		   (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
 		   FW_WM(wm->sr.fbc, FBC_SR) |
 		   FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
 		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
 		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
-	I915_WRITE(DSPFW3,
+	intel_uncore_write(&dev_priv->uncore, DSPFW3,
 		   (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
 		   FW_WM(wm->sr.cursor, CURSOR_SR) |
 		   FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
 		   FW_WM(wm->hpll.plane, HPLL_SR));
 
-	POSTING_READ(DSPFW1);
+	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
 }
 
 #define FW_WM_VLV(value, plane) \
@@ -1007,7 +1007,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 	for_each_pipe(dev_priv, pipe) {
 		trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 
-		I915_WRITE(VLV_DDL(pipe),
+		intel_uncore_write(&dev_priv->uncore, VLV_DDL(pipe),
 			   (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
 			   (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
 			   (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
@@ -1019,35 +1019,35 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 	 * high order bits so that there are no out of bounds values
 	 * present in the registers during the reprogramming.
 	 */
-	I915_WRITE(DSPHOWM, 0);
-	I915_WRITE(DSPHOWM1, 0);
-	I915_WRITE(DSPFW4, 0);
-	I915_WRITE(DSPFW5, 0);
-	I915_WRITE(DSPFW6, 0);
+	intel_uncore_write(&dev_priv->uncore, DSPHOWM, 0);
+	intel_uncore_write(&dev_priv->uncore, DSPHOWM1, 0);
+	intel_uncore_write(&dev_priv->uncore, DSPFW4, 0);
+	intel_uncore_write(&dev_priv->uncore, DSPFW5, 0);
+	intel_uncore_write(&dev_priv->uncore, DSPFW6, 0);
 
-	I915_WRITE(DSPFW1,
+	intel_uncore_write(&dev_priv->uncore, DSPFW1,
 		   FW_WM(wm->sr.plane, SR) |
 		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 		   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 		   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
-	I915_WRITE(DSPFW2,
+	intel_uncore_write(&dev_priv->uncore, DSPFW2,
 		   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
 		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 		   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
-	I915_WRITE(DSPFW3,
+	intel_uncore_write(&dev_priv->uncore, DSPFW3,
 		   FW_WM(wm->sr.cursor, CURSOR_SR));
 
 	if (IS_CHERRYVIEW(dev_priv)) {
-		I915_WRITE(DSPFW7_CHV,
+		intel_uncore_write(&dev_priv->uncore, DSPFW7_CHV,
 			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
 			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
-		I915_WRITE(DSPFW8_CHV,
+		intel_uncore_write(&dev_priv->uncore, DSPFW8_CHV,
 			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
 			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
-		I915_WRITE(DSPFW9_CHV,
+		intel_uncore_write(&dev_priv->uncore, DSPFW9_CHV,
 			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
 			   FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
-		I915_WRITE(DSPHOWM,
+		intel_uncore_write(&dev_priv->uncore, DSPHOWM,
 			   FW_WM(wm->sr.plane >> 9, SR_HI) |
 			   FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
 			   FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
@@ -1059,10 +1059,10 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
 			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
 	} else {
-		I915_WRITE(DSPFW7,
+		intel_uncore_write(&dev_priv->uncore, DSPFW7,
 			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
 			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
-		I915_WRITE(DSPHOWM,
+		intel_uncore_write(&dev_priv->uncore, DSPHOWM,
 			   FW_WM(wm->sr.plane >> 9, SR_HI) |
 			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
 			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
@@ -1072,7 +1072,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
 	}
 
-	POSTING_READ(DSPFW1);
+	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
 }
 
 #undef FW_WM_VLV
@@ -2309,14 +2309,14 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
 		    srwm);
 
 	/* 965 has limitations... */
-	I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
+	intel_uncore_write(&dev_priv->uncore, DSPFW1, FW_WM(srwm, SR) |
 		   FW_WM(8, CURSORB) |
 		   FW_WM(8, PLANEB) |
 		   FW_WM(8, PLANEA));
-	I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
+	intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) |
 		   FW_WM(8, PLANEC_OLD));
 	/* update cursor SR watermark */
-	I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
+	intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
 
 	if (cxsr_enabled)
 		intel_set_memory_cxsr(dev_priv, true);
@@ -2446,10 +2446,10 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 			srwm = 1;
 
 		if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
-			I915_WRITE(FW_BLC_SELF,
+			intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF,
 				   FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
 		else
-			I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
+			intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, srwm & 0x3f);
 	}
 
 	drm_dbg_kms(&dev_priv->drm,
@@ -2463,8 +2463,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
 	fwater_hi = fwater_hi | (1 << 8);
 
-	I915_WRITE(FW_BLC, fwater_lo);
-	I915_WRITE(FW_BLC2, fwater_hi);
+	intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
+	intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
 
 	if (enabled)
 		intel_set_memory_cxsr(dev_priv, true);
@@ -2487,13 +2487,13 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
 				       &i845_wm_info,
 				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
 				       4, pessimal_latency_ns);
-	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
+	fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
 	fwater_lo |= (3<<8) | planea_wm;
 
 	drm_dbg_kms(&dev_priv->drm,
 		    "Setting FIFO watermarks - A: %d\n", planea_wm);
 
-	I915_WRITE(FW_BLC, fwater_lo);
+	intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
 }
 
 /* latency must be in 0.1us units. */
@@ -3533,17 +3533,17 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
 
 	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
 		previous->wm_lp[2] &= ~WM1_LP_SR_EN;
-		I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
+		intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, previous->wm_lp[2]);
 		changed = true;
 	}
 	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
 		previous->wm_lp[1] &= ~WM1_LP_SR_EN;
-		I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
+		intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, previous->wm_lp[1]);
 		changed = true;
 	}
 	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
 		previous->wm_lp[0] &= ~WM1_LP_SR_EN;
-		I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
+		intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, previous->wm_lp[0]);
 		changed = true;
 	}
 
@@ -3573,56 +3573,56 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
 	_ilk_disable_lp_wm(dev_priv, dirty);
 
 	if (dirty & WM_DIRTY_PIPE(PIPE_A))
-		I915_WRITE(WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
+		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
 	if (dirty & WM_DIRTY_PIPE(PIPE_B))
-		I915_WRITE(WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
+		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
 	if (dirty & WM_DIRTY_PIPE(PIPE_C))
-		I915_WRITE(WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
+		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
 
 	if (dirty & WM_DIRTY_DDB) {
 		if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-			val = I915_READ(WM_MISC);
+			val = intel_uncore_read(&dev_priv->uncore, WM_MISC);
 			if (results->partitioning == INTEL_DDB_PART_1_2)
 				val &= ~WM_MISC_DATA_PARTITION_5_6;
 			else
 				val |= WM_MISC_DATA_PARTITION_5_6;
-			I915_WRITE(WM_MISC, val);
+			intel_uncore_write(&dev_priv->uncore, WM_MISC, val);
 		} else {
-			val = I915_READ(DISP_ARB_CTL2);
+			val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2);
 			if (results->partitioning == INTEL_DDB_PART_1_2)
 				val &= ~DISP_DATA_PARTITION_5_6;
 			else
 				val |= DISP_DATA_PARTITION_5_6;
-			I915_WRITE(DISP_ARB_CTL2, val);
+			intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL2, val);
 		}
 	}
 
 	if (dirty & WM_DIRTY_FBC) {
-		val = I915_READ(DISP_ARB_CTL);
+		val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL);
 		if (results->enable_fbc_wm)
 			val &= ~DISP_FBC_WM_DIS;
 		else
 			val |= DISP_FBC_WM_DIS;
-		I915_WRITE(DISP_ARB_CTL, val);
+		intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, val);
 	}
 
 	if (dirty & WM_DIRTY_LP(1) &&
 	    previous->wm_lp_spr[0] != results->wm_lp_spr[0])
-		I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
+		intel_uncore_write(&dev_priv->uncore, WM1S_LP_ILK, results->wm_lp_spr[0]);
 
 	if (INTEL_GEN(dev_priv) >= 7) {
 		if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
-			I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
+			intel_uncore_write(&dev_priv->uncore, WM2S_LP_IVB, results->wm_lp_spr[1]);
 		if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
-			I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
+			intel_uncore_write(&dev_priv->uncore, WM3S_LP_IVB, results->wm_lp_spr[2]);
 	}
 
 	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
-		I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
+		intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, results->wm_lp[0]);
 	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
-		I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
+		intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, results->wm_lp[1]);
 	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
-		I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
+		intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, results->wm_lp[2]);
 
 	dev_priv->wm.hw = *results;
 }
@@ -3639,7 +3639,7 @@ u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
 	u8 enabled_slices_mask = 0;
 
 	for (i = 0; i < max_slices; i++) {
-		if (I915_READ(DBUF_CTL_S(i)) & DBUF_POWER_STATE)
+		if (intel_uncore_read(&dev_priv->uncore, DBUF_CTL_S(i)) & DBUF_POWER_STATE)
 			enabled_slices_mask |= BIT(i);
 	}
 
@@ -4307,12 +4307,12 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
 
 	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
 	if (plane_id == PLANE_CURSOR) {
-		val = I915_READ(CUR_BUF_CFG(pipe));
+		val = intel_uncore_read(&dev_priv->uncore, CUR_BUF_CFG(pipe));
 		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
 		return;
 	}
 
-	val = I915_READ(PLANE_CTL(pipe, plane_id));
+	val = intel_uncore_read(&dev_priv->uncore, PLANE_CTL(pipe, plane_id));
 
 	/* No DDB allocated for disabled planes */
 	if (val & PLANE_CTL_ENABLE)
@@ -4321,11 +4321,11 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
 					      val & PLANE_CTL_ALPHA_MASK);
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
 		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
 	} else {
-		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
-		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
+		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
+		val2 = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
 
 		if (fourcc &&
 		    drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
@@ -6240,9 +6240,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 
 		for (level = 0; level <= max_level; level++) {
 			if (plane_id != PLANE_CURSOR)
-				val = I915_READ(PLANE_WM(pipe, plane_id, level));
+				val = intel_uncore_read(&dev_priv->uncore, PLANE_WM(pipe, plane_id, level));
 			else
-				val = I915_READ(CUR_WM(pipe, level));
+				val = intel_uncore_read(&dev_priv->uncore, CUR_WM(pipe, level));
 
 			skl_wm_level_from_reg_val(val, &wm->wm[level]);
 		}
@@ -6251,9 +6251,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 			wm->sagv_wm0 = wm->wm[0];
 
 		if (plane_id != PLANE_CURSOR)
-			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
+			val = intel_uncore_read(&dev_priv->uncore, PLANE_WM_TRANS(pipe, plane_id));
 		else
-			val = I915_READ(CUR_WM_TRANS(pipe));
+			val = intel_uncore_read(&dev_priv->uncore, CUR_WM_TRANS(pipe));
 
 		skl_wm_level_from_reg_val(val, &wm->trans_wm);
 	}
@@ -6288,7 +6288,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
 	struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
 	enum pipe pipe = crtc->pipe;
 
-	hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe));
+	hw->wm_pipe[pipe] = intel_uncore_read(&dev_priv->uncore, WM0_PIPE_ILK(pipe));
 
 	memset(active, 0, sizeof(*active));
 
@@ -6332,13 +6332,13 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
 {
 	u32 tmp;
 
-	tmp = I915_READ(DSPFW1);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
 	wm->sr.plane = _FW_WM(tmp, SR);
 	wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
 	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
 	wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
 
-	tmp = I915_READ(DSPFW2);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
 	wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
 	wm->sr.fbc = _FW_WM(tmp, FBC_SR);
 	wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
@@ -6346,7 +6346,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
 	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
 	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
 
-	tmp = I915_READ(DSPFW3);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 	wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
 	wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
 	wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
@@ -6360,7 +6360,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
 	u32 tmp;
 
 	for_each_pipe(dev_priv, pipe) {
-		tmp = I915_READ(VLV_DDL(pipe));
+		tmp = intel_uncore_read(&dev_priv->uncore, VLV_DDL(pipe));
 
 		wm->ddl[pipe].plane[PLANE_PRIMARY] =
 			(tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
@@ -6372,34 +6372,34 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
 			(tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
 	}
 
-	tmp = I915_READ(DSPFW1);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
 	wm->sr.plane = _FW_WM(tmp, SR);
 	wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
 	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
 	wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
 
-	tmp = I915_READ(DSPFW2);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
 	wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
 	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
 	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
 
-	tmp = I915_READ(DSPFW3);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 	wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
 
 	if (IS_CHERRYVIEW(dev_priv)) {
-		tmp = I915_READ(DSPFW7_CHV);
+		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7_CHV);
 		wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
 		wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
 
-		tmp = I915_READ(DSPFW8_CHV);
+		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW8_CHV);
 		wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
 		wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
 
-		tmp = I915_READ(DSPFW9_CHV);
+		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW9_CHV);
 		wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
 		wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
 
-		tmp = I915_READ(DSPHOWM);
+		tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
 		wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
 		wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
 		wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
@@ -6411,11 +6411,11 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
 		wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
 		wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
 	} else {
-		tmp = I915_READ(DSPFW7);
+		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7);
 		wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
 		wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
 
-		tmp = I915_READ(DSPHOWM);
+		tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
 		wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
 		wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
 		wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
@@ -6436,7 +6436,7 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
 
 	g4x_read_wm_values(dev_priv, wm);
 
-	wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
+	wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
 
 	for_each_intel_crtc(&dev_priv->drm, crtc) {
 		struct intel_crtc_state *crtc_state =
@@ -6580,7 +6580,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
 
 	vlv_read_wm_values(dev_priv, wm);
 
-	wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
+	wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 	wm->level = VLV_WM_LEVEL_PM2;
 
 	if (IS_CHERRYVIEW(dev_priv)) {
@@ -6727,9 +6727,9 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
  */
 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
 {
-	I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
-	I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
-	I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
+	intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM1_LP_SR_EN);
+	intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM1_LP_SR_EN);
+	intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM1_LP_SR_EN);
 
 	/*
 	 * Don't touch WM1S_LP_EN here.
@@ -6747,25 +6747,25 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
 	for_each_intel_crtc(&dev_priv->drm, crtc)
 		ilk_pipe_wm_get_hw_state(crtc);
 
-	hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
-	hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
-	hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
+	hw->wm_lp[0] = intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK);
+	hw->wm_lp[1] = intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK);
+	hw->wm_lp[2] = intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK);
 
-	hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
+	hw->wm_lp_spr[0] = intel_uncore_read(&dev_priv->uncore, WM1S_LP_ILK);
 	if (INTEL_GEN(dev_priv) >= 7) {
-		hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
-		hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
+		hw->wm_lp_spr[1] = intel_uncore_read(&dev_priv->uncore, WM2S_LP_IVB);
+		hw->wm_lp_spr[2] = intel_uncore_read(&dev_priv->uncore, WM3S_LP_IVB);
 	}
 
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-		hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
+		hw->partitioning = (intel_uncore_read(&dev_priv->uncore, WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
 			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
 	else if (IS_IVYBRIDGE(dev_priv))
-		hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
+		hw->partitioning = (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
 			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
 
 	hw->enable_fbc_wm =
-		!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
+		!(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
 }
 
 /**
@@ -6816,14 +6816,14 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
 	if (!HAS_IPC(dev_priv))
 		return;
 
-	val = I915_READ(DISP_ARB_CTL2);
+	val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2);
 
 	if (dev_priv->ipc_enabled)
 		val |= DISP_IPC_ENABLE;
 	else
 		val &= ~DISP_IPC_ENABLE;
 
-	I915_WRITE(DISP_ARB_CTL2, val);
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL2, val);
 }
 
 static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv)
@@ -6858,7 +6858,7 @@ static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
 	 * gating for the panel power sequencer or it will fail to
 	 * start up when no ports are active.
 	 */
-	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+	intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
@@ -6866,12 +6866,12 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
 	enum pipe pipe;
 
 	for_each_pipe(dev_priv, pipe) {
-		I915_WRITE(DSPCNTR(pipe),
-			   I915_READ(DSPCNTR(pipe)) |
+		intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe),
+			   intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) |
 			   DISPPLANE_TRICKLE_FEED_DISABLE);
 
-		I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
-		POSTING_READ(DSPSURF(pipe));
+		intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(pipe)));
+		intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe));
 	}
 }
 
@@ -6887,10 +6887,10 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
 		   ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
 		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
 
-	I915_WRITE(PCH_3DCGDIS0,
+	intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS0,
 		   MARIUNIT_CLOCK_GATE_DISABLE |
 		   SVSMUNIT_CLOCK_GATE_DISABLE);
-	I915_WRITE(PCH_3DCGDIS1,
+	intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS1,
 		   VFMUNIT_CLOCK_GATE_DISABLE);
 
 	/*
@@ -6900,12 +6900,12 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
 	 * The bit 5 of 0x42020
 	 * The bit 15 of 0x45000
 	 */
-	I915_WRITE(ILK_DISPLAY_CHICKEN2,
-		   (I915_READ(ILK_DISPLAY_CHICKEN2) |
+	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
+		   (intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
 		    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
 	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
-	I915_WRITE(DISP_ARB_CTL,
-		   (I915_READ(DISP_ARB_CTL) |
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL,
+		   (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
 		    DISP_FBC_WM_DIS));
 
 	/*
@@ -6917,18 +6917,18 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
 	 */
 	if (IS_IRONLAKE_M(dev_priv)) {
 		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
-		I915_WRITE(ILK_DISPLAY_CHICKEN1,
-			   I915_READ(ILK_DISPLAY_CHICKEN1) |
+		intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
+			   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
 			   ILK_FBCQ_DIS);
-		I915_WRITE(ILK_DISPLAY_CHICKEN2,
-			   I915_READ(ILK_DISPLAY_CHICKEN2) |
+		intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
+			   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
 			   ILK_DPARB_GATE);
 	}
 
-	I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
+	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
 
-	I915_WRITE(ILK_DISPLAY_CHICKEN2,
-		   I915_READ(ILK_DISPLAY_CHICKEN2) |
+	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
+		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
 		   ILK_ELPIN_409_SELECT);
 
 	g4x_disable_trickle_feed(dev_priv);
@@ -6946,27 +6946,27 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
 	 * gating for the panel power sequencer or it will fail to
 	 * start up when no ports are active.
 	 */
-	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
+	intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
 		   PCH_DPLUNIT_CLOCK_GATE_DISABLE |
 		   PCH_CPUNIT_CLOCK_GATE_DISABLE);
-	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
+	intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN2, intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN2) |
 		   DPLS_EDP_PPS_FIX_DIS);
 	/* The below fixes the weird display corruption, a few pixels shifted
 	 * downward, on (only) LVDS of some HP laptops with IVY.
 	 */
 	for_each_pipe(dev_priv, pipe) {
-		val = I915_READ(TRANS_CHICKEN2(pipe));
+		val = intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN2(pipe));
 		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
 		val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
 		if (dev_priv->vbt.fdi_rx_polarity_inverted)
 			val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
 		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
 		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
-		I915_WRITE(TRANS_CHICKEN2(pipe), val);
+		intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN2(pipe), val);
 	}
 	/* WADP0ClockGatingDisable */
 	for_each_pipe(dev_priv, pipe) {
-		I915_WRITE(TRANS_CHICKEN1(pipe),
+		intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(pipe),
 			   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
 	}
 }
@@ -6975,7 +6975,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
 {
 	u32 tmp;
 
-	tmp = I915_READ(MCH_SSKPD);
+	tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD);
 	if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
 		drm_dbg_kms(&dev_priv->drm,
 			    "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
@@ -6986,14 +6986,14 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
 
-	I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
+	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
 
-	I915_WRITE(ILK_DISPLAY_CHICKEN2,
-		   I915_READ(ILK_DISPLAY_CHICKEN2) |
+	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
+		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
 		   ILK_ELPIN_409_SELECT);
 
-	I915_WRITE(GEN6_UCGCTL1,
-		   I915_READ(GEN6_UCGCTL1) |
+	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
+		   intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
 		   GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
 
@@ -7010,7 +7010,7 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
 	 * WaDisableRCCUnitClockGating:snb
 	 * WaDisableRCPBUnitClockGating:snb
 	 */
-	I915_WRITE(GEN6_UCGCTL2,
+	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
 		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
 
@@ -7025,14 +7025,14 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
 	 *
 	 * WaFbcAsynchFlipDisableFbcQueue:snb
 	 */
-	I915_WRITE(ILK_DISPLAY_CHICKEN1,
-		   I915_READ(ILK_DISPLAY_CHICKEN1) |
+	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
+		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
 		   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
-	I915_WRITE(ILK_DISPLAY_CHICKEN2,
-		   I915_READ(ILK_DISPLAY_CHICKEN2) |
+	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
+		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
 		   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
-	I915_WRITE(ILK_DSPCLK_GATE_D,
-		   I915_READ(ILK_DSPCLK_GATE_D) |
+	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D,
+		   intel_uncore_read(&dev_priv->uncore, ILK_DSPCLK_GATE_D) |
 		   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
 		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
 
@@ -7050,23 +7050,23 @@ static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
 	 * disabled when not needed anymore in order to save power.
 	 */
 	if (HAS_PCH_LPT_LP(dev_priv))
-		I915_WRITE(SOUTH_DSPCLK_GATE_D,
-			   I915_READ(SOUTH_DSPCLK_GATE_D) |
+		intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D,
+			   intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |
 			   PCH_LP_PARTITION_LEVEL_DISABLE);
 
 	/* WADPOClockGatingDisable:hsw */
-	I915_WRITE(TRANS_CHICKEN1(PIPE_A),
-		   I915_READ(TRANS_CHICKEN1(PIPE_A)) |
+	intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A),
+		   intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A)) |
 		   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
 }
 
 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
 {
 	if (HAS_PCH_LPT_LP(dev_priv)) {
-		u32 val = I915_READ(SOUTH_DSPCLK_GATE_D);
+		u32 val = intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D);
 
 		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
-		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
+		intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, val);
 	}
 }
 
@@ -7078,33 +7078,33 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
 	u32 val;
 
 	/* WaTempDisableDOPClkGating:bdw */
-	misccpctl = I915_READ(GEN7_MISCCPCTL);
-	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+	misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
+	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 
-	val = I915_READ(GEN8_L3SQCREG1);
+	val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
 	val &= ~L3_PRIO_CREDITS_MASK;
 	val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
 	val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
-	I915_WRITE(GEN8_L3SQCREG1, val);
+	intel_uncore_write(&dev_priv->uncore, GEN8_L3SQCREG1, val);
 
 	/*
 	 * Wait at least 100 clocks before re-enabling clock gating.
 	 * See the definition of L3SQCREG1 in BSpec.
 	 */
-	POSTING_READ(GEN8_L3SQCREG1);
+	intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
 	udelay(1);
-	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
 }
 
 static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	/* Wa_1409120013:icl,ehl */
-	I915_WRITE(ILK_DPFC_CHICKEN,
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
 		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
 	/* This is not an Wa. Enable to reduce Sampler power */
-	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
-		   I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
+	intel_uncore_write(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
+		   intel_uncore_read(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
 
 	/*Wa_14010594013:icl, ehl */
 	intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
@@ -7114,12 +7114,12 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
 static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	/* Wa_1409120013:tgl */
-	I915_WRITE(ILK_DPFC_CHICKEN,
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
 		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
 	/* Wa_1409825376:tgl (pre-prod)*/
 	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
-		I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
+		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
 			   TGL_VRH_GATING_DIS);
 
 	/* Wa_14011059788:tgl */
@@ -7131,7 +7131,7 @@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	/* Wa_1409836686:dg1[a0] */
 	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
-		I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
+		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
 			   DPT_GATING_DIS);
 }
 
@@ -7141,7 +7141,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
 		return;
 
 	/* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
-	I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
+	intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |
 		   CNP_PWM_CGE_GATING_DISABLE);
 }
 
@@ -7151,35 +7151,35 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
 	cnp_init_clock_gating(dev_priv);
 
 	/* This is not an Wa. Enable for better image quality */
-	I915_WRITE(_3D_CHICKEN3,
+	intel_uncore_write(&dev_priv->uncore, _3D_CHICKEN3,
 		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
 
 	/* WaEnableChickenDCPR:cnl */
-	I915_WRITE(GEN8_CHICKEN_DCPR_1,
-		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
+	intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
+		   intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
 
 	/*
 	 * WaFbcWakeMemOn:cnl
 	 * Display WA #0859: cnl
 	 */
-	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
 		   DISP_FBC_MEMORY_WAKE);
 
-	val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);
+	val = intel_uncore_read(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE);
 	/* ReadHitWriteOnlyDisable:cnl */
 	val |= RCCUNIT_CLKGATE_DIS;
-	I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
+	intel_uncore_write(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE, val);
 
 	/* Wa_2201832410:cnl */
-	val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
+	val = intel_uncore_read(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE);
 	val |= GWUNIT_CLKGATE_DIS;
-	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
+	intel_uncore_write(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE, val);
 
 	/* WaDisableVFclkgate:cnl */
 	/* WaVFUnitClockGatingDisable:cnl */
-	val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
+	val = intel_uncore_read(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE);
 	val |= VFUNIT_CLKGATE_DIS;
-	I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val);
+	intel_uncore_write(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE, val);
 }
 
 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7188,21 +7188,21 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
 	gen9_init_clock_gating(dev_priv);
 
 	/* WAC6entrylatency:cfl */
-	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
+	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
 		   FBC_LLC_FULLY_OPEN);
 
 	/*
 	 * WaFbcTurnOffFbcWatermark:cfl
 	 * Display WA #0562: cfl
 	 */
-	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
 		   DISP_FBC_WM_DIS);
 
 	/*
 	 * WaFbcNukeOnHostModify:cfl
 	 * Display WA #0873: cfl
 	 */
-	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
@@ -7211,31 +7211,31 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 	gen9_init_clock_gating(dev_priv);
 
 	/* WAC6entrylatency:kbl */
-	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
+	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
 		   FBC_LLC_FULLY_OPEN);
 
 	/* WaDisableSDEUnitClockGating:kbl */
 	if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0))
-		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+		intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
 			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaDisableGamClockGating:kbl */
 	if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0))
-		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
+		intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
 			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
 	/*
 	 * WaFbcTurnOffFbcWatermark:kbl
 	 * Display WA #0562: kbl
 	 */
-	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
 		   DISP_FBC_WM_DIS);
 
 	/*
 	 * WaFbcNukeOnHostModify:kbl
 	 * Display WA #0873: kbl
 	 */
-	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
@@ -7244,32 +7244,32 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
 	gen9_init_clock_gating(dev_priv);
 
 	/* WaDisableDopClockGating:skl */
-	I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) &
+	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL) &
 		   ~GEN7_DOP_CLOCK_GATE_ENABLE);
 
 	/* WAC6entrylatency:skl */
-	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
+	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
 		   FBC_LLC_FULLY_OPEN);
 
 	/*
 	 * WaFbcTurnOffFbcWatermark:skl
 	 * Display WA #0562: skl
 	 */
-	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
 		   DISP_FBC_WM_DIS);
 
 	/*
 	 * WaFbcNukeOnHostModify:skl
 	 * Display WA #0873: skl
 	 */
-	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 
 	/*
 	 * WaFbcHighMemBwCorruptionAvoidance:skl
 	 * Display WA #0883: skl
 	 */
-	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_DISABLE_DUMMY0);
 }
 
@@ -7278,42 +7278,42 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
 	enum pipe pipe;
 
 	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
-	I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
-		   I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
+	intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
+		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |
 		   HSW_FBCQ_DIS);
 
 	/* WaSwitchSolVfFArbitrationPriority:bdw */
-	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
+	intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
 
 	/* WaPsrDPAMaskVBlankInSRD:bdw */
-	I915_WRITE(CHICKEN_PAR1_1,
-		   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
+	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
+		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
 
 	/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
 	for_each_pipe(dev_priv, pipe) {
-		I915_WRITE(CHICKEN_PIPESL_1(pipe),
-			   I915_READ(CHICKEN_PIPESL_1(pipe)) |
+		intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
+			   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe)) |
 			   BDW_DPRS_MASK_VBLANK_SRD);
 	}
 
 	/* WaVSRefCountFullforceMissDisable:bdw */
 	/* WaDSRefCountFullforceMissDisable:bdw */
-	I915_WRITE(GEN7_FF_THREAD_MODE,
-		   I915_READ(GEN7_FF_THREAD_MODE) &
+	intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
+		   intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
 		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
 
-	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
+	intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
 		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
 
 	/* WaDisableSDEUnitClockGating:bdw */
-	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaProgramL3SqcReg1Default:bdw */
 	gen8_set_l3sqc_credits(dev_priv, 30, 2);
 
 	/* WaKVMNotificationOnConfigChange:bdw */
-	I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
+	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR2_1, intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR2_1)
 		   | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
 
 	lpt_init_clock_gating(dev_priv);
@@ -7323,24 +7323,24 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
 	 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
 	 * clock gating.
 	 */
-	I915_WRITE(GEN6_UCGCTL1,
-		   I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
+	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
+		   intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
-	I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
-		   I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
+	intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
+		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |
 		   HSW_FBCQ_DIS);
 
 	/* This is required by WaCatErrorRejectionIssue:hsw */
-	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
-		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
+	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+		   intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
 		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
 	/* WaSwitchSolVfFArbitrationPriority:hsw */
-	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
+	intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
 
 	lpt_init_clock_gating(dev_priv);
 }
@@ -7349,26 +7349,26 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	u32 snpcr;
 
-	I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
+	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaFbcAsynchFlipDisableFbcQueue:ivb */
-	I915_WRITE(ILK_DISPLAY_CHICKEN1,
-		   I915_READ(ILK_DISPLAY_CHICKEN1) |
+	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
+		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
 		   ILK_FBCQ_DIS);
 
 	/* WaDisableBackToBackFlipFix:ivb */
-	I915_WRITE(IVB_CHICKEN3,
+	intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
 		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
 		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
 
 	if (IS_IVB_GT1(dev_priv))
-		I915_WRITE(GEN7_ROW_CHICKEN2,
+		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
 	else {
 		/* must write both registers */
-		I915_WRITE(GEN7_ROW_CHICKEN2,
+		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
-		I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
+		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2_GT2,
 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
 	}
 
@@ -7376,20 +7376,20 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
 	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
 	 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
 	 */
-	I915_WRITE(GEN6_UCGCTL2,
+	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
 		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
 
 	/* This is required by WaCatErrorRejectionIssue:ivb */
-	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
-			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
+	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+			intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
 			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
 	g4x_disable_trickle_feed(dev_priv);
 
-	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
+	snpcr = intel_uncore_read(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR);
 	snpcr &= ~GEN6_MBC_SNPCR_MASK;
 	snpcr |= GEN6_MBC_SNPCR_MED;
-	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
+	intel_uncore_write(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR, snpcr);
 
 	if (!HAS_PCH_NOP(dev_priv))
 		cpt_init_clock_gating(dev_priv);
@@ -7400,58 +7400,58 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	/* WaDisableBackToBackFlipFix:vlv */
-	I915_WRITE(IVB_CHICKEN3,
+	intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
 		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
 		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
 
 	/* WaDisableDopClockGating:vlv */
-	I915_WRITE(GEN7_ROW_CHICKEN2,
+	intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
 		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
 
 	/* This is required by WaCatErrorRejectionIssue:vlv */
-	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
-		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
+	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+		   intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
 		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
 	/*
 	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
 	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
 	 */
-	I915_WRITE(GEN6_UCGCTL2,
+	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
 		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaDisableL3Bank2xClockGate:vlv
 	 * Disabling L3 clock gating- MMIO 940c[25] = 1
 	 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
-	I915_WRITE(GEN7_UCGCTL4,
-		   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
+	intel_uncore_write(&dev_priv->uncore, GEN7_UCGCTL4,
+		   intel_uncore_read(&dev_priv->uncore, GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
 
 	/*
 	 * WaDisableVLVClockGating_VBIIssue:vlv
 	 * Disable clock gating on th GCFG unit to prevent a delay
 	 * in the reporting of vblank events.
 	 */
-	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
+	intel_uncore_write(&dev_priv->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
 }
 
 static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	/* WaVSRefCountFullforceMissDisable:chv */
 	/* WaDSRefCountFullforceMissDisable:chv */
-	I915_WRITE(GEN7_FF_THREAD_MODE,
-		   I915_READ(GEN7_FF_THREAD_MODE) &
+	intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
+		   intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
 		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
 
 	/* WaDisableSemaphoreAndSyncFlipWait:chv */
-	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
+	intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
 		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
 
 	/* WaDisableCSUnitClockGating:chv */
-	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
+	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
 		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaDisableSDEUnitClockGating:chv */
-	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
 	/*
@@ -7466,17 +7466,17 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	u32 dspclk_gate;
 
-	I915_WRITE(RENCLK_GATE_D1, 0);
-	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
+	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, 0);
+	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
 		   GS_UNIT_CLOCK_GATE_DISABLE |
 		   CL_UNIT_CLOCK_GATE_DISABLE);
-	I915_WRITE(RAMCLK_GATE_D, 0);
+	intel_uncore_write(&dev_priv->uncore, RAMCLK_GATE_D, 0);
 	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
 		OVRUNIT_CLOCK_GATE_DISABLE |
 		OVCUNIT_CLOCK_GATE_DISABLE;
 	if (IS_GM45(dev_priv))
 		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
-	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
+	intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D, dspclk_gate);
 
 	g4x_disable_trickle_feed(dev_priv);
 }
@@ -7497,49 +7497,49 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
 
 static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
+	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
 		   I965_RCC_CLOCK_GATE_DISABLE |
 		   I965_RCPB_CLOCK_GATE_DISABLE |
 		   I965_ISC_CLOCK_GATE_DISABLE |
 		   I965_FBC_CLOCK_GATE_DISABLE);
-	I915_WRITE(RENCLK_GATE_D2, 0);
-	I915_WRITE(MI_ARB_STATE,
+	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, 0);
+	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
 		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
 }
 
 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	u32 dstate = I915_READ(D_STATE);
+	u32 dstate = intel_uncore_read(&dev_priv->uncore, D_STATE);
 
 	dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
 		DSTATE_DOT_CLOCK_GATING;
-	I915_WRITE(D_STATE, dstate);
+	intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
 
 	if (IS_PINEVIEW(dev_priv))
-		I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
+		intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
 
 	/* IIR "flip pending" means done if this bit is set */
-	I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
+	intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
 
 	/* interrupts should cause a wake up from C3 */
-	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
+	intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
 
 	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
-	I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
+	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
 
-	I915_WRITE(MI_ARB_STATE,
+	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
 		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
 }
 
 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
+	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
 
 	/* interrupts should cause a wake up from C3 */
-	I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
+	intel_uncore_write(&dev_priv->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
 		   _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
 
-	I915_WRITE(MEM_MODE,
+	intel_uncore_write(&dev_priv->uncore, MEM_MODE,
 		   _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
 
 	/*
@@ -7549,13 +7549,13 @@ static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
 	 * abosultely nothing) would not allow FBC to recompress
 	 * until a 2D blit occurs.
 	 */
-	I915_WRITE(SCPD0,
+	intel_uncore_write(&dev_priv->uncore, SCPD0,
 		   _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
 }
 
 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	I915_WRITE(MEM_MODE,
+	intel_uncore_write(&dev_priv->uncore, MEM_MODE,
 		   _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
 		   _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
 }
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 8/9] drm/i915/irq: replace I915_READ()/WRITE() with intel_uncore_read()/write()

[Jani Nikula]

Arguably some of these should use intel_de_read() or intel_de_write(),
however not all. Prioritize I915_READ() and I915_WRITE() removal in
general over migrating to the pedantically correct replacements right
away.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 336 ++++++++++++++++----------------
 1 file changed, 168 insertions(+), 168 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 01f5749a5905..3f43dfe5fffa 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -309,10 +309,10 @@ i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 	lockdep_assert_held(&dev_priv->irq_lock);
 	drm_WARN_ON(&dev_priv->drm, bits & ~mask);
 
-	val = I915_READ(PORT_HOTPLUG_EN);
+	val = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN);
 	val &= ~mask;
 	val |= bits;
-	I915_WRITE(PORT_HOTPLUG_EN, val);
+	intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_EN, val);
 }
 
 /**
@@ -358,8 +358,8 @@ void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 	if (new_val != dev_priv->irq_mask &&
 	    !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {
 		dev_priv->irq_mask = new_val;
-		I915_WRITE(DEIMR, dev_priv->irq_mask);
-		POSTING_READ(DEIMR);
+		intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask);
+		intel_uncore_posting_read(&dev_priv->uncore, DEIMR);
 	}
 }
 
@@ -383,15 +383,15 @@ static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 	if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
 		return;
 
-	old_val = I915_READ(GEN8_DE_PORT_IMR);
+	old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);
 
 	new_val = old_val;
 	new_val &= ~interrupt_mask;
 	new_val |= (~enabled_irq_mask & interrupt_mask);
 
 	if (new_val != old_val) {
-		I915_WRITE(GEN8_DE_PORT_IMR, new_val);
-		POSTING_READ(GEN8_DE_PORT_IMR);
+		intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val);
+		intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);
 	}
 }
 
@@ -422,8 +422,8 @@ void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 
 	if (new_val != dev_priv->de_irq_mask[pipe]) {
 		dev_priv->de_irq_mask[pipe] = new_val;
-		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
-		POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
+		intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+		intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe));
 	}
 }
 
@@ -437,7 +437,7 @@ void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 				  u32 interrupt_mask,
 				  u32 enabled_irq_mask)
 {
-	u32 sdeimr = I915_READ(SDEIMR);
+	u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR);
 	sdeimr &= ~interrupt_mask;
 	sdeimr |= (~enabled_irq_mask & interrupt_mask);
 
@@ -448,8 +448,8 @@ void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 	if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
 		return;
 
-	I915_WRITE(SDEIMR, sdeimr);
-	POSTING_READ(SDEIMR);
+	intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr);
+	intel_uncore_posting_read(&dev_priv->uncore, SDEIMR);
 }
 
 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
@@ -515,8 +515,8 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv,
 	dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 	enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 
-	I915_WRITE(reg, enable_mask | status_mask);
-	POSTING_READ(reg);
+	intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);
+	intel_uncore_posting_read(&dev_priv->uncore, reg);
 }
 
 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
@@ -538,8 +538,8 @@ void i915_disable_pipestat(struct drm_i915_private *dev_priv,
 	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 	enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 
-	I915_WRITE(reg, enable_mask | status_mask);
-	POSTING_READ(reg);
+	intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);
+	intel_uncore_posting_read(&dev_priv->uncore, reg);
 }
 
 static bool i915_has_asle(struct drm_i915_private *dev_priv)
@@ -697,7 +697,7 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
 	if (!vblank->max_vblank_count)
 		return 0;
 
-	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
+	return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe));
 }
 
 /*
@@ -986,9 +986,9 @@ static void ivb_parity_work(struct work_struct *work)
 	if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
 		goto out;
 
-	misccpctl = I915_READ(GEN7_MISCCPCTL);
-	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
-	POSTING_READ(GEN7_MISCCPCTL);
+	misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
+	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+	intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);
 
 	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
 		i915_reg_t reg;
@@ -1002,13 +1002,13 @@ static void ivb_parity_work(struct work_struct *work)
 
 		reg = GEN7_L3CDERRST1(slice);
 
-		error_status = I915_READ(reg);
+		error_status = intel_uncore_read(&dev_priv->uncore, reg);
 		row = GEN7_PARITY_ERROR_ROW(error_status);
 		bank = GEN7_PARITY_ERROR_BANK(error_status);
 		subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 
-		I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
-		POSTING_READ(reg);
+		intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
+		intel_uncore_posting_read(&dev_priv->uncore, reg);
 
 		parity_event[0] = I915_L3_PARITY_UEVENT "=1";
 		parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
@@ -1029,7 +1029,7 @@ static void ivb_parity_work(struct work_struct *work)
 		kfree(parity_event[1]);
 	}
 
-	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
 
 out:
 	drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
@@ -1319,7 +1319,7 @@ static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 				     enum pipe pipe)
 {
 	display_pipe_crc_irq_handler(dev_priv, pipe,
-				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
+				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
 				     0, 0, 0, 0);
 }
 
@@ -1327,11 +1327,11 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 				     enum pipe pipe)
 {
 	display_pipe_crc_irq_handler(dev_priv, pipe,
-				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
-				     I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
-				     I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
-				     I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
-				     I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
+				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
+				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)),
+				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)),
+				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),
+				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));
 }
 
 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
@@ -1340,19 +1340,19 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 	u32 res1, res2;
 
 	if (INTEL_GEN(dev_priv) >= 3)
-		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
+		res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe));
 	else
 		res1 = 0;
 
 	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
-		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
+		res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe));
 	else
 		res2 = 0;
 
 	display_pipe_crc_irq_handler(dev_priv, pipe,
-				     I915_READ(PIPE_CRC_RES_RED(pipe)),
-				     I915_READ(PIPE_CRC_RES_GREEN(pipe)),
-				     I915_READ(PIPE_CRC_RES_BLUE(pipe)),
+				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)),
+				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)),
+				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)),
 				     res1, res2);
 }
 
@@ -1361,7 +1361,7 @@ static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
 	enum pipe pipe;
 
 	for_each_pipe(dev_priv, pipe) {
-		I915_WRITE(PIPESTAT(pipe),
+		intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe),
 			   PIPESTAT_INT_STATUS_MASK |
 			   PIPE_FIFO_UNDERRUN_STATUS);
 
@@ -1415,7 +1415,7 @@ static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
 			continue;
 
 		reg = PIPESTAT(pipe);
-		pipe_stats[pipe] = I915_READ(reg) & status_mask;
+		pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask;
 		enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 
 		/*
@@ -1428,8 +1428,8 @@ static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
 		 * an interrupt is still pending.
 		 */
 		if (pipe_stats[pipe]) {
-			I915_WRITE(reg, pipe_stats[pipe]);
-			I915_WRITE(reg, enable_mask);
+			intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]);
+			intel_uncore_write(&dev_priv->uncore, reg, enable_mask);
 		}
 	}
 	spin_unlock(&dev_priv->irq_lock);
@@ -1545,18 +1545,18 @@ static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
 	 * bits can itself generate a new hotplug interrupt :(
 	 */
 	for (i = 0; i < 10; i++) {
-		u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
+		u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask;
 
 		if (tmp == 0)
 			return hotplug_status;
 
 		hotplug_status |= tmp;
-		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
+		intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status);
 	}
 
 	drm_WARN_ONCE(&dev_priv->drm, 1,
 		      "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
-		      I915_READ(PORT_HOTPLUG_STAT));
+		      intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
 
 	return hotplug_status;
 }
@@ -1605,9 +1605,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		u32 hotplug_status = 0;
 		u32 ier = 0;
 
-		gt_iir = I915_READ(GTIIR);
-		pm_iir = I915_READ(GEN6_PMIIR);
-		iir = I915_READ(VLV_IIR);
+		gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);
+		pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
+		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
 
 		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 			break;
@@ -1627,14 +1627,14 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
 		 * bits this time around.
 		 */
-		I915_WRITE(VLV_MASTER_IER, 0);
-		ier = I915_READ(VLV_IER);
-		I915_WRITE(VLV_IER, 0);
+		intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
+		ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);
+		intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);
 
 		if (gt_iir)
-			I915_WRITE(GTIIR, gt_iir);
+			intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir);
 		if (pm_iir)
-			I915_WRITE(GEN6_PMIIR, pm_iir);
+			intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
 
 		if (iir & I915_DISPLAY_PORT_INTERRUPT)
 			hotplug_status = i9xx_hpd_irq_ack(dev_priv);
@@ -1652,10 +1652,10 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
 		 */
 		if (iir)
-			I915_WRITE(VLV_IIR, iir);
+			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
 
-		I915_WRITE(VLV_IER, ier);
-		I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
+		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
+		intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
 
 		if (gt_iir)
 			gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
@@ -1690,8 +1690,8 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		u32 hotplug_status = 0;
 		u32 ier = 0;
 
-		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
-		iir = I915_READ(VLV_IIR);
+		master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
+		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
 
 		if (master_ctl == 0 && iir == 0)
 			break;
@@ -1711,9 +1711,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
 		 * bits this time around.
 		 */
-		I915_WRITE(GEN8_MASTER_IRQ, 0);
-		ier = I915_READ(VLV_IER);
-		I915_WRITE(VLV_IER, 0);
+		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);
+		ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);
+		intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);
 
 		gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
 
@@ -1734,10 +1734,10 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
 		 */
 		if (iir)
-			I915_WRITE(VLV_IIR, iir);
+			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
 
-		I915_WRITE(VLV_IER, ier);
-		I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
+		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 
 		if (hotplug_status)
 			i9xx_hpd_irq_handler(dev_priv, hotplug_status);
@@ -1761,7 +1761,7 @@ static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
 	 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
 	 * errors.
 	 */
-	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
+	dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
 	if (!hotplug_trigger) {
 		u32 mask = PORTA_HOTPLUG_STATUS_MASK |
 			PORTD_HOTPLUG_STATUS_MASK |
@@ -1770,7 +1770,7 @@ static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
 		dig_hotplug_reg &= ~mask;
 	}
 
-	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
+	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
 	if (!hotplug_trigger)
 		return;
 
@@ -1815,7 +1815,7 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 		for_each_pipe(dev_priv, pipe)
 			drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",
 				pipe_name(pipe),
-				I915_READ(FDI_RX_IIR(pipe)));
+				intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));
 	}
 
 	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
@@ -1834,7 +1834,7 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 
 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
 {
-	u32 err_int = I915_READ(GEN7_ERR_INT);
+	u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT);
 	enum pipe pipe;
 
 	if (err_int & ERR_INT_POISON)
@@ -1852,12 +1852,12 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
 		}
 	}
 
-	I915_WRITE(GEN7_ERR_INT, err_int);
+	intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int);
 }
 
 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
 {
-	u32 serr_int = I915_READ(SERR_INT);
+	u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT);
 	enum pipe pipe;
 
 	if (serr_int & SERR_INT_POISON)
@@ -1867,7 +1867,7 @@ static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
 		if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
 			intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
 
-	I915_WRITE(SERR_INT, serr_int);
+	intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int);
 }
 
 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
@@ -1900,7 +1900,7 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 		for_each_pipe(dev_priv, pipe)
 			drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",
 				pipe_name(pipe),
-				I915_READ(FDI_RX_IIR(pipe)));
+				intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));
 	}
 
 	if (pch_iir & SDE_ERROR_CPT)
@@ -1916,8 +1916,8 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 	if (ddi_hotplug_trigger) {
 		u32 dig_hotplug_reg;
 
-		dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
-		I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
+		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);
+		intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, dig_hotplug_reg);
 
 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 				   ddi_hotplug_trigger, dig_hotplug_reg,
@@ -1928,8 +1928,8 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 	if (tc_hotplug_trigger) {
 		u32 dig_hotplug_reg;
 
-		dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
-		I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
+		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);
+		intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, dig_hotplug_reg);
 
 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 				   tc_hotplug_trigger, dig_hotplug_reg,
@@ -1954,8 +1954,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 	if (hotplug_trigger) {
 		u32 dig_hotplug_reg;
 
-		dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
-		I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
+		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
+		intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
 
 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 				   hotplug_trigger, dig_hotplug_reg,
@@ -1966,8 +1966,8 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 	if (hotplug2_trigger) {
 		u32 dig_hotplug_reg;
 
-		dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
-		I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
+		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);
+		intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, dig_hotplug_reg);
 
 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 				   hotplug2_trigger, dig_hotplug_reg,
@@ -1987,8 +1987,8 @@ static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
 {
 	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
 
-	dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
-	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
+	dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);
+	intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
 
 	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 			   hotplug_trigger, dig_hotplug_reg,
@@ -2029,7 +2029,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
 
 	/* check event from PCH */
 	if (de_iir & DE_PCH_EVENT) {
-		u32 pch_iir = I915_READ(SDEIIR);
+		u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
 
 		if (HAS_PCH_CPT(dev_priv))
 			cpt_irq_handler(dev_priv, pch_iir);
@@ -2037,7 +2037,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
 			ibx_irq_handler(dev_priv, pch_iir);
 
 		/* should clear PCH hotplug event before clear CPU irq */
-		I915_WRITE(SDEIIR, pch_iir);
+		intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
 	}
 
 	if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
@@ -2057,10 +2057,10 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
 		ivb_err_int_handler(dev_priv);
 
 	if (de_iir & DE_EDP_PSR_INT_HSW) {
-		u32 psr_iir = I915_READ(EDP_PSR_IIR);
+		u32 psr_iir = intel_uncore_read(&dev_priv->uncore, EDP_PSR_IIR);
 
 		intel_psr_irq_handler(dev_priv, psr_iir);
-		I915_WRITE(EDP_PSR_IIR, psr_iir);
+		intel_uncore_write(&dev_priv->uncore, EDP_PSR_IIR, psr_iir);
 	}
 
 	if (de_iir & DE_AUX_CHANNEL_A_IVB)
@@ -2076,12 +2076,12 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
 
 	/* check event from PCH */
 	if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
-		u32 pch_iir = I915_READ(SDEIIR);
+		u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
 
 		cpt_irq_handler(dev_priv, pch_iir);
 
 		/* clear PCH hotplug event before clear CPU irq */
-		I915_WRITE(SDEIIR, pch_iir);
+		intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
 	}
 }
 
@@ -2166,8 +2166,8 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
 {
 	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
 
-	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
-	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
+	dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
+	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
 
 	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 			   hotplug_trigger, dig_hotplug_reg,
@@ -2186,8 +2186,8 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 	if (trigger_tc) {
 		u32 dig_hotplug_reg;
 
-		dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
-		I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
+		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);
+		intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
 
 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 				   trigger_tc, dig_hotplug_reg,
@@ -2198,8 +2198,8 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 	if (trigger_tbt) {
 		u32 dig_hotplug_reg;
 
-		dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
-		I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
+		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);
+		intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
 
 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 				   trigger_tbt, dig_hotplug_reg,
@@ -2276,8 +2276,8 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 		else
 			iir_reg = EDP_PSR_IIR;
 
-		psr_iir = I915_READ(iir_reg);
-		I915_WRITE(iir_reg, psr_iir);
+		psr_iir = intel_uncore_read(&dev_priv->uncore, iir_reg);
+		intel_uncore_write(&dev_priv->uncore, iir_reg, psr_iir);
 
 		if (psr_iir)
 			found = true;
@@ -2301,7 +2301,7 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
 	 * Incase of dual link, TE comes from DSI_1
 	 * this is to check if dual link is enabled
 	 */
-	val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
+	val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
 	val &= PORT_SYNC_MODE_ENABLE;
 
 	/*
@@ -2313,7 +2313,7 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
 	dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
 
 	/* Check if DSI configured in command mode */
-	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+	val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans));
 	val = val & OP_MODE_MASK;
 
 	if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) {
@@ -2322,7 +2322,7 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
 	}
 
 	/* Get PIPE for handling VBLANK event */
-	val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+	val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans));
 	switch (val & TRANS_DDI_EDP_INPUT_MASK) {
 	case TRANS_DDI_EDP_INPUT_A_ON:
 		pipe = PIPE_A;
@@ -2342,8 +2342,8 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
 
 	/* clear TE in dsi IIR */
 	port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
-	tmp = I915_READ(DSI_INTR_IDENT_REG(port));
-	I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));
+	intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
 }
 
 static irqreturn_t
@@ -2354,9 +2354,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 	enum pipe pipe;
 
 	if (master_ctl & GEN8_DE_MISC_IRQ) {
-		iir = I915_READ(GEN8_DE_MISC_IIR);
+		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR);
 		if (iir) {
-			I915_WRITE(GEN8_DE_MISC_IIR, iir);
+			intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir);
 			ret = IRQ_HANDLED;
 			gen8_de_misc_irq_handler(dev_priv, iir);
 		} else {
@@ -2366,9 +2366,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 	}
 
 	if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
-		iir = I915_READ(GEN11_DE_HPD_IIR);
+		iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR);
 		if (iir) {
-			I915_WRITE(GEN11_DE_HPD_IIR, iir);
+			intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir);
 			ret = IRQ_HANDLED;
 			gen11_hpd_irq_handler(dev_priv, iir);
 		} else {
@@ -2378,11 +2378,11 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 	}
 
 	if (master_ctl & GEN8_DE_PORT_IRQ) {
-		iir = I915_READ(GEN8_DE_PORT_IIR);
+		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR);
 		if (iir) {
 			bool found = false;
 
-			I915_WRITE(GEN8_DE_PORT_IIR, iir);
+			intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir);
 			ret = IRQ_HANDLED;
 
 			if (iir & gen8_de_port_aux_mask(dev_priv)) {
@@ -2435,7 +2435,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
 			continue;
 
-		iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
+		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe));
 		if (!iir) {
 			drm_err(&dev_priv->drm,
 				"The master control interrupt lied (DE PIPE)!\n");
@@ -2443,7 +2443,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 		}
 
 		ret = IRQ_HANDLED;
-		I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
+		intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir);
 
 		if (iir & GEN8_PIPE_VBLANK)
 			intel_handle_vblank(dev_priv, pipe);
@@ -2472,9 +2472,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 		 * scheme also closed the SDE interrupt handling race we've seen
 		 * on older pch-split platforms. But this needs testing.
 		 */
-		iir = I915_READ(SDEIIR);
+		iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
 		if (iir) {
-			I915_WRITE(SDEIIR, iir);
+			intel_uncore_write(&dev_priv->uncore, SDEIIR, iir);
 			ret = IRQ_HANDLED;
 
 			if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
@@ -2713,7 +2713,7 @@ int i915gm_enable_vblank(struct drm_crtc *crtc)
 	 * only when vblank interrupts are actually enabled.
 	 */
 	if (dev_priv->vblank_enabled++ == 0)
-		I915_WRITE(SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
+		intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
 
 	return i8xx_enable_vblank(crtc);
 }
@@ -2770,16 +2770,16 @@ static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc,
 	else
 		port = PORT_A;
 
-	tmp =  I915_READ(DSI_INTR_MASK_REG(port));
+	tmp =  intel_uncore_read(&dev_priv->uncore, DSI_INTR_MASK_REG(port));
 	if (enable)
 		tmp &= ~DSI_TE_EVENT;
 	else
 		tmp |= DSI_TE_EVENT;
 
-	I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
+	intel_uncore_write(&dev_priv->uncore, DSI_INTR_MASK_REG(port), tmp);
 
-	tmp = I915_READ(DSI_INTR_IDENT_REG(port));
-	I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));
+	intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
 
 	return true;
 }
@@ -2841,7 +2841,7 @@ void i915gm_disable_vblank(struct drm_crtc *crtc)
 	i8xx_disable_vblank(crtc);
 
 	if (--dev_priv->vblank_enabled == 0)
-		I915_WRITE(SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
+		intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
 }
 
 void i965_disable_vblank(struct drm_crtc *crtc)
@@ -2907,7 +2907,7 @@ static void ibx_irq_reset(struct drm_i915_private *dev_priv)
 	GEN3_IRQ_RESET(uncore, SDE);
 
 	if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
-		I915_WRITE(SERR_INT, 0xffffffff);
+		intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff);
 }
 
 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -2920,7 +2920,7 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 		intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
 
 	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
-	intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+	intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
@@ -2983,8 +2983,8 @@ static void ilk_irq_reset(struct drm_i915_private *dev_priv)
 
 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
 {
-	I915_WRITE(VLV_MASTER_IER, 0);
-	POSTING_READ(VLV_MASTER_IER);
+	intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
+	intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
 
 	gen5_gt_irq_reset(&dev_priv->gt);
 
@@ -3135,8 +3135,8 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_uncore *uncore = &dev_priv->uncore;
 
-	I915_WRITE(GEN8_MASTER_IRQ, 0);
-	POSTING_READ(GEN8_MASTER_IRQ);
+	intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);
+	intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
 
 	gen8_gt_irq_reset(&dev_priv->gt);
 
@@ -3182,7 +3182,7 @@ static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	 * duration to 2ms (which is the minimum in the Display Port spec).
 	 * The pulse duration bits are reserved on LPT+.
 	 */
-	hotplug = I915_READ(PCH_PORT_HOTPLUG);
+	hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
 	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
 		     PORTB_HOTPLUG_ENABLE |
 		     PORTC_HOTPLUG_ENABLE |
@@ -3191,7 +3191,7 @@ static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
 		     PORTC_PULSE_DURATION_MASK |
 		     PORTD_PULSE_DURATION_MASK);
 	hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);
-	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
+	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
 }
 
 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
@@ -3240,20 +3240,20 @@ static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
-	hotplug = I915_READ(SHOTPLUG_CTL_DDI);
+	hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);
 	hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) |
 		     SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) |
 		     SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) |
 		     SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D));
 	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables);
-	I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
+	intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, hotplug);
 }
 
 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
-	hotplug = I915_READ(SHOTPLUG_CTL_TC);
+	hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);
 	hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) |
 		     ICP_TC_HPD_ENABLE(HPD_PORT_TC2) |
 		     ICP_TC_HPD_ENABLE(HPD_PORT_TC3) |
@@ -3261,7 +3261,7 @@ static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
 		     ICP_TC_HPD_ENABLE(HPD_PORT_TC5) |
 		     ICP_TC_HPD_ENABLE(HPD_PORT_TC6));
 	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables);
-	I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
+	intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, hotplug);
 }
 
 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
@@ -3272,7 +3272,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
 
 	if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
-		I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
+		intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
 
 	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
 
@@ -3300,12 +3300,12 @@ static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	u32 val;
 
-	val = I915_READ(SOUTH_CHICKEN1);
+	val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);
 	val |= (INVERT_DDIA_HPD |
 		INVERT_DDIB_HPD |
 		INVERT_DDIC_HPD |
 		INVERT_DDID_HPD);
-	I915_WRITE(SOUTH_CHICKEN1, val);
+	intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);
 
 	icp_hpd_irq_setup(dev_priv);
 }
@@ -3314,7 +3314,7 @@ static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
-	hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
+	hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);
 	hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
 		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
 		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
@@ -3322,14 +3322,14 @@ static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
 		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
 		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
 	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
-	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
+	intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, hotplug);
 }
 
 static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
-	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
+	hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);
 	hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
 		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
 		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
@@ -3337,7 +3337,7 @@ static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
 		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
 	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
-	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
+	intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, hotplug);
 }
 
 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
@@ -3348,11 +3348,11 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
 
-	val = I915_READ(GEN11_DE_HPD_IMR);
+	val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
 	val &= ~hotplug_irqs;
 	val |= ~enabled_irqs & hotplug_irqs;
-	I915_WRITE(GEN11_DE_HPD_IMR, val);
-	POSTING_READ(GEN11_DE_HPD_IMR);
+	intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IMR, val);
+	intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
 
 	gen11_tc_hpd_detection_setup(dev_priv);
 	gen11_tbt_hpd_detection_setup(dev_priv);
@@ -3395,25 +3395,25 @@ static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 
 	/* Display WA #1179 WaHardHangonHotPlug: cnp */
 	if (HAS_PCH_CNP(dev_priv)) {
-		val = I915_READ(SOUTH_CHICKEN1);
+		val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);
 		val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
 		val |= CHASSIS_CLK_REQ_DURATION(0xf);
-		I915_WRITE(SOUTH_CHICKEN1, val);
+		intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);
 	}
 
 	/* Enable digital hotplug on the PCH */
-	hotplug = I915_READ(PCH_PORT_HOTPLUG);
+	hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
 	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
 		     PORTB_HOTPLUG_ENABLE |
 		     PORTC_HOTPLUG_ENABLE |
 		     PORTD_HOTPLUG_ENABLE);
 	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables);
-	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
+	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
 
-	hotplug = I915_READ(PCH_PORT_HOTPLUG2);
+	hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);
 	hotplug &= ~PORTE_HOTPLUG_ENABLE;
 	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables);
-	I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
+	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, hotplug);
 }
 
 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
@@ -3421,7 +3421,7 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	u32 hotplug_irqs, enabled_irqs;
 
 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
-		I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
+		intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
 
 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
@@ -3452,11 +3452,11 @@ static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	 * duration to 2ms (which is the minimum in the Display Port spec)
 	 * The pulse duration bits are reserved on HSW+.
 	 */
-	hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
+	hotplug = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);
 	hotplug &= ~(DIGITAL_PORTA_HOTPLUG_ENABLE |
 		     DIGITAL_PORTA_PULSE_DURATION_MASK);
 	hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables);
-	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
+	intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
 }
 
 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
@@ -3506,7 +3506,7 @@ static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
-	hotplug = I915_READ(PCH_PORT_HOTPLUG);
+	hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
 	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
 		     PORTB_HOTPLUG_ENABLE |
 		     PORTC_HOTPLUG_ENABLE |
@@ -3514,7 +3514,7 @@ static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 		     BXT_DDIB_HPD_INVERT |
 		     BXT_DDIC_HPD_INVERT);
 	hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables);
-	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
+	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
 }
 
 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
@@ -3634,8 +3634,8 @@ static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
 		vlv_display_irq_postinstall(dev_priv);
 	spin_unlock_irq(&dev_priv->irq_lock);
 
-	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
-	POSTING_READ(VLV_MASTER_IER);
+	intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
+	intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
 }
 
 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3748,14 +3748,14 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
 
-	I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
+	intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
 
 	if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
 		dg1_master_intr_enable(uncore->regs);
-		POSTING_READ(DG1_MSTR_UNIT_INTR);
+		intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_UNIT_INTR);
 	} else {
 		gen11_master_intr_enable(uncore->regs);
-		POSTING_READ(GEN11_GFX_MSTR_IRQ);
+		intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
 	}
 }
 
@@ -3768,8 +3768,8 @@ static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
 		vlv_display_irq_postinstall(dev_priv);
 	spin_unlock_irq(&dev_priv->irq_lock);
 
-	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
-	POSTING_READ(GEN8_MASTER_IRQ);
+	intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+	intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
 }
 
 static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
@@ -3859,11 +3859,11 @@ static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
 {
 	u32 emr;
 
-	*eir = I915_READ(EIR);
+	*eir = intel_uncore_read(&dev_priv->uncore, EIR);
 
-	I915_WRITE(EIR, *eir);
+	intel_uncore_write(&dev_priv->uncore, EIR, *eir);
 
-	*eir_stuck = I915_READ(EIR);
+	*eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR);
 	if (*eir_stuck == 0)
 		return;
 
@@ -3877,9 +3877,9 @@ static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
 	 * (or by a GPU reset) so we mask any bit that
 	 * remains set.
 	 */
-	emr = I915_READ(EMR);
-	I915_WRITE(EMR, 0xffffffff);
-	I915_WRITE(EMR, emr | *eir_stuck);
+	emr = intel_uncore_read(&dev_priv->uncore, EMR);
+	intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff);
+	intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck);
 }
 
 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
@@ -3943,7 +3943,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
 
 	if (I915_HAS_HOTPLUG(dev_priv)) {
 		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
-		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+		intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
 	}
 
 	i9xx_pipestat_irq_reset(dev_priv);
@@ -3957,7 +3957,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
 	struct intel_uncore *uncore = &dev_priv->uncore;
 	u32 enable_mask;
 
-	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
+	intel_uncore_write(&dev_priv->uncore, EMR, ~(I915_ERROR_PAGE_TABLE |
 			  I915_ERROR_MEMORY_REFRESH));
 
 	/* Unmask the interrupts that we always want on. */
@@ -4010,7 +4010,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 		u32 hotplug_status = 0;
 		u32 iir;
 
-		iir = I915_READ(GEN2_IIR);
+		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
 		if (iir == 0)
 			break;
 
@@ -4027,7 +4027,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 		if (iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
 
-		I915_WRITE(GEN2_IIR, iir);
+		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
 
 		if (iir & I915_USER_INTERRUPT)
 			intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
@@ -4051,7 +4051,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
 	struct intel_uncore *uncore = &dev_priv->uncore;
 
 	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
-	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+	intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
@@ -4078,7 +4078,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
 		error_mask = ~(I915_ERROR_PAGE_TABLE |
 			       I915_ERROR_MEMORY_REFRESH);
 	}
-	I915_WRITE(EMR, error_mask);
+	intel_uncore_write(&dev_priv->uncore, EMR, error_mask);
 
 	/* Unmask the interrupts that we always want on. */
 	dev_priv->irq_mask =
@@ -4154,7 +4154,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 		u32 hotplug_status = 0;
 		u32 iir;
 
-		iir = I915_READ(GEN2_IIR);
+		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
 		if (iir == 0)
 			break;
 
@@ -4170,7 +4170,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 		if (iir & I915_MASTER_ERROR_INTERRUPT)
 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
 
-		I915_WRITE(GEN2_IIR, iir);
+		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
 
 		if (iir & I915_USER_INTERRUPT)
 			intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
-- 
2.20.1

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[Intel-gfx] [PATCH 9/9] drm/i915: remove last traces of I915_READ(), I915_WRITE() and POSTING_READ()

[Jani Nikula]

Good riddance! Remove the macros and their remaining references in
comments.

The following functions should be used instead, depending on the use
case:

- intel_uncore_read(), intel_uncore_write(), intel_uncore_posting_read()

- intel_de_read(), intel_de_write(), intel_de_posting_read()

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dvo.c | 4 ----
 drivers/gpu/drm/i915/i915_drv.h          | 8 --------
 drivers/gpu/drm/i915/i915_reg.h          | 6 ++++--
 drivers/gpu/drm/i915/intel_sideband.c    | 4 ++--
 drivers/gpu/drm/i915/intel_uncore.c      | 2 +-
 drivers/gpu/drm/i915/intel_uncore.h      | 4 ++--
 6 files changed, 9 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 237dbb1ba0ee..090cd76266c6 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -301,12 +301,8 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
 	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;
 
-	/*I915_WRITE(DVOB_SRCDIM,
-	  (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
-	  (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
 	intel_de_write(dev_priv, dvo_srcdim_reg,
 		       (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
-	/*I915_WRITE(DVOB, dvo_val);*/
 	intel_de_write(dev_priv, dvo_reg, dvo_val);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fecb5899cbac..42f60b112436 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1970,14 +1970,6 @@ mkwrite_device_info(struct drm_i915_private *dev_priv)
 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file);
 
-#define __I915_REG_OP(op__, dev_priv__, ...) \
-	intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
-
-#define I915_READ(reg__)	 __I915_REG_OP(read, dev_priv, (reg__))
-#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
-
-#define POSTING_READ(reg__)	__I915_REG_OP(posting_read, dev_priv, (reg__))
-
 /* i915_mm.c */
 int remap_io_mapping(struct vm_area_struct *vma,
 		     unsigned long addr, unsigned long pfn, unsigned long size,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7ea70b7ffcc6..568633448202 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10849,8 +10849,10 @@ enum skl_power_gate {
 #define  CNL_DRAM_RANK_3			(0x2 << 9)
 #define  CNL_DRAM_RANK_4			(0x3 << 9)
 
-/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
- * since on HSW we can't write to it using I915_WRITE. */
+/*
+ * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
+ * since on HSW we can't write to it using intel_uncore_write.
+ */
 #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
 #define D_COMP_BDW			_MMIO(0x138144)
 #define  D_COMP_RCOMP_IN_PROGRESS	(1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 02ebf5a04a9b..0ec0cf191955 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -404,8 +404,8 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
 	lockdep_assert_held(&i915->sb_lock);
 
 	/*
-	 * GEN6_PCODE_* are outside of the forcewake domain, we can
-	 * use te fw I915_READ variants to reduce the amount of work
+	 * GEN6_PCODE_* are outside of the forcewake domain, we can use
+	 * intel_uncore_read/write_fw variants to reduce the amount of work
 	 * required when reading/writing.
 	 */
 
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index ef40edfff412..9ac501bcfdad 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2126,7 +2126,7 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
  * This routine waits until the target register @reg contains the expected
  * @value after applying the @mask, i.e. it waits until ::
  *
- *     (I915_READ(reg) & mask) == value
+ *     (intel_uncore_read(uncore, reg) & mask) == value
  *
  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
  *
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 5dcb7f4183b2..59f0da8f1fbb 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -318,8 +318,8 @@ __uncore_write(write_notrace, 32, l, false)
  * will be implemented using 2 32-bit writes in an arbitrary order with
  * an arbitrary delay between them. This can cause the hardware to
  * act upon the intermediate value, possibly leading to corruption and
- * machine death. For this reason we do not support I915_WRITE64, or
- * uncore->funcs.mmio_writeq.
+ * machine death. For this reason we do not support intel_uncore_write64,
+ * or uncore->funcs.mmio_writeq.
  *
  * When reading a 64-bit value as two 32-bit values, the delay may cause
  * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
-- 
2.20.1

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: nuke remaining legacy reg helpers (I915_READ/WRITE etc.)

[Patchwork]

== Series Details ==

Series: drm/i915: nuke remaining legacy reg helpers (I915_READ/WRITE etc.)
URL   : https://patchwork.freedesktop.org/series/83762/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9851f04c829b drm/i915: remove last users of I915_READ_FW()
-:23: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#23: FILE: drivers/gpu/drm/i915/i915_debugfs.c:1242:
+		rpupei = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;

-:24: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#24: FILE: drivers/gpu/drm/i915/i915_debugfs.c:1243:
+		rpdown = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;

-:25: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#25: FILE: drivers/gpu/drm/i915/i915_debugfs.c:1244:
+		rpdownei = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;

total: 0 errors, 3 warnings, 0 checks, 14 lines checked
d38df7d26218 drm/i915: remove last traces of I915_READ_FW() and I915_WRITE_FW()
9513480437b3 drm/i915/cdclk: prefer intel_de_write() over I915_WRITE()
301253565834 drm/i915/debugfs: replace I915_READ()+I915_WRITE() with intel_uncore_rmw()
a62091be81ec drm/i915/debugfs: replace I915_READ() with intel_uncore_read()
-:380: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#380: FILE: drivers/gpu/drm/i915/i915_debugfs.c:879:
+		rpupei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;

-:381: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#381: FILE: drivers/gpu/drm/i915/i915_debugfs.c:880:
+		rpcurup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;

-:382: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#382: FILE: drivers/gpu/drm/i915/i915_debugfs.c:881:
+		rpprevup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;

-:383: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#383: FILE: drivers/gpu/drm/i915/i915_debugfs.c:882:
+		rpdownei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;

-:384: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#384: FILE: drivers/gpu/drm/i915/i915_debugfs.c:883:
+		rpcurdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;

-:385: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#385: FILE: drivers/gpu/drm/i915/i915_debugfs.c:884:
+		rpprevdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;

-:393: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#393: FILE: drivers/gpu/drm/i915/i915_debugfs.c:890:
+			pm_ier = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);

-:394: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#394: FILE: drivers/gpu/drm/i915/i915_debugfs.c:891:
+			pm_imr = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);

total: 0 errors, 8 warnings, 0 checks, 405 lines checked
0ea2a583a565 drm/i915/suspend: replace I915_READ()/WRITE() with intel_de_read()/write()
-:29: CHECK:CAMELCASE: Avoid CamelCase: <saveSWF0>
#29: FILE: drivers/gpu/drm/i915/i915_suspend.c:43:
+			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i));

-:30: CHECK:CAMELCASE: Avoid CamelCase: <saveSWF1>
#30: FILE: drivers/gpu/drm/i915/i915_suspend.c:44:
+			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));

-:34: CHECK:CAMELCASE: Avoid CamelCase: <saveSWF3>
#34: FILE: drivers/gpu/drm/i915/i915_suspend.c:47:
+			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));

-:86: CHECK:CAMELCASE: Avoid CamelCase: <saveDSPARB>
#86: FILE: drivers/gpu/drm/i915/i915_suspend.c:92:
+		dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB);

total: 0 errors, 0 warnings, 4 checks, 79 lines checked
67149b9d146a drm/i915/pm: replace I915_READ()/WRITE() with intel_uncore_read()/write()
-:25: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#25: FILE: drivers/gpu/drm/i915/intel_pm.c:85:
+		intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
+			   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) |

-:33: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#33: FILE: drivers/gpu/drm/i915/intel_pm.c:91:
+	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
+		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);

-:39: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#39: FILE: drivers/gpu/drm/i915/intel_pm.c:95:
+	intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
+		   intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);

-:46: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#46: FILE: drivers/gpu/drm/i915/intel_pm.c:101:
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |

-:55: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#55: FILE: drivers/gpu/drm/i915/intel_pm.c:110:
+	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |

-:63: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#63: FILE: drivers/gpu/drm/i915/intel_pm.c:117:
+	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |

-:71: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#71: FILE: drivers/gpu/drm/i915/intel_pm.c:124:
+	intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |

-:87: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#87: FILE: drivers/gpu/drm/i915/intel_pm.c:139:
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |

-:95: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#95: FILE: drivers/gpu/drm/i915/intel_pm.c:146:
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |

-:104: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#104: FILE: drivers/gpu/drm/i915/intel_pm.c:159:
+	intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |

-:288: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#288: FILE: drivers/gpu/drm/i915/intel_pm.c:979:
+	intel_uncore_write(&dev_priv->uncore, DSPFW1,
 		   FW_WM(wm->sr.plane, SR) |

-:294: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#294: FILE: drivers/gpu/drm/i915/intel_pm.c:984:
+	intel_uncore_write(&dev_priv->uncore, DSPFW2,
 		   (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |

-:302: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#302: FILE: drivers/gpu/drm/i915/intel_pm.c:991:
+	intel_uncore_write(&dev_priv->uncore, DSPFW3,
 		   (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |

-:318: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#318: FILE: drivers/gpu/drm/i915/intel_pm.c:1011:
+		intel_uncore_write(&dev_priv->uncore, VLV_DDL(pipe),
 			   (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |

-:338: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#338: FILE: drivers/gpu/drm/i915/intel_pm.c:1029:
+	intel_uncore_write(&dev_priv->uncore, DSPFW1,
 		   FW_WM(wm->sr.plane, SR) |

-:344: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#344: FILE: drivers/gpu/drm/i915/intel_pm.c:1034:
+	intel_uncore_write(&dev_priv->uncore, DSPFW2,
 		   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |

-:349: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#349: FILE: drivers/gpu/drm/i915/intel_pm.c:1038:
+	intel_uncore_write(&dev_priv->uncore, DSPFW3,
 		   FW_WM(wm->sr.cursor, CURSOR_SR));

-:354: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#354: FILE: drivers/gpu/drm/i915/intel_pm.c:1042:
+		intel_uncore_write(&dev_priv->uncore, DSPFW7_CHV,
 			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |

-:358: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#358: FILE: drivers/gpu/drm/i915/intel_pm.c:1045:
+		intel_uncore_write(&dev_priv->uncore, DSPFW8_CHV,
 			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |

-:362: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#362: FILE: drivers/gpu/drm/i915/intel_pm.c:1048:
+		intel_uncore_write(&dev_priv->uncore, DSPFW9_CHV,
 			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |

-:366: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#366: FILE: drivers/gpu/drm/i915/intel_pm.c:1051:
+		intel_uncore_write(&dev_priv->uncore, DSPHOWM,
 			   FW_WM(wm->sr.plane >> 9, SR_HI) |

-:375: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#375: FILE: drivers/gpu/drm/i915/intel_pm.c:1063:
+		intel_uncore_write(&dev_priv->uncore, DSPFW7,
 			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |

-:379: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#379: FILE: drivers/gpu/drm/i915/intel_pm.c:1066:
+		intel_uncore_write(&dev_priv->uncore, DSPHOWM,
 			   FW_WM(wm->sr.plane >> 9, SR_HI) |

-:415: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#415: FILE: drivers/gpu/drm/i915/intel_pm.c:2450:
+			intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF,
 				   FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));

-:586: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#586: FILE: drivers/gpu/drm/i915/intel_pm.c:6243:
+				val = intel_uncore_read(&dev_priv->uncore, PLANE_WM(pipe, plane_id, level));

-:729: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#729: FILE: drivers/gpu/drm/i915/intel_pm.c:6730:
+	intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM1_LP_SR_EN);

-:730: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#730: FILE: drivers/gpu/drm/i915/intel_pm.c:6731:
+	intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM1_LP_SR_EN);

-:731: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#731: FILE: drivers/gpu/drm/i915/intel_pm.c:6732:
+	intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM1_LP_SR_EN);

-:757: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#757: FILE: drivers/gpu/drm/i915/intel_pm.c:6761:
+		hw->partitioning = (intel_uncore_read(&dev_priv->uncore, WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?

-:761: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#761: FILE: drivers/gpu/drm/i915/intel_pm.c:6764:
+		hw->partitioning = (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?

-:803: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#803: FILE: drivers/gpu/drm/i915/intel_pm.c:6870:
+		intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe),
+			   intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) |

-:808: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#808: FILE: drivers/gpu/drm/i915/intel_pm.c:6873:
+		intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(pipe)));

-:819: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#819: FILE: drivers/gpu/drm/i915/intel_pm.c:6891:
+	intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS0,
 		   MARIUNIT_CLOCK_GATE_DISABLE |

-:823: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#823: FILE: drivers/gpu/drm/i915/intel_pm.c:6894:
+	intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS1,
 		   VFMUNIT_CLOCK_GATE_DISABLE);

-:833: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#833: FILE: drivers/gpu/drm/i915/intel_pm.c:6904:
+	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
+		   (intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |

-:839: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#839: FILE: drivers/gpu/drm/i915/intel_pm.c:6908:
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL,
+		   (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |

-:850: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#850: FILE: drivers/gpu/drm/i915/intel_pm.c:6921:
+		intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
+			   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |

-:855: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#855: FILE: drivers/gpu/drm/i915/intel_pm.c:6924:
+		intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
+			   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |

-:865: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#865: FILE: drivers/gpu/drm/i915/intel_pm.c:6931:
+	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
+		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |

-:878: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#878: FILE: drivers/gpu/drm/i915/intel_pm.c:6952:
+	intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN2, intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN2) |

-:899: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#899: FILE: drivers/gpu/drm/i915/intel_pm.c:6970:
+		intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(pipe),
 			   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);

-:921: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#921: FILE: drivers/gpu/drm/i915/intel_pm.c:6992:
+	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
+		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |

-:927: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#927: FILE: drivers/gpu/drm/i915/intel_pm.c:6996:
+	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
+		   intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |

-:937: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#937: FILE: drivers/gpu/drm/i915/intel_pm.c:7014:
+	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
 		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |

-:947: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#947: FILE: drivers/gpu/drm/i915/intel_pm.c:7029:
+	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
+		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |

-:952: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#952: FILE: drivers/gpu/drm/i915/intel_pm.c:7032:
+	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
+		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |

-:957: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#957: FILE: drivers/gpu/drm/i915/intel_pm.c:7035:
+	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D,
+		   intel_uncore_read(&dev_priv->uncore, ILK_DSPCLK_GATE_D) |

-:968: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#968: FILE: drivers/gpu/drm/i915/intel_pm.c:7054:
+		intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D,
+			   intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |

-:975: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#975: FILE: drivers/gpu/drm/i915/intel_pm.c:7059:
+	intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A),
+		   intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A)) |

-:998: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#998: FILE: drivers/gpu/drm/i915/intel_pm.c:7082:
+	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);

-:1024: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1024: FILE: drivers/gpu/drm/i915/intel_pm.c:7103:
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
 		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);

-:1030: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#1030: FILE: drivers/gpu/drm/i915/intel_pm.c:7107:
+		   intel_uncore_read(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);

-:1030: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1030: FILE: drivers/gpu/drm/i915/intel_pm.c:7107:
+	intel_uncore_write(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
+		   intel_uncore_read(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);

-:1040: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1040: FILE: drivers/gpu/drm/i915/intel_pm.c:7118:
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
 		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);

-:1045: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#1045: FILE: drivers/gpu/drm/i915/intel_pm.c:7122:
+		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |

-:1054: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#1054: FILE: drivers/gpu/drm/i915/intel_pm.c:7134:
+		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |

-:1063: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#1063: FILE: drivers/gpu/drm/i915/intel_pm.c:7144:
+	intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |

-:1073: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1073: FILE: drivers/gpu/drm/i915/intel_pm.c:7155:
+	intel_uncore_write(&dev_priv->uncore, _3D_CHICKEN3,
 		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));

-:1079: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1079: FILE: drivers/gpu/drm/i915/intel_pm.c:7159:
+	intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
+		   intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);

-:1086: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#1086: FILE: drivers/gpu/drm/i915/intel_pm.c:7165:
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |

-:1118: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#1118: FILE: drivers/gpu/drm/i915/intel_pm.c:7191:
+	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |

-:1126: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#1126: FILE: drivers/gpu/drm/i915/intel_pm.c:7198:
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |

-:1134: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#1134: FILE: drivers/gpu/drm/i915/intel_pm.c:7205:
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |

-:1143: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#1143: FILE: drivers/gpu/drm/i915/intel_pm.c:7214:
+	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |

-:1149: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#1149: FILE: drivers/gpu/drm/i915/intel_pm.c:7219:
+		intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |

-:1155: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#1155: FILE: drivers/gpu/drm/i915/intel_pm.c:7224:
+		intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |

-:1163: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#1163: FILE: drivers/gpu/drm/i915/intel_pm.c:7231:
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |

-:1171: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#1171: FILE: drivers/gpu/drm/i915/intel_pm.c:7238:
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |

-:1180: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#1180: FILE: drivers/gpu/drm/i915/intel_pm.c:7247:
+	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL) &

-:1185: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#1185: FILE: drivers/gpu/drm/i915/intel_pm.c:7251:
+	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |

-:1193: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#1193: FILE: drivers/gpu/drm/i915/intel_pm.c:7258:
+	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |

-:1201: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#1201: FILE: drivers/gpu/drm/i915/intel_pm.c:7265:
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |

-:1209: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#1209: FILE: drivers/gpu/drm/i915/intel_pm.c:7272:
+	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |

-:1220: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1220: FILE: drivers/gpu/drm/i915/intel_pm.c:7282:
+	intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
+		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |

-:1225: WARNING:LONG_LINE: line length of 134 exceeds 100 columns
#1225: FILE: drivers/gpu/drm/i915/intel_pm.c:7286:
+	intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);

-:1231: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1231: FILE: drivers/gpu/drm/i915/intel_pm.c:7290:
+	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
+		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);

-:1238: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1238: FILE: drivers/gpu/drm/i915/intel_pm.c:7295:
+		intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
+			   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe)) |

-:1247: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1247: FILE: drivers/gpu/drm/i915/intel_pm.c:7302:
+	intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
+		   intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &

-:1252: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1252: FILE: drivers/gpu/drm/i915/intel_pm.c:7306:
+	intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
 		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));

-:1256: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#1256: FILE: drivers/gpu/drm/i915/intel_pm.c:7309:
+	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |

-:1264: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#1264: FILE: drivers/gpu/drm/i915/intel_pm.c:7316:
+	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR2_1, intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR2_1)

-:1275: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#1275: FILE: drivers/gpu/drm/i915/intel_pm.c:7327:
+		   intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);

-:1275: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1275: FILE: drivers/gpu/drm/i915/intel_pm.c:7327:
+	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
+		   intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);

-:1284: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1284: FILE: drivers/gpu/drm/i915/intel_pm.c:7334:
+	intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
+		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |

-:1291: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1291: FILE: drivers/gpu/drm/i915/intel_pm.c:7339:
+	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+		   intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

-:1296: WARNING:LONG_LINE: line length of 134 exceeds 100 columns
#1296: FILE: drivers/gpu/drm/i915/intel_pm.c:7343:
+	intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);

-:1311: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1311: FILE: drivers/gpu/drm/i915/intel_pm.c:7356:
+	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
+		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |

-:1317: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1317: FILE: drivers/gpu/drm/i915/intel_pm.c:7361:
+	intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
 		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |

-:1323: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1323: FILE: drivers/gpu/drm/i915/intel_pm.c:7366:
+		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

-:1328: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1328: FILE: drivers/gpu/drm/i915/intel_pm.c:7370:
+		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

-:1331: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1331: FILE: drivers/gpu/drm/i915/intel_pm.c:7372:
+		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2_GT2,
 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

-:1340: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1340: FILE: drivers/gpu/drm/i915/intel_pm.c:7380:
+	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
 		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);

-:1346: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1346: FILE: drivers/gpu/drm/i915/intel_pm.c:7384:
+	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+			intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

-:1366: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1366: FILE: drivers/gpu/drm/i915/intel_pm.c:7404:
+	intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
 		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |

-:1372: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1372: FILE: drivers/gpu/drm/i915/intel_pm.c:7409:
+	intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
 		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

-:1378: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1378: FILE: drivers/gpu/drm/i915/intel_pm.c:7413:
+	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+		   intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

-:1387: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1387: FILE: drivers/gpu/drm/i915/intel_pm.c:7421:
+	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
 		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);

-:1395: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#1395: FILE: drivers/gpu/drm/i915/intel_pm.c:7427:
+		   intel_uncore_read(&dev_priv->uncore, GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);

-:1395: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1395: FILE: drivers/gpu/drm/i915/intel_pm.c:7427:
+	intel_uncore_write(&dev_priv->uncore, GEN7_UCGCTL4,
+		   intel_uncore_read(&dev_priv->uncore, GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);

-:1413: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1413: FILE: drivers/gpu/drm/i915/intel_pm.c:7442:
+	intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
+		   intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &

-:1419: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1419: FILE: drivers/gpu/drm/i915/intel_pm.c:7447:
+	intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
 		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));

-:1423: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#1423: FILE: drivers/gpu/drm/i915/intel_pm.c:7450:
+	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |

-:1428: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#1428: FILE: drivers/gpu/drm/i915/intel_pm.c:7454:
+	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |

-:1468: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1468: FILE: drivers/gpu/drm/i915/intel_pm.c:7507:
+	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
 		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));

-:1483: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#1483: FILE: drivers/gpu/drm/i915/intel_pm.c:7519:
+		intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));

-:1495: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#1495: FILE: drivers/gpu/drm/i915/intel_pm.c:7528:
+	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));

-:1499: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1499: FILE: drivers/gpu/drm/i915/intel_pm.c:7531:
+	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
 		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));

-:1514: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1514: FILE: drivers/gpu/drm/i915/intel_pm.c:7543:
+	intel_uncore_write(&dev_priv->uncore, MEM_MODE,
 		   _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));

-:1523: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1523: FILE: drivers/gpu/drm/i915/intel_pm.c:7553:
+	intel_uncore_write(&dev_priv->uncore, SCPD0,
 		   _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));

-:1530: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1530: FILE: drivers/gpu/drm/i915/intel_pm.c:7559:
+	intel_uncore_write(&dev_priv->uncore, MEM_MODE,
 		   _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |

total: 0 errors, 44 warnings, 66 checks, 1449 lines checked
3b


_______________________________________________
Intel-gfx mailing list
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: nuke remaining legacy reg helpers (I915_READ/WRITE etc.)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 3154 bytes --]

== Series Details ==

Series: drm/i915: nuke remaining legacy reg helpers (I915_READ/WRITE etc.)
URL   : https://patchwork.freedesktop.org/series/83762/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9312 -> Patchwork_18894
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/index.html

New tests
---------

  New tests have been introduced between CI_DRM_9312 and Patchwork_18894:

### New CI tests (1) ###

  * boot:
    - Statuses : 40 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18894 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@kms_busy@basic@flip:
    - {fi-tgl-dsi}:       [DMESG-WARN][1] ([i915#1982]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/fi-tgl-dsi/igt@kms_busy@basic@flip.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/fi-tgl-dsi/igt@kms_busy@basic@flip.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - fi-icl-u2:          [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982


Participating hosts (44 -> 40)
------------------------------

  Additional (1): fi-tgl-y 
  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-pnv-d510 fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9312 -> Patchwork_18894

  CI-20190529: 20190529
  CI_DRM_9312: 88b74d59a27aa168f7cd2dec199c33ee71fe8bb0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5847: 8cffaebec5228a5042cc6928ac582a0589e2de3e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18894: 3d231cbcc15eccab10761eba9bff4851d19a0905 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3d231cbcc15e drm/i915: remove last traces of I915_READ(), I915_WRITE() and POSTING_READ()
3b0dcd03f814 drm/i915/irq: replace I915_READ()/WRITE() with intel_uncore_read()/write()
67149b9d146a drm/i915/pm: replace I915_READ()/WRITE() with intel_uncore_read()/write()
0ea2a583a565 drm/i915/suspend: replace I915_READ()/WRITE() with intel_de_read()/write()
a62091be81ec drm/i915/debugfs: replace I915_READ() with intel_uncore_read()
301253565834 drm/i915/debugfs: replace I915_READ()+I915_WRITE() with intel_uncore_rmw()
9513480437b3 drm/i915/cdclk: prefer intel_de_write() over I915_WRITE()
d38df7d26218 drm/i915: remove last traces of I915_READ_FW() and I915_WRITE_FW()
9851f04c829b drm/i915: remove last users of I915_READ_FW()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/index.html

[-- Attachment #1.2: Type: text/html, Size: 3946 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: nuke remaining legacy reg helpers (I915_READ/WRITE etc.)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 21937 bytes --]

== Series Details ==

Series: drm/i915: nuke remaining legacy reg helpers (I915_READ/WRITE etc.)
URL   : https://patchwork.freedesktop.org/series/83762/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9312_full -> Patchwork_18894_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18894_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18894_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18894_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_eio@in-flight-internal-immediate:
    - shard-snb:          [PASS][1] -> [TIMEOUT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-snb7/igt@gem_eio@in-flight-internal-immediate.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-snb6/igt@gem_eio@in-flight-internal-immediate.html

  * igt@gem_exec_create@basic:
    - shard-glk:          [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk8/igt@gem_exec_create@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-glk4/igt@gem_exec_create@basic.html

  * igt@kms_ccs@pipe-a-crc-primary-basic:
    - shard-skl:          [PASS][5] -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl9/igt@kms_ccs@pipe-a-crc-primary-basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl3/igt@kms_ccs@pipe-a-crc-primary-basic.html

  * igt@perf_pmu@interrupts-sync:
    - shard-hsw:          [PASS][7] -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw8/igt@perf_pmu@interrupts-sync.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-hsw2/igt@perf_pmu@interrupts-sync.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9312_full and Patchwork_18894_full:

### New CI tests (1) ###

  * boot:
    - Statuses : 200 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18894_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_reloc@basic-many-active@rcs0:
    - shard-hsw:          [PASS][9] -> [FAIL][10] ([i915#2389])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw1/igt@gem_exec_reloc@basic-many-active@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-hsw2/igt@gem_exec_reloc@basic-many-active@rcs0.html

  * igt@gem_exec_whisper@basic-forked:
    - shard-glk:          [PASS][11] -> [DMESG-WARN][12] ([i915#118] / [i915#95])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk8/igt@gem_exec_whisper@basic-forked.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-glk2/igt@gem_exec_whisper@basic-forked.html

  * igt@i915_module_load@reload:
    - shard-iclb:         [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb5/igt@i915_module_load@reload.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-iclb2/igt@i915_module_load@reload.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([i915#54]) +3 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html

  * igt@kms_cursor_edge_walk@pipe-d-64x64-top-edge:
    - shard-tglb:         [PASS][17] -> [DMESG-WARN][18] ([i915#1982])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb3/igt@kms_cursor_edge_walk@pipe-d-64x64-top-edge.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-tglb3/igt@kms_cursor_edge_walk@pipe-d-64x64-top-edge.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [PASS][19] -> [FAIL][20] ([i915#96])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic:
    - shard-tglb:         [PASS][21] -> [FAIL][22] ([i915#2346])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb3/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-tglb:         [PASS][23] -> [FAIL][24] ([i915#2598])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
    - shard-kbl:          [PASS][25] -> [DMESG-WARN][26] ([i915#180])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate@a-edp1:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([i915#2122])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html

  * igt@kms_flip@plain-flip-ts-check@a-hdmi-a1:
    - shard-glk:          [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk6/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-glk3/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([i915#1188]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_lowres@pipe-a-tiling-yf:
    - shard-skl:          [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) +10 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@kms_plane_lowres@pipe-a-tiling-yf.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl1/igt@kms_plane_lowres@pipe-a-tiling-yf.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [PASS][35] -> [SKIP][36] ([fdo#109441]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-iclb6/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-a:
    - shard-apl:          [PASS][37] -> [DMESG-WARN][38] ([i915#1635] / [i915#1982]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-apl7/igt@kms_universal_plane@disable-primary-vs-flip-pipe-a.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-apl8/igt@kms_universal_plane@disable-primary-vs-flip-pipe-a.html

  * igt@kms_vblank@pipe-c-query-forked-busy:
    - shard-kbl:          [PASS][39] -> [DMESG-WARN][40] ([i915#1982]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-kbl2/igt@kms_vblank@pipe-c-query-forked-busy.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-kbl1/igt@kms_vblank@pipe-c-query-forked-busy.html

  * igt@prime_vgem@sync@rcs0:
    - shard-iclb:         [PASS][41] -> [INCOMPLETE][42] ([i915#409])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb1/igt@prime_vgem@sync@rcs0.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-iclb3/igt@prime_vgem@sync@rcs0.html

  
#### Possible fixes ####

  * igt@gem_exec_create@basic:
    - shard-snb:          [FAIL][43] ([i915#1037]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-snb7/igt@gem_exec_create@basic.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-snb7/igt@gem_exec_create@basic.html

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [INCOMPLETE][45] ([i915#198]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@gem_softpin@noreloc-s3.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl3/igt@gem_softpin@noreloc-s3.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-skl:          [DMESG-WARN][47] ([i915#1436] / [i915#716]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@gen9_exec_parse@allowed-all.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl1/igt@gen9_exec_parse@allowed-all.html

  * {igt@kms_async_flips@alternate-sync-async-flip}:
    - shard-tglb:         [FAIL][49] ([i915#2521]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb1/igt@kms_async_flips@alternate-sync-async-flip.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-tglb6/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-random:
    - shard-skl:          [FAIL][51] ([i915#54]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [FAIL][53] ([i915#2346]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-tglb:         [FAIL][55] ([i915#2346]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb8/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_cursor_legacy@short-flip-before-cursor-toggle:
    - shard-apl:          [DMESG-WARN][57] ([i915#1635] / [i915#1982]) -> [PASS][58] +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-apl7/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-apl8/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled:
    - shard-skl:          [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +3 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl1/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html

  * igt@kms_flip@basic-plain-flip@a-hdmi-a1:
    - shard-glk:          [DMESG-WARN][61] ([i915#1982]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk7/igt@kms_flip@basic-plain-flip@a-hdmi-a1.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-glk7/igt@kms_flip@basic-plain-flip@a-hdmi-a1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
    - shard-skl:          [FAIL][63] ([i915#2122]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
    - shard-snb:          [FAIL][65] ([i915#2546]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-snb7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-snb7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][67] ([fdo#108145] / [i915#265]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][69] ([fdo#109441]) -> [PASS][70] +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_vblank@pipe-c-query-forked-busy:
    - shard-hsw:          [DMESG-WARN][71] ([i915#1982]) -> [PASS][72] +2 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw6/igt@kms_vblank@pipe-c-query-forked-busy.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-hsw7/igt@kms_vblank@pipe-c-query-forked-busy.html
    - shard-iclb:         [DMESG-WARN][73] ([i915#1982]) -> [PASS][74] +1 similar issue
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb7/igt@kms_vblank@pipe-c-query-forked-busy.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-iclb1/igt@kms_vblank@pipe-c-query-forked-busy.html

  * igt@perf@short-reads:
    - shard-skl:          [FAIL][75] ([i915#51]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl4/igt@perf@short-reads.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl10/igt@perf@short-reads.html

  
#### Warnings ####

  * igt@core_hotunplug@hotrebind-lateclose:
    - shard-hsw:          [WARN][77] ([i915#2283]) -> [FAIL][78] ([i915#2644])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw4/igt@core_hotunplug@hotrebind-lateclose.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-hsw6/igt@core_hotunplug@hotrebind-lateclose.html

  * igt@gem_exec_create@forked:
    - shard-hsw:          [FAIL][79] -> [FAIL][80] ([i915#1888])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw8/igt@gem_exec_create@forked.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-hsw2/igt@gem_exec_create@forked.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [SKIP][81] ([fdo#109349]) -> [DMESG-WARN][82] ([i915#1226])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-apl:          [INCOMPLETE][83] ([i915#1635] / [i915#2635]) -> [DMESG-WARN][84] ([i915#1635] / [i915#2635])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-apl8/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-apl2/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  * igt@runner@aborted:
    - shard-iclb:         ([FAIL][85], [FAIL][86], [FAIL][87]) ([i915#1814] / [i915#2439] / [i915#483]) -> ([FAIL][88], [FAIL][89], [FAIL][90], [FAIL][91]) ([i915#1814] / [i915#2426] / [i915#2439] / [i915#409] / [i915#483])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb6/igt@runner@aborted.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb3/igt@runner@aborted.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb2/igt@runner@aborted.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-iclb1/igt@runner@aborted.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-iclb6/igt@runner@aborted.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-iclb3/igt@runner@aborted.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-iclb7/igt@runner@aborted.html
    - shard-glk:          ([FAIL][92], [FAIL][93], [FAIL][94]) ([i915#1611] / [i915#1814] / [i915#2439] / [k.org#202321]) -> ([FAIL][95], [FAIL][96], [FAIL][97]) ([i915#1611] / [i915#1814] / [i915#2439] / [i915#483] / [k.org#202321])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk4/igt@runner@aborted.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk2/igt@runner@aborted.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk6/igt@runner@aborted.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-glk8/igt@runner@aborted.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-glk1/igt@runner@aborted.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-glk3/igt@runner@aborted.html
    - shard-skl:          ([FAIL][98], [FAIL][99]) ([i915#1436] / [i915#1611] / [i915#2439] / [i915#483]) -> [FAIL][100] ([i915#1611] / [i915#2439])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@runner@aborted.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl6/igt@runner@aborted.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/shard-skl8/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
  [i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598
  [i915#2635]: https://gitlab.freedesktop.org/drm/intel/issues/2635
  [i915#2644]: https://gitlab.freedesktop.org/drm/intel/issues/2644
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
  [i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
  [i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
  [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9312 -> Patchwork_18894

  CI-20190529: 20190529
  CI_DRM_9312: 88b74d59a27aa168f7cd2dec199c33ee71fe8bb0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5847: 8cffaebec5228a5042cc6928ac582a0589e2de3e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18894: 3d231cbcc15eccab10761eba9bff4851d19a0905 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18894/index.html

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[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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Re: [Intel-gfx] [PATCH 1/9] drm/i915: remove last users of I915_READ_FW()

[Rodrigo Vivi]

On Thu, Nov 12, 2020 at 01:44:34PM +0200, Jani Nikula wrote:
> Use the preferred intel_uncore_read_fw() instead.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 77e76b665098..7cbca268cb61 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1238,10 +1238,10 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
>  		u32 rpdown, rpdownei;
>  
>  		intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> -		rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
> -		rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
> -		rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
> -		rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
> +		rpup = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
> +		rpupei = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
> +		rpdown = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
> +		rpdownei = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
>  		intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>  
>  		seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
> -- 
> 2.20.1
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 2/9] drm/i915: remove last traces of I915_READ_FW() and I915_WRITE_FW()

[Rodrigo Vivi]

On Thu, Nov 12, 2020 at 01:44:35PM +0200, Jani Nikula wrote:
> Good riddance! Remove the macros and their remaining references in
> comments.
> 
> intel_uncore_read_fw() and intel_uncore_write_fw() should be used
> instead.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h     | 29 -----------------------------
>  drivers/gpu/drm/i915/intel_uncore.c |  2 +-
>  drivers/gpu/drm/i915/intel_uncore.h |  2 +-
>  3 files changed, 2 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 15be8debae54..fecb5899cbac 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1978,35 +1978,6 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data,
>  
>  #define POSTING_READ(reg__)	__I915_REG_OP(posting_read, dev_priv, (reg__))
>  
> -/* These are untraced mmio-accessors that are only valid to be used inside
> - * critical sections, such as inside IRQ handlers, where forcewake is explicitly
> - * controlled.
> - *
> - * Think twice, and think again, before using these.
> - *
> - * As an example, these accessors can possibly be used between:
> - *
> - * spin_lock_irq(&dev_priv->uncore.lock);
> - * intel_uncore_forcewake_get__locked();
> - *
> - * and
> - *
> - * intel_uncore_forcewake_put__locked();
> - * spin_unlock_irq(&dev_priv->uncore.lock);
> - *
> - *
> - * Note: some registers may not need forcewake held, so
> - * intel_uncore_forcewake_{get,put} can be omitted, see
> - * intel_uncore_forcewake_for_reg().
> - *
> - * Certain architectures will die if the same cacheline is concurrently accessed
> - * by different clients (e.g. on Ivybridge). Access to registers should
> - * therefore generally be serialised, by either the dev_priv->uncore.lock or
> - * a more localised lock guarding all access to that bank of registers.
> - */
> -#define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
> -#define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
> -
>  /* i915_mm.c */
>  int remap_io_mapping(struct vm_area_struct *vma,
>  		     unsigned long addr, unsigned long pfn, unsigned long size,
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 1c14a07eba7d..ef40edfff412 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2070,7 +2070,7 @@ int i915_reg_read_ioctl(struct drm_device *dev,
>   * This routine waits until the target register @reg contains the expected
>   * @value after applying the @mask, i.e. it waits until ::
>   *
> - *     (I915_READ_FW(reg) & mask) == value
> + *     (intel_uncore_read_fw(uncore, reg) & mask) == value
>   *
>   * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
>   * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index bd2467284295..5dcb7f4183b2 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -216,7 +216,7 @@ void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
>  
>  /*
>   * Like above but the caller must manage the uncore.lock itself.
> - * Must be used with I915_READ_FW and friends.
> + * Must be used with intel_uncore_read_fw() and friends.
>   */
>  void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
>  					enum forcewake_domains domains);
> -- 
> 2.20.1
> 
> _______________________________________________
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Re: [Intel-gfx] [PATCH 3/9] drm/i915/cdclk: prefer intel_de_write() over I915_WRITE()

[Rodrigo Vivi]

On Thu, Nov 12, 2020 at 01:44:36PM +0200, Jani Nikula wrote:
> Let's try to not add new ones while we're phasing out I915_READ() and
> I915_WRITE().
> 
> Fixes: 27a6bc802bd9 ("drm/i915/dg1: Initialize RAWCLK properly")
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index c449d28d0560..088d5908176c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2710,8 +2710,8 @@ static int dg1_rawclk(struct drm_i915_private *dev_priv)
>  	 * DG1 always uses a 38.4 MHz rawclk.  The bspec tells us
>  	 * "Program Numerator=2, Denominator=4, Divider=37 decimal."
>  	 */
> -	I915_WRITE(PCH_RAWCLK_FREQ,
> -		   CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
> +	intel_de_write(dev_priv, PCH_RAWCLK_FREQ,
> +		       CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
>  
>  	return 38400;
>  }
> -- 
> 2.20.1
> 
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Re: [Intel-gfx] [PATCH 4/9] drm/i915/debugfs: replace I915_READ()+I915_WRITE() with intel_uncore_rmw()

[Rodrigo Vivi]

On Thu, Nov 12, 2020 at 01:44:37PM +0200, Jani Nikula wrote:
> Remove the last I915_WRITE() use in i915_debugfs.c.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 8 ++------
>  1 file changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 7cbca268cb61..151734a1a496 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1562,13 +1562,9 @@ i915_cache_sharing_set(void *data, u64 val)
>  	drm_dbg(&dev_priv->drm,
>  		"Manually setting uncore sharing to %llu\n", val);
>  	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
> -		u32 snpcr;
> -
>  		/* Update the cache sharing policy here as well */
> -		snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
> -		snpcr &= ~GEN6_MBC_SNPCR_MASK;
> -		snpcr |= val << GEN6_MBC_SNPCR_SHIFT;
> -		I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
> +		intel_uncore_rmw(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR,
> +				 GEN6_MBC_SNPCR_MASK, val << GEN6_MBC_SNPCR_SHIFT);
>  	}
>  
>  	return 0;
> -- 
> 2.20.1
> 
> _______________________________________________
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Re: [Intel-gfx] [PATCH 5/9] drm/i915/debugfs: replace I915_READ() with intel_uncore_read()

[Rodrigo Vivi]

On Thu, Nov 12, 2020 at 01:44:38PM +0200, Jani Nikula wrote:
> Another straggler with I915_READ() uses gone.
> 
> Arguably some of these should use intel_de_read(), however not
> all. Prioritize I915_READ() removal in general over migrating to the
> pedantically correct replacement right away.

I agree!

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 214 ++++++++++++++--------------
>  1 file changed, 107 insertions(+), 107 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 151734a1a496..a8b0a67250b5 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -397,37 +397,37 @@ static void gen8_display_interrupt_info(struct seq_file *m)
>  		}
>  		seq_printf(m, "Pipe %c IMR:\t%08x\n",
>  			   pipe_name(pipe),
> -			   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
> +			   intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)));
>  		seq_printf(m, "Pipe %c IIR:\t%08x\n",
>  			   pipe_name(pipe),
> -			   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
> +			   intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)));
>  		seq_printf(m, "Pipe %c IER:\t%08x\n",
>  			   pipe_name(pipe),
> -			   I915_READ(GEN8_DE_PIPE_IER(pipe)));
> +			   intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IER(pipe)));
>  
>  		intel_display_power_put(dev_priv, power_domain, wakeref);
>  	}
>  
>  	seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
> -		   I915_READ(GEN8_DE_PORT_IMR));
> +		   intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR));
>  	seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
> -		   I915_READ(GEN8_DE_PORT_IIR));
> +		   intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR));
>  	seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
> -		   I915_READ(GEN8_DE_PORT_IER));
> +		   intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IER));
>  
>  	seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
> -		   I915_READ(GEN8_DE_MISC_IMR));
> +		   intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IMR));
>  	seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
> -		   I915_READ(GEN8_DE_MISC_IIR));
> +		   intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR));
>  	seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
> -		   I915_READ(GEN8_DE_MISC_IER));
> +		   intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IER));
>  
>  	seq_printf(m, "PCU interrupt mask:\t%08x\n",
> -		   I915_READ(GEN8_PCU_IMR));
> +		   intel_uncore_read(&dev_priv->uncore, GEN8_PCU_IMR));
>  	seq_printf(m, "PCU interrupt identity:\t%08x\n",
> -		   I915_READ(GEN8_PCU_IIR));
> +		   intel_uncore_read(&dev_priv->uncore, GEN8_PCU_IIR));
>  	seq_printf(m, "PCU interrupt enable:\t%08x\n",
> -		   I915_READ(GEN8_PCU_IER));
> +		   intel_uncore_read(&dev_priv->uncore, GEN8_PCU_IER));
>  }
>  
>  static int i915_interrupt_info(struct seq_file *m, void *data)
> @@ -443,16 +443,16 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>  		intel_wakeref_t pref;
>  
>  		seq_printf(m, "Master Interrupt Control:\t%08x\n",
> -			   I915_READ(GEN8_MASTER_IRQ));
> +			   intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ));
>  
>  		seq_printf(m, "Display IER:\t%08x\n",
> -			   I915_READ(VLV_IER));
> +			   intel_uncore_read(&dev_priv->uncore, VLV_IER));
>  		seq_printf(m, "Display IIR:\t%08x\n",
> -			   I915_READ(VLV_IIR));
> +			   intel_uncore_read(&dev_priv->uncore, VLV_IIR));
>  		seq_printf(m, "Display IIR_RW:\t%08x\n",
> -			   I915_READ(VLV_IIR_RW));
> +			   intel_uncore_read(&dev_priv->uncore, VLV_IIR_RW));
>  		seq_printf(m, "Display IMR:\t%08x\n",
> -			   I915_READ(VLV_IMR));
> +			   intel_uncore_read(&dev_priv->uncore, VLV_IMR));
>  		for_each_pipe(dev_priv, pipe) {
>  			enum intel_display_power_domain power_domain;
>  
> @@ -467,71 +467,71 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>  
>  			seq_printf(m, "Pipe %c stat:\t%08x\n",
>  				   pipe_name(pipe),
> -				   I915_READ(PIPESTAT(pipe)));
> +				   intel_uncore_read(&dev_priv->uncore, PIPESTAT(pipe)));
>  
>  			intel_display_power_put(dev_priv, power_domain, pref);
>  		}
>  
>  		pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
>  		seq_printf(m, "Port hotplug:\t%08x\n",
> -			   I915_READ(PORT_HOTPLUG_EN));
> +			   intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN));
>  		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
> -			   I915_READ(VLV_DPFLIPSTAT));
> +			   intel_uncore_read(&dev_priv->uncore, VLV_DPFLIPSTAT));
>  		seq_printf(m, "DPINVGTT:\t%08x\n",
> -			   I915_READ(DPINVGTT));
> +			   intel_uncore_read(&dev_priv->uncore, DPINVGTT));
>  		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref);
>  
>  		for (i = 0; i < 4; i++) {
>  			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
> -				   i, I915_READ(GEN8_GT_IMR(i)));
> +				   i, intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(i)));
>  			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
> -				   i, I915_READ(GEN8_GT_IIR(i)));
> +				   i, intel_uncore_read(&dev_priv->uncore, GEN8_GT_IIR(i)));
>  			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
> -				   i, I915_READ(GEN8_GT_IER(i)));
> +				   i, intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(i)));
>  		}
>  
>  		seq_printf(m, "PCU interrupt mask:\t%08x\n",
> -			   I915_READ(GEN8_PCU_IMR));
> +			   intel_uncore_read(&dev_priv->uncore, GEN8_PCU_IMR));
>  		seq_printf(m, "PCU interrupt identity:\t%08x\n",
> -			   I915_READ(GEN8_PCU_IIR));
> +			   intel_uncore_read(&dev_priv->uncore, GEN8_PCU_IIR));
>  		seq_printf(m, "PCU interrupt enable:\t%08x\n",
> -			   I915_READ(GEN8_PCU_IER));
> +			   intel_uncore_read(&dev_priv->uncore, GEN8_PCU_IER));
>  	} else if (INTEL_GEN(dev_priv) >= 11) {
>  		if (HAS_MASTER_UNIT_IRQ(dev_priv))
>  			seq_printf(m, "Master Unit Interrupt Control:  %08x\n",
> -				   I915_READ(DG1_MSTR_UNIT_INTR));
> +				   intel_uncore_read(&dev_priv->uncore, DG1_MSTR_UNIT_INTR));
>  
>  		seq_printf(m, "Master Interrupt Control:  %08x\n",
> -			   I915_READ(GEN11_GFX_MSTR_IRQ));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ));
>  
>  		seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
> -			   I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_RENDER_COPY_INTR_ENABLE));
>  		seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
> -			   I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_VCS_VECS_INTR_ENABLE));
>  		seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
> -			   I915_READ(GEN11_GUC_SG_INTR_ENABLE));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_GUC_SG_INTR_ENABLE));
>  		seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
> -			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE));
>  		seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
> -			   I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE));
>  		seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
> -			   I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_GUNIT_CSME_INTR_ENABLE));
>  
>  		seq_printf(m, "Display Interrupt Control:\t%08x\n",
> -			   I915_READ(GEN11_DISPLAY_INT_CTL));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL));
>  
>  		gen8_display_interrupt_info(m);
>  	} else if (INTEL_GEN(dev_priv) >= 8) {
>  		seq_printf(m, "Master Interrupt Control:\t%08x\n",
> -			   I915_READ(GEN8_MASTER_IRQ));
> +			   intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ));
>  
>  		for (i = 0; i < 4; i++) {
>  			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
> -				   i, I915_READ(GEN8_GT_IMR(i)));
> +				   i, intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(i)));
>  			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
> -				   i, I915_READ(GEN8_GT_IIR(i)));
> +				   i, intel_uncore_read(&dev_priv->uncore, GEN8_GT_IIR(i)));
>  			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
> -				   i, I915_READ(GEN8_GT_IER(i)));
> +				   i, intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(i)));
>  		}
>  
>  		gen8_display_interrupt_info(m);
> @@ -539,13 +539,13 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>  		intel_wakeref_t pref;
>  
>  		seq_printf(m, "Display IER:\t%08x\n",
> -			   I915_READ(VLV_IER));
> +			   intel_uncore_read(&dev_priv->uncore, VLV_IER));
>  		seq_printf(m, "Display IIR:\t%08x\n",
> -			   I915_READ(VLV_IIR));
> +			   intel_uncore_read(&dev_priv->uncore, VLV_IIR));
>  		seq_printf(m, "Display IIR_RW:\t%08x\n",
> -			   I915_READ(VLV_IIR_RW));
> +			   intel_uncore_read(&dev_priv->uncore, VLV_IIR_RW));
>  		seq_printf(m, "Display IMR:\t%08x\n",
> -			   I915_READ(VLV_IMR));
> +			   intel_uncore_read(&dev_priv->uncore, VLV_IMR));
>  		for_each_pipe(dev_priv, pipe) {
>  			enum intel_display_power_domain power_domain;
>  
> @@ -560,87 +560,87 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>  
>  			seq_printf(m, "Pipe %c stat:\t%08x\n",
>  				   pipe_name(pipe),
> -				   I915_READ(PIPESTAT(pipe)));
> +				   intel_uncore_read(&dev_priv->uncore, PIPESTAT(pipe)));
>  			intel_display_power_put(dev_priv, power_domain, pref);
>  		}
>  
>  		seq_printf(m, "Master IER:\t%08x\n",
> -			   I915_READ(VLV_MASTER_IER));
> +			   intel_uncore_read(&dev_priv->uncore, VLV_MASTER_IER));
>  
>  		seq_printf(m, "Render IER:\t%08x\n",
> -			   I915_READ(GTIER));
> +			   intel_uncore_read(&dev_priv->uncore, GTIER));
>  		seq_printf(m, "Render IIR:\t%08x\n",
> -			   I915_READ(GTIIR));
> +			   intel_uncore_read(&dev_priv->uncore, GTIIR));
>  		seq_printf(m, "Render IMR:\t%08x\n",
> -			   I915_READ(GTIMR));
> +			   intel_uncore_read(&dev_priv->uncore, GTIMR));
>  
>  		seq_printf(m, "PM IER:\t\t%08x\n",
> -			   I915_READ(GEN6_PMIER));
> +			   intel_uncore_read(&dev_priv->uncore, GEN6_PMIER));
>  		seq_printf(m, "PM IIR:\t\t%08x\n",
> -			   I915_READ(GEN6_PMIIR));
> +			   intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR));
>  		seq_printf(m, "PM IMR:\t\t%08x\n",
> -			   I915_READ(GEN6_PMIMR));
> +			   intel_uncore_read(&dev_priv->uncore, GEN6_PMIMR));
>  
>  		pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
>  		seq_printf(m, "Port hotplug:\t%08x\n",
> -			   I915_READ(PORT_HOTPLUG_EN));
> +			   intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN));
>  		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
> -			   I915_READ(VLV_DPFLIPSTAT));
> +			   intel_uncore_read(&dev_priv->uncore, VLV_DPFLIPSTAT));
>  		seq_printf(m, "DPINVGTT:\t%08x\n",
> -			   I915_READ(DPINVGTT));
> +			   intel_uncore_read(&dev_priv->uncore, DPINVGTT));
>  		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref);
>  
>  	} else if (!HAS_PCH_SPLIT(dev_priv)) {
>  		seq_printf(m, "Interrupt enable:    %08x\n",
> -			   I915_READ(GEN2_IER));
> +			   intel_uncore_read(&dev_priv->uncore, GEN2_IER));
>  		seq_printf(m, "Interrupt identity:  %08x\n",
> -			   I915_READ(GEN2_IIR));
> +			   intel_uncore_read(&dev_priv->uncore, GEN2_IIR));
>  		seq_printf(m, "Interrupt mask:      %08x\n",
> -			   I915_READ(GEN2_IMR));
> +			   intel_uncore_read(&dev_priv->uncore, GEN2_IMR));
>  		for_each_pipe(dev_priv, pipe)
>  			seq_printf(m, "Pipe %c stat:         %08x\n",
>  				   pipe_name(pipe),
> -				   I915_READ(PIPESTAT(pipe)));
> +				   intel_uncore_read(&dev_priv->uncore, PIPESTAT(pipe)));
>  	} else {
>  		seq_printf(m, "North Display Interrupt enable:		%08x\n",
> -			   I915_READ(DEIER));
> +			   intel_uncore_read(&dev_priv->uncore, DEIER));
>  		seq_printf(m, "North Display Interrupt identity:	%08x\n",
> -			   I915_READ(DEIIR));
> +			   intel_uncore_read(&dev_priv->uncore, DEIIR));
>  		seq_printf(m, "North Display Interrupt mask:		%08x\n",
> -			   I915_READ(DEIMR));
> +			   intel_uncore_read(&dev_priv->uncore, DEIMR));
>  		seq_printf(m, "South Display Interrupt enable:		%08x\n",
> -			   I915_READ(SDEIER));
> +			   intel_uncore_read(&dev_priv->uncore, SDEIER));
>  		seq_printf(m, "South Display Interrupt identity:	%08x\n",
> -			   I915_READ(SDEIIR));
> +			   intel_uncore_read(&dev_priv->uncore, SDEIIR));
>  		seq_printf(m, "South Display Interrupt mask:		%08x\n",
> -			   I915_READ(SDEIMR));
> +			   intel_uncore_read(&dev_priv->uncore, SDEIMR));
>  		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
> -			   I915_READ(GTIER));
> +			   intel_uncore_read(&dev_priv->uncore, GTIER));
>  		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
> -			   I915_READ(GTIIR));
> +			   intel_uncore_read(&dev_priv->uncore, GTIIR));
>  		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
> -			   I915_READ(GTIMR));
> +			   intel_uncore_read(&dev_priv->uncore, GTIMR));
>  	}
>  
>  	if (INTEL_GEN(dev_priv) >= 11) {
>  		seq_printf(m, "RCS Intr Mask:\t %08x\n",
> -			   I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_RCS0_RSVD_INTR_MASK));
>  		seq_printf(m, "BCS Intr Mask:\t %08x\n",
> -			   I915_READ(GEN11_BCS_RSVD_INTR_MASK));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_BCS_RSVD_INTR_MASK));
>  		seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
> -			   I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_VCS0_VCS1_INTR_MASK));
>  		seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
> -			   I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_VCS2_VCS3_INTR_MASK));
>  		seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
> -			   I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_VECS0_VECS1_INTR_MASK));
>  		seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
> -			   I915_READ(GEN11_GUC_SG_INTR_MASK));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_GUC_SG_INTR_MASK));
>  		seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
> -			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK));
>  		seq_printf(m, "Crypto Intr Mask:\t %08x\n",
> -			   I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_CRYPTO_RSVD_INTR_MASK));
>  		seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
> -			   I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
> +			   intel_uncore_read(&dev_priv->uncore, GEN11_GUNIT_CSME_INTR_MASK));
>  
>  	} else if (INTEL_GEN(dev_priv) >= 6) {
>  		for_each_uabi_engine(engine, dev_priv) {
> @@ -802,7 +802,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		u32 rpmodectl, freq_sts;
>  
> -		rpmodectl = I915_READ(GEN6_RP_CONTROL);
> +		rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL);
>  		seq_printf(m, "Video Turbo Mode: %s\n",
>  			   yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
>  		seq_printf(m, "HW control enabled: %s\n",
> @@ -847,19 +847,19 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
>  		int max_freq;
>  
> -		rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> +		rp_state_limits = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_LIMITS);
>  		if (IS_GEN9_LP(dev_priv)) {
> -			rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> -			gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
> +			rp_state_cap = intel_uncore_read(&dev_priv->uncore, BXT_RP_STATE_CAP);
> +			gt_perf_status = intel_uncore_read(&dev_priv->uncore, BXT_GT_PERF_STATUS);
>  		} else {
> -			rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> -			gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
> +			rp_state_cap = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_CAP);
> +			gt_perf_status = intel_uncore_read(&dev_priv->uncore, GEN6_GT_PERF_STATUS);
>  		}
>  
>  		/* RPSTAT1 is in the GT power well */
>  		intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>  
> -		reqf = I915_READ(GEN6_RPNSWREQ);
> +		reqf = intel_uncore_read(&dev_priv->uncore, GEN6_RPNSWREQ);
>  		if (INTEL_GEN(dev_priv) >= 9)
>  			reqf >>= 23;
>  		else {
> @@ -871,24 +871,24 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		}
>  		reqf = intel_gpu_freq(rps, reqf);
>  
> -		rpmodectl = I915_READ(GEN6_RP_CONTROL);
> -		rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
> -		rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
> -
> -		rpstat = I915_READ(GEN6_RPSTAT1);
> -		rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
> -		rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
> -		rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
> -		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
> -		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
> -		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
> +		rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL);
> +		rpinclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_UP_THRESHOLD);
> +		rpdeclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_DOWN_THRESHOLD);
> +
> +		rpstat = intel_uncore_read(&dev_priv->uncore, GEN6_RPSTAT1);
> +		rpupei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
> +		rpcurup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
> +		rpprevup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
> +		rpdownei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
> +		rpcurdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
> +		rpprevdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
>  		cagf = intel_rps_read_actual_frequency(rps);
>  
>  		intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>  
>  		if (INTEL_GEN(dev_priv) >= 11) {
> -			pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
> -			pm_imr = I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK);
> +			pm_ier = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
> +			pm_imr = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
>  			/*
>  			 * The equivalent to the PM ISR & IIR cannot be read
>  			 * without affecting the current state of the system
> @@ -896,17 +896,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  			pm_isr = 0;
>  			pm_iir = 0;
>  		} else if (INTEL_GEN(dev_priv) >= 8) {
> -			pm_ier = I915_READ(GEN8_GT_IER(2));
> -			pm_imr = I915_READ(GEN8_GT_IMR(2));
> -			pm_isr = I915_READ(GEN8_GT_ISR(2));
> -			pm_iir = I915_READ(GEN8_GT_IIR(2));
> +			pm_ier = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(2));
> +			pm_imr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(2));
> +			pm_isr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_ISR(2));
> +			pm_iir = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IIR(2));
>  		} else {
> -			pm_ier = I915_READ(GEN6_PMIER);
> -			pm_imr = I915_READ(GEN6_PMIMR);
> -			pm_isr = I915_READ(GEN6_PMISR);
> -			pm_iir = I915_READ(GEN6_PMIIR);
> +			pm_ier = intel_uncore_read(&dev_priv->uncore, GEN6_PMIER);
> +			pm_imr = intel_uncore_read(&dev_priv->uncore, GEN6_PMIMR);
> +			pm_isr = intel_uncore_read(&dev_priv->uncore, GEN6_PMISR);
> +			pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
>  		}
> -		pm_mask = I915_READ(GEN6_PMINTRMSK);
> +		pm_mask = intel_uncore_read(&dev_priv->uncore, GEN6_PMINTRMSK);
>  
>  		seq_printf(m, "Video Turbo Mode: %s\n",
>  			   yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
> @@ -1540,7 +1540,7 @@ i915_cache_sharing_get(void *data, u64 *val)
>  		return -ENODEV;
>  
>  	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
> -		snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
> +		snpcr = intel_uncore_read(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR);
>  
>  	*val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
>  
> -- 
> 2.20.1
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 1/9] drm/i915: remove last users of I915_READ_FW()

[Chris Wilson]

Quoting Jani Nikula (2020-11-12 11:44:34)
> Use the preferred intel_uncore_read_fw() instead.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 77e76b665098..7cbca268cb61 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1238,10 +1238,10 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
>                 u32 rpdown, rpdownei;
>  
>                 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> -               rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
> -               rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
> -               rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
> -               rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
> +               rpup = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
> +               rpupei = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
> +               rpdown = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
> +               rpdownei = intel_uncore_read_fw(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
>                 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);

This information is no longer [as] relevant. We can just remove the if
block.
-Chris
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Re: [Intel-gfx] [PATCH 2/9] drm/i915: remove last traces of I915_READ_FW() and I915_WRITE_FW()

[Chris Wilson]

Quoting Jani Nikula (2020-11-12 11:44:35)
> Good riddance! Remove the macros and their remaining references in
> comments.
> 
> intel_uncore_read_fw() and intel_uncore_write_fw() should be used
> instead.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Given the previous patch removing the last user,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [Intel-gfx] [PATCH 6/9] drm/i915/suspend: replace I915_READ()/WRITE() with intel_de_read()/write()

[Rodrigo Vivi]

On Thu, Nov 12, 2020 at 01:44:39PM +0200, Jani Nikula wrote:
> Another straggler with I915_READ() and I915_WRITE() uses gone.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_suspend.c | 33 +++++++++++++++--------------
>  1 file changed, 17 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index db2111fc809e..63212df33c9e 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -24,6 +24,7 @@
>   * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>   */
>  
> +#include "display/intel_de.h"
>  #include "display/intel_fbc.h"
>  #include "display/intel_gmbus.h"
>  #include "display/intel_vga.h"
> @@ -39,21 +40,21 @@ static void intel_save_swf(struct drm_i915_private *dev_priv)
>  	/* Scratch space */
>  	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
>  		for (i = 0; i < 7; i++) {
> -			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
> -			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> +			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i));
> +			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
>  		}
>  		for (i = 0; i < 3; i++)
> -			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
> +			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
>  	} else if (IS_GEN(dev_priv, 2)) {
>  		for (i = 0; i < 7; i++)
> -			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> +			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
>  	} else if (HAS_GMCH(dev_priv)) {
>  		for (i = 0; i < 16; i++) {
> -			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
> -			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> +			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i));
> +			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
>  		}
>  		for (i = 0; i < 3; i++)
> -			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
> +			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
>  	}
>  }
>  
> @@ -64,21 +65,21 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv)
>  	/* Scratch space */
>  	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
>  		for (i = 0; i < 7; i++) {
> -			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
> -			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> +			intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]);
> +			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
>  		}
>  		for (i = 0; i < 3; i++)
> -			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
> +			intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
>  	} else if (IS_GEN(dev_priv, 2)) {
>  		for (i = 0; i < 7; i++)
> -			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> +			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
>  	} else if (HAS_GMCH(dev_priv)) {
>  		for (i = 0; i < 16; i++) {
> -			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
> -			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> +			intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]);
> +			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
>  		}
>  		for (i = 0; i < 3; i++)
> -			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
> +			intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
>  	}
>  }
>  
> @@ -88,7 +89,7 @@ void i915_save_display(struct drm_i915_private *dev_priv)
>  
>  	/* Display arbitration control */
>  	if (INTEL_GEN(dev_priv) <= 4)
> -		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
> +		dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB);
>  
>  	if (IS_GEN(dev_priv, 4))
>  		pci_read_config_word(pdev, GCDGMBUS,
> @@ -109,7 +110,7 @@ void i915_restore_display(struct drm_i915_private *dev_priv)
>  
>  	/* Display arbitration */
>  	if (INTEL_GEN(dev_priv) <= 4)
> -		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
> +		intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB);
>  
>  	/* only restore FBC info on the platform that supports FBC*/
>  	intel_fbc_global_disable(dev_priv);
> -- 
> 2.20.1
> 
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Re: [Intel-gfx] [PATCH 4/9] drm/i915/debugfs: replace I915_READ()+I915_WRITE() with intel_uncore_rmw()

[Chris Wilson]

Quoting Jani Nikula (2020-11-12 11:44:37)
> Remove the last I915_WRITE() use in i915_debugfs.c.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 8 ++------
>  1 file changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 7cbca268cb61..151734a1a496 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1562,13 +1562,9 @@ i915_cache_sharing_set(void *data, u64 val)
>         drm_dbg(&dev_priv->drm,
>                 "Manually setting uncore sharing to %llu\n", val);
>         with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
> -               u32 snpcr;
> -
>                 /* Update the cache sharing policy here as well */
> -               snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
> -               snpcr &= ~GEN6_MBC_SNPCR_MASK;
> -               snpcr |= val << GEN6_MBC_SNPCR_SHIFT;
> -               I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
> +               intel_uncore_rmw(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR,
> +                                GEN6_MBC_SNPCR_MASK, val << GEN6_MBC_SNPCR_SHIFT);
>         }

Remove the braces, or remove the entire i915_cache_sharing file. A debug
interface with no validation or user.
-Chris
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Re: [Intel-gfx] [PATCH 7/9] drm/i915/pm: replace I915_READ()/WRITE() with intel_uncore_read()/write()

[Rodrigo Vivi]

On Thu, Nov 12, 2020 at 01:44:40PM +0200, Jani Nikula wrote:
> Arguably some of these should use intel_de_read() or intel_de_write(),
> however not all. Prioritize I915_READ() and I915_WRITE() removal in
> general over migrating to the pedantically correct replacements right
> away.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 552 ++++++++++++++++----------------
>  1 file changed, 276 insertions(+), 276 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bbec56f97832..c0ed82665706 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -81,24 +81,24 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>  		 * Must match Sampler, Pixel Back End, and Media. See
>  		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
>  		 */
> -		I915_WRITE(CHICKEN_PAR1_1,
> -			   I915_READ(CHICKEN_PAR1_1) |
> +		intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
> +			   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) |

why not converting them to rmw?

>  			   SKL_DE_COMPRESSED_HASH_MODE);
>  	}
>  
>  	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
> -	I915_WRITE(CHICKEN_PAR1_1,
> -		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
> +		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
>  
>  	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
> -	I915_WRITE(GEN8_CHICKEN_DCPR_1,
> -		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
> +	intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
> +		   intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>  
>  	/*
>  	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
>  	 * Display WA #0859: skl,bxt,kbl,glk,cfl
>  	 */
> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>  		   DISP_FBC_MEMORY_WAKE);
>  }
>  
> @@ -107,21 +107,21 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
>  	gen9_init_clock_gating(dev_priv);
>  
>  	/* WaDisableSDEUnitClockGating:bxt */
> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> +	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>  
>  	/*
>  	 * FIXME:
>  	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
>  	 */
> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> +	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
>  		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
>  
>  	/*
>  	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
>  	 * to stay fully on.
>  	 */
> -	I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
> +	intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
>  		   PWM1_GATING_DIS | PWM2_GATING_DIS);
>  
>  	/*
> @@ -130,20 +130,20 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
>  	 * is off and a MMIO access is attempted by any privilege
>  	 * application, using batch buffers or any other means.
>  	 */
> -	I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950));
> +	intel_uncore_write(&dev_priv->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
>  
>  	/*
>  	 * WaFbcTurnOffFbcWatermark:bxt
>  	 * Display WA #0562: bxt
>  	 */
> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>  		   DISP_FBC_WM_DIS);
>  
>  	/*
>  	 * WaFbcHighMemBwCorruptionAvoidance:bxt
>  	 * Display WA #0883: bxt
>  	 */
> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
>  		   ILK_DPFC_DISABLE_DUMMY0);
>  }
>  
> @@ -156,7 +156,7 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
>  	 * Backlight PWM may stop in the asserted state, causing backlight
>  	 * to stay fully on.
>  	 */
> -	I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
> +	intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
>  		   PWM1_GATING_DIS | PWM2_GATING_DIS);
>  }
>  
> @@ -164,7 +164,7 @@ static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
>  {
>  	u32 tmp;
>  
> -	tmp = I915_READ(CLKCFG);
> +	tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
>  
>  	switch (tmp & CLKCFG_FSB_MASK) {
>  	case CLKCFG_FSB_533:
> @@ -194,7 +194,7 @@ static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
>  	}
>  
>  	/* detect pineview DDR3 setting */
> -	tmp = I915_READ(CSHRDDR3CTL);
> +	tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL);
>  	dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
>  }
>  
> @@ -365,39 +365,39 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
>  	u32 val;
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> -		was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
> -		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> -		POSTING_READ(FW_BLC_SELF_VLV);
> +		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
> +		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> +		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF_VLV);
>  	} else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
> -		was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
> -		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
> -		POSTING_READ(FW_BLC_SELF);
> +		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
> +		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
> +		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
>  	} else if (IS_PINEVIEW(dev_priv)) {
> -		val = I915_READ(DSPFW3);
> +		val = intel_uncore_read(&dev_priv->uncore, DSPFW3);
>  		was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
>  		if (enable)
>  			val |= PINEVIEW_SELF_REFRESH_EN;
>  		else
>  			val &= ~PINEVIEW_SELF_REFRESH_EN;
> -		I915_WRITE(DSPFW3, val);
> -		POSTING_READ(DSPFW3);
> +		intel_uncore_write(&dev_priv->uncore, DSPFW3, val);
> +		intel_uncore_posting_read(&dev_priv->uncore, DSPFW3);
>  	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
> -		was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
> +		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
>  		val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
>  			       _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
> -		I915_WRITE(FW_BLC_SELF, val);
> -		POSTING_READ(FW_BLC_SELF);
> +		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, val);
> +		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
>  	} else if (IS_I915GM(dev_priv)) {
>  		/*
>  		 * FIXME can't find a bit like this for 915G, and
>  		 * and yet it does have the related watermark in
>  		 * FW_BLC_SELF. What's going on?
>  		 */
> -		was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
> +		was_enabled = intel_uncore_read(&dev_priv->uncore, INSTPM) & INSTPM_SELF_EN;
>  		val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
>  			       _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
> -		I915_WRITE(INSTPM, val);
> -		POSTING_READ(INSTPM);
> +		intel_uncore_write(&dev_priv->uncore, INSTPM, val);
> +		intel_uncore_posting_read(&dev_priv->uncore, INSTPM);
>  	} else {
>  		return false;
>  	}
> @@ -493,20 +493,20 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
>  
>  	switch (pipe) {
>  	case PIPE_A:
> -		dsparb = I915_READ(DSPARB);
> -		dsparb2 = I915_READ(DSPARB2);
> +		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> +		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
>  		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
>  		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
>  		break;
>  	case PIPE_B:
> -		dsparb = I915_READ(DSPARB);
> -		dsparb2 = I915_READ(DSPARB2);
> +		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> +		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
>  		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
>  		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
>  		break;
>  	case PIPE_C:
> -		dsparb2 = I915_READ(DSPARB2);
> -		dsparb3 = I915_READ(DSPARB3);
> +		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
> +		dsparb3 = intel_uncore_read(&dev_priv->uncore, DSPARB3);
>  		sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
>  		sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
>  		break;
> @@ -524,7 +524,7 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
>  static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
>  			      enum i9xx_plane_id i9xx_plane)
>  {
> -	u32 dsparb = I915_READ(DSPARB);
> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
>  	int size;
>  
>  	size = dsparb & 0x7f;
> @@ -540,7 +540,7 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
>  static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
>  			      enum i9xx_plane_id i9xx_plane)
>  {
> -	u32 dsparb = I915_READ(DSPARB);
> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
>  	int size;
>  
>  	size = dsparb & 0x1ff;
> @@ -557,7 +557,7 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
>  static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
>  			      enum i9xx_plane_id i9xx_plane)
>  {
> -	u32 dsparb = I915_READ(DSPARB);
> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
>  	int size;
>  
>  	size = dsparb & 0x7f;
> @@ -910,38 +910,38 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
>  		wm = intel_calculate_wm(clock, &pnv_display_wm,
>  					pnv_display_wm.fifo_size,
>  					cpp, latency->display_sr);
> -		reg = I915_READ(DSPFW1);
> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
>  		reg &= ~DSPFW_SR_MASK;
>  		reg |= FW_WM(wm, SR);
> -		I915_WRITE(DSPFW1, reg);
> +		intel_uncore_write(&dev_priv->uncore, DSPFW1, reg);
>  		drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
>  
>  		/* cursor SR */
>  		wm = intel_calculate_wm(clock, &pnv_cursor_wm,
>  					pnv_display_wm.fifo_size,
>  					4, latency->cursor_sr);
> -		reg = I915_READ(DSPFW3);
> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
>  		reg &= ~DSPFW_CURSOR_SR_MASK;
>  		reg |= FW_WM(wm, CURSOR_SR);
> -		I915_WRITE(DSPFW3, reg);
> +		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
>  
>  		/* Display HPLL off SR */
>  		wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
>  					pnv_display_hplloff_wm.fifo_size,
>  					cpp, latency->display_hpll_disable);
> -		reg = I915_READ(DSPFW3);
> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
>  		reg &= ~DSPFW_HPLL_SR_MASK;
>  		reg |= FW_WM(wm, HPLL_SR);
> -		I915_WRITE(DSPFW3, reg);
> +		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
>  
>  		/* cursor HPLL off SR */
>  		wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
>  					pnv_display_hplloff_wm.fifo_size,
>  					4, latency->cursor_hpll_disable);
> -		reg = I915_READ(DSPFW3);
> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
>  		reg &= ~DSPFW_HPLL_CURSOR_MASK;
>  		reg |= FW_WM(wm, HPLL_CURSOR);
> -		I915_WRITE(DSPFW3, reg);
> +		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
>  		drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
>  
>  		intel_set_memory_cxsr(dev_priv, true);
> @@ -975,25 +975,25 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
>  	for_each_pipe(dev_priv, pipe)
>  		trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
>  
> -	I915_WRITE(DSPFW1,
> +	intel_uncore_write(&dev_priv->uncore, DSPFW1,
>  		   FW_WM(wm->sr.plane, SR) |
>  		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
>  		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
>  		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
> -	I915_WRITE(DSPFW2,
> +	intel_uncore_write(&dev_priv->uncore, DSPFW2,
>  		   (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
>  		   FW_WM(wm->sr.fbc, FBC_SR) |
>  		   FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
>  		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
>  		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
>  		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
> -	I915_WRITE(DSPFW3,
> +	intel_uncore_write(&dev_priv->uncore, DSPFW3,
>  		   (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
>  		   FW_WM(wm->sr.cursor, CURSOR_SR) |
>  		   FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
>  		   FW_WM(wm->hpll.plane, HPLL_SR));
>  
> -	POSTING_READ(DSPFW1);
> +	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
>  }
>  
>  #define FW_WM_VLV(value, plane) \
> @@ -1007,7 +1007,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
>  	for_each_pipe(dev_priv, pipe) {
>  		trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
>  
> -		I915_WRITE(VLV_DDL(pipe),
> +		intel_uncore_write(&dev_priv->uncore, VLV_DDL(pipe),
>  			   (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
>  			   (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
>  			   (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
> @@ -1019,35 +1019,35 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
>  	 * high order bits so that there are no out of bounds values
>  	 * present in the registers during the reprogramming.
>  	 */
> -	I915_WRITE(DSPHOWM, 0);
> -	I915_WRITE(DSPHOWM1, 0);
> -	I915_WRITE(DSPFW4, 0);
> -	I915_WRITE(DSPFW5, 0);
> -	I915_WRITE(DSPFW6, 0);
> +	intel_uncore_write(&dev_priv->uncore, DSPHOWM, 0);
> +	intel_uncore_write(&dev_priv->uncore, DSPHOWM1, 0);
> +	intel_uncore_write(&dev_priv->uncore, DSPFW4, 0);
> +	intel_uncore_write(&dev_priv->uncore, DSPFW5, 0);
> +	intel_uncore_write(&dev_priv->uncore, DSPFW6, 0);
>  
> -	I915_WRITE(DSPFW1,
> +	intel_uncore_write(&dev_priv->uncore, DSPFW1,
>  		   FW_WM(wm->sr.plane, SR) |
>  		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
>  		   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
>  		   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
> -	I915_WRITE(DSPFW2,
> +	intel_uncore_write(&dev_priv->uncore, DSPFW2,
>  		   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
>  		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
>  		   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
> -	I915_WRITE(DSPFW3,
> +	intel_uncore_write(&dev_priv->uncore, DSPFW3,
>  		   FW_WM(wm->sr.cursor, CURSOR_SR));
>  
>  	if (IS_CHERRYVIEW(dev_priv)) {
> -		I915_WRITE(DSPFW7_CHV,
> +		intel_uncore_write(&dev_priv->uncore, DSPFW7_CHV,
>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
> -		I915_WRITE(DSPFW8_CHV,
> +		intel_uncore_write(&dev_priv->uncore, DSPFW8_CHV,
>  			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
>  			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
> -		I915_WRITE(DSPFW9_CHV,
> +		intel_uncore_write(&dev_priv->uncore, DSPFW9_CHV,
>  			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
>  			   FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
> -		I915_WRITE(DSPHOWM,
> +		intel_uncore_write(&dev_priv->uncore, DSPHOWM,
>  			   FW_WM(wm->sr.plane >> 9, SR_HI) |
>  			   FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
>  			   FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
> @@ -1059,10 +1059,10 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
>  	} else {
> -		I915_WRITE(DSPFW7,
> +		intel_uncore_write(&dev_priv->uncore, DSPFW7,
>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
> -		I915_WRITE(DSPHOWM,
> +		intel_uncore_write(&dev_priv->uncore, DSPHOWM,
>  			   FW_WM(wm->sr.plane >> 9, SR_HI) |
>  			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
>  			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
> @@ -1072,7 +1072,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
>  	}
>  
> -	POSTING_READ(DSPFW1);
> +	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
>  }
>  
>  #undef FW_WM_VLV
> @@ -2309,14 +2309,14 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
>  		    srwm);
>  
>  	/* 965 has limitations... */
> -	I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
> +	intel_uncore_write(&dev_priv->uncore, DSPFW1, FW_WM(srwm, SR) |
>  		   FW_WM(8, CURSORB) |
>  		   FW_WM(8, PLANEB) |
>  		   FW_WM(8, PLANEA));
> -	I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
> +	intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) |
>  		   FW_WM(8, PLANEC_OLD));
>  	/* update cursor SR watermark */
> -	I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
> +	intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
>  
>  	if (cxsr_enabled)
>  		intel_set_memory_cxsr(dev_priv, true);
> @@ -2446,10 +2446,10 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  			srwm = 1;
>  
>  		if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
> -			I915_WRITE(FW_BLC_SELF,
> +			intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF,
>  				   FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
>  		else
> -			I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
> +			intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, srwm & 0x3f);
>  	}
>  
>  	drm_dbg_kms(&dev_priv->drm,
> @@ -2463,8 +2463,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  	fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
>  	fwater_hi = fwater_hi | (1 << 8);
>  
> -	I915_WRITE(FW_BLC, fwater_lo);
> -	I915_WRITE(FW_BLC2, fwater_hi);
> +	intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
> +	intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
>  
>  	if (enabled)
>  		intel_set_memory_cxsr(dev_priv, true);
> @@ -2487,13 +2487,13 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
>  				       &i845_wm_info,
>  				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
>  				       4, pessimal_latency_ns);
> -	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
> +	fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
>  	fwater_lo |= (3<<8) | planea_wm;
>  
>  	drm_dbg_kms(&dev_priv->drm,
>  		    "Setting FIFO watermarks - A: %d\n", planea_wm);
>  
> -	I915_WRITE(FW_BLC, fwater_lo);
> +	intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
>  }
>  
>  /* latency must be in 0.1us units. */
> @@ -3533,17 +3533,17 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
>  
>  	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
>  		previous->wm_lp[2] &= ~WM1_LP_SR_EN;
> -		I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
> +		intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, previous->wm_lp[2]);
>  		changed = true;
>  	}
>  	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
>  		previous->wm_lp[1] &= ~WM1_LP_SR_EN;
> -		I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
> +		intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, previous->wm_lp[1]);
>  		changed = true;
>  	}
>  	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
>  		previous->wm_lp[0] &= ~WM1_LP_SR_EN;
> -		I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
> +		intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, previous->wm_lp[0]);
>  		changed = true;
>  	}
>  
> @@ -3573,56 +3573,56 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
>  	_ilk_disable_lp_wm(dev_priv, dirty);
>  
>  	if (dirty & WM_DIRTY_PIPE(PIPE_A))
> -		I915_WRITE(WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
> +		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
>  	if (dirty & WM_DIRTY_PIPE(PIPE_B))
> -		I915_WRITE(WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
> +		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
>  	if (dirty & WM_DIRTY_PIPE(PIPE_C))
> -		I915_WRITE(WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
> +		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
>  
>  	if (dirty & WM_DIRTY_DDB) {
>  		if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> -			val = I915_READ(WM_MISC);
> +			val = intel_uncore_read(&dev_priv->uncore, WM_MISC);
>  			if (results->partitioning == INTEL_DDB_PART_1_2)
>  				val &= ~WM_MISC_DATA_PARTITION_5_6;
>  			else
>  				val |= WM_MISC_DATA_PARTITION_5_6;
> -			I915_WRITE(WM_MISC, val);
> +			intel_uncore_write(&dev_priv->uncore, WM_MISC, val);
>  		} else {
> -			val = I915_READ(DISP_ARB_CTL2);
> +			val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2);
>  			if (results->partitioning == INTEL_DDB_PART_1_2)
>  				val &= ~DISP_DATA_PARTITION_5_6;
>  			else
>  				val |= DISP_DATA_PARTITION_5_6;
> -			I915_WRITE(DISP_ARB_CTL2, val);
> +			intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL2, val);
>  		}
>  	}
>  
>  	if (dirty & WM_DIRTY_FBC) {
> -		val = I915_READ(DISP_ARB_CTL);
> +		val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL);
>  		if (results->enable_fbc_wm)
>  			val &= ~DISP_FBC_WM_DIS;
>  		else
>  			val |= DISP_FBC_WM_DIS;
> -		I915_WRITE(DISP_ARB_CTL, val);
> +		intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, val);
>  	}
>  
>  	if (dirty & WM_DIRTY_LP(1) &&
>  	    previous->wm_lp_spr[0] != results->wm_lp_spr[0])
> -		I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
> +		intel_uncore_write(&dev_priv->uncore, WM1S_LP_ILK, results->wm_lp_spr[0]);
>  
>  	if (INTEL_GEN(dev_priv) >= 7) {
>  		if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
> -			I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
> +			intel_uncore_write(&dev_priv->uncore, WM2S_LP_IVB, results->wm_lp_spr[1]);
>  		if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
> -			I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
> +			intel_uncore_write(&dev_priv->uncore, WM3S_LP_IVB, results->wm_lp_spr[2]);
>  	}
>  
>  	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
> -		I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
> +		intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, results->wm_lp[0]);
>  	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
> -		I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
> +		intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, results->wm_lp[1]);
>  	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
> -		I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
> +		intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, results->wm_lp[2]);
>  
>  	dev_priv->wm.hw = *results;
>  }
> @@ -3639,7 +3639,7 @@ u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
>  	u8 enabled_slices_mask = 0;
>  
>  	for (i = 0; i < max_slices; i++) {
> -		if (I915_READ(DBUF_CTL_S(i)) & DBUF_POWER_STATE)
> +		if (intel_uncore_read(&dev_priv->uncore, DBUF_CTL_S(i)) & DBUF_POWER_STATE)
>  			enabled_slices_mask |= BIT(i);
>  	}
>  
> @@ -4307,12 +4307,12 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>  
>  	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
>  	if (plane_id == PLANE_CURSOR) {
> -		val = I915_READ(CUR_BUF_CFG(pipe));
> +		val = intel_uncore_read(&dev_priv->uncore, CUR_BUF_CFG(pipe));
>  		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
>  		return;
>  	}
>  
> -	val = I915_READ(PLANE_CTL(pipe, plane_id));
> +	val = intel_uncore_read(&dev_priv->uncore, PLANE_CTL(pipe, plane_id));
>  
>  	/* No DDB allocated for disabled planes */
>  	if (val & PLANE_CTL_ENABLE)
> @@ -4321,11 +4321,11 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>  					      val & PLANE_CTL_ALPHA_MASK);
>  
>  	if (INTEL_GEN(dev_priv) >= 11) {
> -		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> +		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
>  		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
>  	} else {
> -		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> -		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
> +		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
> +		val2 = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
>  
>  		if (fourcc &&
>  		    drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
> @@ -6240,9 +6240,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>  
>  		for (level = 0; level <= max_level; level++) {
>  			if (plane_id != PLANE_CURSOR)
> -				val = I915_READ(PLANE_WM(pipe, plane_id, level));
> +				val = intel_uncore_read(&dev_priv->uncore, PLANE_WM(pipe, plane_id, level));
>  			else
> -				val = I915_READ(CUR_WM(pipe, level));
> +				val = intel_uncore_read(&dev_priv->uncore, CUR_WM(pipe, level));
>  
>  			skl_wm_level_from_reg_val(val, &wm->wm[level]);
>  		}
> @@ -6251,9 +6251,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>  			wm->sagv_wm0 = wm->wm[0];
>  
>  		if (plane_id != PLANE_CURSOR)
> -			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
> +			val = intel_uncore_read(&dev_priv->uncore, PLANE_WM_TRANS(pipe, plane_id));
>  		else
> -			val = I915_READ(CUR_WM_TRANS(pipe));
> +			val = intel_uncore_read(&dev_priv->uncore, CUR_WM_TRANS(pipe));
>  
>  		skl_wm_level_from_reg_val(val, &wm->trans_wm);
>  	}
> @@ -6288,7 +6288,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
>  	struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
>  	enum pipe pipe = crtc->pipe;
>  
> -	hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe));
> +	hw->wm_pipe[pipe] = intel_uncore_read(&dev_priv->uncore, WM0_PIPE_ILK(pipe));
>  
>  	memset(active, 0, sizeof(*active));
>  
> @@ -6332,13 +6332,13 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
>  {
>  	u32 tmp;
>  
> -	tmp = I915_READ(DSPFW1);
> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
>  	wm->sr.plane = _FW_WM(tmp, SR);
>  	wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
>  	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
>  	wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
>  
> -	tmp = I915_READ(DSPFW2);
> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
>  	wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
>  	wm->sr.fbc = _FW_WM(tmp, FBC_SR);
>  	wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
> @@ -6346,7 +6346,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
>  	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
>  	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
>  
> -	tmp = I915_READ(DSPFW3);
> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
>  	wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
>  	wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
>  	wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
> @@ -6360,7 +6360,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
>  	u32 tmp;
>  
>  	for_each_pipe(dev_priv, pipe) {
> -		tmp = I915_READ(VLV_DDL(pipe));
> +		tmp = intel_uncore_read(&dev_priv->uncore, VLV_DDL(pipe));
>  
>  		wm->ddl[pipe].plane[PLANE_PRIMARY] =
>  			(tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
> @@ -6372,34 +6372,34 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
>  			(tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
>  	}
>  
> -	tmp = I915_READ(DSPFW1);
> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
>  	wm->sr.plane = _FW_WM(tmp, SR);
>  	wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
>  	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
>  	wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
>  
> -	tmp = I915_READ(DSPFW2);
> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
>  	wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
>  	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
>  	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
>  
> -	tmp = I915_READ(DSPFW3);
> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
>  	wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
>  
>  	if (IS_CHERRYVIEW(dev_priv)) {
> -		tmp = I915_READ(DSPFW7_CHV);
> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7_CHV);
>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
>  
> -		tmp = I915_READ(DSPFW8_CHV);
> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW8_CHV);
>  		wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
>  		wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
>  
> -		tmp = I915_READ(DSPFW9_CHV);
> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW9_CHV);
>  		wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
>  		wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
>  
> -		tmp = I915_READ(DSPHOWM);
> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
>  		wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
>  		wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
>  		wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
> @@ -6411,11 +6411,11 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
>  		wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
>  		wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
>  	} else {
> -		tmp = I915_READ(DSPFW7);
> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7);
>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
>  
> -		tmp = I915_READ(DSPHOWM);
> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
>  		wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
> @@ -6436,7 +6436,7 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  
>  	g4x_read_wm_values(dev_priv, wm);
>  
> -	wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
> +	wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
>  
>  	for_each_intel_crtc(&dev_priv->drm, crtc) {
>  		struct intel_crtc_state *crtc_state =
> @@ -6580,7 +6580,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  
>  	vlv_read_wm_values(dev_priv, wm);
>  
> -	wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
> +	wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>  	wm->level = VLV_WM_LEVEL_PM2;
>  
>  	if (IS_CHERRYVIEW(dev_priv)) {
> @@ -6727,9 +6727,9 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
>   */
>  static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
>  {
> -	I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
> -	I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
> -	I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
> +	intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM1_LP_SR_EN);
> +	intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM1_LP_SR_EN);
> +	intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM1_LP_SR_EN);
>  
>  	/*
>  	 * Don't touch WM1S_LP_EN here.
> @@ -6747,25 +6747,25 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  	for_each_intel_crtc(&dev_priv->drm, crtc)
>  		ilk_pipe_wm_get_hw_state(crtc);
>  
> -	hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
> -	hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
> -	hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
> +	hw->wm_lp[0] = intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK);
> +	hw->wm_lp[1] = intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK);
> +	hw->wm_lp[2] = intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK);
>  
> -	hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
> +	hw->wm_lp_spr[0] = intel_uncore_read(&dev_priv->uncore, WM1S_LP_ILK);
>  	if (INTEL_GEN(dev_priv) >= 7) {
> -		hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
> -		hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
> +		hw->wm_lp_spr[1] = intel_uncore_read(&dev_priv->uncore, WM2S_LP_IVB);
> +		hw->wm_lp_spr[2] = intel_uncore_read(&dev_priv->uncore, WM3S_LP_IVB);
>  	}
>  
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> -		hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
> +		hw->partitioning = (intel_uncore_read(&dev_priv->uncore, WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
>  			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
>  	else if (IS_IVYBRIDGE(dev_priv))
> -		hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
> +		hw->partitioning = (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
>  			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
>  
>  	hw->enable_fbc_wm =
> -		!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
> +		!(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
>  }
>  
>  /**
> @@ -6816,14 +6816,14 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
>  	if (!HAS_IPC(dev_priv))
>  		return;
>  
> -	val = I915_READ(DISP_ARB_CTL2);
> +	val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2);
>  
>  	if (dev_priv->ipc_enabled)
>  		val |= DISP_IPC_ENABLE;
>  	else
>  		val &= ~DISP_IPC_ENABLE;
>  
> -	I915_WRITE(DISP_ARB_CTL2, val);
> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL2, val);
>  }
>  
>  static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv)
> @@ -6858,7 +6858,7 @@ static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
>  	 * gating for the panel power sequencer or it will fail to
>  	 * start up when no ports are active.
>  	 */
> -	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> +	intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
>  }
>  
>  static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> @@ -6866,12 +6866,12 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
>  	enum pipe pipe;
>  
>  	for_each_pipe(dev_priv, pipe) {
> -		I915_WRITE(DSPCNTR(pipe),
> -			   I915_READ(DSPCNTR(pipe)) |
> +		intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe),
> +			   intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) |
>  			   DISPPLANE_TRICKLE_FEED_DISABLE);
>  
> -		I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
> -		POSTING_READ(DSPSURF(pipe));
> +		intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(pipe)));
> +		intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe));
>  	}
>  }
>  
> @@ -6887,10 +6887,10 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
>  		   ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
>  		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
>  
> -	I915_WRITE(PCH_3DCGDIS0,
> +	intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS0,
>  		   MARIUNIT_CLOCK_GATE_DISABLE |
>  		   SVSMUNIT_CLOCK_GATE_DISABLE);
> -	I915_WRITE(PCH_3DCGDIS1,
> +	intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS1,
>  		   VFMUNIT_CLOCK_GATE_DISABLE);
>  
>  	/*
> @@ -6900,12 +6900,12 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
>  	 * The bit 5 of 0x42020
>  	 * The bit 15 of 0x45000
>  	 */
> -	I915_WRITE(ILK_DISPLAY_CHICKEN2,
> -		   (I915_READ(ILK_DISPLAY_CHICKEN2) |
> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
> +		   (intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
>  		    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
>  	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
> -	I915_WRITE(DISP_ARB_CTL,
> -		   (I915_READ(DISP_ARB_CTL) |
> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL,
> +		   (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>  		    DISP_FBC_WM_DIS));
>  
>  	/*
> @@ -6917,18 +6917,18 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
>  	 */
>  	if (IS_IRONLAKE_M(dev_priv)) {
>  		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
> -		I915_WRITE(ILK_DISPLAY_CHICKEN1,
> -			   I915_READ(ILK_DISPLAY_CHICKEN1) |
> +		intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
> +			   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
>  			   ILK_FBCQ_DIS);
> -		I915_WRITE(ILK_DISPLAY_CHICKEN2,
> -			   I915_READ(ILK_DISPLAY_CHICKEN2) |
> +		intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
> +			   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
>  			   ILK_DPARB_GATE);
>  	}
>  
> -	I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
> +	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
>  
> -	I915_WRITE(ILK_DISPLAY_CHICKEN2,
> -		   I915_READ(ILK_DISPLAY_CHICKEN2) |
> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
>  		   ILK_ELPIN_409_SELECT);
>  
>  	g4x_disable_trickle_feed(dev_priv);
> @@ -6946,27 +6946,27 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
>  	 * gating for the panel power sequencer or it will fail to
>  	 * start up when no ports are active.
>  	 */
> -	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
> +	intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
>  		   PCH_DPLUNIT_CLOCK_GATE_DISABLE |
>  		   PCH_CPUNIT_CLOCK_GATE_DISABLE);
> -	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
> +	intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN2, intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN2) |
>  		   DPLS_EDP_PPS_FIX_DIS);
>  	/* The below fixes the weird display corruption, a few pixels shifted
>  	 * downward, on (only) LVDS of some HP laptops with IVY.
>  	 */
>  	for_each_pipe(dev_priv, pipe) {
> -		val = I915_READ(TRANS_CHICKEN2(pipe));
> +		val = intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN2(pipe));
>  		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
>  		val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
>  		if (dev_priv->vbt.fdi_rx_polarity_inverted)
>  			val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
>  		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
>  		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
> -		I915_WRITE(TRANS_CHICKEN2(pipe), val);
> +		intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN2(pipe), val);
>  	}
>  	/* WADP0ClockGatingDisable */
>  	for_each_pipe(dev_priv, pipe) {
> -		I915_WRITE(TRANS_CHICKEN1(pipe),
> +		intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(pipe),
>  			   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
>  	}
>  }
> @@ -6975,7 +6975,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
>  {
>  	u32 tmp;
>  
> -	tmp = I915_READ(MCH_SSKPD);
> +	tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD);
>  	if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
> @@ -6986,14 +6986,14 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
>  
> -	I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
> +	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
>  
> -	I915_WRITE(ILK_DISPLAY_CHICKEN2,
> -		   I915_READ(ILK_DISPLAY_CHICKEN2) |
> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
>  		   ILK_ELPIN_409_SELECT);
>  
> -	I915_WRITE(GEN6_UCGCTL1,
> -		   I915_READ(GEN6_UCGCTL1) |
> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
> +		   intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
>  		   GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
>  		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
>  
> @@ -7010,7 +7010,7 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
>  	 * WaDisableRCCUnitClockGating:snb
>  	 * WaDisableRCPBUnitClockGating:snb
>  	 */
> -	I915_WRITE(GEN6_UCGCTL2,
> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
>  		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
>  		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
>  
> @@ -7025,14 +7025,14 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
>  	 *
>  	 * WaFbcAsynchFlipDisableFbcQueue:snb
>  	 */
> -	I915_WRITE(ILK_DISPLAY_CHICKEN1,
> -		   I915_READ(ILK_DISPLAY_CHICKEN1) |
> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
>  		   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
> -	I915_WRITE(ILK_DISPLAY_CHICKEN2,
> -		   I915_READ(ILK_DISPLAY_CHICKEN2) |
> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
>  		   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> -	I915_WRITE(ILK_DSPCLK_GATE_D,
> -		   I915_READ(ILK_DSPCLK_GATE_D) |
> +	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D,
> +		   intel_uncore_read(&dev_priv->uncore, ILK_DSPCLK_GATE_D) |
>  		   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
>  		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
>  
> @@ -7050,23 +7050,23 @@ static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
>  	 * disabled when not needed anymore in order to save power.
>  	 */
>  	if (HAS_PCH_LPT_LP(dev_priv))
> -		I915_WRITE(SOUTH_DSPCLK_GATE_D,
> -			   I915_READ(SOUTH_DSPCLK_GATE_D) |
> +		intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D,
> +			   intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |
>  			   PCH_LP_PARTITION_LEVEL_DISABLE);
>  
>  	/* WADPOClockGatingDisable:hsw */
> -	I915_WRITE(TRANS_CHICKEN1(PIPE_A),
> -		   I915_READ(TRANS_CHICKEN1(PIPE_A)) |
> +	intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A),
> +		   intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A)) |
>  		   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
>  }
>  
>  static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
>  {
>  	if (HAS_PCH_LPT_LP(dev_priv)) {
> -		u32 val = I915_READ(SOUTH_DSPCLK_GATE_D);
> +		u32 val = intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D);
>  
>  		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> -		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> +		intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, val);
>  	}
>  }
>  
> @@ -7078,33 +7078,33 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
>  	u32 val;
>  
>  	/* WaTempDisableDOPClkGating:bdw */
> -	misccpctl = I915_READ(GEN7_MISCCPCTL);
> -	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
> +	misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
> +	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
>  
> -	val = I915_READ(GEN8_L3SQCREG1);
> +	val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
>  	val &= ~L3_PRIO_CREDITS_MASK;
>  	val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
>  	val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
> -	I915_WRITE(GEN8_L3SQCREG1, val);
> +	intel_uncore_write(&dev_priv->uncore, GEN8_L3SQCREG1, val);
>  
>  	/*
>  	 * Wait at least 100 clocks before re-enabling clock gating.
>  	 * See the definition of L3SQCREG1 in BSpec.
>  	 */
> -	POSTING_READ(GEN8_L3SQCREG1);
> +	intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
>  	udelay(1);
> -	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
> +	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
>  }
>  
>  static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	/* Wa_1409120013:icl,ehl */
> -	I915_WRITE(ILK_DPFC_CHICKEN,
> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>  
>  	/* This is not an Wa. Enable to reduce Sampler power */
> -	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> -		   I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
> +	intel_uncore_write(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
> +		   intel_uncore_read(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
>  
>  	/*Wa_14010594013:icl, ehl */
>  	intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
> @@ -7114,12 +7114,12 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
>  static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	/* Wa_1409120013:tgl */
> -	I915_WRITE(ILK_DPFC_CHICKEN,
> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>  
>  	/* Wa_1409825376:tgl (pre-prod)*/
>  	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
> -		I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
> +		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>  			   TGL_VRH_GATING_DIS);
>  
>  	/* Wa_14011059788:tgl */
> @@ -7131,7 +7131,7 @@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	/* Wa_1409836686:dg1[a0] */
>  	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
> -		I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
> +		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>  			   DPT_GATING_DIS);
>  }
>  
> @@ -7141,7 +7141,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
>  		return;
>  
>  	/* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
> -	I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
> +	intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |
>  		   CNP_PWM_CGE_GATING_DISABLE);
>  }
>  
> @@ -7151,35 +7151,35 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
>  	cnp_init_clock_gating(dev_priv);
>  
>  	/* This is not an Wa. Enable for better image quality */
> -	I915_WRITE(_3D_CHICKEN3,
> +	intel_uncore_write(&dev_priv->uncore, _3D_CHICKEN3,
>  		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
>  
>  	/* WaEnableChickenDCPR:cnl */
> -	I915_WRITE(GEN8_CHICKEN_DCPR_1,
> -		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
> +	intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
> +		   intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>  
>  	/*
>  	 * WaFbcWakeMemOn:cnl
>  	 * Display WA #0859: cnl
>  	 */
> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>  		   DISP_FBC_MEMORY_WAKE);
>  
> -	val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);
> +	val = intel_uncore_read(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE);
>  	/* ReadHitWriteOnlyDisable:cnl */
>  	val |= RCCUNIT_CLKGATE_DIS;
> -	I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
> +	intel_uncore_write(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE, val);
>  
>  	/* Wa_2201832410:cnl */
> -	val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
> +	val = intel_uncore_read(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE);
>  	val |= GWUNIT_CLKGATE_DIS;
> -	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
> +	intel_uncore_write(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE, val);
>  
>  	/* WaDisableVFclkgate:cnl */
>  	/* WaVFUnitClockGatingDisable:cnl */
> -	val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
> +	val = intel_uncore_read(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE);
>  	val |= VFUNIT_CLKGATE_DIS;
> -	I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val);
> +	intel_uncore_write(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE, val);
>  }
>  
>  static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
> @@ -7188,21 +7188,21 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
>  	gen9_init_clock_gating(dev_priv);
>  
>  	/* WAC6entrylatency:cfl */
> -	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
> +	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
>  		   FBC_LLC_FULLY_OPEN);
>  
>  	/*
>  	 * WaFbcTurnOffFbcWatermark:cfl
>  	 * Display WA #0562: cfl
>  	 */
> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>  		   DISP_FBC_WM_DIS);
>  
>  	/*
>  	 * WaFbcNukeOnHostModify:cfl
>  	 * Display WA #0873: cfl
>  	 */
> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
>  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>  }
>  
> @@ -7211,31 +7211,31 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
>  	gen9_init_clock_gating(dev_priv);
>  
>  	/* WAC6entrylatency:kbl */
> -	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
> +	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
>  		   FBC_LLC_FULLY_OPEN);
>  
>  	/* WaDisableSDEUnitClockGating:kbl */
>  	if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0))
> -		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> +		intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
>  			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>  
>  	/* WaDisableGamClockGating:kbl */
>  	if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0))
> -		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> +		intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
>  			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
>  
>  	/*
>  	 * WaFbcTurnOffFbcWatermark:kbl
>  	 * Display WA #0562: kbl
>  	 */
> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>  		   DISP_FBC_WM_DIS);
>  
>  	/*
>  	 * WaFbcNukeOnHostModify:kbl
>  	 * Display WA #0873: kbl
>  	 */
> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
>  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>  }
>  
> @@ -7244,32 +7244,32 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
>  	gen9_init_clock_gating(dev_priv);
>  
>  	/* WaDisableDopClockGating:skl */
> -	I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) &
> +	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL) &
>  		   ~GEN7_DOP_CLOCK_GATE_ENABLE);
>  
>  	/* WAC6entrylatency:skl */
> -	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
> +	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
>  		   FBC_LLC_FULLY_OPEN);
>  
>  	/*
>  	 * WaFbcTurnOffFbcWatermark:skl
>  	 * Display WA #0562: skl
>  	 */
> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>  		   DISP_FBC_WM_DIS);
>  
>  	/*
>  	 * WaFbcNukeOnHostModify:skl
>  	 * Display WA #0873: skl
>  	 */
> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
>  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>  
>  	/*
>  	 * WaFbcHighMemBwCorruptionAvoidance:skl
>  	 * Display WA #0883: skl
>  	 */
> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
>  		   ILK_DPFC_DISABLE_DUMMY0);
>  }
>  
> @@ -7278,42 +7278,42 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
>  	enum pipe pipe;
>  
>  	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> -	I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
> -		   I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
> +		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |
>  		   HSW_FBCQ_DIS);
>  
>  	/* WaSwitchSolVfFArbitrationPriority:bdw */
> -	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> +	intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>  
>  	/* WaPsrDPAMaskVBlankInSRD:bdw */
> -	I915_WRITE(CHICKEN_PAR1_1,
> -		   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
> +		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
>  
>  	/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
>  	for_each_pipe(dev_priv, pipe) {
> -		I915_WRITE(CHICKEN_PIPESL_1(pipe),
> -			   I915_READ(CHICKEN_PIPESL_1(pipe)) |
> +		intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
> +			   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe)) |
>  			   BDW_DPRS_MASK_VBLANK_SRD);
>  	}
>  
>  	/* WaVSRefCountFullforceMissDisable:bdw */
>  	/* WaDSRefCountFullforceMissDisable:bdw */
> -	I915_WRITE(GEN7_FF_THREAD_MODE,
> -		   I915_READ(GEN7_FF_THREAD_MODE) &
> +	intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
> +		   intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
>  		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
>  
> -	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> +	intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
>  		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
>  
>  	/* WaDisableSDEUnitClockGating:bdw */
> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> +	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>  
>  	/* WaProgramL3SqcReg1Default:bdw */
>  	gen8_set_l3sqc_credits(dev_priv, 30, 2);
>  
>  	/* WaKVMNotificationOnConfigChange:bdw */
> -	I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR2_1, intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR2_1)
>  		   | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
>  
>  	lpt_init_clock_gating(dev_priv);
> @@ -7323,24 +7323,24 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
>  	 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
>  	 * clock gating.
>  	 */
> -	I915_WRITE(GEN6_UCGCTL1,
> -		   I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
> +		   intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
>  }
>  
>  static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> -	I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
> -		   I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
> +		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |
>  		   HSW_FBCQ_DIS);
>  
>  	/* This is required by WaCatErrorRejectionIssue:hsw */
> -	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> -		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> +	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> +		   intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>  		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>  
>  	/* WaSwitchSolVfFArbitrationPriority:hsw */
> -	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> +	intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>  
>  	lpt_init_clock_gating(dev_priv);
>  }
> @@ -7349,26 +7349,26 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	u32 snpcr;
>  
> -	I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
> +	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
>  
>  	/* WaFbcAsynchFlipDisableFbcQueue:ivb */
> -	I915_WRITE(ILK_DISPLAY_CHICKEN1,
> -		   I915_READ(ILK_DISPLAY_CHICKEN1) |
> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
>  		   ILK_FBCQ_DIS);
>  
>  	/* WaDisableBackToBackFlipFix:ivb */
> -	I915_WRITE(IVB_CHICKEN3,
> +	intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
>  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
>  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
>  
>  	if (IS_IVB_GT1(dev_priv))
> -		I915_WRITE(GEN7_ROW_CHICKEN2,
> +		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
>  			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>  	else {
>  		/* must write both registers */
> -		I915_WRITE(GEN7_ROW_CHICKEN2,
> +		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
>  			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> -		I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
> +		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2_GT2,
>  			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>  	}
>  
> @@ -7376,20 +7376,20 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>  	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>  	 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
>  	 */
> -	I915_WRITE(GEN6_UCGCTL2,
> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
>  		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>  
>  	/* This is required by WaCatErrorRejectionIssue:ivb */
> -	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> -			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> +	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> +			intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>  			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>  
>  	g4x_disable_trickle_feed(dev_priv);
>  
> -	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
> +	snpcr = intel_uncore_read(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR);
>  	snpcr &= ~GEN6_MBC_SNPCR_MASK;
>  	snpcr |= GEN6_MBC_SNPCR_MED;
> -	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
> +	intel_uncore_write(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR, snpcr);
>  
>  	if (!HAS_PCH_NOP(dev_priv))
>  		cpt_init_clock_gating(dev_priv);
> @@ -7400,58 +7400,58 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>  static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	/* WaDisableBackToBackFlipFix:vlv */
> -	I915_WRITE(IVB_CHICKEN3,
> +	intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
>  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
>  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
>  
>  	/* WaDisableDopClockGating:vlv */
> -	I915_WRITE(GEN7_ROW_CHICKEN2,
> +	intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
>  		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>  
>  	/* This is required by WaCatErrorRejectionIssue:vlv */
> -	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> -		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> +	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> +		   intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>  		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>  
>  	/*
>  	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>  	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
>  	 */
> -	I915_WRITE(GEN6_UCGCTL2,
> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
>  		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>  
>  	/* WaDisableL3Bank2xClockGate:vlv
>  	 * Disabling L3 clock gating- MMIO 940c[25] = 1
>  	 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
> -	I915_WRITE(GEN7_UCGCTL4,
> -		   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
> +	intel_uncore_write(&dev_priv->uncore, GEN7_UCGCTL4,
> +		   intel_uncore_read(&dev_priv->uncore, GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
>  
>  	/*
>  	 * WaDisableVLVClockGating_VBIIssue:vlv
>  	 * Disable clock gating on th GCFG unit to prevent a delay
>  	 * in the reporting of vblank events.
>  	 */
> -	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
> +	intel_uncore_write(&dev_priv->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
>  }
>  
>  static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	/* WaVSRefCountFullforceMissDisable:chv */
>  	/* WaDSRefCountFullforceMissDisable:chv */
> -	I915_WRITE(GEN7_FF_THREAD_MODE,
> -		   I915_READ(GEN7_FF_THREAD_MODE) &
> +	intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
> +		   intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
>  		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
>  
>  	/* WaDisableSemaphoreAndSyncFlipWait:chv */
> -	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> +	intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
>  		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
>  
>  	/* WaDisableCSUnitClockGating:chv */
> -	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
>  		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
>  
>  	/* WaDisableSDEUnitClockGating:chv */
> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> +	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>  
>  	/*
> @@ -7466,17 +7466,17 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	u32 dspclk_gate;
>  
> -	I915_WRITE(RENCLK_GATE_D1, 0);
> -	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, 0);
> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
>  		   GS_UNIT_CLOCK_GATE_DISABLE |
>  		   CL_UNIT_CLOCK_GATE_DISABLE);
> -	I915_WRITE(RAMCLK_GATE_D, 0);
> +	intel_uncore_write(&dev_priv->uncore, RAMCLK_GATE_D, 0);
>  	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
>  		OVRUNIT_CLOCK_GATE_DISABLE |
>  		OVCUNIT_CLOCK_GATE_DISABLE;
>  	if (IS_GM45(dev_priv))
>  		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
> -	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
> +	intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D, dspclk_gate);
>  
>  	g4x_disable_trickle_feed(dev_priv);
>  }
> @@ -7497,49 +7497,49 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
>  
>  static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> -	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
>  		   I965_RCC_CLOCK_GATE_DISABLE |
>  		   I965_RCPB_CLOCK_GATE_DISABLE |
>  		   I965_ISC_CLOCK_GATE_DISABLE |
>  		   I965_FBC_CLOCK_GATE_DISABLE);
> -	I915_WRITE(RENCLK_GATE_D2, 0);
> -	I915_WRITE(MI_ARB_STATE,
> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, 0);
> +	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
>  		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
>  }
>  
>  static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> -	u32 dstate = I915_READ(D_STATE);
> +	u32 dstate = intel_uncore_read(&dev_priv->uncore, D_STATE);
>  
>  	dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
>  		DSTATE_DOT_CLOCK_GATING;
> -	I915_WRITE(D_STATE, dstate);
> +	intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
>  
>  	if (IS_PINEVIEW(dev_priv))
> -		I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
> +		intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
>  
>  	/* IIR "flip pending" means done if this bit is set */
> -	I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
> +	intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
>  
>  	/* interrupts should cause a wake up from C3 */
> -	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
> +	intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
>  
>  	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
> -	I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
> +	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
>  
> -	I915_WRITE(MI_ARB_STATE,
> +	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
>  		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
>  }
>  
>  static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> -	I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
>  
>  	/* interrupts should cause a wake up from C3 */
> -	I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
> +	intel_uncore_write(&dev_priv->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
>  		   _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
>  
> -	I915_WRITE(MEM_MODE,
> +	intel_uncore_write(&dev_priv->uncore, MEM_MODE,
>  		   _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
>  
>  	/*
> @@ -7549,13 +7549,13 @@ static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
>  	 * abosultely nothing) would not allow FBC to recompress
>  	 * until a 2D blit occurs.
>  	 */
> -	I915_WRITE(SCPD0,
> +	intel_uncore_write(&dev_priv->uncore, SCPD0,
>  		   _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
>  }
>  
>  static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> -	I915_WRITE(MEM_MODE,
> +	intel_uncore_write(&dev_priv->uncore, MEM_MODE,
>  		   _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
>  		   _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
>  }
> -- 
> 2.20.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 9/9] drm/i915: remove last traces of I915_READ(), I915_WRITE() and POSTING_READ()

[Rodrigo Vivi]

On Thu, Nov 12, 2020 at 01:44:42PM +0200, Jani Nikula wrote:
> Good riddance! Remove the macros and their remaining references in
> comments.
> 
> The following functions should be used instead, depending on the use
> case:
> 
> - intel_uncore_read(), intel_uncore_write(), intel_uncore_posting_read()
> 
> - intel_de_read(), intel_de_write(), intel_de_posting_read()
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dvo.c | 4 ----
>  drivers/gpu/drm/i915/i915_drv.h          | 8 --------
>  drivers/gpu/drm/i915/i915_reg.h          | 6 ++++--
>  drivers/gpu/drm/i915/intel_sideband.c    | 4 ++--
>  drivers/gpu/drm/i915/intel_uncore.c      | 2 +-
>  drivers/gpu/drm/i915/intel_uncore.h      | 4 ++--
>  6 files changed, 9 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index 237dbb1ba0ee..090cd76266c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -301,12 +301,8 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
>  		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;
>  
> -	/*I915_WRITE(DVOB_SRCDIM,
> -	  (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
> -	  (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
>  	intel_de_write(dev_priv, dvo_srcdim_reg,
>  		       (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
> -	/*I915_WRITE(DVOB, dvo_val);*/
>  	intel_de_write(dev_priv, dvo_reg, dvo_val);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fecb5899cbac..42f60b112436 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1970,14 +1970,6 @@ mkwrite_device_info(struct drm_i915_private *dev_priv)
>  int i915_reg_read_ioctl(struct drm_device *dev, void *data,
>  			struct drm_file *file);
>  
> -#define __I915_REG_OP(op__, dev_priv__, ...) \
> -	intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
> -
> -#define I915_READ(reg__)	 __I915_REG_OP(read, dev_priv, (reg__))
> -#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
> -
> -#define POSTING_READ(reg__)	__I915_REG_OP(posting_read, dev_priv, (reg__))
> -
>  /* i915_mm.c */
>  int remap_io_mapping(struct vm_area_struct *vma,
>  		     unsigned long addr, unsigned long pfn, unsigned long size,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7ea70b7ffcc6..568633448202 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10849,8 +10849,10 @@ enum skl_power_gate {
>  #define  CNL_DRAM_RANK_3			(0x2 << 9)
>  #define  CNL_DRAM_RANK_4			(0x3 << 9)
>  
> -/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
> - * since on HSW we can't write to it using I915_WRITE. */
> +/*
> + * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
> + * since on HSW we can't write to it using intel_uncore_write.
> + */
>  #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
>  #define D_COMP_BDW			_MMIO(0x138144)
>  #define  D_COMP_RCOMP_IN_PROGRESS	(1 << 9)
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 02ebf5a04a9b..0ec0cf191955 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -404,8 +404,8 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
>  	lockdep_assert_held(&i915->sb_lock);
>  
>  	/*
> -	 * GEN6_PCODE_* are outside of the forcewake domain, we can
> -	 * use te fw I915_READ variants to reduce the amount of work
> +	 * GEN6_PCODE_* are outside of the forcewake domain, we can use
> +	 * intel_uncore_read/write_fw variants to reduce the amount of work
>  	 * required when reading/writing.
>  	 */
>  
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index ef40edfff412..9ac501bcfdad 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2126,7 +2126,7 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
>   * This routine waits until the target register @reg contains the expected
>   * @value after applying the @mask, i.e. it waits until ::
>   *
> - *     (I915_READ(reg) & mask) == value
> + *     (intel_uncore_read(uncore, reg) & mask) == value
>   *
>   * Otherwise, the wait will timeout after @timeout_ms milliseconds.
>   *
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 5dcb7f4183b2..59f0da8f1fbb 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -318,8 +318,8 @@ __uncore_write(write_notrace, 32, l, false)
>   * will be implemented using 2 32-bit writes in an arbitrary order with
>   * an arbitrary delay between them. This can cause the hardware to
>   * act upon the intermediate value, possibly leading to corruption and
> - * machine death. For this reason we do not support I915_WRITE64, or
> - * uncore->funcs.mmio_writeq.
> + * machine death. For this reason we do not support intel_uncore_write64,
> + * or uncore->funcs.mmio_writeq.
>   *
>   * When reading a 64-bit value as two 32-bit values, the delay may cause
>   * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
> -- 
> 2.20.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 7/9] drm/i915/pm: replace I915_READ()/WRITE() with intel_uncore_read()/write()

[Jani Nikula]

On Thu, 12 Nov 2020, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Thu, Nov 12, 2020 at 01:44:40PM +0200, Jani Nikula wrote:
>> Arguably some of these should use intel_de_read() or intel_de_write(),
>> however not all. Prioritize I915_READ() and I915_WRITE() removal in
>> general over migrating to the pedantically correct replacements right
>> away.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_pm.c | 552 ++++++++++++++++----------------
>>  1 file changed, 276 insertions(+), 276 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index bbec56f97832..c0ed82665706 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -81,24 +81,24 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>>  		 * Must match Sampler, Pixel Back End, and Media. See
>>  		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
>>  		 */
>> -		I915_WRITE(CHICKEN_PAR1_1,
>> -			   I915_READ(CHICKEN_PAR1_1) |
>> +		intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
>> +			   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) |
>
> why not converting them to rmw?

That's actually a functional change I didn't want to make. The rmw
function only writes if the value has changed, while the code currently
writes unconditionally. I'd have to check the registers whether that
makes a difference. Likely not for most registers, but also don't want
to introduce subtle bugs with a superficially non-functional conversion.

BR,
Jani.


>
>>  			   SKL_DE_COMPRESSED_HASH_MODE);
>>  	}
>>  
>>  	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
>> -	I915_WRITE(CHICKEN_PAR1_1,
>> -		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
>> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
>> +		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
>>  
>>  	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
>> -	I915_WRITE(GEN8_CHICKEN_DCPR_1,
>> -		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>> +	intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
>> +		   intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>>  
>>  	/*
>>  	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
>>  	 * Display WA #0859: skl,bxt,kbl,glk,cfl
>>  	 */
>> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>>  		   DISP_FBC_MEMORY_WAKE);
>>  }
>>  
>> @@ -107,21 +107,21 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	gen9_init_clock_gating(dev_priv);
>>  
>>  	/* WaDisableSDEUnitClockGating:bxt */
>> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>> +	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
>>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>>  
>>  	/*
>>  	 * FIXME:
>>  	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
>>  	 */
>> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>> +	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
>>  		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
>>  
>>  	/*
>>  	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
>>  	 * to stay fully on.
>>  	 */
>> -	I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
>> +	intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
>>  		   PWM1_GATING_DIS | PWM2_GATING_DIS);
>>  
>>  	/*
>> @@ -130,20 +130,20 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	 * is off and a MMIO access is attempted by any privilege
>>  	 * application, using batch buffers or any other means.
>>  	 */
>> -	I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950));
>> +	intel_uncore_write(&dev_priv->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
>>  
>>  	/*
>>  	 * WaFbcTurnOffFbcWatermark:bxt
>>  	 * Display WA #0562: bxt
>>  	 */
>> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>>  		   DISP_FBC_WM_DIS);
>>  
>>  	/*
>>  	 * WaFbcHighMemBwCorruptionAvoidance:bxt
>>  	 * Display WA #0883: bxt
>>  	 */
>> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
>>  		   ILK_DPFC_DISABLE_DUMMY0);
>>  }
>>  
>> @@ -156,7 +156,7 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	 * Backlight PWM may stop in the asserted state, causing backlight
>>  	 * to stay fully on.
>>  	 */
>> -	I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
>> +	intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
>>  		   PWM1_GATING_DIS | PWM2_GATING_DIS);
>>  }
>>  
>> @@ -164,7 +164,7 @@ static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
>>  {
>>  	u32 tmp;
>>  
>> -	tmp = I915_READ(CLKCFG);
>> +	tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
>>  
>>  	switch (tmp & CLKCFG_FSB_MASK) {
>>  	case CLKCFG_FSB_533:
>> @@ -194,7 +194,7 @@ static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
>>  	}
>>  
>>  	/* detect pineview DDR3 setting */
>> -	tmp = I915_READ(CSHRDDR3CTL);
>> +	tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL);
>>  	dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
>>  }
>>  
>> @@ -365,39 +365,39 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
>>  	u32 val;
>>  
>>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>> -		was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>> -		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
>> -		POSTING_READ(FW_BLC_SELF_VLV);
>> +		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>> +		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
>> +		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF_VLV);
>>  	} else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
>> -		was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
>> -		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
>> -		POSTING_READ(FW_BLC_SELF);
>> +		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
>> +		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
>> +		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
>>  	} else if (IS_PINEVIEW(dev_priv)) {
>> -		val = I915_READ(DSPFW3);
>> +		val = intel_uncore_read(&dev_priv->uncore, DSPFW3);
>>  		was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
>>  		if (enable)
>>  			val |= PINEVIEW_SELF_REFRESH_EN;
>>  		else
>>  			val &= ~PINEVIEW_SELF_REFRESH_EN;
>> -		I915_WRITE(DSPFW3, val);
>> -		POSTING_READ(DSPFW3);
>> +		intel_uncore_write(&dev_priv->uncore, DSPFW3, val);
>> +		intel_uncore_posting_read(&dev_priv->uncore, DSPFW3);
>>  	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
>> -		was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
>> +		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
>>  		val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
>>  			       _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
>> -		I915_WRITE(FW_BLC_SELF, val);
>> -		POSTING_READ(FW_BLC_SELF);
>> +		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, val);
>> +		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
>>  	} else if (IS_I915GM(dev_priv)) {
>>  		/*
>>  		 * FIXME can't find a bit like this for 915G, and
>>  		 * and yet it does have the related watermark in
>>  		 * FW_BLC_SELF. What's going on?
>>  		 */
>> -		was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
>> +		was_enabled = intel_uncore_read(&dev_priv->uncore, INSTPM) & INSTPM_SELF_EN;
>>  		val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
>>  			       _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
>> -		I915_WRITE(INSTPM, val);
>> -		POSTING_READ(INSTPM);
>> +		intel_uncore_write(&dev_priv->uncore, INSTPM, val);
>> +		intel_uncore_posting_read(&dev_priv->uncore, INSTPM);
>>  	} else {
>>  		return false;
>>  	}
>> @@ -493,20 +493,20 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
>>  
>>  	switch (pipe) {
>>  	case PIPE_A:
>> -		dsparb = I915_READ(DSPARB);
>> -		dsparb2 = I915_READ(DSPARB2);
>> +		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
>> +		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
>>  		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
>>  		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
>>  		break;
>>  	case PIPE_B:
>> -		dsparb = I915_READ(DSPARB);
>> -		dsparb2 = I915_READ(DSPARB2);
>> +		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
>> +		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
>>  		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
>>  		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
>>  		break;
>>  	case PIPE_C:
>> -		dsparb2 = I915_READ(DSPARB2);
>> -		dsparb3 = I915_READ(DSPARB3);
>> +		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
>> +		dsparb3 = intel_uncore_read(&dev_priv->uncore, DSPARB3);
>>  		sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
>>  		sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
>>  		break;
>> @@ -524,7 +524,7 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
>>  static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
>>  			      enum i9xx_plane_id i9xx_plane)
>>  {
>> -	u32 dsparb = I915_READ(DSPARB);
>> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
>>  	int size;
>>  
>>  	size = dsparb & 0x7f;
>> @@ -540,7 +540,7 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
>>  static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
>>  			      enum i9xx_plane_id i9xx_plane)
>>  {
>> -	u32 dsparb = I915_READ(DSPARB);
>> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
>>  	int size;
>>  
>>  	size = dsparb & 0x1ff;
>> @@ -557,7 +557,7 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
>>  static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
>>  			      enum i9xx_plane_id i9xx_plane)
>>  {
>> -	u32 dsparb = I915_READ(DSPARB);
>> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
>>  	int size;
>>  
>>  	size = dsparb & 0x7f;
>> @@ -910,38 +910,38 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
>>  		wm = intel_calculate_wm(clock, &pnv_display_wm,
>>  					pnv_display_wm.fifo_size,
>>  					cpp, latency->display_sr);
>> -		reg = I915_READ(DSPFW1);
>> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
>>  		reg &= ~DSPFW_SR_MASK;
>>  		reg |= FW_WM(wm, SR);
>> -		I915_WRITE(DSPFW1, reg);
>> +		intel_uncore_write(&dev_priv->uncore, DSPFW1, reg);
>>  		drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
>>  
>>  		/* cursor SR */
>>  		wm = intel_calculate_wm(clock, &pnv_cursor_wm,
>>  					pnv_display_wm.fifo_size,
>>  					4, latency->cursor_sr);
>> -		reg = I915_READ(DSPFW3);
>> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
>>  		reg &= ~DSPFW_CURSOR_SR_MASK;
>>  		reg |= FW_WM(wm, CURSOR_SR);
>> -		I915_WRITE(DSPFW3, reg);
>> +		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
>>  
>>  		/* Display HPLL off SR */
>>  		wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
>>  					pnv_display_hplloff_wm.fifo_size,
>>  					cpp, latency->display_hpll_disable);
>> -		reg = I915_READ(DSPFW3);
>> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
>>  		reg &= ~DSPFW_HPLL_SR_MASK;
>>  		reg |= FW_WM(wm, HPLL_SR);
>> -		I915_WRITE(DSPFW3, reg);
>> +		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
>>  
>>  		/* cursor HPLL off SR */
>>  		wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
>>  					pnv_display_hplloff_wm.fifo_size,
>>  					4, latency->cursor_hpll_disable);
>> -		reg = I915_READ(DSPFW3);
>> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
>>  		reg &= ~DSPFW_HPLL_CURSOR_MASK;
>>  		reg |= FW_WM(wm, HPLL_CURSOR);
>> -		I915_WRITE(DSPFW3, reg);
>> +		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
>>  		drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
>>  
>>  		intel_set_memory_cxsr(dev_priv, true);
>> @@ -975,25 +975,25 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
>>  	for_each_pipe(dev_priv, pipe)
>>  		trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
>>  
>> -	I915_WRITE(DSPFW1,
>> +	intel_uncore_write(&dev_priv->uncore, DSPFW1,
>>  		   FW_WM(wm->sr.plane, SR) |
>>  		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
>>  		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
>>  		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
>> -	I915_WRITE(DSPFW2,
>> +	intel_uncore_write(&dev_priv->uncore, DSPFW2,
>>  		   (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
>>  		   FW_WM(wm->sr.fbc, FBC_SR) |
>>  		   FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
>>  		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
>>  		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
>>  		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
>> -	I915_WRITE(DSPFW3,
>> +	intel_uncore_write(&dev_priv->uncore, DSPFW3,
>>  		   (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
>>  		   FW_WM(wm->sr.cursor, CURSOR_SR) |
>>  		   FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
>>  		   FW_WM(wm->hpll.plane, HPLL_SR));
>>  
>> -	POSTING_READ(DSPFW1);
>> +	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
>>  }
>>  
>>  #define FW_WM_VLV(value, plane) \
>> @@ -1007,7 +1007,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
>>  	for_each_pipe(dev_priv, pipe) {
>>  		trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
>>  
>> -		I915_WRITE(VLV_DDL(pipe),
>> +		intel_uncore_write(&dev_priv->uncore, VLV_DDL(pipe),
>>  			   (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
>>  			   (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
>>  			   (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
>> @@ -1019,35 +1019,35 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
>>  	 * high order bits so that there are no out of bounds values
>>  	 * present in the registers during the reprogramming.
>>  	 */
>> -	I915_WRITE(DSPHOWM, 0);
>> -	I915_WRITE(DSPHOWM1, 0);
>> -	I915_WRITE(DSPFW4, 0);
>> -	I915_WRITE(DSPFW5, 0);
>> -	I915_WRITE(DSPFW6, 0);
>> +	intel_uncore_write(&dev_priv->uncore, DSPHOWM, 0);
>> +	intel_uncore_write(&dev_priv->uncore, DSPHOWM1, 0);
>> +	intel_uncore_write(&dev_priv->uncore, DSPFW4, 0);
>> +	intel_uncore_write(&dev_priv->uncore, DSPFW5, 0);
>> +	intel_uncore_write(&dev_priv->uncore, DSPFW6, 0);
>>  
>> -	I915_WRITE(DSPFW1,
>> +	intel_uncore_write(&dev_priv->uncore, DSPFW1,
>>  		   FW_WM(wm->sr.plane, SR) |
>>  		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
>>  		   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
>>  		   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
>> -	I915_WRITE(DSPFW2,
>> +	intel_uncore_write(&dev_priv->uncore, DSPFW2,
>>  		   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
>>  		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
>>  		   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
>> -	I915_WRITE(DSPFW3,
>> +	intel_uncore_write(&dev_priv->uncore, DSPFW3,
>>  		   FW_WM(wm->sr.cursor, CURSOR_SR));
>>  
>>  	if (IS_CHERRYVIEW(dev_priv)) {
>> -		I915_WRITE(DSPFW7_CHV,
>> +		intel_uncore_write(&dev_priv->uncore, DSPFW7_CHV,
>>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
>>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
>> -		I915_WRITE(DSPFW8_CHV,
>> +		intel_uncore_write(&dev_priv->uncore, DSPFW8_CHV,
>>  			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
>>  			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
>> -		I915_WRITE(DSPFW9_CHV,
>> +		intel_uncore_write(&dev_priv->uncore, DSPFW9_CHV,
>>  			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
>>  			   FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
>> -		I915_WRITE(DSPHOWM,
>> +		intel_uncore_write(&dev_priv->uncore, DSPHOWM,
>>  			   FW_WM(wm->sr.plane >> 9, SR_HI) |
>>  			   FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
>>  			   FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
>> @@ -1059,10 +1059,10 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
>>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
>>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
>>  	} else {
>> -		I915_WRITE(DSPFW7,
>> +		intel_uncore_write(&dev_priv->uncore, DSPFW7,
>>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
>>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
>> -		I915_WRITE(DSPHOWM,
>> +		intel_uncore_write(&dev_priv->uncore, DSPHOWM,
>>  			   FW_WM(wm->sr.plane >> 9, SR_HI) |
>>  			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
>>  			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
>> @@ -1072,7 +1072,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
>>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
>>  	}
>>  
>> -	POSTING_READ(DSPFW1);
>> +	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
>>  }
>>  
>>  #undef FW_WM_VLV
>> @@ -2309,14 +2309,14 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
>>  		    srwm);
>>  
>>  	/* 965 has limitations... */
>> -	I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
>> +	intel_uncore_write(&dev_priv->uncore, DSPFW1, FW_WM(srwm, SR) |
>>  		   FW_WM(8, CURSORB) |
>>  		   FW_WM(8, PLANEB) |
>>  		   FW_WM(8, PLANEA));
>> -	I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
>> +	intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) |
>>  		   FW_WM(8, PLANEC_OLD));
>>  	/* update cursor SR watermark */
>> -	I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
>> +	intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
>>  
>>  	if (cxsr_enabled)
>>  		intel_set_memory_cxsr(dev_priv, true);
>> @@ -2446,10 +2446,10 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>>  			srwm = 1;
>>  
>>  		if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
>> -			I915_WRITE(FW_BLC_SELF,
>> +			intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF,
>>  				   FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
>>  		else
>> -			I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
>> +			intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, srwm & 0x3f);
>>  	}
>>  
>>  	drm_dbg_kms(&dev_priv->drm,
>> @@ -2463,8 +2463,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>>  	fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
>>  	fwater_hi = fwater_hi | (1 << 8);
>>  
>> -	I915_WRITE(FW_BLC, fwater_lo);
>> -	I915_WRITE(FW_BLC2, fwater_hi);
>> +	intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
>> +	intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
>>  
>>  	if (enabled)
>>  		intel_set_memory_cxsr(dev_priv, true);
>> @@ -2487,13 +2487,13 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
>>  				       &i845_wm_info,
>>  				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
>>  				       4, pessimal_latency_ns);
>> -	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
>> +	fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
>>  	fwater_lo |= (3<<8) | planea_wm;
>>  
>>  	drm_dbg_kms(&dev_priv->drm,
>>  		    "Setting FIFO watermarks - A: %d\n", planea_wm);
>>  
>> -	I915_WRITE(FW_BLC, fwater_lo);
>> +	intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
>>  }
>>  
>>  /* latency must be in 0.1us units. */
>> @@ -3533,17 +3533,17 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
>>  
>>  	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
>>  		previous->wm_lp[2] &= ~WM1_LP_SR_EN;
>> -		I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
>> +		intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, previous->wm_lp[2]);
>>  		changed = true;
>>  	}
>>  	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
>>  		previous->wm_lp[1] &= ~WM1_LP_SR_EN;
>> -		I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
>> +		intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, previous->wm_lp[1]);
>>  		changed = true;
>>  	}
>>  	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
>>  		previous->wm_lp[0] &= ~WM1_LP_SR_EN;
>> -		I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
>> +		intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, previous->wm_lp[0]);
>>  		changed = true;
>>  	}
>>  
>> @@ -3573,56 +3573,56 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
>>  	_ilk_disable_lp_wm(dev_priv, dirty);
>>  
>>  	if (dirty & WM_DIRTY_PIPE(PIPE_A))
>> -		I915_WRITE(WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
>> +		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
>>  	if (dirty & WM_DIRTY_PIPE(PIPE_B))
>> -		I915_WRITE(WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
>> +		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
>>  	if (dirty & WM_DIRTY_PIPE(PIPE_C))
>> -		I915_WRITE(WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
>> +		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
>>  
>>  	if (dirty & WM_DIRTY_DDB) {
>>  		if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>> -			val = I915_READ(WM_MISC);
>> +			val = intel_uncore_read(&dev_priv->uncore, WM_MISC);
>>  			if (results->partitioning == INTEL_DDB_PART_1_2)
>>  				val &= ~WM_MISC_DATA_PARTITION_5_6;
>>  			else
>>  				val |= WM_MISC_DATA_PARTITION_5_6;
>> -			I915_WRITE(WM_MISC, val);
>> +			intel_uncore_write(&dev_priv->uncore, WM_MISC, val);
>>  		} else {
>> -			val = I915_READ(DISP_ARB_CTL2);
>> +			val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2);
>>  			if (results->partitioning == INTEL_DDB_PART_1_2)
>>  				val &= ~DISP_DATA_PARTITION_5_6;
>>  			else
>>  				val |= DISP_DATA_PARTITION_5_6;
>> -			I915_WRITE(DISP_ARB_CTL2, val);
>> +			intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL2, val);
>>  		}
>>  	}
>>  
>>  	if (dirty & WM_DIRTY_FBC) {
>> -		val = I915_READ(DISP_ARB_CTL);
>> +		val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL);
>>  		if (results->enable_fbc_wm)
>>  			val &= ~DISP_FBC_WM_DIS;
>>  		else
>>  			val |= DISP_FBC_WM_DIS;
>> -		I915_WRITE(DISP_ARB_CTL, val);
>> +		intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, val);
>>  	}
>>  
>>  	if (dirty & WM_DIRTY_LP(1) &&
>>  	    previous->wm_lp_spr[0] != results->wm_lp_spr[0])
>> -		I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
>> +		intel_uncore_write(&dev_priv->uncore, WM1S_LP_ILK, results->wm_lp_spr[0]);
>>  
>>  	if (INTEL_GEN(dev_priv) >= 7) {
>>  		if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
>> -			I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
>> +			intel_uncore_write(&dev_priv->uncore, WM2S_LP_IVB, results->wm_lp_spr[1]);
>>  		if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
>> -			I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
>> +			intel_uncore_write(&dev_priv->uncore, WM3S_LP_IVB, results->wm_lp_spr[2]);
>>  	}
>>  
>>  	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
>> -		I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
>> +		intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, results->wm_lp[0]);
>>  	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
>> -		I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
>> +		intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, results->wm_lp[1]);
>>  	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
>> -		I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
>> +		intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, results->wm_lp[2]);
>>  
>>  	dev_priv->wm.hw = *results;
>>  }
>> @@ -3639,7 +3639,7 @@ u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
>>  	u8 enabled_slices_mask = 0;
>>  
>>  	for (i = 0; i < max_slices; i++) {
>> -		if (I915_READ(DBUF_CTL_S(i)) & DBUF_POWER_STATE)
>> +		if (intel_uncore_read(&dev_priv->uncore, DBUF_CTL_S(i)) & DBUF_POWER_STATE)
>>  			enabled_slices_mask |= BIT(i);
>>  	}
>>  
>> @@ -4307,12 +4307,12 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>>  
>>  	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
>>  	if (plane_id == PLANE_CURSOR) {
>> -		val = I915_READ(CUR_BUF_CFG(pipe));
>> +		val = intel_uncore_read(&dev_priv->uncore, CUR_BUF_CFG(pipe));
>>  		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
>>  		return;
>>  	}
>>  
>> -	val = I915_READ(PLANE_CTL(pipe, plane_id));
>> +	val = intel_uncore_read(&dev_priv->uncore, PLANE_CTL(pipe, plane_id));
>>  
>>  	/* No DDB allocated for disabled planes */
>>  	if (val & PLANE_CTL_ENABLE)
>> @@ -4321,11 +4321,11 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>>  					      val & PLANE_CTL_ALPHA_MASK);
>>  
>>  	if (INTEL_GEN(dev_priv) >= 11) {
>> -		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
>> +		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
>>  		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
>>  	} else {
>> -		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
>> -		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
>> +		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
>> +		val2 = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
>>  
>>  		if (fourcc &&
>>  		    drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
>> @@ -6240,9 +6240,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>>  
>>  		for (level = 0; level <= max_level; level++) {
>>  			if (plane_id != PLANE_CURSOR)
>> -				val = I915_READ(PLANE_WM(pipe, plane_id, level));
>> +				val = intel_uncore_read(&dev_priv->uncore, PLANE_WM(pipe, plane_id, level));
>>  			else
>> -				val = I915_READ(CUR_WM(pipe, level));
>> +				val = intel_uncore_read(&dev_priv->uncore, CUR_WM(pipe, level));
>>  
>>  			skl_wm_level_from_reg_val(val, &wm->wm[level]);
>>  		}
>> @@ -6251,9 +6251,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>>  			wm->sagv_wm0 = wm->wm[0];
>>  
>>  		if (plane_id != PLANE_CURSOR)
>> -			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
>> +			val = intel_uncore_read(&dev_priv->uncore, PLANE_WM_TRANS(pipe, plane_id));
>>  		else
>> -			val = I915_READ(CUR_WM_TRANS(pipe));
>> +			val = intel_uncore_read(&dev_priv->uncore, CUR_WM_TRANS(pipe));
>>  
>>  		skl_wm_level_from_reg_val(val, &wm->trans_wm);
>>  	}
>> @@ -6288,7 +6288,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
>>  	struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
>>  	enum pipe pipe = crtc->pipe;
>>  
>> -	hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe));
>> +	hw->wm_pipe[pipe] = intel_uncore_read(&dev_priv->uncore, WM0_PIPE_ILK(pipe));
>>  
>>  	memset(active, 0, sizeof(*active));
>>  
>> @@ -6332,13 +6332,13 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
>>  {
>>  	u32 tmp;
>>  
>> -	tmp = I915_READ(DSPFW1);
>> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
>>  	wm->sr.plane = _FW_WM(tmp, SR);
>>  	wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
>>  	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
>>  	wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
>>  
>> -	tmp = I915_READ(DSPFW2);
>> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
>>  	wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
>>  	wm->sr.fbc = _FW_WM(tmp, FBC_SR);
>>  	wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
>> @@ -6346,7 +6346,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
>>  	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
>>  	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
>>  
>> -	tmp = I915_READ(DSPFW3);
>> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
>>  	wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
>>  	wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
>>  	wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
>> @@ -6360,7 +6360,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
>>  	u32 tmp;
>>  
>>  	for_each_pipe(dev_priv, pipe) {
>> -		tmp = I915_READ(VLV_DDL(pipe));
>> +		tmp = intel_uncore_read(&dev_priv->uncore, VLV_DDL(pipe));
>>  
>>  		wm->ddl[pipe].plane[PLANE_PRIMARY] =
>>  			(tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
>> @@ -6372,34 +6372,34 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
>>  			(tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
>>  	}
>>  
>> -	tmp = I915_READ(DSPFW1);
>> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
>>  	wm->sr.plane = _FW_WM(tmp, SR);
>>  	wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
>>  	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
>>  	wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
>>  
>> -	tmp = I915_READ(DSPFW2);
>> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
>>  	wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
>>  	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
>>  	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
>>  
>> -	tmp = I915_READ(DSPFW3);
>> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
>>  	wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
>>  
>>  	if (IS_CHERRYVIEW(dev_priv)) {
>> -		tmp = I915_READ(DSPFW7_CHV);
>> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7_CHV);
>>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
>>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
>>  
>> -		tmp = I915_READ(DSPFW8_CHV);
>> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW8_CHV);
>>  		wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
>>  		wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
>>  
>> -		tmp = I915_READ(DSPFW9_CHV);
>> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW9_CHV);
>>  		wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
>>  		wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
>>  
>> -		tmp = I915_READ(DSPHOWM);
>> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
>>  		wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
>>  		wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
>>  		wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
>> @@ -6411,11 +6411,11 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
>>  		wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
>>  		wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
>>  	} else {
>> -		tmp = I915_READ(DSPFW7);
>> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7);
>>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
>>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
>>  
>> -		tmp = I915_READ(DSPHOWM);
>> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
>>  		wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
>>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
>>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
>> @@ -6436,7 +6436,7 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
>>  
>>  	g4x_read_wm_values(dev_priv, wm);
>>  
>> -	wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
>> +	wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
>>  
>>  	for_each_intel_crtc(&dev_priv->drm, crtc) {
>>  		struct intel_crtc_state *crtc_state =
>> @@ -6580,7 +6580,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
>>  
>>  	vlv_read_wm_values(dev_priv, wm);
>>  
>> -	wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>> +	wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>>  	wm->level = VLV_WM_LEVEL_PM2;
>>  
>>  	if (IS_CHERRYVIEW(dev_priv)) {
>> @@ -6727,9 +6727,9 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
>>   */
>>  static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
>>  {
>> -	I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
>> -	I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
>> -	I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
>> +	intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM1_LP_SR_EN);
>> +	intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM1_LP_SR_EN);
>> +	intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM1_LP_SR_EN);
>>  
>>  	/*
>>  	 * Don't touch WM1S_LP_EN here.
>> @@ -6747,25 +6747,25 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
>>  	for_each_intel_crtc(&dev_priv->drm, crtc)
>>  		ilk_pipe_wm_get_hw_state(crtc);
>>  
>> -	hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
>> -	hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
>> -	hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
>> +	hw->wm_lp[0] = intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK);
>> +	hw->wm_lp[1] = intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK);
>> +	hw->wm_lp[2] = intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK);
>>  
>> -	hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
>> +	hw->wm_lp_spr[0] = intel_uncore_read(&dev_priv->uncore, WM1S_LP_ILK);
>>  	if (INTEL_GEN(dev_priv) >= 7) {
>> -		hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
>> -		hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
>> +		hw->wm_lp_spr[1] = intel_uncore_read(&dev_priv->uncore, WM2S_LP_IVB);
>> +		hw->wm_lp_spr[2] = intel_uncore_read(&dev_priv->uncore, WM3S_LP_IVB);
>>  	}
>>  
>>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>> -		hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
>> +		hw->partitioning = (intel_uncore_read(&dev_priv->uncore, WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
>>  			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
>>  	else if (IS_IVYBRIDGE(dev_priv))
>> -		hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
>> +		hw->partitioning = (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
>>  			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
>>  
>>  	hw->enable_fbc_wm =
>> -		!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
>> +		!(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
>>  }
>>  
>>  /**
>> @@ -6816,14 +6816,14 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
>>  	if (!HAS_IPC(dev_priv))
>>  		return;
>>  
>> -	val = I915_READ(DISP_ARB_CTL2);
>> +	val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2);
>>  
>>  	if (dev_priv->ipc_enabled)
>>  		val |= DISP_IPC_ENABLE;
>>  	else
>>  		val &= ~DISP_IPC_ENABLE;
>>  
>> -	I915_WRITE(DISP_ARB_CTL2, val);
>> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL2, val);
>>  }
>>  
>>  static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv)
>> @@ -6858,7 +6858,7 @@ static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	 * gating for the panel power sequencer or it will fail to
>>  	 * start up when no ports are active.
>>  	 */
>> -	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
>> +	intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
>>  }
>>  
>>  static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
>> @@ -6866,12 +6866,12 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
>>  	enum pipe pipe;
>>  
>>  	for_each_pipe(dev_priv, pipe) {
>> -		I915_WRITE(DSPCNTR(pipe),
>> -			   I915_READ(DSPCNTR(pipe)) |
>> +		intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe),
>> +			   intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) |
>>  			   DISPPLANE_TRICKLE_FEED_DISABLE);
>>  
>> -		I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
>> -		POSTING_READ(DSPSURF(pipe));
>> +		intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(pipe)));
>> +		intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe));
>>  	}
>>  }
>>  
>> @@ -6887,10 +6887,10 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
>>  		   ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
>>  		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
>>  
>> -	I915_WRITE(PCH_3DCGDIS0,
>> +	intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS0,
>>  		   MARIUNIT_CLOCK_GATE_DISABLE |
>>  		   SVSMUNIT_CLOCK_GATE_DISABLE);
>> -	I915_WRITE(PCH_3DCGDIS1,
>> +	intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS1,
>>  		   VFMUNIT_CLOCK_GATE_DISABLE);
>>  
>>  	/*
>> @@ -6900,12 +6900,12 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	 * The bit 5 of 0x42020
>>  	 * The bit 15 of 0x45000
>>  	 */
>> -	I915_WRITE(ILK_DISPLAY_CHICKEN2,
>> -		   (I915_READ(ILK_DISPLAY_CHICKEN2) |
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
>> +		   (intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
>>  		    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
>>  	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
>> -	I915_WRITE(DISP_ARB_CTL,
>> -		   (I915_READ(DISP_ARB_CTL) |
>> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL,
>> +		   (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>>  		    DISP_FBC_WM_DIS));
>>  
>>  	/*
>> @@ -6917,18 +6917,18 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	 */
>>  	if (IS_IRONLAKE_M(dev_priv)) {
>>  		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
>> -		I915_WRITE(ILK_DISPLAY_CHICKEN1,
>> -			   I915_READ(ILK_DISPLAY_CHICKEN1) |
>> +		intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
>> +			   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
>>  			   ILK_FBCQ_DIS);
>> -		I915_WRITE(ILK_DISPLAY_CHICKEN2,
>> -			   I915_READ(ILK_DISPLAY_CHICKEN2) |
>> +		intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
>> +			   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
>>  			   ILK_DPARB_GATE);
>>  	}
>>  
>> -	I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
>>  
>> -	I915_WRITE(ILK_DISPLAY_CHICKEN2,
>> -		   I915_READ(ILK_DISPLAY_CHICKEN2) |
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
>> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
>>  		   ILK_ELPIN_409_SELECT);
>>  
>>  	g4x_disable_trickle_feed(dev_priv);
>> @@ -6946,27 +6946,27 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	 * gating for the panel power sequencer or it will fail to
>>  	 * start up when no ports are active.
>>  	 */
>> -	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
>> +	intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
>>  		   PCH_DPLUNIT_CLOCK_GATE_DISABLE |
>>  		   PCH_CPUNIT_CLOCK_GATE_DISABLE);
>> -	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
>> +	intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN2, intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN2) |
>>  		   DPLS_EDP_PPS_FIX_DIS);
>>  	/* The below fixes the weird display corruption, a few pixels shifted
>>  	 * downward, on (only) LVDS of some HP laptops with IVY.
>>  	 */
>>  	for_each_pipe(dev_priv, pipe) {
>> -		val = I915_READ(TRANS_CHICKEN2(pipe));
>> +		val = intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN2(pipe));
>>  		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
>>  		val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
>>  		if (dev_priv->vbt.fdi_rx_polarity_inverted)
>>  			val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
>>  		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
>>  		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
>> -		I915_WRITE(TRANS_CHICKEN2(pipe), val);
>> +		intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN2(pipe), val);
>>  	}
>>  	/* WADP0ClockGatingDisable */
>>  	for_each_pipe(dev_priv, pipe) {
>> -		I915_WRITE(TRANS_CHICKEN1(pipe),
>> +		intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(pipe),
>>  			   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
>>  	}
>>  }
>> @@ -6975,7 +6975,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
>>  {
>>  	u32 tmp;
>>  
>> -	tmp = I915_READ(MCH_SSKPD);
>> +	tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD);
>>  	if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
>>  		drm_dbg_kms(&dev_priv->drm,
>>  			    "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
>> @@ -6986,14 +6986,14 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>>  	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
>>  
>> -	I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
>>  
>> -	I915_WRITE(ILK_DISPLAY_CHICKEN2,
>> -		   I915_READ(ILK_DISPLAY_CHICKEN2) |
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
>> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
>>  		   ILK_ELPIN_409_SELECT);
>>  
>> -	I915_WRITE(GEN6_UCGCTL1,
>> -		   I915_READ(GEN6_UCGCTL1) |
>> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
>> +		   intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
>>  		   GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
>>  		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
>>  
>> @@ -7010,7 +7010,7 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	 * WaDisableRCCUnitClockGating:snb
>>  	 * WaDisableRCPBUnitClockGating:snb
>>  	 */
>> -	I915_WRITE(GEN6_UCGCTL2,
>> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
>>  		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
>>  		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
>>  
>> @@ -7025,14 +7025,14 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	 *
>>  	 * WaFbcAsynchFlipDisableFbcQueue:snb
>>  	 */
>> -	I915_WRITE(ILK_DISPLAY_CHICKEN1,
>> -		   I915_READ(ILK_DISPLAY_CHICKEN1) |
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
>> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
>>  		   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
>> -	I915_WRITE(ILK_DISPLAY_CHICKEN2,
>> -		   I915_READ(ILK_DISPLAY_CHICKEN2) |
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
>> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
>>  		   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
>> -	I915_WRITE(ILK_DSPCLK_GATE_D,
>> -		   I915_READ(ILK_DSPCLK_GATE_D) |
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D,
>> +		   intel_uncore_read(&dev_priv->uncore, ILK_DSPCLK_GATE_D) |
>>  		   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
>>  		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
>>  
>> @@ -7050,23 +7050,23 @@ static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	 * disabled when not needed anymore in order to save power.
>>  	 */
>>  	if (HAS_PCH_LPT_LP(dev_priv))
>> -		I915_WRITE(SOUTH_DSPCLK_GATE_D,
>> -			   I915_READ(SOUTH_DSPCLK_GATE_D) |
>> +		intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D,
>> +			   intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |
>>  			   PCH_LP_PARTITION_LEVEL_DISABLE);
>>  
>>  	/* WADPOClockGatingDisable:hsw */
>> -	I915_WRITE(TRANS_CHICKEN1(PIPE_A),
>> -		   I915_READ(TRANS_CHICKEN1(PIPE_A)) |
>> +	intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A),
>> +		   intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A)) |
>>  		   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
>>  }
>>  
>>  static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
>>  {
>>  	if (HAS_PCH_LPT_LP(dev_priv)) {
>> -		u32 val = I915_READ(SOUTH_DSPCLK_GATE_D);
>> +		u32 val = intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D);
>>  
>>  		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
>> -		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
>> +		intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, val);
>>  	}
>>  }
>>  
>> @@ -7078,33 +7078,33 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
>>  	u32 val;
>>  
>>  	/* WaTempDisableDOPClkGating:bdw */
>> -	misccpctl = I915_READ(GEN7_MISCCPCTL);
>> -	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
>> +	misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
>> +	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
>>  
>> -	val = I915_READ(GEN8_L3SQCREG1);
>> +	val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
>>  	val &= ~L3_PRIO_CREDITS_MASK;
>>  	val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
>>  	val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
>> -	I915_WRITE(GEN8_L3SQCREG1, val);
>> +	intel_uncore_write(&dev_priv->uncore, GEN8_L3SQCREG1, val);
>>  
>>  	/*
>>  	 * Wait at least 100 clocks before re-enabling clock gating.
>>  	 * See the definition of L3SQCREG1 in BSpec.
>>  	 */
>> -	POSTING_READ(GEN8_L3SQCREG1);
>> +	intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
>>  	udelay(1);
>> -	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
>> +	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
>>  }
>>  
>>  static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>>  	/* Wa_1409120013:icl,ehl */
>> -	I915_WRITE(ILK_DPFC_CHICKEN,
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
>>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>>  
>>  	/* This is not an Wa. Enable to reduce Sampler power */
>> -	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
>> -		   I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
>> +	intel_uncore_write(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
>> +		   intel_uncore_read(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
>>  
>>  	/*Wa_14010594013:icl, ehl */
>>  	intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
>> @@ -7114,12 +7114,12 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
>>  static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>>  	/* Wa_1409120013:tgl */
>> -	I915_WRITE(ILK_DPFC_CHICKEN,
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
>>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>>  
>>  	/* Wa_1409825376:tgl (pre-prod)*/
>>  	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
>> -		I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
>> +		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>>  			   TGL_VRH_GATING_DIS);
>>  
>>  	/* Wa_14011059788:tgl */
>> @@ -7131,7 +7131,7 @@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>>  	/* Wa_1409836686:dg1[a0] */
>>  	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
>> -		I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
>> +		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>>  			   DPT_GATING_DIS);
>>  }
>>  
>> @@ -7141,7 +7141,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
>>  		return;
>>  
>>  	/* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
>> -	I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
>> +	intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |
>>  		   CNP_PWM_CGE_GATING_DISABLE);
>>  }
>>  
>> @@ -7151,35 +7151,35 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	cnp_init_clock_gating(dev_priv);
>>  
>>  	/* This is not an Wa. Enable for better image quality */
>> -	I915_WRITE(_3D_CHICKEN3,
>> +	intel_uncore_write(&dev_priv->uncore, _3D_CHICKEN3,
>>  		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
>>  
>>  	/* WaEnableChickenDCPR:cnl */
>> -	I915_WRITE(GEN8_CHICKEN_DCPR_1,
>> -		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>> +	intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
>> +		   intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>>  
>>  	/*
>>  	 * WaFbcWakeMemOn:cnl
>>  	 * Display WA #0859: cnl
>>  	 */
>> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>>  		   DISP_FBC_MEMORY_WAKE);
>>  
>> -	val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);
>> +	val = intel_uncore_read(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE);
>>  	/* ReadHitWriteOnlyDisable:cnl */
>>  	val |= RCCUNIT_CLKGATE_DIS;
>> -	I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
>> +	intel_uncore_write(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE, val);
>>  
>>  	/* Wa_2201832410:cnl */
>> -	val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
>> +	val = intel_uncore_read(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE);
>>  	val |= GWUNIT_CLKGATE_DIS;
>> -	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
>> +	intel_uncore_write(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE, val);
>>  
>>  	/* WaDisableVFclkgate:cnl */
>>  	/* WaVFUnitClockGatingDisable:cnl */
>> -	val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
>> +	val = intel_uncore_read(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE);
>>  	val |= VFUNIT_CLKGATE_DIS;
>> -	I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val);
>> +	intel_uncore_write(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE, val);
>>  }
>>  
>>  static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
>> @@ -7188,21 +7188,21 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	gen9_init_clock_gating(dev_priv);
>>  
>>  	/* WAC6entrylatency:cfl */
>> -	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
>> +	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
>>  		   FBC_LLC_FULLY_OPEN);
>>  
>>  	/*
>>  	 * WaFbcTurnOffFbcWatermark:cfl
>>  	 * Display WA #0562: cfl
>>  	 */
>> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>>  		   DISP_FBC_WM_DIS);
>>  
>>  	/*
>>  	 * WaFbcNukeOnHostModify:cfl
>>  	 * Display WA #0873: cfl
>>  	 */
>> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
>>  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>>  }
>>  
>> @@ -7211,31 +7211,31 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	gen9_init_clock_gating(dev_priv);
>>  
>>  	/* WAC6entrylatency:kbl */
>> -	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
>> +	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
>>  		   FBC_LLC_FULLY_OPEN);
>>  
>>  	/* WaDisableSDEUnitClockGating:kbl */
>>  	if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0))
>> -		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>> +		intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
>>  			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>>  
>>  	/* WaDisableGamClockGating:kbl */
>>  	if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0))
>> -		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
>> +		intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
>>  			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
>>  
>>  	/*
>>  	 * WaFbcTurnOffFbcWatermark:kbl
>>  	 * Display WA #0562: kbl
>>  	 */
>> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>>  		   DISP_FBC_WM_DIS);
>>  
>>  	/*
>>  	 * WaFbcNukeOnHostModify:kbl
>>  	 * Display WA #0873: kbl
>>  	 */
>> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
>>  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>>  }
>>  
>> @@ -7244,32 +7244,32 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	gen9_init_clock_gating(dev_priv);
>>  
>>  	/* WaDisableDopClockGating:skl */
>> -	I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) &
>> +	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL) &
>>  		   ~GEN7_DOP_CLOCK_GATE_ENABLE);
>>  
>>  	/* WAC6entrylatency:skl */
>> -	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
>> +	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
>>  		   FBC_LLC_FULLY_OPEN);
>>  
>>  	/*
>>  	 * WaFbcTurnOffFbcWatermark:skl
>>  	 * Display WA #0562: skl
>>  	 */
>> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
>>  		   DISP_FBC_WM_DIS);
>>  
>>  	/*
>>  	 * WaFbcNukeOnHostModify:skl
>>  	 * Display WA #0873: skl
>>  	 */
>> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
>>  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>>  
>>  	/*
>>  	 * WaFbcHighMemBwCorruptionAvoidance:skl
>>  	 * Display WA #0883: skl
>>  	 */
>> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
>>  		   ILK_DPFC_DISABLE_DUMMY0);
>>  }
>>  
>> @@ -7278,42 +7278,42 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	enum pipe pipe;
>>  
>>  	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
>> -	I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
>> -		   I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
>> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
>> +		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |
>>  		   HSW_FBCQ_DIS);
>>  
>>  	/* WaSwitchSolVfFArbitrationPriority:bdw */
>> -	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>> +	intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>>  
>>  	/* WaPsrDPAMaskVBlankInSRD:bdw */
>> -	I915_WRITE(CHICKEN_PAR1_1,
>> -		   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
>> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
>> +		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
>>  
>>  	/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
>>  	for_each_pipe(dev_priv, pipe) {
>> -		I915_WRITE(CHICKEN_PIPESL_1(pipe),
>> -			   I915_READ(CHICKEN_PIPESL_1(pipe)) |
>> +		intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
>> +			   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe)) |
>>  			   BDW_DPRS_MASK_VBLANK_SRD);
>>  	}
>>  
>>  	/* WaVSRefCountFullforceMissDisable:bdw */
>>  	/* WaDSRefCountFullforceMissDisable:bdw */
>> -	I915_WRITE(GEN7_FF_THREAD_MODE,
>> -		   I915_READ(GEN7_FF_THREAD_MODE) &
>> +	intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
>> +		   intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
>>  		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
>>  
>> -	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
>> +	intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
>>  		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
>>  
>>  	/* WaDisableSDEUnitClockGating:bdw */
>> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>> +	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
>>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>>  
>>  	/* WaProgramL3SqcReg1Default:bdw */
>>  	gen8_set_l3sqc_credits(dev_priv, 30, 2);
>>  
>>  	/* WaKVMNotificationOnConfigChange:bdw */
>> -	I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
>> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR2_1, intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR2_1)
>>  		   | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
>>  
>>  	lpt_init_clock_gating(dev_priv);
>> @@ -7323,24 +7323,24 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
>>  	 * clock gating.
>>  	 */
>> -	I915_WRITE(GEN6_UCGCTL1,
>> -		   I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
>> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
>> +		   intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
>>  }
>>  
>>  static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>>  	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
>> -	I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
>> -		   I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
>> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
>> +		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |
>>  		   HSW_FBCQ_DIS);
>>  
>>  	/* This is required by WaCatErrorRejectionIssue:hsw */
>> -	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>> -		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>> +	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>> +		   intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>>  		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>>  
>>  	/* WaSwitchSolVfFArbitrationPriority:hsw */
>> -	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>> +	intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>>  
>>  	lpt_init_clock_gating(dev_priv);
>>  }
>> @@ -7349,26 +7349,26 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>>  	u32 snpcr;
>>  
>> -	I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
>>  
>>  	/* WaFbcAsynchFlipDisableFbcQueue:ivb */
>> -	I915_WRITE(ILK_DISPLAY_CHICKEN1,
>> -		   I915_READ(ILK_DISPLAY_CHICKEN1) |
>> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
>> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
>>  		   ILK_FBCQ_DIS);
>>  
>>  	/* WaDisableBackToBackFlipFix:ivb */
>> -	I915_WRITE(IVB_CHICKEN3,
>> +	intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
>>  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
>>  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
>>  
>>  	if (IS_IVB_GT1(dev_priv))
>> -		I915_WRITE(GEN7_ROW_CHICKEN2,
>> +		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
>>  			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>>  	else {
>>  		/* must write both registers */
>> -		I915_WRITE(GEN7_ROW_CHICKEN2,
>> +		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
>>  			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>> -		I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
>> +		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2_GT2,
>>  			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>>  	}
>>  
>> @@ -7376,20 +7376,20 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>>  	 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
>>  	 */
>> -	I915_WRITE(GEN6_UCGCTL2,
>> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
>>  		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>>  
>>  	/* This is required by WaCatErrorRejectionIssue:ivb */
>> -	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>> -			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>> +	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>> +			intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>>  			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>>  
>>  	g4x_disable_trickle_feed(dev_priv);
>>  
>> -	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
>> +	snpcr = intel_uncore_read(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR);
>>  	snpcr &= ~GEN6_MBC_SNPCR_MASK;
>>  	snpcr |= GEN6_MBC_SNPCR_MED;
>> -	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
>> +	intel_uncore_write(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR, snpcr);
>>  
>>  	if (!HAS_PCH_NOP(dev_priv))
>>  		cpt_init_clock_gating(dev_priv);
>> @@ -7400,58 +7400,58 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
>>  static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>>  	/* WaDisableBackToBackFlipFix:vlv */
>> -	I915_WRITE(IVB_CHICKEN3,
>> +	intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
>>  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
>>  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
>>  
>>  	/* WaDisableDopClockGating:vlv */
>> -	I915_WRITE(GEN7_ROW_CHICKEN2,
>> +	intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
>>  		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>>  
>>  	/* This is required by WaCatErrorRejectionIssue:vlv */
>> -	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>> -		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>> +	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>> +		   intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>>  		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>>  
>>  	/*
>>  	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>>  	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
>>  	 */
>> -	I915_WRITE(GEN6_UCGCTL2,
>> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
>>  		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>>  
>>  	/* WaDisableL3Bank2xClockGate:vlv
>>  	 * Disabling L3 clock gating- MMIO 940c[25] = 1
>>  	 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
>> -	I915_WRITE(GEN7_UCGCTL4,
>> -		   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
>> +	intel_uncore_write(&dev_priv->uncore, GEN7_UCGCTL4,
>> +		   intel_uncore_read(&dev_priv->uncore, GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
>>  
>>  	/*
>>  	 * WaDisableVLVClockGating_VBIIssue:vlv
>>  	 * Disable clock gating on th GCFG unit to prevent a delay
>>  	 * in the reporting of vblank events.
>>  	 */
>> -	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
>> +	intel_uncore_write(&dev_priv->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
>>  }
>>  
>>  static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>>  	/* WaVSRefCountFullforceMissDisable:chv */
>>  	/* WaDSRefCountFullforceMissDisable:chv */
>> -	I915_WRITE(GEN7_FF_THREAD_MODE,
>> -		   I915_READ(GEN7_FF_THREAD_MODE) &
>> +	intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
>> +		   intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
>>  		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
>>  
>>  	/* WaDisableSemaphoreAndSyncFlipWait:chv */
>> -	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
>> +	intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
>>  		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
>>  
>>  	/* WaDisableCSUnitClockGating:chv */
>> -	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
>> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
>>  		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
>>  
>>  	/* WaDisableSDEUnitClockGating:chv */
>> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>> +	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
>>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>>  
>>  	/*
>> @@ -7466,17 +7466,17 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>>  	u32 dspclk_gate;
>>  
>> -	I915_WRITE(RENCLK_GATE_D1, 0);
>> -	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
>> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, 0);
>> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
>>  		   GS_UNIT_CLOCK_GATE_DISABLE |
>>  		   CL_UNIT_CLOCK_GATE_DISABLE);
>> -	I915_WRITE(RAMCLK_GATE_D, 0);
>> +	intel_uncore_write(&dev_priv->uncore, RAMCLK_GATE_D, 0);
>>  	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
>>  		OVRUNIT_CLOCK_GATE_DISABLE |
>>  		OVCUNIT_CLOCK_GATE_DISABLE;
>>  	if (IS_GM45(dev_priv))
>>  		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
>> -	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
>> +	intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D, dspclk_gate);
>>  
>>  	g4x_disable_trickle_feed(dev_priv);
>>  }
>> @@ -7497,49 +7497,49 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
>>  
>>  static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>> -	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
>> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
>>  		   I965_RCC_CLOCK_GATE_DISABLE |
>>  		   I965_RCPB_CLOCK_GATE_DISABLE |
>>  		   I965_ISC_CLOCK_GATE_DISABLE |
>>  		   I965_FBC_CLOCK_GATE_DISABLE);
>> -	I915_WRITE(RENCLK_GATE_D2, 0);
>> -	I915_WRITE(MI_ARB_STATE,
>> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, 0);
>> +	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
>>  		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
>>  }
>>  
>>  static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>> -	u32 dstate = I915_READ(D_STATE);
>> +	u32 dstate = intel_uncore_read(&dev_priv->uncore, D_STATE);
>>  
>>  	dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
>>  		DSTATE_DOT_CLOCK_GATING;
>> -	I915_WRITE(D_STATE, dstate);
>> +	intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
>>  
>>  	if (IS_PINEVIEW(dev_priv))
>> -		I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
>> +		intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
>>  
>>  	/* IIR "flip pending" means done if this bit is set */
>> -	I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
>> +	intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
>>  
>>  	/* interrupts should cause a wake up from C3 */
>> -	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
>> +	intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
>>  
>>  	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
>> -	I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
>> +	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
>>  
>> -	I915_WRITE(MI_ARB_STATE,
>> +	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
>>  		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
>>  }
>>  
>>  static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>> -	I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
>> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
>>  
>>  	/* interrupts should cause a wake up from C3 */
>> -	I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
>> +	intel_uncore_write(&dev_priv->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
>>  		   _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
>>  
>> -	I915_WRITE(MEM_MODE,
>> +	intel_uncore_write(&dev_priv->uncore, MEM_MODE,
>>  		   _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
>>  
>>  	/*
>> @@ -7549,13 +7549,13 @@ static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
>>  	 * abosultely nothing) would not allow FBC to recompress
>>  	 * until a 2D blit occurs.
>>  	 */
>> -	I915_WRITE(SCPD0,
>> +	intel_uncore_write(&dev_priv->uncore, SCPD0,
>>  		   _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
>>  }
>>  
>>  static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>> -	I915_WRITE(MEM_MODE,
>> +	intel_uncore_write(&dev_priv->uncore, MEM_MODE,
>>  		   _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
>>  		   _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
>>  }
>> -- 
>> 2.20.1
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 7/9] drm/i915/pm: replace I915_READ()/WRITE() with intel_uncore_read()/write()

[Rodrigo Vivi]

On Fri, Nov 13, 2020 at 09:47:07AM +0200, Jani Nikula wrote:
> On Thu, 12 Nov 2020, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > On Thu, Nov 12, 2020 at 01:44:40PM +0200, Jani Nikula wrote:
> >> Arguably some of these should use intel_de_read() or intel_de_write(),
> >> however not all. Prioritize I915_READ() and I915_WRITE() removal in
> >> general over migrating to the pedantically correct replacements right
> >> away.
> >> 
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/intel_pm.c | 552 ++++++++++++++++----------------
> >>  1 file changed, 276 insertions(+), 276 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> index bbec56f97832..c0ed82665706 100644
> >> --- a/drivers/gpu/drm/i915/intel_pm.c
> >> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> @@ -81,24 +81,24 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  		 * Must match Sampler, Pixel Back End, and Media. See
> >>  		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
> >>  		 */
> >> -		I915_WRITE(CHICKEN_PAR1_1,
> >> -			   I915_READ(CHICKEN_PAR1_1) |
> >> +		intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
> >> +			   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) |
> >
> > why not converting them to rmw?
> 
> That's actually a functional change I didn't want to make. The rmw
> function only writes if the value has changed, while the code currently
> writes unconditionally. I'd have to check the registers whether that
> makes a difference. Likely not for most registers, but also don't want
> to introduce subtle bugs with a superficially non-functional conversion.

It makes a lot of sense. Recently, I had similar concern with this rmw
function exactly because it was not necessarily doing the write call.

> 
> BR,
> Jani.
> 
> 
> >
> >>  			   SKL_DE_COMPRESSED_HASH_MODE);
> >>  	}
> >>  
> >>  	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
> >> -	I915_WRITE(CHICKEN_PAR1_1,
> >> -		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
> >> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
> >> +		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
> >>  
> >>  	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
> >> -	I915_WRITE(GEN8_CHICKEN_DCPR_1,
> >> -		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
> >> +	intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
> >> +		   intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
> >>  
> >>  	/*
> >>  	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
> >>  	 * Display WA #0859: skl,bxt,kbl,glk,cfl
> >>  	 */
> >> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> >> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
> >>  		   DISP_FBC_MEMORY_WAKE);
> >>  }
> >>  
> >> @@ -107,21 +107,21 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	gen9_init_clock_gating(dev_priv);
> >>  
> >>  	/* WaDisableSDEUnitClockGating:bxt */
> >> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> >> +	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
> >>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> >>  
> >>  	/*
> >>  	 * FIXME:
> >>  	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
> >>  	 */
> >> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> >> +	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
> >>  		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
> >>  
> >>  	/*
> >>  	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
> >>  	 * to stay fully on.
> >>  	 */
> >> -	I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
> >> +	intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
> >>  		   PWM1_GATING_DIS | PWM2_GATING_DIS);
> >>  
> >>  	/*
> >> @@ -130,20 +130,20 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	 * is off and a MMIO access is attempted by any privilege
> >>  	 * application, using batch buffers or any other means.
> >>  	 */
> >> -	I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950));
> >> +	intel_uncore_write(&dev_priv->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
> >>  
> >>  	/*
> >>  	 * WaFbcTurnOffFbcWatermark:bxt
> >>  	 * Display WA #0562: bxt
> >>  	 */
> >> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> >> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
> >>  		   DISP_FBC_WM_DIS);
> >>  
> >>  	/*
> >>  	 * WaFbcHighMemBwCorruptionAvoidance:bxt
> >>  	 * Display WA #0883: bxt
> >>  	 */
> >> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
> >>  		   ILK_DPFC_DISABLE_DUMMY0);
> >>  }
> >>  
> >> @@ -156,7 +156,7 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	 * Backlight PWM may stop in the asserted state, causing backlight
> >>  	 * to stay fully on.
> >>  	 */
> >> -	I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
> >> +	intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
> >>  		   PWM1_GATING_DIS | PWM2_GATING_DIS);
> >>  }
> >>  
> >> @@ -164,7 +164,7 @@ static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
> >>  {
> >>  	u32 tmp;
> >>  
> >> -	tmp = I915_READ(CLKCFG);
> >> +	tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
> >>  
> >>  	switch (tmp & CLKCFG_FSB_MASK) {
> >>  	case CLKCFG_FSB_533:
> >> @@ -194,7 +194,7 @@ static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
> >>  	}
> >>  
> >>  	/* detect pineview DDR3 setting */
> >> -	tmp = I915_READ(CSHRDDR3CTL);
> >> +	tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL);
> >>  	dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
> >>  }
> >>  
> >> @@ -365,39 +365,39 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
> >>  	u32 val;
> >>  
> >>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> >> -		was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
> >> -		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> >> -		POSTING_READ(FW_BLC_SELF_VLV);
> >> +		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
> >> +		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> >> +		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF_VLV);
> >>  	} else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
> >> -		was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
> >> -		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
> >> -		POSTING_READ(FW_BLC_SELF);
> >> +		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
> >> +		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
> >> +		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
> >>  	} else if (IS_PINEVIEW(dev_priv)) {
> >> -		val = I915_READ(DSPFW3);
> >> +		val = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> >>  		was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
> >>  		if (enable)
> >>  			val |= PINEVIEW_SELF_REFRESH_EN;
> >>  		else
> >>  			val &= ~PINEVIEW_SELF_REFRESH_EN;
> >> -		I915_WRITE(DSPFW3, val);
> >> -		POSTING_READ(DSPFW3);
> >> +		intel_uncore_write(&dev_priv->uncore, DSPFW3, val);
> >> +		intel_uncore_posting_read(&dev_priv->uncore, DSPFW3);
> >>  	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
> >> -		was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
> >> +		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
> >>  		val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
> >>  			       _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
> >> -		I915_WRITE(FW_BLC_SELF, val);
> >> -		POSTING_READ(FW_BLC_SELF);
> >> +		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, val);
> >> +		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
> >>  	} else if (IS_I915GM(dev_priv)) {
> >>  		/*
> >>  		 * FIXME can't find a bit like this for 915G, and
> >>  		 * and yet it does have the related watermark in
> >>  		 * FW_BLC_SELF. What's going on?
> >>  		 */
> >> -		was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
> >> +		was_enabled = intel_uncore_read(&dev_priv->uncore, INSTPM) & INSTPM_SELF_EN;
> >>  		val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
> >>  			       _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
> >> -		I915_WRITE(INSTPM, val);
> >> -		POSTING_READ(INSTPM);
> >> +		intel_uncore_write(&dev_priv->uncore, INSTPM, val);
> >> +		intel_uncore_posting_read(&dev_priv->uncore, INSTPM);
> >>  	} else {
> >>  		return false;
> >>  	}
> >> @@ -493,20 +493,20 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
> >>  
> >>  	switch (pipe) {
> >>  	case PIPE_A:
> >> -		dsparb = I915_READ(DSPARB);
> >> -		dsparb2 = I915_READ(DSPARB2);
> >> +		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> >> +		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
> >>  		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
> >>  		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
> >>  		break;
> >>  	case PIPE_B:
> >> -		dsparb = I915_READ(DSPARB);
> >> -		dsparb2 = I915_READ(DSPARB2);
> >> +		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> >> +		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
> >>  		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
> >>  		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
> >>  		break;
> >>  	case PIPE_C:
> >> -		dsparb2 = I915_READ(DSPARB2);
> >> -		dsparb3 = I915_READ(DSPARB3);
> >> +		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
> >> +		dsparb3 = intel_uncore_read(&dev_priv->uncore, DSPARB3);
> >>  		sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
> >>  		sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
> >>  		break;
> >> @@ -524,7 +524,7 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
> >>  static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
> >>  			      enum i9xx_plane_id i9xx_plane)
> >>  {
> >> -	u32 dsparb = I915_READ(DSPARB);
> >> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> >>  	int size;
> >>  
> >>  	size = dsparb & 0x7f;
> >> @@ -540,7 +540,7 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
> >>  static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
> >>  			      enum i9xx_plane_id i9xx_plane)
> >>  {
> >> -	u32 dsparb = I915_READ(DSPARB);
> >> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> >>  	int size;
> >>  
> >>  	size = dsparb & 0x1ff;
> >> @@ -557,7 +557,7 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
> >>  static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
> >>  			      enum i9xx_plane_id i9xx_plane)
> >>  {
> >> -	u32 dsparb = I915_READ(DSPARB);
> >> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> >>  	int size;
> >>  
> >>  	size = dsparb & 0x7f;
> >> @@ -910,38 +910,38 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
> >>  		wm = intel_calculate_wm(clock, &pnv_display_wm,
> >>  					pnv_display_wm.fifo_size,
> >>  					cpp, latency->display_sr);
> >> -		reg = I915_READ(DSPFW1);
> >> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
> >>  		reg &= ~DSPFW_SR_MASK;
> >>  		reg |= FW_WM(wm, SR);
> >> -		I915_WRITE(DSPFW1, reg);
> >> +		intel_uncore_write(&dev_priv->uncore, DSPFW1, reg);
> >>  		drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
> >>  
> >>  		/* cursor SR */
> >>  		wm = intel_calculate_wm(clock, &pnv_cursor_wm,
> >>  					pnv_display_wm.fifo_size,
> >>  					4, latency->cursor_sr);
> >> -		reg = I915_READ(DSPFW3);
> >> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> >>  		reg &= ~DSPFW_CURSOR_SR_MASK;
> >>  		reg |= FW_WM(wm, CURSOR_SR);
> >> -		I915_WRITE(DSPFW3, reg);
> >> +		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
> >>  
> >>  		/* Display HPLL off SR */
> >>  		wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
> >>  					pnv_display_hplloff_wm.fifo_size,
> >>  					cpp, latency->display_hpll_disable);
> >> -		reg = I915_READ(DSPFW3);
> >> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> >>  		reg &= ~DSPFW_HPLL_SR_MASK;
> >>  		reg |= FW_WM(wm, HPLL_SR);
> >> -		I915_WRITE(DSPFW3, reg);
> >> +		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
> >>  
> >>  		/* cursor HPLL off SR */
> >>  		wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
> >>  					pnv_display_hplloff_wm.fifo_size,
> >>  					4, latency->cursor_hpll_disable);
> >> -		reg = I915_READ(DSPFW3);
> >> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> >>  		reg &= ~DSPFW_HPLL_CURSOR_MASK;
> >>  		reg |= FW_WM(wm, HPLL_CURSOR);
> >> -		I915_WRITE(DSPFW3, reg);
> >> +		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
> >>  		drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
> >>  
> >>  		intel_set_memory_cxsr(dev_priv, true);
> >> @@ -975,25 +975,25 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
> >>  	for_each_pipe(dev_priv, pipe)
> >>  		trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
> >>  
> >> -	I915_WRITE(DSPFW1,
> >> +	intel_uncore_write(&dev_priv->uncore, DSPFW1,
> >>  		   FW_WM(wm->sr.plane, SR) |
> >>  		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
> >>  		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
> >>  		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
> >> -	I915_WRITE(DSPFW2,
> >> +	intel_uncore_write(&dev_priv->uncore, DSPFW2,
> >>  		   (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
> >>  		   FW_WM(wm->sr.fbc, FBC_SR) |
> >>  		   FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
> >>  		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
> >>  		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
> >>  		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
> >> -	I915_WRITE(DSPFW3,
> >> +	intel_uncore_write(&dev_priv->uncore, DSPFW3,
> >>  		   (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
> >>  		   FW_WM(wm->sr.cursor, CURSOR_SR) |
> >>  		   FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
> >>  		   FW_WM(wm->hpll.plane, HPLL_SR));
> >>  
> >> -	POSTING_READ(DSPFW1);
> >> +	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
> >>  }
> >>  
> >>  #define FW_WM_VLV(value, plane) \
> >> @@ -1007,7 +1007,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
> >>  	for_each_pipe(dev_priv, pipe) {
> >>  		trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
> >>  
> >> -		I915_WRITE(VLV_DDL(pipe),
> >> +		intel_uncore_write(&dev_priv->uncore, VLV_DDL(pipe),
> >>  			   (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
> >>  			   (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
> >>  			   (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
> >> @@ -1019,35 +1019,35 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
> >>  	 * high order bits so that there are no out of bounds values
> >>  	 * present in the registers during the reprogramming.
> >>  	 */
> >> -	I915_WRITE(DSPHOWM, 0);
> >> -	I915_WRITE(DSPHOWM1, 0);
> >> -	I915_WRITE(DSPFW4, 0);
> >> -	I915_WRITE(DSPFW5, 0);
> >> -	I915_WRITE(DSPFW6, 0);
> >> +	intel_uncore_write(&dev_priv->uncore, DSPHOWM, 0);
> >> +	intel_uncore_write(&dev_priv->uncore, DSPHOWM1, 0);
> >> +	intel_uncore_write(&dev_priv->uncore, DSPFW4, 0);
> >> +	intel_uncore_write(&dev_priv->uncore, DSPFW5, 0);
> >> +	intel_uncore_write(&dev_priv->uncore, DSPFW6, 0);
> >>  
> >> -	I915_WRITE(DSPFW1,
> >> +	intel_uncore_write(&dev_priv->uncore, DSPFW1,
> >>  		   FW_WM(wm->sr.plane, SR) |
> >>  		   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
> >>  		   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
> >>  		   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
> >> -	I915_WRITE(DSPFW2,
> >> +	intel_uncore_write(&dev_priv->uncore, DSPFW2,
> >>  		   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
> >>  		   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
> >>  		   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
> >> -	I915_WRITE(DSPFW3,
> >> +	intel_uncore_write(&dev_priv->uncore, DSPFW3,
> >>  		   FW_WM(wm->sr.cursor, CURSOR_SR));
> >>  
> >>  	if (IS_CHERRYVIEW(dev_priv)) {
> >> -		I915_WRITE(DSPFW7_CHV,
> >> +		intel_uncore_write(&dev_priv->uncore, DSPFW7_CHV,
> >>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
> >>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
> >> -		I915_WRITE(DSPFW8_CHV,
> >> +		intel_uncore_write(&dev_priv->uncore, DSPFW8_CHV,
> >>  			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
> >>  			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
> >> -		I915_WRITE(DSPFW9_CHV,
> >> +		intel_uncore_write(&dev_priv->uncore, DSPFW9_CHV,
> >>  			   FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
> >>  			   FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
> >> -		I915_WRITE(DSPHOWM,
> >> +		intel_uncore_write(&dev_priv->uncore, DSPHOWM,
> >>  			   FW_WM(wm->sr.plane >> 9, SR_HI) |
> >>  			   FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
> >>  			   FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
> >> @@ -1059,10 +1059,10 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
> >>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
> >>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
> >>  	} else {
> >> -		I915_WRITE(DSPFW7,
> >> +		intel_uncore_write(&dev_priv->uncore, DSPFW7,
> >>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
> >>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
> >> -		I915_WRITE(DSPHOWM,
> >> +		intel_uncore_write(&dev_priv->uncore, DSPHOWM,
> >>  			   FW_WM(wm->sr.plane >> 9, SR_HI) |
> >>  			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
> >>  			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
> >> @@ -1072,7 +1072,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
> >>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
> >>  	}
> >>  
> >> -	POSTING_READ(DSPFW1);
> >> +	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
> >>  }
> >>  
> >>  #undef FW_WM_VLV
> >> @@ -2309,14 +2309,14 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
> >>  		    srwm);
> >>  
> >>  	/* 965 has limitations... */
> >> -	I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
> >> +	intel_uncore_write(&dev_priv->uncore, DSPFW1, FW_WM(srwm, SR) |
> >>  		   FW_WM(8, CURSORB) |
> >>  		   FW_WM(8, PLANEB) |
> >>  		   FW_WM(8, PLANEA));
> >> -	I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
> >> +	intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) |
> >>  		   FW_WM(8, PLANEC_OLD));
> >>  	/* update cursor SR watermark */
> >> -	I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
> >> +	intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
> >>  
> >>  	if (cxsr_enabled)
> >>  		intel_set_memory_cxsr(dev_priv, true);
> >> @@ -2446,10 +2446,10 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> >>  			srwm = 1;
> >>  
> >>  		if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
> >> -			I915_WRITE(FW_BLC_SELF,
> >> +			intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF,
> >>  				   FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
> >>  		else
> >> -			I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
> >> +			intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, srwm & 0x3f);
> >>  	}
> >>  
> >>  	drm_dbg_kms(&dev_priv->drm,
> >> @@ -2463,8 +2463,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> >>  	fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
> >>  	fwater_hi = fwater_hi | (1 << 8);
> >>  
> >> -	I915_WRITE(FW_BLC, fwater_lo);
> >> -	I915_WRITE(FW_BLC2, fwater_hi);
> >> +	intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
> >> +	intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
> >>  
> >>  	if (enabled)
> >>  		intel_set_memory_cxsr(dev_priv, true);
> >> @@ -2487,13 +2487,13 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
> >>  				       &i845_wm_info,
> >>  				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
> >>  				       4, pessimal_latency_ns);
> >> -	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
> >> +	fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
> >>  	fwater_lo |= (3<<8) | planea_wm;
> >>  
> >>  	drm_dbg_kms(&dev_priv->drm,
> >>  		    "Setting FIFO watermarks - A: %d\n", planea_wm);
> >>  
> >> -	I915_WRITE(FW_BLC, fwater_lo);
> >> +	intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
> >>  }
> >>  
> >>  /* latency must be in 0.1us units. */
> >> @@ -3533,17 +3533,17 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
> >>  
> >>  	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
> >>  		previous->wm_lp[2] &= ~WM1_LP_SR_EN;
> >> -		I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
> >> +		intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, previous->wm_lp[2]);
> >>  		changed = true;
> >>  	}
> >>  	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
> >>  		previous->wm_lp[1] &= ~WM1_LP_SR_EN;
> >> -		I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
> >> +		intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, previous->wm_lp[1]);
> >>  		changed = true;
> >>  	}
> >>  	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
> >>  		previous->wm_lp[0] &= ~WM1_LP_SR_EN;
> >> -		I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
> >> +		intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, previous->wm_lp[0]);
> >>  		changed = true;
> >>  	}
> >>  
> >> @@ -3573,56 +3573,56 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
> >>  	_ilk_disable_lp_wm(dev_priv, dirty);
> >>  
> >>  	if (dirty & WM_DIRTY_PIPE(PIPE_A))
> >> -		I915_WRITE(WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
> >> +		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
> >>  	if (dirty & WM_DIRTY_PIPE(PIPE_B))
> >> -		I915_WRITE(WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
> >> +		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
> >>  	if (dirty & WM_DIRTY_PIPE(PIPE_C))
> >> -		I915_WRITE(WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
> >> +		intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
> >>  
> >>  	if (dirty & WM_DIRTY_DDB) {
> >>  		if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> >> -			val = I915_READ(WM_MISC);
> >> +			val = intel_uncore_read(&dev_priv->uncore, WM_MISC);
> >>  			if (results->partitioning == INTEL_DDB_PART_1_2)
> >>  				val &= ~WM_MISC_DATA_PARTITION_5_6;
> >>  			else
> >>  				val |= WM_MISC_DATA_PARTITION_5_6;
> >> -			I915_WRITE(WM_MISC, val);
> >> +			intel_uncore_write(&dev_priv->uncore, WM_MISC, val);
> >>  		} else {
> >> -			val = I915_READ(DISP_ARB_CTL2);
> >> +			val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2);
> >>  			if (results->partitioning == INTEL_DDB_PART_1_2)
> >>  				val &= ~DISP_DATA_PARTITION_5_6;
> >>  			else
> >>  				val |= DISP_DATA_PARTITION_5_6;
> >> -			I915_WRITE(DISP_ARB_CTL2, val);
> >> +			intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL2, val);
> >>  		}
> >>  	}
> >>  
> >>  	if (dirty & WM_DIRTY_FBC) {
> >> -		val = I915_READ(DISP_ARB_CTL);
> >> +		val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL);
> >>  		if (results->enable_fbc_wm)
> >>  			val &= ~DISP_FBC_WM_DIS;
> >>  		else
> >>  			val |= DISP_FBC_WM_DIS;
> >> -		I915_WRITE(DISP_ARB_CTL, val);
> >> +		intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, val);
> >>  	}
> >>  
> >>  	if (dirty & WM_DIRTY_LP(1) &&
> >>  	    previous->wm_lp_spr[0] != results->wm_lp_spr[0])
> >> -		I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
> >> +		intel_uncore_write(&dev_priv->uncore, WM1S_LP_ILK, results->wm_lp_spr[0]);
> >>  
> >>  	if (INTEL_GEN(dev_priv) >= 7) {
> >>  		if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
> >> -			I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
> >> +			intel_uncore_write(&dev_priv->uncore, WM2S_LP_IVB, results->wm_lp_spr[1]);
> >>  		if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
> >> -			I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
> >> +			intel_uncore_write(&dev_priv->uncore, WM3S_LP_IVB, results->wm_lp_spr[2]);
> >>  	}
> >>  
> >>  	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
> >> -		I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
> >> +		intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, results->wm_lp[0]);
> >>  	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
> >> -		I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
> >> +		intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, results->wm_lp[1]);
> >>  	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
> >> -		I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
> >> +		intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, results->wm_lp[2]);
> >>  
> >>  	dev_priv->wm.hw = *results;
> >>  }
> >> @@ -3639,7 +3639,7 @@ u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
> >>  	u8 enabled_slices_mask = 0;
> >>  
> >>  	for (i = 0; i < max_slices; i++) {
> >> -		if (I915_READ(DBUF_CTL_S(i)) & DBUF_POWER_STATE)
> >> +		if (intel_uncore_read(&dev_priv->uncore, DBUF_CTL_S(i)) & DBUF_POWER_STATE)
> >>  			enabled_slices_mask |= BIT(i);
> >>  	}
> >>  
> >> @@ -4307,12 +4307,12 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
> >>  
> >>  	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
> >>  	if (plane_id == PLANE_CURSOR) {
> >> -		val = I915_READ(CUR_BUF_CFG(pipe));
> >> +		val = intel_uncore_read(&dev_priv->uncore, CUR_BUF_CFG(pipe));
> >>  		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
> >>  		return;
> >>  	}
> >>  
> >> -	val = I915_READ(PLANE_CTL(pipe, plane_id));
> >> +	val = intel_uncore_read(&dev_priv->uncore, PLANE_CTL(pipe, plane_id));
> >>  
> >>  	/* No DDB allocated for disabled planes */
> >>  	if (val & PLANE_CTL_ENABLE)
> >> @@ -4321,11 +4321,11 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
> >>  					      val & PLANE_CTL_ALPHA_MASK);
> >>  
> >>  	if (INTEL_GEN(dev_priv) >= 11) {
> >> -		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> >> +		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
> >>  		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
> >>  	} else {
> >> -		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> >> -		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
> >> +		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
> >> +		val2 = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
> >>  
> >>  		if (fourcc &&
> >>  		    drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
> >> @@ -6240,9 +6240,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> >>  
> >>  		for (level = 0; level <= max_level; level++) {
> >>  			if (plane_id != PLANE_CURSOR)
> >> -				val = I915_READ(PLANE_WM(pipe, plane_id, level));
> >> +				val = intel_uncore_read(&dev_priv->uncore, PLANE_WM(pipe, plane_id, level));
> >>  			else
> >> -				val = I915_READ(CUR_WM(pipe, level));
> >> +				val = intel_uncore_read(&dev_priv->uncore, CUR_WM(pipe, level));
> >>  
> >>  			skl_wm_level_from_reg_val(val, &wm->wm[level]);
> >>  		}
> >> @@ -6251,9 +6251,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> >>  			wm->sagv_wm0 = wm->wm[0];
> >>  
> >>  		if (plane_id != PLANE_CURSOR)
> >> -			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
> >> +			val = intel_uncore_read(&dev_priv->uncore, PLANE_WM_TRANS(pipe, plane_id));
> >>  		else
> >> -			val = I915_READ(CUR_WM_TRANS(pipe));
> >> +			val = intel_uncore_read(&dev_priv->uncore, CUR_WM_TRANS(pipe));
> >>  
> >>  		skl_wm_level_from_reg_val(val, &wm->trans_wm);
> >>  	}
> >> @@ -6288,7 +6288,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
> >>  	struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
> >>  	enum pipe pipe = crtc->pipe;
> >>  
> >> -	hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe));
> >> +	hw->wm_pipe[pipe] = intel_uncore_read(&dev_priv->uncore, WM0_PIPE_ILK(pipe));
> >>  
> >>  	memset(active, 0, sizeof(*active));
> >>  
> >> @@ -6332,13 +6332,13 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
> >>  {
> >>  	u32 tmp;
> >>  
> >> -	tmp = I915_READ(DSPFW1);
> >> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
> >>  	wm->sr.plane = _FW_WM(tmp, SR);
> >>  	wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
> >>  	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
> >>  	wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
> >>  
> >> -	tmp = I915_READ(DSPFW2);
> >> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
> >>  	wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
> >>  	wm->sr.fbc = _FW_WM(tmp, FBC_SR);
> >>  	wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
> >> @@ -6346,7 +6346,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
> >>  	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
> >>  	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
> >>  
> >> -	tmp = I915_READ(DSPFW3);
> >> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> >>  	wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
> >>  	wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
> >>  	wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
> >> @@ -6360,7 +6360,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
> >>  	u32 tmp;
> >>  
> >>  	for_each_pipe(dev_priv, pipe) {
> >> -		tmp = I915_READ(VLV_DDL(pipe));
> >> +		tmp = intel_uncore_read(&dev_priv->uncore, VLV_DDL(pipe));
> >>  
> >>  		wm->ddl[pipe].plane[PLANE_PRIMARY] =
> >>  			(tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
> >> @@ -6372,34 +6372,34 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
> >>  			(tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
> >>  	}
> >>  
> >> -	tmp = I915_READ(DSPFW1);
> >> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
> >>  	wm->sr.plane = _FW_WM(tmp, SR);
> >>  	wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
> >>  	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
> >>  	wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
> >>  
> >> -	tmp = I915_READ(DSPFW2);
> >> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
> >>  	wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
> >>  	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
> >>  	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
> >>  
> >> -	tmp = I915_READ(DSPFW3);
> >> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> >>  	wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
> >>  
> >>  	if (IS_CHERRYVIEW(dev_priv)) {
> >> -		tmp = I915_READ(DSPFW7_CHV);
> >> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7_CHV);
> >>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
> >>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
> >>  
> >> -		tmp = I915_READ(DSPFW8_CHV);
> >> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW8_CHV);
> >>  		wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
> >>  		wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
> >>  
> >> -		tmp = I915_READ(DSPFW9_CHV);
> >> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW9_CHV);
> >>  		wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
> >>  		wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
> >>  
> >> -		tmp = I915_READ(DSPHOWM);
> >> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
> >>  		wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
> >>  		wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
> >>  		wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
> >> @@ -6411,11 +6411,11 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
> >>  		wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
> >>  		wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
> >>  	} else {
> >> -		tmp = I915_READ(DSPFW7);
> >> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7);
> >>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
> >>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
> >>  
> >> -		tmp = I915_READ(DSPHOWM);
> >> +		tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
> >>  		wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
> >>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
> >>  		wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
> >> @@ -6436,7 +6436,7 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
> >>  
> >>  	g4x_read_wm_values(dev_priv, wm);
> >>  
> >> -	wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
> >> +	wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
> >>  
> >>  	for_each_intel_crtc(&dev_priv->drm, crtc) {
> >>  		struct intel_crtc_state *crtc_state =
> >> @@ -6580,7 +6580,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
> >>  
> >>  	vlv_read_wm_values(dev_priv, wm);
> >>  
> >> -	wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
> >> +	wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
> >>  	wm->level = VLV_WM_LEVEL_PM2;
> >>  
> >>  	if (IS_CHERRYVIEW(dev_priv)) {
> >> @@ -6727,9 +6727,9 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
> >>   */
> >>  static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
> >>  {
> >> -	I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
> >> -	I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
> >> -	I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
> >> +	intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM1_LP_SR_EN);
> >> +	intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM1_LP_SR_EN);
> >> +	intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM1_LP_SR_EN);
> >>  
> >>  	/*
> >>  	 * Don't touch WM1S_LP_EN here.
> >> @@ -6747,25 +6747,25 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
> >>  	for_each_intel_crtc(&dev_priv->drm, crtc)
> >>  		ilk_pipe_wm_get_hw_state(crtc);
> >>  
> >> -	hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
> >> -	hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
> >> -	hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
> >> +	hw->wm_lp[0] = intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK);
> >> +	hw->wm_lp[1] = intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK);
> >> +	hw->wm_lp[2] = intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK);
> >>  
> >> -	hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
> >> +	hw->wm_lp_spr[0] = intel_uncore_read(&dev_priv->uncore, WM1S_LP_ILK);
> >>  	if (INTEL_GEN(dev_priv) >= 7) {
> >> -		hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
> >> -		hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
> >> +		hw->wm_lp_spr[1] = intel_uncore_read(&dev_priv->uncore, WM2S_LP_IVB);
> >> +		hw->wm_lp_spr[2] = intel_uncore_read(&dev_priv->uncore, WM3S_LP_IVB);
> >>  	}
> >>  
> >>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> >> -		hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
> >> +		hw->partitioning = (intel_uncore_read(&dev_priv->uncore, WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
> >>  			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
> >>  	else if (IS_IVYBRIDGE(dev_priv))
> >> -		hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
> >> +		hw->partitioning = (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
> >>  			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
> >>  
> >>  	hw->enable_fbc_wm =
> >> -		!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
> >> +		!(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
> >>  }
> >>  
> >>  /**
> >> @@ -6816,14 +6816,14 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
> >>  	if (!HAS_IPC(dev_priv))
> >>  		return;
> >>  
> >> -	val = I915_READ(DISP_ARB_CTL2);
> >> +	val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2);
> >>  
> >>  	if (dev_priv->ipc_enabled)
> >>  		val |= DISP_IPC_ENABLE;
> >>  	else
> >>  		val &= ~DISP_IPC_ENABLE;
> >>  
> >> -	I915_WRITE(DISP_ARB_CTL2, val);
> >> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL2, val);
> >>  }
> >>  
> >>  static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv)
> >> @@ -6858,7 +6858,7 @@ static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	 * gating for the panel power sequencer or it will fail to
> >>  	 * start up when no ports are active.
> >>  	 */
> >> -	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> >> +	intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> >>  }
> >>  
> >>  static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> >> @@ -6866,12 +6866,12 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> >>  	enum pipe pipe;
> >>  
> >>  	for_each_pipe(dev_priv, pipe) {
> >> -		I915_WRITE(DSPCNTR(pipe),
> >> -			   I915_READ(DSPCNTR(pipe)) |
> >> +		intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe),
> >> +			   intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) |
> >>  			   DISPPLANE_TRICKLE_FEED_DISABLE);
> >>  
> >> -		I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
> >> -		POSTING_READ(DSPSURF(pipe));
> >> +		intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(pipe)));
> >> +		intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe));
> >>  	}
> >>  }
> >>  
> >> @@ -6887,10 +6887,10 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  		   ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> >>  		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
> >>  
> >> -	I915_WRITE(PCH_3DCGDIS0,
> >> +	intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS0,
> >>  		   MARIUNIT_CLOCK_GATE_DISABLE |
> >>  		   SVSMUNIT_CLOCK_GATE_DISABLE);
> >> -	I915_WRITE(PCH_3DCGDIS1,
> >> +	intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS1,
> >>  		   VFMUNIT_CLOCK_GATE_DISABLE);
> >>  
> >>  	/*
> >> @@ -6900,12 +6900,12 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	 * The bit 5 of 0x42020
> >>  	 * The bit 15 of 0x45000
> >>  	 */
> >> -	I915_WRITE(ILK_DISPLAY_CHICKEN2,
> >> -		   (I915_READ(ILK_DISPLAY_CHICKEN2) |
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
> >> +		   (intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
> >>  		    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
> >>  	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
> >> -	I915_WRITE(DISP_ARB_CTL,
> >> -		   (I915_READ(DISP_ARB_CTL) |
> >> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL,
> >> +		   (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
> >>  		    DISP_FBC_WM_DIS));
> >>  
> >>  	/*
> >> @@ -6917,18 +6917,18 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	 */
> >>  	if (IS_IRONLAKE_M(dev_priv)) {
> >>  		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
> >> -		I915_WRITE(ILK_DISPLAY_CHICKEN1,
> >> -			   I915_READ(ILK_DISPLAY_CHICKEN1) |
> >> +		intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
> >> +			   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
> >>  			   ILK_FBCQ_DIS);
> >> -		I915_WRITE(ILK_DISPLAY_CHICKEN2,
> >> -			   I915_READ(ILK_DISPLAY_CHICKEN2) |
> >> +		intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
> >> +			   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
> >>  			   ILK_DPARB_GATE);
> >>  	}
> >>  
> >> -	I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
> >>  
> >> -	I915_WRITE(ILK_DISPLAY_CHICKEN2,
> >> -		   I915_READ(ILK_DISPLAY_CHICKEN2) |
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
> >> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
> >>  		   ILK_ELPIN_409_SELECT);
> >>  
> >>  	g4x_disable_trickle_feed(dev_priv);
> >> @@ -6946,27 +6946,27 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	 * gating for the panel power sequencer or it will fail to
> >>  	 * start up when no ports are active.
> >>  	 */
> >> -	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
> >> +	intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
> >>  		   PCH_DPLUNIT_CLOCK_GATE_DISABLE |
> >>  		   PCH_CPUNIT_CLOCK_GATE_DISABLE);
> >> -	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
> >> +	intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN2, intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN2) |
> >>  		   DPLS_EDP_PPS_FIX_DIS);
> >>  	/* The below fixes the weird display corruption, a few pixels shifted
> >>  	 * downward, on (only) LVDS of some HP laptops with IVY.
> >>  	 */
> >>  	for_each_pipe(dev_priv, pipe) {
> >> -		val = I915_READ(TRANS_CHICKEN2(pipe));
> >> +		val = intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN2(pipe));
> >>  		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> >>  		val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> >>  		if (dev_priv->vbt.fdi_rx_polarity_inverted)
> >>  			val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> >>  		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
> >>  		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
> >> -		I915_WRITE(TRANS_CHICKEN2(pipe), val);
> >> +		intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN2(pipe), val);
> >>  	}
> >>  	/* WADP0ClockGatingDisable */
> >>  	for_each_pipe(dev_priv, pipe) {
> >> -		I915_WRITE(TRANS_CHICKEN1(pipe),
> >> +		intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(pipe),
> >>  			   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> >>  	}
> >>  }
> >> @@ -6975,7 +6975,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
> >>  {
> >>  	u32 tmp;
> >>  
> >> -	tmp = I915_READ(MCH_SSKPD);
> >> +	tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD);
> >>  	if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
> >>  		drm_dbg_kms(&dev_priv->drm,
> >>  			    "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
> >> @@ -6986,14 +6986,14 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  {
> >>  	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> >>  
> >> -	I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
> >>  
> >> -	I915_WRITE(ILK_DISPLAY_CHICKEN2,
> >> -		   I915_READ(ILK_DISPLAY_CHICKEN2) |
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
> >> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
> >>  		   ILK_ELPIN_409_SELECT);
> >>  
> >> -	I915_WRITE(GEN6_UCGCTL1,
> >> -		   I915_READ(GEN6_UCGCTL1) |
> >> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
> >> +		   intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
> >>  		   GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
> >>  		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
> >>  
> >> @@ -7010,7 +7010,7 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	 * WaDisableRCCUnitClockGating:snb
> >>  	 * WaDisableRCPBUnitClockGating:snb
> >>  	 */
> >> -	I915_WRITE(GEN6_UCGCTL2,
> >> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
> >>  		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
> >>  		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
> >>  
> >> @@ -7025,14 +7025,14 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	 *
> >>  	 * WaFbcAsynchFlipDisableFbcQueue:snb
> >>  	 */
> >> -	I915_WRITE(ILK_DISPLAY_CHICKEN1,
> >> -		   I915_READ(ILK_DISPLAY_CHICKEN1) |
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
> >> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
> >>  		   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
> >> -	I915_WRITE(ILK_DISPLAY_CHICKEN2,
> >> -		   I915_READ(ILK_DISPLAY_CHICKEN2) |
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
> >> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
> >>  		   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> >> -	I915_WRITE(ILK_DSPCLK_GATE_D,
> >> -		   I915_READ(ILK_DSPCLK_GATE_D) |
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D,
> >> +		   intel_uncore_read(&dev_priv->uncore, ILK_DSPCLK_GATE_D) |
> >>  		   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
> >>  		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
> >>  
> >> @@ -7050,23 +7050,23 @@ static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	 * disabled when not needed anymore in order to save power.
> >>  	 */
> >>  	if (HAS_PCH_LPT_LP(dev_priv))
> >> -		I915_WRITE(SOUTH_DSPCLK_GATE_D,
> >> -			   I915_READ(SOUTH_DSPCLK_GATE_D) |
> >> +		intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D,
> >> +			   intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |
> >>  			   PCH_LP_PARTITION_LEVEL_DISABLE);
> >>  
> >>  	/* WADPOClockGatingDisable:hsw */
> >> -	I915_WRITE(TRANS_CHICKEN1(PIPE_A),
> >> -		   I915_READ(TRANS_CHICKEN1(PIPE_A)) |
> >> +	intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A),
> >> +		   intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A)) |
> >>  		   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> >>  }
> >>  
> >>  static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
> >>  {
> >>  	if (HAS_PCH_LPT_LP(dev_priv)) {
> >> -		u32 val = I915_READ(SOUTH_DSPCLK_GATE_D);
> >> +		u32 val = intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D);
> >>  
> >>  		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> >> -		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> >> +		intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, val);
> >>  	}
> >>  }
> >>  
> >> @@ -7078,33 +7078,33 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> >>  	u32 val;
> >>  
> >>  	/* WaTempDisableDOPClkGating:bdw */
> >> -	misccpctl = I915_READ(GEN7_MISCCPCTL);
> >> -	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
> >> +	misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
> >> +	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
> >>  
> >> -	val = I915_READ(GEN8_L3SQCREG1);
> >> +	val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
> >>  	val &= ~L3_PRIO_CREDITS_MASK;
> >>  	val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
> >>  	val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
> >> -	I915_WRITE(GEN8_L3SQCREG1, val);
> >> +	intel_uncore_write(&dev_priv->uncore, GEN8_L3SQCREG1, val);
> >>  
> >>  	/*
> >>  	 * Wait at least 100 clocks before re-enabling clock gating.
> >>  	 * See the definition of L3SQCREG1 in BSpec.
> >>  	 */
> >> -	POSTING_READ(GEN8_L3SQCREG1);
> >> +	intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
> >>  	udelay(1);
> >> -	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
> >> +	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
> >>  }
> >>  
> >>  static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  {
> >>  	/* Wa_1409120013:icl,ehl */
> >> -	I915_WRITE(ILK_DPFC_CHICKEN,
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
> >>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> >>  
> >>  	/* This is not an Wa. Enable to reduce Sampler power */
> >> -	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> >> -		   I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
> >> +	intel_uncore_write(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
> >> +		   intel_uncore_read(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
> >>  
> >>  	/*Wa_14010594013:icl, ehl */
> >>  	intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
> >> @@ -7114,12 +7114,12 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  {
> >>  	/* Wa_1409120013:tgl */
> >> -	I915_WRITE(ILK_DPFC_CHICKEN,
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
> >>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> >>  
> >>  	/* Wa_1409825376:tgl (pre-prod)*/
> >>  	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
> >> -		I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
> >> +		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
> >>  			   TGL_VRH_GATING_DIS);
> >>  
> >>  	/* Wa_14011059788:tgl */
> >> @@ -7131,7 +7131,7 @@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  {
> >>  	/* Wa_1409836686:dg1[a0] */
> >>  	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
> >> -		I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
> >> +		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
> >>  			   DPT_GATING_DIS);
> >>  }
> >>  
> >> @@ -7141,7 +7141,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  		return;
> >>  
> >>  	/* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
> >> -	I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
> >> +	intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |
> >>  		   CNP_PWM_CGE_GATING_DISABLE);
> >>  }
> >>  
> >> @@ -7151,35 +7151,35 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	cnp_init_clock_gating(dev_priv);
> >>  
> >>  	/* This is not an Wa. Enable for better image quality */
> >> -	I915_WRITE(_3D_CHICKEN3,
> >> +	intel_uncore_write(&dev_priv->uncore, _3D_CHICKEN3,
> >>  		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> >>  
> >>  	/* WaEnableChickenDCPR:cnl */
> >> -	I915_WRITE(GEN8_CHICKEN_DCPR_1,
> >> -		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
> >> +	intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
> >> +		   intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
> >>  
> >>  	/*
> >>  	 * WaFbcWakeMemOn:cnl
> >>  	 * Display WA #0859: cnl
> >>  	 */
> >> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> >> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
> >>  		   DISP_FBC_MEMORY_WAKE);
> >>  
> >> -	val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);
> >> +	val = intel_uncore_read(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE);
> >>  	/* ReadHitWriteOnlyDisable:cnl */
> >>  	val |= RCCUNIT_CLKGATE_DIS;
> >> -	I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
> >> +	intel_uncore_write(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE, val);
> >>  
> >>  	/* Wa_2201832410:cnl */
> >> -	val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
> >> +	val = intel_uncore_read(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE);
> >>  	val |= GWUNIT_CLKGATE_DIS;
> >> -	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
> >> +	intel_uncore_write(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE, val);
> >>  
> >>  	/* WaDisableVFclkgate:cnl */
> >>  	/* WaVFUnitClockGatingDisable:cnl */
> >> -	val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
> >> +	val = intel_uncore_read(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE);
> >>  	val |= VFUNIT_CLKGATE_DIS;
> >> -	I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val);
> >> +	intel_uncore_write(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE, val);
> >>  }
> >>  
> >>  static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
> >> @@ -7188,21 +7188,21 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	gen9_init_clock_gating(dev_priv);
> >>  
> >>  	/* WAC6entrylatency:cfl */
> >> -	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
> >> +	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
> >>  		   FBC_LLC_FULLY_OPEN);
> >>  
> >>  	/*
> >>  	 * WaFbcTurnOffFbcWatermark:cfl
> >>  	 * Display WA #0562: cfl
> >>  	 */
> >> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> >> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
> >>  		   DISP_FBC_WM_DIS);
> >>  
> >>  	/*
> >>  	 * WaFbcNukeOnHostModify:cfl
> >>  	 * Display WA #0873: cfl
> >>  	 */
> >> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
> >>  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> >>  }
> >>  
> >> @@ -7211,31 +7211,31 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	gen9_init_clock_gating(dev_priv);
> >>  
> >>  	/* WAC6entrylatency:kbl */
> >> -	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
> >> +	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
> >>  		   FBC_LLC_FULLY_OPEN);
> >>  
> >>  	/* WaDisableSDEUnitClockGating:kbl */
> >>  	if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0))
> >> -		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> >> +		intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
> >>  			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> >>  
> >>  	/* WaDisableGamClockGating:kbl */
> >>  	if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0))
> >> -		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> >> +		intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
> >>  			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> >>  
> >>  	/*
> >>  	 * WaFbcTurnOffFbcWatermark:kbl
> >>  	 * Display WA #0562: kbl
> >>  	 */
> >> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> >> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
> >>  		   DISP_FBC_WM_DIS);
> >>  
> >>  	/*
> >>  	 * WaFbcNukeOnHostModify:kbl
> >>  	 * Display WA #0873: kbl
> >>  	 */
> >> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
> >>  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> >>  }
> >>  
> >> @@ -7244,32 +7244,32 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	gen9_init_clock_gating(dev_priv);
> >>  
> >>  	/* WaDisableDopClockGating:skl */
> >> -	I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) &
> >> +	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL) &
> >>  		   ~GEN7_DOP_CLOCK_GATE_ENABLE);
> >>  
> >>  	/* WAC6entrylatency:skl */
> >> -	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
> >> +	intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
> >>  		   FBC_LLC_FULLY_OPEN);
> >>  
> >>  	/*
> >>  	 * WaFbcTurnOffFbcWatermark:skl
> >>  	 * Display WA #0562: skl
> >>  	 */
> >> -	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> >> +	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
> >>  		   DISP_FBC_WM_DIS);
> >>  
> >>  	/*
> >>  	 * WaFbcNukeOnHostModify:skl
> >>  	 * Display WA #0873: skl
> >>  	 */
> >> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
> >>  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> >>  
> >>  	/*
> >>  	 * WaFbcHighMemBwCorruptionAvoidance:skl
> >>  	 * Display WA #0883: skl
> >>  	 */
> >> -	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
> >>  		   ILK_DPFC_DISABLE_DUMMY0);
> >>  }
> >>  
> >> @@ -7278,42 +7278,42 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	enum pipe pipe;
> >>  
> >>  	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> >> -	I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
> >> -		   I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
> >> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
> >> +		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |
> >>  		   HSW_FBCQ_DIS);
> >>  
> >>  	/* WaSwitchSolVfFArbitrationPriority:bdw */
> >> -	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> >> +	intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> >>  
> >>  	/* WaPsrDPAMaskVBlankInSRD:bdw */
> >> -	I915_WRITE(CHICKEN_PAR1_1,
> >> -		   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
> >> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
> >> +		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
> >>  
> >>  	/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
> >>  	for_each_pipe(dev_priv, pipe) {
> >> -		I915_WRITE(CHICKEN_PIPESL_1(pipe),
> >> -			   I915_READ(CHICKEN_PIPESL_1(pipe)) |
> >> +		intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
> >> +			   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe)) |
> >>  			   BDW_DPRS_MASK_VBLANK_SRD);
> >>  	}
> >>  
> >>  	/* WaVSRefCountFullforceMissDisable:bdw */
> >>  	/* WaDSRefCountFullforceMissDisable:bdw */
> >> -	I915_WRITE(GEN7_FF_THREAD_MODE,
> >> -		   I915_READ(GEN7_FF_THREAD_MODE) &
> >> +	intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
> >> +		   intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
> >>  		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
> >>  
> >> -	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> >> +	intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
> >>  		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> >>  
> >>  	/* WaDisableSDEUnitClockGating:bdw */
> >> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> >> +	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
> >>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> >>  
> >>  	/* WaProgramL3SqcReg1Default:bdw */
> >>  	gen8_set_l3sqc_credits(dev_priv, 30, 2);
> >>  
> >>  	/* WaKVMNotificationOnConfigChange:bdw */
> >> -	I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
> >> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR2_1, intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR2_1)
> >>  		   | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
> >>  
> >>  	lpt_init_clock_gating(dev_priv);
> >> @@ -7323,24 +7323,24 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
> >>  	 * clock gating.
> >>  	 */
> >> -	I915_WRITE(GEN6_UCGCTL1,
> >> -		   I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> >> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
> >> +		   intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> >>  }
> >>  
> >>  static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  {
> >>  	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> >> -	I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
> >> -		   I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
> >> +	intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
> >> +		   intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |
> >>  		   HSW_FBCQ_DIS);
> >>  
> >>  	/* This is required by WaCatErrorRejectionIssue:hsw */
> >> -	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> >> -		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> >> +	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> >> +		   intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> >>  		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
> >>  
> >>  	/* WaSwitchSolVfFArbitrationPriority:hsw */
> >> -	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> >> +	intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> >>  
> >>  	lpt_init_clock_gating(dev_priv);
> >>  }
> >> @@ -7349,26 +7349,26 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  {
> >>  	u32 snpcr;
> >>  
> >> -	I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
> >>  
> >>  	/* WaFbcAsynchFlipDisableFbcQueue:ivb */
> >> -	I915_WRITE(ILK_DISPLAY_CHICKEN1,
> >> -		   I915_READ(ILK_DISPLAY_CHICKEN1) |
> >> +	intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
> >> +		   intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
> >>  		   ILK_FBCQ_DIS);
> >>  
> >>  	/* WaDisableBackToBackFlipFix:ivb */
> >> -	I915_WRITE(IVB_CHICKEN3,
> >> +	intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
> >>  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> >>  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
> >>  
> >>  	if (IS_IVB_GT1(dev_priv))
> >> -		I915_WRITE(GEN7_ROW_CHICKEN2,
> >> +		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
> >>  			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> >>  	else {
> >>  		/* must write both registers */
> >> -		I915_WRITE(GEN7_ROW_CHICKEN2,
> >> +		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
> >>  			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> >> -		I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
> >> +		intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2_GT2,
> >>  			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> >>  	}
> >>  
> >> @@ -7376,20 +7376,20 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> >>  	 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
> >>  	 */
> >> -	I915_WRITE(GEN6_UCGCTL2,
> >> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
> >>  		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
> >>  
> >>  	/* This is required by WaCatErrorRejectionIssue:ivb */
> >> -	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> >> -			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> >> +	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> >> +			intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> >>  			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
> >>  
> >>  	g4x_disable_trickle_feed(dev_priv);
> >>  
> >> -	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
> >> +	snpcr = intel_uncore_read(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR);
> >>  	snpcr &= ~GEN6_MBC_SNPCR_MASK;
> >>  	snpcr |= GEN6_MBC_SNPCR_MED;
> >> -	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
> >> +	intel_uncore_write(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR, snpcr);
> >>  
> >>  	if (!HAS_PCH_NOP(dev_priv))
> >>  		cpt_init_clock_gating(dev_priv);
> >> @@ -7400,58 +7400,58 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  {
> >>  	/* WaDisableBackToBackFlipFix:vlv */
> >> -	I915_WRITE(IVB_CHICKEN3,
> >> +	intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
> >>  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> >>  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
> >>  
> >>  	/* WaDisableDopClockGating:vlv */
> >> -	I915_WRITE(GEN7_ROW_CHICKEN2,
> >> +	intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
> >>  		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> >>  
> >>  	/* This is required by WaCatErrorRejectionIssue:vlv */
> >> -	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> >> -		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> >> +	intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> >> +		   intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> >>  		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
> >>  
> >>  	/*
> >>  	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> >>  	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
> >>  	 */
> >> -	I915_WRITE(GEN6_UCGCTL2,
> >> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
> >>  		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
> >>  
> >>  	/* WaDisableL3Bank2xClockGate:vlv
> >>  	 * Disabling L3 clock gating- MMIO 940c[25] = 1
> >>  	 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
> >> -	I915_WRITE(GEN7_UCGCTL4,
> >> -		   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
> >> +	intel_uncore_write(&dev_priv->uncore, GEN7_UCGCTL4,
> >> +		   intel_uncore_read(&dev_priv->uncore, GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
> >>  
> >>  	/*
> >>  	 * WaDisableVLVClockGating_VBIIssue:vlv
> >>  	 * Disable clock gating on th GCFG unit to prevent a delay
> >>  	 * in the reporting of vblank events.
> >>  	 */
> >> -	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
> >> +	intel_uncore_write(&dev_priv->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
> >>  }
> >>  
> >>  static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  {
> >>  	/* WaVSRefCountFullforceMissDisable:chv */
> >>  	/* WaDSRefCountFullforceMissDisable:chv */
> >> -	I915_WRITE(GEN7_FF_THREAD_MODE,
> >> -		   I915_READ(GEN7_FF_THREAD_MODE) &
> >> +	intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
> >> +		   intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
> >>  		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
> >>  
> >>  	/* WaDisableSemaphoreAndSyncFlipWait:chv */
> >> -	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> >> +	intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
> >>  		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> >>  
> >>  	/* WaDisableCSUnitClockGating:chv */
> >> -	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> >> +	intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
> >>  		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
> >>  
> >>  	/* WaDisableSDEUnitClockGating:chv */
> >> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> >> +	intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
> >>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> >>  
> >>  	/*
> >> @@ -7466,17 +7466,17 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  {
> >>  	u32 dspclk_gate;
> >>  
> >> -	I915_WRITE(RENCLK_GATE_D1, 0);
> >> -	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
> >> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, 0);
> >> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
> >>  		   GS_UNIT_CLOCK_GATE_DISABLE |
> >>  		   CL_UNIT_CLOCK_GATE_DISABLE);
> >> -	I915_WRITE(RAMCLK_GATE_D, 0);
> >> +	intel_uncore_write(&dev_priv->uncore, RAMCLK_GATE_D, 0);
> >>  	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
> >>  		OVRUNIT_CLOCK_GATE_DISABLE |
> >>  		OVCUNIT_CLOCK_GATE_DISABLE;
> >>  	if (IS_GM45(dev_priv))
> >>  		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
> >> -	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
> >> +	intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D, dspclk_gate);
> >>  
> >>  	g4x_disable_trickle_feed(dev_priv);
> >>  }
> >> @@ -7497,49 +7497,49 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  
> >>  static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  {
> >> -	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
> >> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
> >>  		   I965_RCC_CLOCK_GATE_DISABLE |
> >>  		   I965_RCPB_CLOCK_GATE_DISABLE |
> >>  		   I965_ISC_CLOCK_GATE_DISABLE |
> >>  		   I965_FBC_CLOCK_GATE_DISABLE);
> >> -	I915_WRITE(RENCLK_GATE_D2, 0);
> >> -	I915_WRITE(MI_ARB_STATE,
> >> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, 0);
> >> +	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
> >>  		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
> >>  }
> >>  
> >>  static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  {
> >> -	u32 dstate = I915_READ(D_STATE);
> >> +	u32 dstate = intel_uncore_read(&dev_priv->uncore, D_STATE);
> >>  
> >>  	dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
> >>  		DSTATE_DOT_CLOCK_GATING;
> >> -	I915_WRITE(D_STATE, dstate);
> >> +	intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
> >>  
> >>  	if (IS_PINEVIEW(dev_priv))
> >> -		I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
> >> +		intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
> >>  
> >>  	/* IIR "flip pending" means done if this bit is set */
> >> -	I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
> >> +	intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
> >>  
> >>  	/* interrupts should cause a wake up from C3 */
> >> -	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
> >> +	intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
> >>  
> >>  	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
> >> -	I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
> >> +	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
> >>  
> >> -	I915_WRITE(MI_ARB_STATE,
> >> +	intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
> >>  		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
> >>  }
> >>  
> >>  static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  {
> >> -	I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
> >> +	intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
> >>  
> >>  	/* interrupts should cause a wake up from C3 */
> >> -	I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
> >> +	intel_uncore_write(&dev_priv->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
> >>  		   _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
> >>  
> >> -	I915_WRITE(MEM_MODE,
> >> +	intel_uncore_write(&dev_priv->uncore, MEM_MODE,
> >>  		   _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
> >>  
> >>  	/*
> >> @@ -7549,13 +7549,13 @@ static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  	 * abosultely nothing) would not allow FBC to recompress
> >>  	 * until a 2D blit occurs.
> >>  	 */
> >> -	I915_WRITE(SCPD0,
> >> +	intel_uncore_write(&dev_priv->uncore, SCPD0,
> >>  		   _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
> >>  }
> >>  
> >>  static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
> >>  {
> >> -	I915_WRITE(MEM_MODE,
> >> +	intel_uncore_write(&dev_priv->uncore, MEM_MODE,
> >>  		   _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
> >>  		   _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
> >>  }
> >> -- 
> >> 2.20.1
> >> 
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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