* [Intel-gfx] [CI 01/15] drm/i915: Copy the plane hw state directly for Y planes
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 02/15] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3 Manasi Navare
` (18 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
When doing the plane state copy from the UV plane to the Y plane
let's just copy the hw state directly instead of using the original
uapi state. The UV plane has already had its uapi state copied into
its hw state, so this extra detour via the uapi state for the Y plane
is pointless.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 12 ++++++++++++
drivers/gpu/drm/i915/display/intel_atomic_plane.h | 2 ++
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 3334ff253600..f47558efb3c2 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -265,6 +265,18 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
}
+void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
+ const struct intel_plane_state *from_plane_state)
+{
+ intel_plane_clear_hw_state(plane_state);
+
+ memcpy(&plane_state->hw, &from_plane_state->hw,
+ sizeof(plane_state->hw));
+
+ if (plane_state->hw.fb)
+ drm_framebuffer_get(plane_state->hw.fb);
+}
+
void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 59dd1fbb02ea..24a3a148aa62 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -25,6 +25,8 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
const struct intel_plane_state *from_plane_state);
+void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
+ const struct intel_plane_state *from_plane_state);
void intel_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bc532711470b..a1b975ab3bb0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12792,7 +12792,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
memcpy(linked_state->color_plane, plane_state->color_plane,
sizeof(linked_state->color_plane));
- intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
+ intel_plane_copy_hw_state(linked_state, plane_state);
linked_state->uapi.src = plane_state->uapi.src;
linked_state->uapi.dst = plane_state->uapi.dst;
--
2.19.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [CI 02/15] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 01/15] drm/i915: Copy the plane hw state directly for Y planes Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 03/15] drm/i915: Try to make bigjoiner work in atomic check Manasi Navare
` (17 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
v13:
* Allow bigjoiner if hdisplay >5120
v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in downstream_mode_valid (Ville)
v11:
* Make intel_dp_can_bigjoiner non static
so it can be used in intel_display (Manasi)
v10:
* Simplify logic (Ville)
* Allow bigjoiner on edp (Ville)
v9:
* Restric Bigjoiner on PORT A (Ville)
v8:
* use source dotclock for max dotclock (Manasi)
v7:
* Add can_bigjoiner() helper (Ville)
* Pass bigjoiner to plane_size validation (Ville)
v6:
* Rebase after dp_downstream mode valid changes (Manasi)
v5:
* Increase max plane width to support 8K with bigjoiner (Maarten)
v4:
* Rebase (Manasi)
Changes since v1:
- Disallow bigjoiner on eDP.
Changes since v2:
- Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
and split off the downstream and source checking to its own function.
(Ville)
v3:
* Rebase (Manasi)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
[vsyrjala:
* Keep bigjoiner disabled until everything is ready
* Appease checkpatch]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
drivers/gpu/drm/i915/display/intel_display.h | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 81 ++++++++++++++++----
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
7 files changed, 76 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a1b975ab3bb0..16c55d8fe4dc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17780,7 +17780,8 @@ intel_mode_valid(struct drm_device *dev,
enum drm_mode_status
intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
- const struct drm_display_mode *mode)
+ const struct drm_display_mode *mode,
+ bool bigjoiner)
{
int plane_width_max, plane_height_max;
@@ -17797,7 +17798,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
* too big for that.
*/
if (INTEL_GEN(dev_priv) >= 11) {
- plane_width_max = 5120;
+ plane_width_max = 5120 << bigjoiner;
plane_height_max = 4320;
} else {
plane_width_max = 5120;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 6be14e8571aa..5e0d42d82c11 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -513,7 +513,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
enum drm_mode_status
intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
- const struct drm_display_mode *mode);
+ const struct drm_display_mode *mode,
+ bool bigjoiner);
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ec8359f03aaf..5ad59610eb12 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -254,6 +254,20 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
return max_link_clock * max_lanes;
}
+bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &intel_dig_port->base;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ /* FIXME remove once everything is in place */
+ return false;
+
+ return INTEL_GEN(dev_priv) >= 12 ||
+ (INTEL_GEN(dev_priv) == 11 &&
+ encoder->port != PORT_A);
+}
+
static int cnl_max_source_rate(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -519,7 +533,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay)
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -537,6 +552,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
mode_hdisplay;
+
+ if (bigjoiner)
+ max_bpp_small_joiner_ram *= 2;
+
drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
max_bpp_small_joiner_ram);
@@ -546,6 +565,15 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
*/
bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
+ if (bigjoiner) {
+ u32 max_bpp_bigjoiner =
+ i915->max_cdclk_freq * 48 /
+ intel_dp_mode_to_fec_clock(mode_clock);
+
+ DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
+ bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
+ }
+
/* Error out if the max bpp is less than smallest allowed valid bpp */
if (bits_per_pixel < valid_dsc_bpp[0]) {
drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
@@ -568,7 +596,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
}
static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay)
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 min_slice_count, i;
@@ -595,12 +624,18 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
/* Find the closest match to the valid slice count values */
for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
- if (valid_dsc_slicecount[i] >
- drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
- false))
+ u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
+
+ if (test_slice_count >
+ drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
break;
- if (min_slice_count <= valid_dsc_slicecount[i])
- return valid_dsc_slicecount[i];
+
+ /* big joiner needs small joiner to be enabled */
+ if (bigjoiner && test_slice_count < 4)
+ continue;
+
+ if (min_slice_count <= test_slice_count)
+ return test_slice_count;
}
drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
@@ -717,6 +752,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
u16 dsc_max_output_bpp = 0;
u8 dsc_slice_count = 0;
enum drm_mode_status status;
+ bool dsc = false, bigjoiner = false;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
@@ -737,6 +773,14 @@ intel_dp_mode_valid(struct drm_connector *connector,
if (mode->clock < 10000)
return MODE_CLOCK_LOW;
+ if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
+ intel_dp_can_bigjoiner(intel_dp)) {
+ bigjoiner = true;
+ max_dotclk *= 2;
+ }
+ if (target_clock > max_dotclk)
+ return MODE_CLOCK_HIGH;
+
max_link_clock = intel_dp_max_link_rate(intel_dp);
max_lanes = intel_dp_max_lane_count(intel_dp);
@@ -765,16 +809,23 @@ intel_dp_mode_valid(struct drm_connector *connector,
max_link_clock,
max_lanes,
target_clock,
- mode->hdisplay) >> 4;
+ mode->hdisplay,
+ bigjoiner) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
- mode->hdisplay);
+ mode->hdisplay,
+ bigjoiner);
}
+
+ dsc = dsc_max_output_bpp && dsc_slice_count;
}
- if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
- target_clock > max_dotclk)
+ /* big joiner configuration needs DSC */
+ if (bigjoiner && !dsc)
+ return MODE_CLOCK_HIGH;
+
+ if (mode_rate > max_rate && !dsc)
return MODE_CLOCK_HIGH;
status = intel_dp_mode_valid_downstream(intel_connector,
@@ -782,7 +833,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
if (status != MODE_OK)
return status;
- return intel_mode_valid_max_plane_size(dev_priv, mode);
+ return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
}
u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
@@ -2351,11 +2402,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->port_clock,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay);
+ adjusted_mode->crtc_hdisplay,
+ false);
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay);
+ adjusted_mode->crtc_hdisplay,
+ false);
if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP/Slice Count not supported\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3f862b4fd34f..b871a09b6901 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -106,6 +106,7 @@ bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
+bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c8fcec4d0788..0c8684634fca 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -714,7 +714,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
return 0;
}
- *status = intel_mode_valid_max_plane_size(dev_priv, mode);
+ *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
index afa4e6817e8c..f453ceb8d149 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -75,7 +75,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
return MODE_CLOCK_HIGH;
}
- return intel_mode_valid_max_plane_size(dev_priv, mode);
+ return intel_mode_valid_max_plane_size(dev_priv, mode, false);
}
struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f90838bc74fb..82674a8853c6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2274,7 +2274,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
if (status != MODE_OK)
return status;
- return intel_mode_valid_max_plane_size(dev_priv, mode);
+ return intel_mode_valid_max_plane_size(dev_priv, mode, false);
}
bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [CI 03/15] drm/i915: Try to make bigjoiner work in atomic check
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 01/15] drm/i915: Copy the plane hw state directly for Y planes Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 02/15] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3 Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 04/15] drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave Manasi Navare
` (16 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
When the clock is higher than the dotclock, try with 2 pipes enabled.
If we can enable 2, then we will go into big joiner mode, and steal
the adjacent crtc.
This only links the crtc's in software, no hardware or plane
programming is done yet. Blobs are also copied from the master's
crtc_state, so it doesn't depend at commit time on the other
crtc_state.
v6:
* Enable dSC for any mode->hdisplay > 5120
v5:
* Remove intel_dp_max_dotclock (Manasi)
v4:
* Fixes in intel_crtc_compute_config (Ville)
v3:
* Manual Rebase (Manasi)
Changes since v1:
- Rename pipe timings to transcoder timings, as they are now different.
Changes since v2:
- Rework bigjoiner checks; always disable slave when recalculating
master. No need to have a separate bigjoiner pass any more.
- Use pipe_mode instead of transcoder_mode, to clean up the code.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
[vsyrjala:
* hskew isn't a thing
* Do the dsc compute if bigjoiner is enabled, not the other way around]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 156 +++++++++++++++++-
.../drm/i915/display/intel_display_types.h | 9 +
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++-
3 files changed, 175 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 16c55d8fe4dc..70c68082f7fc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8194,6 +8194,19 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
int clock_limit = dev_priv->max_dotclk_freq;
drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode);
+
+ /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
+ if (pipe_config->bigjoiner) {
+ pipe_mode->crtc_clock /= 2;
+ pipe_mode->crtc_hdisplay /= 2;
+ pipe_mode->crtc_hblank_start /= 2;
+ pipe_mode->crtc_hblank_end /= 2;
+ pipe_mode->crtc_hsync_start /= 2;
+ pipe_mode->crtc_hsync_end /= 2;
+ pipe_mode->crtc_htotal /= 2;
+ pipe_config->pipe_src_w /= 2;
+ }
+
intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
if (INTEL_GEN(dev_priv) < 4) {
@@ -12917,6 +12930,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
if (mode_changed && crtc_state->hw.enable &&
dev_priv->display.crtc_compute_clock &&
+ !crtc_state->bigjoiner_slave &&
!drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
if (ret)
@@ -13462,6 +13476,15 @@ intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
{
const struct intel_crtc_state *from_crtc_state = crtc_state;
+ if (crtc_state->bigjoiner_slave) {
+ from_crtc_state = intel_atomic_get_new_crtc_state(state,
+ crtc_state->bigjoiner_linked_crtc);
+
+ /* No need to copy state if the master state is unchanged */
+ if (!from_crtc_state)
+ return;
+ }
+
intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
}
@@ -13497,6 +13520,47 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
crtc_state->hw.ctm);
}
+static int
+copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
+ const struct intel_crtc_state *from_crtc_state)
+{
+ struct intel_crtc_state *saved_state;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL);
+ if (!saved_state)
+ return -ENOMEM;
+
+ saved_state->uapi = crtc_state->uapi;
+ saved_state->scaler_state = crtc_state->scaler_state;
+ saved_state->shared_dpll = crtc_state->shared_dpll;
+ saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
+ saved_state->crc_enabled = crtc_state->crc_enabled;
+
+ intel_crtc_free_hw_state(crtc_state);
+ memcpy(crtc_state, saved_state, sizeof(*crtc_state));
+ kfree(saved_state);
+
+ /* Re-init hw state */
+ memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
+ crtc_state->hw.enable = from_crtc_state->hw.enable;
+ crtc_state->hw.active = from_crtc_state->hw.active;
+ crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode;
+ crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
+
+ /* Some fixups */
+ crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
+ crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;
+ crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
+ crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
+ crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);
+ crtc_state->bigjoiner_slave = true;
+ crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;
+ crtc_state->has_audio = false;
+
+ return 0;
+}
+
static int
intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
@@ -15079,6 +15143,75 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
return false;
}
+static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
+ struct intel_crtc *slave, *master;
+
+ /* slave being enabled, is master is still claiming this crtc? */
+ if (old_crtc_state->bigjoiner_slave) {
+ slave = crtc;
+ master = old_crtc_state->bigjoiner_linked_crtc;
+ master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
+ if (!master_crtc_state || !needs_modeset(master_crtc_state))
+ goto claimed;
+ }
+
+ if (!new_crtc_state->bigjoiner)
+ return 0;
+
+ if (1 + crtc->pipe >= INTEL_NUM_PIPES(dev_priv)) {
+ DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
+ "CRTC + 1 to be used, doesn't exist\n",
+ crtc->base.base.id, crtc->base.name);
+ return -EINVAL;
+ }
+
+ slave = new_crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
+ slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
+ master = crtc;
+ if (IS_ERR(slave_crtc_state))
+ return PTR_ERR(slave_crtc_state);
+
+ /* master being enabled, slave was already configured? */
+ if (slave_crtc_state->uapi.enable)
+ goto claimed;
+
+ DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
+ slave->base.base.id, slave->base.name);
+
+ return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
+
+claimed:
+ DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
+ "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
+ slave->base.base.id, slave->base.name,
+ master->base.base.id, master->base.name);
+ return -EINVAL;
+}
+
+static int kill_bigjoiner_slave(struct intel_atomic_state *state,
+ struct intel_crtc_state *master_crtc_state)
+{
+ struct intel_crtc_state *slave_crtc_state =
+ intel_atomic_get_crtc_state(&state->base,
+ master_crtc_state->bigjoiner_linked_crtc);
+
+ if (IS_ERR(slave_crtc_state))
+ return PTR_ERR(slave_crtc_state);
+
+ slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
+ slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
+ slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
+ intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
+ return 0;
+}
+
/**
* DOC: asynchronous flip implementation
*
@@ -15246,16 +15379,33 @@ static int intel_atomic_check(struct drm_device *dev,
continue;
}
+ /* Kill old bigjoiner link, we may re-establish afterwards */
+ if (old_crtc_state->bigjoiner && !old_crtc_state->bigjoiner_slave) {
+ ret = kill_bigjoiner_slave(state, new_crtc_state);
+ if (ret)
+ goto fail;
+ }
+
+ if (!new_crtc_state->uapi.enable) {
+ if (!new_crtc_state->bigjoiner_slave) {
+ intel_crtc_copy_uapi_to_hw_state(state, new_crtc_state);
+ any_ms = true;
+ }
+ continue;
+ }
+
ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
if (ret)
goto fail;
- if (!new_crtc_state->hw.enable)
- continue;
-
ret = intel_modeset_pipe_config(state, new_crtc_state);
if (ret)
goto fail;
+
+ ret = intel_atomic_check_bigjoiner(state, crtc, old_crtc_state,
+ new_crtc_state);
+ if (ret)
+ goto fail;
}
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5bb7adc1ff3e..b3d94e6cd7c5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1079,6 +1079,15 @@ struct intel_crtc_state {
/* enable pipe csc? */
bool csc_enable;
+ /* enable pipe big joiner? */
+ bool bigjoiner;
+
+ /* big joiner slave crtc? */
+ bool bigjoiner_slave;
+
+ /* linked crtc for bigjoiner, either slave or master */
+ struct intel_crtc *bigjoiner_linked_crtc;
+
/* Display Stream compression state */
struct {
bool compression_enable;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5ad59610eb12..9430caf053cd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2403,12 +2403,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
- false);
+ pipe_config->bigjoiner);
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
- false);
+ pipe_config->bigjoiner);
if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP/Slice Count not supported\n");
@@ -2424,14 +2424,15 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* is greater than the maximum Cdclock and if slice count is even
* then we need to use 2 VDSC instances.
*/
- if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
- if (pipe_config->dsc.slice_count > 1) {
- pipe_config->dsc.dsc_split = true;
- } else {
+ if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
+ pipe_config->bigjoiner) {
+ if (pipe_config->dsc.slice_count < 2) {
drm_dbg_kms(&dev_priv->drm,
"Cannot split stream to use 2 VDSC instances\n");
return -EINVAL;
}
+
+ pipe_config->dsc.dsc_split = true;
}
ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
@@ -2502,6 +2503,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
intel_dp->common_rates[limits.max_clock],
limits.max_bpp, adjusted_mode->crtc_clock);
+ if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
+ adjusted_mode->crtc_hdisplay > 5120) &&
+ intel_dp_can_bigjoiner(intel_dp))
+ pipe_config->bigjoiner = true;
+
/*
* Optimize for slow and wide. This is the place to add alternative
* optimization policy.
@@ -2510,7 +2516,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
/* enable compression if the mode doesn't fit available BW */
drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
- if (ret || intel_dp->force_dsc_en) {
+ if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
conn_state, &limits);
if (ret < 0)
--
2.19.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [CI 04/15] drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (2 preceding siblings ...)
2020-11-17 19:47 ` [Intel-gfx] [CI 03/15] drm/i915: Try to make bigjoiner work in atomic check Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2021-03-02 10:20 ` Jani Nikula
2020-11-17 19:47 ` [Intel-gfx] [CI 05/15] drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner Manasi Navare
` (15 subsequent siblings)
19 siblings, 1 reply; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
Make vdsc work when no output is enabled. The big joiner needs VDSC
on the slave, so enable it and set the appropriate bits.
So remove encoder usage from dsc functions.
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
drivers/gpu/drm/i915/display/intel_display.c | 3 +
drivers/gpu/drm/i915/display/intel_dp.c | 6 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 201 ++++++++++---------
drivers/gpu/drm/i915/display/intel_vdsc.h | 6 +-
6 files changed, 110 insertions(+), 117 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 769bb1b0d543..e83364b5774f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1492,7 +1492,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- intel_dsc_get_config(encoder, pipe_config);
+ intel_dsc_get_config(pipe_config);
/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
pipe_config->port_clock = intel_dpll_get_freq(i915,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9d80e47e9558..f13d3cf465a2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2296,13 +2296,6 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
intel_phy_is_tc(dev_priv, phy))
intel_display_power_get(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
-
- /*
- * VDSC power is needed when DSC is enabled
- */
- if (crtc_state->dsc.compression_enable)
- intel_display_power_get(dev_priv,
- intel_dsc_power_domain(crtc_state));
}
void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
@@ -4577,7 +4570,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
return;
- intel_dsc_get_config(encoder, pipe_config);
+ intel_dsc_get_config(pipe_config);
temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (temp & TRANS_DDI_PHSYNC)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 70c68082f7fc..36c780a67721 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7508,6 +7508,9 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
if (crtc_state->shared_dpll)
mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
+ if (crtc_state->dsc.compression_enable)
+ mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
+
return mask;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9430caf053cd..857f39779654 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2103,12 +2103,10 @@ static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
- struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
-
- if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
return false;
- return intel_dsc_source_support(encoder, crtc_state) &&
+ return intel_dsc_source_support(crtc_state) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index c5735c365659..e2716a67b281 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -332,11 +332,10 @@ static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
return &rc_parameters[row_index][column_index];
}
-bool intel_dsc_source_support(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum pipe pipe = crtc->pipe;
@@ -490,11 +489,10 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
}
-static void intel_dsc_pps_configure(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
enum pipe pipe = crtc->pipe;
u32 pps_val = 0;
@@ -503,6 +501,9 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
int i = 0;
+ if (crtc_state->bigjoiner)
+ num_vdsc_instances *= 2;
+
/* Populate PICTURE_PARAMETER_SET_0 registers */
pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
DSC_VER_MIN_SHIFT |
@@ -973,55 +974,6 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
}
}
-void intel_dsc_get_config(struct intel_encoder *encoder,
- struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- enum pipe pipe = crtc->pipe;
- enum intel_display_power_domain power_domain;
- intel_wakeref_t wakeref;
- u32 dss_ctl1, dss_ctl2, val;
-
- if (!intel_dsc_source_support(encoder, crtc_state))
- return;
-
- power_domain = intel_dsc_power_domain(crtc_state);
-
- wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
- if (!wakeref)
- return;
-
- if (!is_pipe_dsc(crtc_state)) {
- dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);
- dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2);
- } else {
- dss_ctl1 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
- dss_ctl2 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL2(pipe));
- }
-
- crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
- if (!crtc_state->dsc.compression_enable)
- goto out;
-
- crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
- (dss_ctl1 & JOINER_ENABLE);
-
- /* FIXME: add more state readout as needed */
-
- /* PPS1 */
- if (!is_pipe_dsc(crtc_state))
- val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
- else
- val = intel_de_read(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
- vdsc_cfg->bits_per_pixel = val;
- crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
-out:
- intel_display_power_put(dev_priv, power_domain, wakeref);
-}
-
static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1060,77 +1012,126 @@ static void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
sizeof(dp_dsc_pps_sdp));
}
+static i915_reg_t dss_ctl1_reg(const struct intel_crtc_state *crtc_state)
+{
+ enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+
+ if (crtc_state->cpu_transcoder == TRANSCODER_EDP)
+ return DSS_CTL1;
+
+ return ICL_PIPE_DSS_CTL1(pipe);
+}
+
+static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
+{
+ enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+
+ if (crtc_state->cpu_transcoder == TRANSCODER_EDP)
+ return DSS_CTL2;
+
+ return ICL_PIPE_DSS_CTL2(pipe);
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum pipe pipe = crtc->pipe;
- i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 dss_ctl1_val = 0;
u32 dss_ctl2_val = 0;
if (!crtc_state->dsc.compression_enable)
return;
- /* Enable Power wells for VDSC/joining */
- intel_display_power_get(dev_priv,
- intel_dsc_power_domain(crtc_state));
-
- intel_dsc_pps_configure(encoder, crtc_state);
+ intel_dsc_pps_configure(crtc_state);
- if (encoder->type == INTEL_OUTPUT_DSI)
- intel_dsc_dsi_pps_write(encoder, crtc_state);
- else
- intel_dsc_dp_pps_write(encoder, crtc_state);
-
- if (!is_pipe_dsc(crtc_state)) {
- dss_ctl1_reg = DSS_CTL1;
- dss_ctl2_reg = DSS_CTL2;
- } else {
- dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
- dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ if (!crtc_state->bigjoiner_slave) {
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+ intel_dsc_dsi_pps_write(encoder, crtc_state);
+ else
+ intel_dsc_dp_pps_write(encoder, crtc_state);
}
+
dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
if (crtc_state->dsc.dsc_split) {
dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
dss_ctl1_val |= JOINER_ENABLE;
}
- intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val);
- intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val);
+ if (crtc_state->bigjoiner) {
+ dss_ctl1_val |= BIG_JOINER_ENABLE;
+ if (!crtc_state->bigjoiner_slave)
+ dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
+ }
+ intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
+ intel_de_write(dev_priv, dss_ctl2_reg(crtc_state), dss_ctl2_val);
}
void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
- i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
- u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
if (!old_crtc_state->dsc.compression_enable)
return;
- if (!is_pipe_dsc(old_crtc_state)) {
- dss_ctl1_reg = DSS_CTL1;
- dss_ctl2_reg = DSS_CTL2;
- } else {
- dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
- dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
+ intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
+}
+
+void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ enum intel_display_power_domain power_domain;
+ intel_wakeref_t wakeref;
+ u32 dss_ctl1, dss_ctl2, val;
+
+ if (!intel_dsc_source_support(crtc_state))
+ return;
+
+ power_domain = intel_dsc_power_domain(crtc_state);
+
+ wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
+ if (!wakeref)
+ return;
+
+ dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
+ dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc_state));
+
+ crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
+ if (!crtc_state->dsc.compression_enable)
+ goto out;
+
+ crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
+ (dss_ctl1 & JOINER_ENABLE);
+
+ if (dss_ctl1 & BIG_JOINER_ENABLE) {
+ crtc_state->bigjoiner = true;
+
+ if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) {
+ crtc_state->bigjoiner_slave = true;
+ if (!WARN_ON(crtc->pipe == PIPE_A))
+ crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
+ } else {
+ if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
+ crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
+ }
}
- dss_ctl1_val = intel_de_read(dev_priv, dss_ctl1_reg);
- if (dss_ctl1_val & JOINER_ENABLE)
- dss_ctl1_val &= ~JOINER_ENABLE;
- intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val);
-
- dss_ctl2_val = intel_de_read(dev_priv, dss_ctl2_reg);
- if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
- dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
- dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
- RIGHT_BRANCH_VDSC_ENABLE);
- intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val);
-
- /* Disable Power wells for VDSC/joining */
- intel_display_power_put_unchecked(dev_priv,
- intel_dsc_power_domain(old_crtc_state));
+
+ /* FIXME: add more state readout as needed */
+
+ /* PPS1 */
+ if (!is_pipe_dsc(crtc_state))
+ val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
+ else
+ val = intel_de_read(dev_priv,
+ ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
+ vdsc_cfg->bits_per_pixel = val;
+ crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+out:
+ intel_display_power_put(dev_priv, power_domain, wakeref);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index e56a3254c214..65d301c23580 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -11,15 +11,13 @@
struct intel_encoder;
struct intel_crtc_state;
-bool intel_dsc_source_support(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state);
+bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
int intel_dsc_compute_params(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
-void intel_dsc_get_config(struct intel_encoder *encoder,
- struct intel_crtc_state *crtc_state);
+void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
enum intel_display_power_domain
intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
--
2.19.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [Intel-gfx] [CI 04/15] drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave
2020-11-17 19:47 ` [Intel-gfx] [CI 04/15] drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave Manasi Navare
@ 2021-03-02 10:20 ` Jani Nikula
0 siblings, 0 replies; 26+ messages in thread
From: Jani Nikula @ 2021-03-02 10:20 UTC (permalink / raw)
To: Manasi Navare, intel-gfx
On Tue, 17 Nov 2020, Manasi Navare <manasi.d.navare@intel.com> wrote:
> Make vdsc work when no output is enabled. The big joiner needs VDSC
> on the slave, so enable it and set the appropriate bits.
> So remove encoder usage from dsc functions.
Hi Manasi -
I'm reading intel_vdsc.c code for something else, and stumbled upon the
changes introduced in this patch that I think break ICL DSI DSC.
Please fix.
> -void intel_dsc_get_config(struct intel_encoder *encoder,
> - struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - enum pipe pipe = crtc->pipe;
> - enum intel_display_power_domain power_domain;
> - intel_wakeref_t wakeref;
> - u32 dss_ctl1, dss_ctl2, val;
> -
> - if (!intel_dsc_source_support(encoder, crtc_state))
> - return;
> -
> - power_domain = intel_dsc_power_domain(crtc_state);
> -
> - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
> - if (!wakeref)
> - return;
> -
> - if (!is_pipe_dsc(crtc_state)) {
> - dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);
> - dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2);
Note how is_pipe_dsc() decides which registers to use. We'll use pipe
dsc for non-eDP/DSI transcoders on gen 11, and all transcoders on gen
12+.
(Gen 12+ also does not have separate eDP transcoder.)
> +static i915_reg_t dss_ctl1_reg(const struct intel_crtc_state *crtc_state)
> +{
> + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> +
> + if (crtc_state->cpu_transcoder == TRANSCODER_EDP)
> + return DSS_CTL1;
> +
> + return ICL_PIPE_DSS_CTL1(pipe);
> +}
> +
> +static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
> +{
> + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> +
> + if (crtc_state->cpu_transcoder == TRANSCODER_EDP)
> + return DSS_CTL2;
> +
> + return ICL_PIPE_DSS_CTL2(pipe);
> +}
However, after the changes, here we only look at cpu_transcoder to make
the decision on the registers. This works for gen 12+ and gen 11 eDP,
but picks the wrong registers on gen 11 DSI DSC.
Bypassing is_pipe_dsc() also skips the crucial check and warning on
trying to use pipe A DSC engine on ICL, which CI would have caught. If
the issue only causes a black or garbled screen, we can't detect that.
---
There's nothing wrong with adding abstractions for dss_ctl{1,2}_reg, but
they certainly do not belong in the same patch with everything else that
is going on here. If separated, the functional change would have stood
out better, and review would have had a better chance of catching it.
BR,
Jani.
> +
> void intel_dsc_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum pipe pipe = crtc->pipe;
> - i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 dss_ctl1_val = 0;
> u32 dss_ctl2_val = 0;
>
> if (!crtc_state->dsc.compression_enable)
> return;
>
> - /* Enable Power wells for VDSC/joining */
> - intel_display_power_get(dev_priv,
> - intel_dsc_power_domain(crtc_state));
> -
> - intel_dsc_pps_configure(encoder, crtc_state);
> + intel_dsc_pps_configure(crtc_state);
>
> - if (encoder->type == INTEL_OUTPUT_DSI)
> - intel_dsc_dsi_pps_write(encoder, crtc_state);
> - else
> - intel_dsc_dp_pps_write(encoder, crtc_state);
> -
> - if (!is_pipe_dsc(crtc_state)) {
> - dss_ctl1_reg = DSS_CTL1;
> - dss_ctl2_reg = DSS_CTL2;
> - } else {
> - dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
> - dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
> + if (!crtc_state->bigjoiner_slave) {
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> + intel_dsc_dsi_pps_write(encoder, crtc_state);
> + else
> + intel_dsc_dp_pps_write(encoder, crtc_state);
> }
> +
> dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
> if (crtc_state->dsc.dsc_split) {
> dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
> dss_ctl1_val |= JOINER_ENABLE;
> }
> - intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val);
> - intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val);
> + if (crtc_state->bigjoiner) {
> + dss_ctl1_val |= BIG_JOINER_ENABLE;
> + if (!crtc_state->bigjoiner_slave)
> + dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
> + }
> + intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
> + intel_de_write(dev_priv, dss_ctl2_reg(crtc_state), dss_ctl2_val);
> }
>
> void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum pipe pipe = crtc->pipe;
> - i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> - u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
>
> if (!old_crtc_state->dsc.compression_enable)
> return;
>
> - if (!is_pipe_dsc(old_crtc_state)) {
> - dss_ctl1_reg = DSS_CTL1;
> - dss_ctl2_reg = DSS_CTL2;
> - } else {
> - dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
> - dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
> + intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
> + intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
> +}
> +
> +void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> +{
> + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + enum intel_display_power_domain power_domain;
> + intel_wakeref_t wakeref;
> + u32 dss_ctl1, dss_ctl2, val;
> +
> + if (!intel_dsc_source_support(crtc_state))
> + return;
> +
> + power_domain = intel_dsc_power_domain(crtc_state);
> +
> + wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
> + if (!wakeref)
> + return;
> +
> + dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
> + dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc_state));
> +
> + crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
> + if (!crtc_state->dsc.compression_enable)
> + goto out;
> +
> + crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
> + (dss_ctl1 & JOINER_ENABLE);
> +
> + if (dss_ctl1 & BIG_JOINER_ENABLE) {
> + crtc_state->bigjoiner = true;
> +
> + if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) {
> + crtc_state->bigjoiner_slave = true;
> + if (!WARN_ON(crtc->pipe == PIPE_A))
> + crtc_state->bigjoiner_linked_crtc =
> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
> + } else {
> + if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
> + crtc_state->bigjoiner_linked_crtc =
> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
> + }
> }
> - dss_ctl1_val = intel_de_read(dev_priv, dss_ctl1_reg);
> - if (dss_ctl1_val & JOINER_ENABLE)
> - dss_ctl1_val &= ~JOINER_ENABLE;
> - intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val);
> -
> - dss_ctl2_val = intel_de_read(dev_priv, dss_ctl2_reg);
> - if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
> - dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
> - dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
> - RIGHT_BRANCH_VDSC_ENABLE);
> - intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val);
> -
> - /* Disable Power wells for VDSC/joining */
> - intel_display_power_put_unchecked(dev_priv,
> - intel_dsc_power_domain(old_crtc_state));
> +
> + /* FIXME: add more state readout as needed */
> +
> + /* PPS1 */
> + if (!is_pipe_dsc(crtc_state))
> + val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
> + else
> + val = intel_de_read(dev_priv,
> + ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> + vdsc_cfg->bits_per_pixel = val;
> + crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> +out:
> + intel_display_power_put(dev_priv, power_domain, wakeref);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index e56a3254c214..65d301c23580 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -11,15 +11,13 @@
> struct intel_encoder;
> struct intel_crtc_state;
>
> -bool intel_dsc_source_support(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state);
> +bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
> void intel_dsc_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
> int intel_dsc_compute_params(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config);
> -void intel_dsc_get_config(struct intel_encoder *encoder,
> - struct intel_crtc_state *crtc_state);
> +void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
> enum intel_display_power_domain
> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
--
Jani Nikula, Intel Open Source Graphics Center
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] [CI 05/15] drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (3 preceding siblings ...)
2020-11-17 19:47 ` [Intel-gfx] [CI 04/15] drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 06/15] drm/i915: HW state readout for Bigjoiner case Manasi Navare
` (14 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
Enabling is done in a special sequence and so should plane updates
be. Ideally the end user never notices the second pipe is used.
This way ideally everything will be tear free, and updates are
really atomic as userspace expects it.
This uses generic modeset_enables() calls like trans port sync
but still has special handling for disable since for slave we
should not disable things like encoder, plls that are not enabled
for slave.
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
[vsyrjala: Appease checkpatch]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 25 +++-
drivers/gpu/drm/i915/display/intel_display.c | 118 +++++++++++++++----
2 files changed, 118 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f13d3cf465a2..81c4043ce42a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -28,6 +28,7 @@
#include <drm/drm_scdc_helper.h>
#include "i915_drv.h"
+#include "i915_trace.h"
#include "intel_audio.h"
#include "intel_combo_phy.h"
#include "intel_connector.h"
@@ -3665,7 +3666,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
/* 7.l Configure and enable FEC if needed */
intel_ddi_enable_fec(encoder, crtc_state);
- intel_dsc_enable(encoder, crtc_state);
+ if (!crtc_state->bigjoiner)
+ intel_dsc_enable(encoder, crtc_state);
}
static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -3737,7 +3739,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
if (!is_mst)
intel_ddi_enable_pipe_clock(encoder, crtc_state);
- intel_dsc_enable(encoder, crtc_state);
+ if (!crtc_state->bigjoiner)
+ intel_dsc_enable(encoder, crtc_state);
}
static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -3988,6 +3991,21 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
ilk_pfit_disable(old_crtc_state);
}
+ if (old_crtc_state->bigjoiner_linked_crtc) {
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(old_crtc_state->uapi.state);
+ struct intel_crtc *slave =
+ old_crtc_state->bigjoiner_linked_crtc;
+ const struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave);
+
+ intel_crtc_vblank_off(old_slave_crtc_state);
+ trace_intel_pipe_disable(slave);
+
+ intel_dsc_disable(old_slave_crtc_state);
+ skl_scaler_disable(old_slave_crtc_state);
+ }
+
/*
* When called from DP MST code:
* - old_conn_state will be NULL
@@ -4206,7 +4224,8 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
{
drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
- intel_ddi_enable_transcoder_func(encoder, crtc_state);
+ if (!crtc_state->bigjoiner_slave)
+ intel_ddi_enable_transcoder_func(encoder, crtc_state);
intel_enable_pipe(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 36c780a67721..e5a56904f33f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7138,6 +7138,45 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
intel_de_write(dev_priv, reg, val);
}
+static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
+ struct intel_crtc_state *master_crtc_state;
+ struct drm_connector_state *conn_state;
+ struct drm_connector *conn;
+ struct intel_encoder *encoder = NULL;
+ int i;
+
+ if (crtc_state->bigjoiner_slave)
+ master = crtc_state->bigjoiner_linked_crtc;
+
+ master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
+
+ for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
+ if (conn_state->crtc != &master->base)
+ continue;
+
+ encoder = to_intel_encoder(conn_state->best_encoder);
+ break;
+ }
+
+ if (!crtc_state->bigjoiner_slave) {
+ /* need to enable VDSC, which we skipped in pre-enable */
+ intel_dsc_enable(encoder, crtc_state);
+ } else {
+ /*
+ * Enable sequence steps 1-7 on bigjoiner master
+ */
+ intel_encoders_pre_pll_enable(state, master);
+ intel_enable_shared_dpll(master_crtc_state);
+ intel_encoders_pre_enable(state, master);
+
+ /* and DSC on slave */
+ intel_dsc_enable(NULL, crtc_state);
+ }
+}
+
static void hsw_crtc_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -7151,34 +7190,39 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
if (drm_WARN_ON(&dev_priv->drm, crtc->active))
return;
- intel_encoders_pre_pll_enable(state, crtc);
-
- if (new_crtc_state->shared_dpll)
- intel_enable_shared_dpll(new_crtc_state);
+ if (!new_crtc_state->bigjoiner) {
+ intel_encoders_pre_pll_enable(state, crtc);
- intel_encoders_pre_enable(state, crtc);
+ if (new_crtc_state->shared_dpll)
+ intel_enable_shared_dpll(new_crtc_state);
- if (!transcoder_is_dsi(cpu_transcoder))
- intel_set_transcoder_timings(new_crtc_state);
+ intel_encoders_pre_enable(state, crtc);
+ } else {
+ icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
+ }
intel_set_pipe_src_size(new_crtc_state);
+ if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+ bdw_set_pipemisc(new_crtc_state);
- if (cpu_transcoder != TRANSCODER_EDP &&
- !transcoder_is_dsi(cpu_transcoder))
- intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
- new_crtc_state->pixel_multiplier - 1);
+ if (!new_crtc_state->bigjoiner_slave || !transcoder_is_dsi(cpu_transcoder)) {
+ if (!transcoder_is_dsi(cpu_transcoder))
+ intel_set_transcoder_timings(new_crtc_state);
- if (new_crtc_state->has_pch_encoder)
- intel_cpu_transcoder_set_m_n(new_crtc_state,
- &new_crtc_state->fdi_m_n, NULL);
+ if (cpu_transcoder != TRANSCODER_EDP &&
+ !transcoder_is_dsi(cpu_transcoder))
+ intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
+ new_crtc_state->pixel_multiplier - 1);
+
+ if (new_crtc_state->has_pch_encoder)
+ intel_cpu_transcoder_set_m_n(new_crtc_state,
+ &new_crtc_state->fdi_m_n, NULL);
- if (!transcoder_is_dsi(cpu_transcoder)) {
hsw_set_frame_start_delay(new_crtc_state);
- hsw_set_pipeconf(new_crtc_state);
}
- if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
- bdw_set_pipemisc(new_crtc_state);
+ if (!transcoder_is_dsi(cpu_transcoder))
+ hsw_set_pipeconf(new_crtc_state);
crtc->active = true;
@@ -7214,6 +7258,11 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
if (INTEL_GEN(dev_priv) >= 11)
icl_pipe_mbus_enable(crtc);
+ if (new_crtc_state->bigjoiner_slave) {
+ trace_intel_pipe_enable(crtc);
+ intel_crtc_vblank_on(new_crtc_state);
+ }
+
intel_encoders_enable(state, crtc);
if (psl_clkgate_wa) {
@@ -15708,6 +15757,9 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
dev_priv->display.crtc_enable(state, crtc);
+ if (new_crtc_state->bigjoiner_slave)
+ return;
+
/* vblanks work again, re-enable pipe CRC. */
intel_crtc_enable_pipe_crc(crtc);
}
@@ -15770,8 +15822,21 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);
+
intel_crtc_disable_planes(state, crtc);
+ /*
+ * We still need special handling for disabling bigjoiner master
+ * and slaves since for slave we do not have encoder or plls
+ * so we dont need to disable those.
+ */
+ if (old_crtc_state->bigjoiner) {
+ intel_crtc_disable_planes(state,
+ old_crtc_state->bigjoiner_linked_crtc);
+ old_crtc_state->bigjoiner_linked_crtc->active = false;
+ }
+
/*
* We need to disable pipe CRC before disabling the pipe,
* or we race against vblank off.
@@ -15800,7 +15865,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
/* Only disable port sync and MST slaves */
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (!needs_modeset(new_crtc_state))
+ if (!needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner)
continue;
if (!old_crtc_state->hw.active)
@@ -15825,10 +15890,18 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!needs_modeset(new_crtc_state) ||
- (handled & BIT(crtc->pipe)))
+ (handled & BIT(crtc->pipe)) ||
+ old_crtc_state->bigjoiner_slave)
continue;
intel_pre_plane_update(state, crtc);
+ if (old_crtc_state->bigjoiner) {
+ struct intel_crtc *slave =
+ old_crtc_state->bigjoiner_linked_crtc;
+
+ intel_pre_plane_update(state, slave);
+ }
+
if (old_crtc_state->hw.active)
intel_old_crtc_state_disables(state, old_crtc_state,
new_crtc_state, crtc);
@@ -15926,7 +15999,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
continue;
if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
- is_trans_port_sync_master(new_crtc_state))
+ is_trans_port_sync_master(new_crtc_state) ||
+ (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave))
continue;
modeset_pipes &= ~BIT(pipe);
@@ -15936,7 +16010,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
/*
* Then we enable all remaining pipes that depend on other
- * pipes: MST slaves and port sync masters.
+ * pipes: MST slaves and port sync masters, big joiner master
*/
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
enum pipe pipe = crtc->pipe;
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [CI 06/15] drm/i915: HW state readout for Bigjoiner case
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (4 preceding siblings ...)
2020-11-17 19:47 ` [Intel-gfx] [CI 05/15] drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 07/15] drm/i915: Add crtcs affected by bigjoiner to the state Manasi Navare
` (13 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
Skip iterating over bigjoiner slaves, only the master has the state we
care about.
Add the width of the bigjoiner slave to the reconstructed fb.
Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
master.
And last, disable bigjoiner slave from primary if reconstruction fails.
v3:
* Fix the ddi_get_config slave error (Ankit Nautiyal)
v2:
* Unsupported bigjoiner config for initial fb (Ville)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
[vsyrjala:
* Don't do any hw->uapi state copy for bigjoiner slave
* We still have hw.mode so no need to pass it in
* Appease checkpatch]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 -
drivers/gpu/drm/i915/display/intel_ddi.c | 37 ++-
drivers/gpu/drm/i915/display/intel_display.c | 307 ++++++++++++------
.../drm/i915/display/intel_display_types.h | 1 +
4 files changed, 238 insertions(+), 109 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index e83364b5774f..a9439b415603 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1492,8 +1492,6 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- intel_dsc_get_config(pipe_config);
-
/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
pipe_config->port_clock = intel_dpll_get_freq(i915,
pipe_config->shared_dpll,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 81c4043ce42a..c580a1de150d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4577,20 +4577,14 @@ static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
crtc_state->sync_mode_slaves_mask);
}
-void intel_ddi_get_config(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
+static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
u32 temp, flags = 0;
- /* XXX: DSI transcoder paranoia */
- if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
- return;
-
- intel_dsc_get_config(pipe_config);
-
temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (temp & TRANS_DDI_PHSYNC)
flags |= DRM_MODE_FLAG_PHSYNC;
@@ -4684,6 +4678,30 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
default:
break;
}
+}
+
+void intel_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+
+ /* XXX: DSI transcoder paranoia */
+ if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
+ return;
+
+ if (pipe_config->bigjoiner_slave) {
+ /* read out pipe settings from master */
+ enum transcoder save = pipe_config->cpu_transcoder;
+
+ /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
+ WARN_ON(pipe_config->output_types);
+ pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
+ intel_ddi_read_func_ctl(encoder, pipe_config);
+ pipe_config->cpu_transcoder = save;
+ } else {
+ intel_ddi_read_func_ctl(encoder, pipe_config);
+ }
pipe_config->has_audio =
intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
@@ -4709,7 +4727,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
}
- intel_ddi_clock_get(encoder, pipe_config);
+ if (!pipe_config->bigjoiner_slave)
+ intel_ddi_clock_get(encoder, pipe_config);
if (IS_GEN9_LP(dev_priv))
pipe_config->lane_lat_optim_mask =
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e5a56904f33f..68c4f6cca82d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3631,6 +3631,8 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
struct intel_plane *intel_plane = to_intel_plane(primary);
struct intel_plane_state *intel_state =
to_intel_plane_state(plane_state);
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(intel_crtc->base.state);
struct drm_framebuffer *fb;
struct i915_vma *vma;
@@ -3653,7 +3655,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
if (c == &intel_crtc->base)
continue;
- if (!to_intel_crtc(c)->active)
+ if (!to_intel_crtc_state(c->state)->uapi.active)
continue;
state = to_intel_plane_state(c->primary->state);
@@ -3675,6 +3677,11 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
* pretend the BIOS never had it enabled.
*/
intel_plane_disable_noatomic(intel_crtc, intel_plane);
+ if (crtc_state->bigjoiner) {
+ struct intel_crtc *slave =
+ crtc_state->bigjoiner_linked_crtc;
+ intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
+ }
return;
@@ -8220,13 +8227,27 @@ static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state
drm_mode_copy(pipe_mode, adjusted_mode);
+ if (crtc_state->bigjoiner) {
+ /*
+ * transcoder is programmed to the full mode,
+ * but pipe timings are half of the transcoder mode
+ */
+ pipe_mode->crtc_hdisplay /= 2;
+ pipe_mode->crtc_hblank_start /= 2;
+ pipe_mode->crtc_hblank_end /= 2;
+ pipe_mode->crtc_hsync_start /= 2;
+ pipe_mode->crtc_hsync_end /= 2;
+ pipe_mode->crtc_htotal /= 2;
+ pipe_mode->crtc_clock /= 2;
+ }
+
intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
intel_mode_from_crtc_timings(adjusted_mode, adjusted_mode);
intel_crtc_compute_pixel_rate(crtc_state);
drm_mode_copy(mode, adjusted_mode);
- mode->hdisplay = crtc_state->pipe_src_w;
+ mode->hdisplay = crtc_state->pipe_src_w << crtc_state->bigjoiner;
mode->vdisplay = crtc_state->pipe_src_h;
}
@@ -10698,6 +10719,7 @@ static void
skl_get_initial_plane_config(struct intel_crtc *crtc,
struct intel_initial_plane_config *plane_config)
{
+ struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
@@ -10714,6 +10736,12 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
drm_WARN_ON(dev, pipe != crtc->pipe);
+ if (crtc_state->bigjoiner) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Unsupported bigjoiner configuration for initial FB\n");
+ return;
+ }
+
intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
if (!intel_fb) {
drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
@@ -11365,6 +11393,8 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
} else {
tmp = intel_de_read(dev_priv,
TRANS_DDI_FUNC_CTL(cpu_transcoder));
+ if (!(tmp & TRANS_DDI_FUNC_ENABLE))
+ return;
if (INTEL_GEN(dev_priv) >= 12)
port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
else
@@ -11433,10 +11463,19 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
active = true;
}
- if (!active)
- goto out;
+ intel_dsc_get_config(pipe_config);
+
+ if (!active) {
+ /* bigjoiner slave doesn't enable transcoder */
+ if (!pipe_config->bigjoiner_slave)
+ goto out;
- if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
+ active = true;
+ pipe_config->pixel_multiplier = 1;
+
+ /* we cannot read out most state, so don't bother.. */
+ pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
+ } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
INTEL_GEN(dev_priv) >= 11) {
hsw_get_ddi_port_state(crtc, pipe_config);
intel_get_transcoder_timings(crtc, pipe_config);
@@ -11511,7 +11550,10 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
}
}
- if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
+ if (pipe_config->bigjoiner_slave) {
+ /* Cannot be read out as a slave, set to 0. */
+ pipe_config->pixel_multiplier = 0;
+ } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
pipe_config->pixel_multiplier =
intel_de_read(dev_priv,
@@ -13555,6 +13597,9 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
{
+ if (crtc_state->bigjoiner_slave)
+ return;
+
crtc_state->uapi.enable = crtc_state->hw.enable;
crtc_state->uapi.active = crtc_state->hw.active;
drm_WARN_ON(crtc_state->uapi.crtc->dev,
@@ -14196,35 +14241,53 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(output_types);
- PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
- PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
- PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
- PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
- PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
- PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
-
- PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
- PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
- PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
- PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
- PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
- PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
-
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
-
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
-
- PIPE_CONF_CHECK_I(pixel_multiplier);
+ /* FIXME do the readout properly and get rid of this quirk */
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
+
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
+ PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
+
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
+
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
+
+ PIPE_CONF_CHECK_I(pixel_multiplier);
+
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+ DRM_MODE_FLAG_INTERLACE);
+
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+ DRM_MODE_FLAG_PHSYNC);
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+ DRM_MODE_FLAG_NHSYNC);
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+ DRM_MODE_FLAG_PVSYNC);
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+ DRM_MODE_FLAG_NVSYNC);
+ }
+ }
+
PIPE_CONF_CHECK_I(output_format);
PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
@@ -14234,24 +14297,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
PIPE_CONF_CHECK_BOOL(has_infoframe);
- PIPE_CONF_CHECK_BOOL(fec_enable);
+ /* FIXME do the readout properly and get rid of this quirk */
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
+ PIPE_CONF_CHECK_BOOL(fec_enable);
PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_INTERLACE);
-
- if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_PHSYNC);
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_NHSYNC);
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_PVSYNC);
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_NVSYNC);
- }
-
PIPE_CONF_CHECK_X(gmch_pfit.control);
/* pfit ratios are autocomputed by the hw on gen4+ */
if (INTEL_GEN(dev_priv) < 4)
@@ -14277,7 +14328,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
}
PIPE_CONF_CHECK_I(scaler_state.scaler_id);
- PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
+ /* FIXME do the readout properly and get rid of this quirk */
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
+ PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
PIPE_CONF_CHECK_X(gamma_mode);
if (IS_CHERRYVIEW(dev_priv))
@@ -14298,49 +14351,53 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(double_wide);
PIPE_CONF_CHECK_P(shared_dpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
- PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
- PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
- PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.spll);
- PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
- PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
- PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
- PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
-
- PIPE_CONF_CHECK_X(dsi_pll.ctrl);
- PIPE_CONF_CHECK_X(dsi_pll.div);
-
- if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
- PIPE_CONF_CHECK_I(pipe_bpp);
-
- PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
- PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
- PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
-
- PIPE_CONF_CHECK_I(min_voltage_level);
+
+ /* FIXME do the readout properly and get rid of this quirk */
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
+ PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
+ PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
+ PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
+ PIPE_CONF_CHECK_X(dpll_hw_state.spll);
+ PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
+ PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
+
+ PIPE_CONF_CHECK_X(dsi_pll.ctrl);
+ PIPE_CONF_CHECK_X(dsi_pll.div);
+
+ if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
+ PIPE_CONF_CHECK_I(pipe_bpp);
+
+ PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
+
+ PIPE_CONF_CHECK_I(min_voltage_level);
+ }
PIPE_CONF_CHECK_X(infoframes.enable);
PIPE_CONF_CHECK_X(infoframes.gcp);
@@ -14352,6 +14409,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
+ PIPE_CONF_CHECK_BOOL(bigjoiner);
+ PIPE_CONF_CHECK_BOOL(bigjoiner_slave);
+ PIPE_CONF_CHECK_P(bigjoiner_linked_crtc);
PIPE_CONF_CHECK_I(dsc.compression_enable);
PIPE_CONF_CHECK_I(dsc.dsc_split);
@@ -14623,6 +14683,7 @@ verify_crtc_state(struct intel_crtc *crtc,
struct intel_encoder *encoder;
struct intel_crtc_state *pipe_config = old_crtc_state;
struct drm_atomic_state *state = old_crtc_state->uapi.state;
+ struct intel_crtc *master = crtc;
__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
intel_crtc_free_hw_state(old_crtc_state);
@@ -14650,7 +14711,10 @@ verify_crtc_state(struct intel_crtc *crtc,
"(expected %i, found %i)\n",
new_crtc_state->hw.active, crtc->active);
- for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
+ if (new_crtc_state->bigjoiner_slave)
+ master = new_crtc_state->bigjoiner_linked_crtc;
+
+ for_each_encoder_on_crtc(dev, &master->base, encoder) {
enum pipe pipe;
bool active;
@@ -14660,7 +14724,7 @@ verify_crtc_state(struct intel_crtc *crtc,
encoder->base.base.id, active,
new_crtc_state->hw.active);
- I915_STATE_WARN(active && crtc->pipe != pipe,
+ I915_STATE_WARN(active && master->pipe != pipe,
"Encoder connected to wrong pipe %c\n",
pipe_name(pipe));
@@ -18566,7 +18630,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
for_each_intel_crtc(dev, crtc) {
struct intel_initial_plane_config plane_config = {};
- if (!crtc->active)
+ if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
continue;
/*
@@ -18877,7 +18941,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
/* Adjust the state of the output pipe according to whether we
* have active connectors/encoders. */
- if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
+ if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
+ !crtc_state->bigjoiner_slave)
intel_crtc_disable_noatomic(crtc, ctx);
if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
@@ -19092,6 +19157,16 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
intel_encoder_get_config(encoder, crtc_state);
if (encoder->sync_state)
encoder->sync_state(encoder, crtc_state);
+
+ /* read out to slave crtc as well for bigjoiner */
+ if (crtc_state->bigjoiner) {
+ /* encoder should read be linked to bigjoiner master */
+ WARN_ON(crtc_state->bigjoiner_slave);
+
+ crtc = crtc_state->bigjoiner_linked_crtc;
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+ intel_encoder_get_config(encoder, crtc_state);
+ }
} else {
encoder->base.crtc = NULL;
}
@@ -19147,6 +19222,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
struct intel_plane *plane;
int min_cdclk = 0;
+ if (crtc_state->bigjoiner_slave)
+ continue;
+
if (crtc_state->hw.active) {
/*
* The initial mode needs to be set in order to keep
@@ -19207,6 +19285,39 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
intel_bw_crtc_update(bw_state, crtc_state);
intel_pipe_config_sanity_check(dev_priv, crtc_state);
+
+ /* discard our incomplete slave state, copy it from master */
+ if (crtc_state->bigjoiner && crtc_state->hw.active) {
+ struct intel_crtc *slave = crtc_state->bigjoiner_linked_crtc;
+ struct intel_crtc_state *slave_crtc_state =
+ to_intel_crtc_state(slave->base.state);
+
+ copy_bigjoiner_crtc_state(slave_crtc_state, crtc_state);
+ slave->base.mode = crtc->base.mode;
+
+ cdclk_state->min_cdclk[slave->pipe] = min_cdclk;
+ cdclk_state->min_voltage_level[slave->pipe] =
+ crtc_state->min_voltage_level;
+
+ for_each_intel_plane_on_crtc(&dev_priv->drm, slave, plane) {
+ const struct intel_plane_state *plane_state =
+ to_intel_plane_state(plane->base.state);
+
+ /*
+ * FIXME don't have the fb yet, so can't
+ * use intel_plane_data_rate() :(
+ */
+ if (plane_state->uapi.visible)
+ crtc_state->data_rate[plane->id] =
+ 4 * crtc_state->pixel_rate;
+ else
+ crtc_state->data_rate[plane->id] = 0;
+ }
+
+ intel_bw_crtc_update(bw_state, slave_crtc_state);
+ drm_calc_timestamping_constants(&slave->base,
+ &slave_crtc_state->hw.adjusted_mode);
+ }
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b3d94e6cd7c5..ce82d654d0f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -850,6 +850,7 @@ struct intel_crtc_state {
* accordingly.
*/
#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
+#define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */
unsigned long quirks;
unsigned fb_bits; /* framebuffers to flip */
--
2.19.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [CI 07/15] drm/i915: Add crtcs affected by bigjoiner to the state
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (5 preceding siblings ...)
2020-11-17 19:47 ` [Intel-gfx] [CI 06/15] drm/i915: HW state readout for Bigjoiner case Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 08/15] drm/i915: Add planes " Manasi Navare
` (12 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make sure both crtcs participating in the bigjoiner stuff
are in the state.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 25 ++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 68c4f6cca82d..0784495e2310 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15461,6 +15461,27 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
return 0;
}
+static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
+{
+ const struct intel_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ struct intel_crtc_state *linked_crtc_state;
+
+ if (!crtc_state->bigjoiner)
+ continue;
+
+ linked_crtc_state = intel_atomic_get_crtc_state(&state->base,
+ crtc_state->bigjoiner_linked_crtc);
+ if (IS_ERR(linked_crtc_state))
+ return PTR_ERR(linked_crtc_state);
+ }
+
+ return 0;
+}
+
/**
* intel_atomic_check - validate state object
* @dev: drm device
@@ -15486,6 +15507,10 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
+ ret = intel_bigjoiner_add_affected_crtcs(state);
+ if (ret)
+ goto fail;
+
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!needs_modeset(new_crtc_state)) {
--
2.19.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [CI 08/15] drm/i915: Add planes affected by bigjoiner to the state
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (6 preceding siblings ...)
2020-11-17 19:47 ` [Intel-gfx] [CI 07/15] drm/i915: Add crtcs affected by bigjoiner to the state Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 09/15] drm/i915: Get the uapi state from the correct plane when bigjoiner is used Manasi Navare
` (11 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make sure both the bigjoiner "master" and "slave" plane are
in the state whenever either of them is in the state.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 42 ++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0784495e2310..78f89ecdda79 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15108,6 +15108,44 @@ static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
}
+static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_crtc *other)
+{
+ const struct intel_plane_state *plane_state;
+ struct intel_plane *plane;
+ u8 plane_ids = 0;
+ int i;
+
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ if (plane->pipe == crtc->pipe)
+ plane_ids |= BIT(plane->id);
+ }
+
+ return intel_crtc_add_planes_to_state(state, other, plane_ids);
+}
+
+static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
+{
+ const struct intel_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ int ret;
+
+ if (!crtc_state->bigjoiner)
+ continue;
+
+ ret = intel_crtc_add_bigjoiner_planes(state, crtc,
+ crtc_state->bigjoiner_linked_crtc);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int intel_atomic_check_planes(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -15121,6 +15159,10 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state)
if (ret)
return ret;
+ ret = intel_bigjoiner_add_affected_planes(state);
+ if (ret)
+ return ret;
+
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
ret = intel_plane_atomic_check(state, plane);
if (ret) {
--
2.19.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [CI 09/15] drm/i915: Get the uapi state from the correct plane when bigjoiner is used
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (7 preceding siblings ...)
2020-11-17 19:47 ` [Intel-gfx] [CI 08/15] drm/i915: Add planes " Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 10/15] drm/i915: Add bigjoiner aware plane clipping checks Manasi Navare
` (10 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
When using bigjoiner userspace is only controlling the "master"
plane, so use its uapi state for the "slave" plane as well.
hw.crtc needs a bit of magic since we don't want to copy that from
the uapi state (as it points to the wrong pipe for the "slave
" plane). Instead we pass the right crtc in explicitly but only
assign it when the uapi state indicates the plane to be logically
enabled (ie. uapi.crtc != NULL).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 59 +++++++++++++------
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
3 files changed, 46 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index f47558efb3c2..7abb0e3d6c0b 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -247,11 +247,19 @@ static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
}
void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
- const struct intel_plane_state *from_plane_state)
+ const struct intel_plane_state *from_plane_state,
+ struct intel_crtc *crtc)
{
intel_plane_clear_hw_state(plane_state);
- plane_state->hw.crtc = from_plane_state->uapi.crtc;
+ /*
+ * For the bigjoiner slave uapi.crtc will point at
+ * the master crtc. So we explicitly assign the right
+ * slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates
+ * the plane is logically enabled on the uapi level.
+ */
+ plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;
+
plane_state->hw.fb = from_plane_state->uapi.fb;
if (plane_state->hw.fb)
drm_framebuffer_get(plane_state->hw.fb);
@@ -331,15 +339,16 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
old_plane_state, new_plane_state);
}
-static struct intel_crtc *
-get_crtc_from_states(const struct intel_plane_state *old_plane_state,
- const struct intel_plane_state *new_plane_state)
+static struct intel_plane *
+intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
{
- if (new_plane_state->uapi.crtc)
- return to_intel_crtc(new_plane_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_plane *plane;
- if (old_plane_state->uapi.crtc)
- return to_intel_crtc(old_plane_state->uapi.crtc);
+ for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
+ if (plane->id == plane_id)
+ return plane;
+ }
return NULL;
}
@@ -347,23 +356,37 @@ get_crtc_from_states(const struct intel_plane_state *old_plane_state,
int intel_plane_atomic_check(struct intel_atomic_state *state,
struct intel_plane *plane)
{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
const struct intel_plane_state *old_plane_state =
intel_atomic_get_old_plane_state(state, plane);
- struct intel_crtc *crtc =
- get_crtc_from_states(old_plane_state, new_plane_state);
- const struct intel_crtc_state *old_crtc_state;
- struct intel_crtc_state *new_crtc_state;
+ const struct intel_plane_state *new_master_plane_state;
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, plane->pipe);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
+ struct intel_plane *master_plane =
+ intel_crtc_get_plane(new_crtc_state->bigjoiner_linked_crtc,
+ plane->id);
+
+ new_master_plane_state =
+ intel_atomic_get_new_plane_state(state, master_plane);
+ } else {
+ new_master_plane_state = new_plane_state;
+ }
+
+ intel_plane_copy_uapi_to_hw_state(new_plane_state,
+ new_master_plane_state,
+ crtc);
- intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
new_plane_state->uapi.visible = false;
- if (!crtc)
+ if (!new_crtc_state)
return 0;
- old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
- new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
-
return intel_plane_atomic_check_with_state(old_crtc_state,
new_crtc_state,
old_plane_state,
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 24a3a148aa62..5cae9db41062 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -24,7 +24,8 @@ unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
- const struct intel_plane_state *from_plane_state);
+ const struct intel_plane_state *from_plane_state,
+ struct intel_crtc *crtc);
void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
const struct intel_plane_state *from_plane_state);
void intel_update_plane(struct intel_plane *plane,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 78f89ecdda79..e1ed65127647 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3718,7 +3718,8 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
drm_framebuffer_get(fb);
plane_state->crtc = &intel_crtc->base;
- intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
+ intel_plane_copy_uapi_to_hw_state(intel_state, intel_state,
+ intel_crtc);
intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
@@ -16981,7 +16982,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
new_plane_state->uapi.crtc_w = crtc_w;
new_plane_state->uapi.crtc_h = crtc_h;
- intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
+ intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc);
ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
old_plane_state, new_plane_state);
--
2.19.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [CI 10/15] drm/i915: Add bigjoiner aware plane clipping checks
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (8 preceding siblings ...)
2020-11-17 19:47 ` [Intel-gfx] [CI 09/15] drm/i915: Get the uapi state from the correct plane when bigjoiner is used Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 11/15] drm/i915: Add debugfs dumping for bigjoiner, v3 Manasi Navare
` (9 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
We need to look at hw.fb for the framebuffer, and add the translation
for the slave_plane_state. With these changes we set the correct
rectangle on the bigjoiner slave, and don't set incorrect
src/dst/visibility on the slave plane.
v2:
* Manual rebase (Manasi)
v3:
* hw.rotation instead of uapi.rotation (Ville)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 60 +++++++++++++++++++
.../gpu/drm/i915/display/intel_atomic_plane.h | 4 ++
drivers/gpu/drm/i915/display/intel_display.c | 19 +++---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 +++----
4 files changed, 80 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 7abb0e3d6c0b..7e9f84b00859 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -271,6 +271,9 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
plane_state->hw.color_range = from_plane_state->uapi.color_range;
plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
+
+ plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
+ plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
}
void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
@@ -514,6 +517,63 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
}
}
+int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
+ struct intel_crtc_state *crtc_state,
+ int min_scale, int max_scale,
+ bool can_position)
+{
+ struct drm_framebuffer *fb = plane_state->hw.fb;
+ struct drm_rect *src = &plane_state->uapi.src;
+ struct drm_rect *dst = &plane_state->uapi.dst;
+ unsigned int rotation = plane_state->hw.rotation;
+ struct drm_rect clip = {};
+ int hscale, vscale;
+
+ if (!fb) {
+ plane_state->uapi.visible = false;
+ return 0;
+ }
+
+ drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
+
+ /* Check scaling */
+ hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
+ vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
+ if (hscale < 0 || vscale < 0) {
+ DRM_DEBUG_KMS("Invalid scaling of plane\n");
+ drm_rect_debug_print("src: ", src, true);
+ drm_rect_debug_print("dst: ", dst, false);
+ return -ERANGE;
+ }
+
+ if (crtc_state->hw.enable) {
+ clip.x2 = crtc_state->pipe_src_w;
+ clip.y2 = crtc_state->pipe_src_h;
+ }
+
+ /* right side of the image is on the slave crtc, adjust dst to match */
+ if (crtc_state->bigjoiner_slave)
+ drm_rect_translate(dst, -crtc_state->pipe_src_w, 0);
+
+ /*
+ * FIXME: This might need further adjustment for seamless scaling
+ * with phase information, for the 2p2 and 2p1 scenarios.
+ */
+ plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, &clip);
+
+ drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
+
+ if (!can_position && plane_state->uapi.visible &&
+ !drm_rect_equals(dst, &clip)) {
+ DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
+ drm_rect_debug_print("dst: ", dst, false);
+ drm_rect_debug_print("clip: ", &clip, false);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
.prepare_fb = intel_prepare_plane_fb,
.cleanup_fb = intel_cleanup_plane_fb,
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 5cae9db41062..5c78a087ed86 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -55,6 +55,10 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
struct intel_plane *plane,
bool *need_cdclk_calc);
+int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
+ struct intel_crtc_state *crtc_state,
+ int min_scale, int max_scale,
+ bool can_position);
void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e1ed65127647..22224b8c4998 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4315,12 +4315,10 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
- i9xx_plane_has_windowing(plane),
- true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_HELPER_NO_SCALING,
+ i9xx_plane_has_windowing(plane));
if (ret)
return ret;
@@ -11698,11 +11696,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
return -EINVAL;
}
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
- true, true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_HELPER_NO_SCALING,
+ true);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index a3ab44694118..019a2d6d807a 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2187,10 +2187,8 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
}
}
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- min_scale, max_scale,
- true, true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ min_scale, max_scale, true);
if (ret)
return ret;
@@ -2245,11 +2243,10 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
- true, true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_HELPER_NO_SCALING,
+ true);
if (ret)
return ret;
@@ -2456,10 +2453,8 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
max_scale = skl_plane_max_scale(dev_priv, fb);
}
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- min_scale, max_scale,
- true, true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ min_scale, max_scale, true);
if (ret)
return ret;
--
2.19.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [CI 11/15] drm/i915: Add debugfs dumping for bigjoiner, v3.
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (9 preceding siblings ...)
2020-11-17 19:47 ` [Intel-gfx] [CI 10/15] drm/i915: Add bigjoiner aware plane clipping checks Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 12/15] drm/i915: Disable legacy cursor fastpath for bigjoiner Manasi Navare
` (8 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Dump debugfs and planar links as well, this will make it easier to debug
when things go wrong.
v4:
* Rebase
Changes since v1:
- Report planar slaves as such, now that we have the plane_state switch.
Changes since v2:
- Rebase on top of the new plane format dumping
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 25 ++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 00b79593bcef..ca41e8c00ad7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -755,6 +755,17 @@ static void plane_rotation(char *buf, size_t bufsize, unsigned int rotation)
rotation);
}
+static const char *plane_visibility(const struct intel_plane_state *plane_state)
+{
+ if (plane_state->uapi.visible)
+ return "visible";
+
+ if (plane_state->planar_slave)
+ return "planar-slave";
+
+ return "hidden";
+}
+
static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane)
{
const struct intel_plane_state *plane_state =
@@ -773,13 +784,19 @@ static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane)
plane_rotation(rot_str, sizeof(rot_str),
plane_state->uapi.rotation);
- seq_printf(m, "\t\tuapi: [FB:%d] %s,0x%llx,%dx%d, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n",
+ seq_printf(m, "\t\tuapi: [FB:%d] %s,0x%llx,%dx%d, visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n",
fb ? fb->base.id : 0, fb ? format_name.str : "n/a",
fb ? fb->modifier : 0,
fb ? fb->width : 0, fb ? fb->height : 0,
+ plane_visibility(plane_state),
DRM_RECT_FP_ARG(&src),
DRM_RECT_ARG(&dst),
rot_str);
+
+ if (plane_state->planar_linked_plane)
+ seq_printf(m, "\t\tplanar: Linked to [PLANE:%d:%s] as a %s\n",
+ plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name,
+ plane_state->planar_slave ? "slave" : "master");
}
static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane)
@@ -875,6 +892,12 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
intel_scaler_info(m, crtc);
}
+ if (crtc_state->bigjoiner)
+ seq_printf(m, "\tLinked to [CRTC:%d:%s] as a %s\n",
+ crtc_state->bigjoiner_linked_crtc->base.base.id,
+ crtc_state->bigjoiner_linked_crtc->base.name,
+ crtc_state->bigjoiner_slave ? "slave" : "master");
+
for_each_intel_encoder_mask(&dev_priv->drm, encoder,
crtc_state->uapi.encoder_mask)
intel_encoder_info(m, crtc, encoder);
--
2.19.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [CI 12/15] drm/i915: Disable legacy cursor fastpath for bigjoiner
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (10 preceding siblings ...)
2020-11-17 19:47 ` [Intel-gfx] [CI 11/15] drm/i915: Add debugfs dumping for bigjoiner, v3 Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 13/15] drm/i915: Fix cursor src/dst rectangle with bigjoiner Manasi Navare
` (7 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The legacy cursor fastpath code doesn't deal with bigjoiner.
Disable the fastpath for now.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 22224b8c4998..4d11d5b0606b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16931,9 +16931,11 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
/*
* When crtc is inactive or there is a modeset pending,
* wait for it to complete in the slowpath
+ *
+ * FIXME bigjoiner fastpath would be good
*/
if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
- crtc_state->update_pipe)
+ crtc_state->update_pipe || crtc_state->bigjoiner)
goto slow;
/*
--
2.19.1
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^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [CI 13/15] drm/i915: Fix cursor src/dst rectangle with bigjoiner
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (11 preceding siblings ...)
2020-11-17 19:47 ` [Intel-gfx] [CI 12/15] drm/i915: Disable legacy cursor fastpath for bigjoiner Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 14/15] drm/i915: Add bigjoiner state dump Manasi Navare
` (6 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We can't call drm_plane_state_src() this late for the slave plane since
it would consult the wrong uapi state. We've alreayd done the correct
uapi->hw copy earlier, so let's just preserve the unclipped src/dst
rects using a temp copy across the intel_atomic_plane_check_clipping()
call.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4d11d5b0606b..acd64e788a36 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11689,6 +11689,8 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
{
const struct drm_framebuffer *fb = plane_state->hw.fb;
struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_rect src = plane_state->uapi.src;
+ const struct drm_rect dst = plane_state->uapi.dst;
int ret;
if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
@@ -11704,8 +11706,8 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
return ret;
/* Use the unclipped src/dst rectangles, which we program to hw */
- plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
- plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
+ plane_state->uapi.src = src;
+ plane_state->uapi.dst = dst;
ret = intel_cursor_check_surface(plane_state);
if (ret)
--
2.19.1
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^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [CI 14/15] drm/i915: Add bigjoiner state dump
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (12 preceding siblings ...)
2020-11-17 19:47 ` [Intel-gfx] [CI 13/15] drm/i915: Fix cursor src/dst rectangle with bigjoiner Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-17 19:47 ` [Intel-gfx] [CI 15/15] drm/i915: Enable bigjoiner Manasi Navare
` (5 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a big of bigjoiner information to the state dump.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index acd64e788a36..5c07c74d4397 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13384,6 +13384,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
transcoder_name(pipe_config->master_transcoder),
pipe_config->sync_mode_slaves_mask);
+ drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s\n",
+ pipe_config->bigjoiner_slave ? "slave" :
+ pipe_config->bigjoiner ? "master" : "no");
+
if (pipe_config->has_pch_encoder)
intel_dump_m_n_config(pipe_config, "fdi",
pipe_config->fdi_lanes,
--
2.19.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] [CI 15/15] drm/i915: Enable bigjoiner
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (13 preceding siblings ...)
2020-11-17 19:47 ` [Intel-gfx] [CI 14/15] drm/i915: Add bigjoiner state dump Manasi Navare
@ 2020-11-17 19:47 ` Manasi Navare
2020-11-18 2:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Rebased remaining big joiner series Patchwork
` (4 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Manasi Navare @ 2020-11-17 19:47 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Enough plumbing should be in place to throw the bigjoiner switch.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 857f39779654..3896d08c4177 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -260,9 +260,6 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
struct intel_encoder *encoder = &intel_dig_port->base;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- /* FIXME remove once everything is in place */
- return false;
-
return INTEL_GEN(dev_priv) >= 12 ||
(INTEL_GEN(dev_priv) == 11 &&
encoder->port != PORT_A);
--
2.19.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 26+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Rebased remaining big joiner series
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (14 preceding siblings ...)
2020-11-17 19:47 ` [Intel-gfx] [CI 15/15] drm/i915: Enable bigjoiner Manasi Navare
@ 2020-11-18 2:02 ` Patchwork
2020-11-18 2:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-11-18 2:02 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: Rebased remaining big joiner series
URL : https://patchwork.freedesktop.org/series/83990/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d8255ae03ad0 drm/i915: Copy the plane hw state directly for Y planes
385ac914e475 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
f5d68c7c35ae drm/i915: Try to make bigjoiner work in atomic check
-:79: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#79: FILE: drivers/gpu/drm/i915/display/intel_display.c:13481:
+ crtc_state->bigjoiner_linked_crtc);
-:125: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#125: FILE: drivers/gpu/drm/i915/display/intel_display.c:13555:
+ crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
-:169: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#169: FILE: drivers/gpu/drm/i915/display/intel_display.c:15174:
+ slave = new_crtc_state->bigjoiner_linked_crtc =
-:203: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#203: FILE: drivers/gpu/drm/i915/display/intel_display.c:15208:
+ slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
-:204: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#204: FILE: drivers/gpu/drm/i915/display/intel_display.c:15209:
+ slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
-:205: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#205: FILE: drivers/gpu/drm/i915/display/intel_display.c:15210:
+ slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
-:205: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#205: FILE: drivers/gpu/drm/i915/display/intel_display.c:15210:
+ slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
total: 0 errors, 2 warnings, 5 checks, 266 lines checked
2352c92d6e9d drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave
8bd4ba682f50 drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner
cf90185fc58a drm/i915: HW state readout for Bigjoiner case
-:92: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns
#92: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4697:
+ /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
-:94: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#94: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4699:
+ pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
-:121: WARNING:TABSTOP: Statements should start on a tabstop
#121: FILE: drivers/gpu/drm/i915/display/intel_display.c:3634:
+ struct intel_crtc_state *crtc_state =
-:603: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#603: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:853:
+#define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */
^
total: 0 errors, 3 warnings, 1 checks, 531 lines checked
0482905e2737 drm/i915: Add crtcs affected by bigjoiner to the state
827d41a94f1c drm/i915: Add planes affected by bigjoiner to the state
12a124f7192b drm/i915: Get the uapi state from the correct plane when bigjoiner is used
5cab172f2ad0 drm/i915: Add bigjoiner aware plane clipping checks
58ce13d4bfd2 drm/i915: Add debugfs dumping for bigjoiner, v3.
-:47: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#47: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:787:
+ seq_printf(m, "\t\tuapi: [FB:%d] %s,0x%llx,%dx%d, visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n",
-:58: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#58: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:798:
+ plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name,
total: 0 errors, 2 warnings, 0 checks, 49 lines checked
7076c6782390 drm/i915: Disable legacy cursor fastpath for bigjoiner
40d4ac57744a drm/i915: Fix cursor src/dst rectangle with bigjoiner
1f7c0f835d55 drm/i915: Add bigjoiner state dump
e3f81d0a69ee drm/i915: Enable bigjoiner
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Rebased remaining big joiner series
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (15 preceding siblings ...)
2020-11-18 2:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Rebased remaining big joiner series Patchwork
@ 2020-11-18 2:03 ` Patchwork
2020-11-18 2:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-11-18 2:03 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: Rebased remaining big joiner series
URL : https://patchwork.freedesktop.org/series/83990/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
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^ permalink raw reply [flat|nested] 26+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Rebased remaining big joiner series
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (16 preceding siblings ...)
2020-11-18 2:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-11-18 2:31 ` Patchwork
2020-11-18 10:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-11-18 19:49 ` [Intel-gfx] [CI 00/15] " Navare, Manasi
19 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-11-18 2:31 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 7509 bytes --]
== Series Details ==
Series: Rebased remaining big joiner series
URL : https://patchwork.freedesktop.org/series/83990/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9350 -> Patchwork_18928
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/index.html
New tests
---------
New tests have been introduced between CI_DRM_9350 and Patchwork_18928:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18928 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0:
- fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([i915#1635])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-bxt-dsi/igt@gem_exec_suspend@basic-s0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/fi-bxt-dsi/igt@gem_exec_suspend@basic-s0.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_busy@basic@modeset:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-tgl-y/igt@kms_busy@basic@modeset.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/fi-tgl-y/igt@kms_busy@basic@modeset.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
* igt@prime_vgem@basic-write:
- fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-tgl-y/igt@prime_vgem@basic-write.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/fi-tgl-y/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_busy@basic@flip:
- {fi-kbl-7560u}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-kbl-7560u/igt@kms_busy@basic@flip.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/fi-kbl-7560u/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-apl-guc: [DMESG-WARN][17] ([i915#1635] / [i915#1982]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-apl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/fi-apl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-tgl-y: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
* igt@vgem_basic@setversion:
- fi-tgl-y: [DMESG-WARN][23] ([i915#402]) -> [PASS][24] +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-tgl-y/igt@vgem_basic@setversion.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/fi-tgl-y/igt@vgem_basic@setversion.html
#### Warnings ####
* igt@i915_pm_rpm@basic-rte:
- fi-tgl-y: [DMESG-WARN][25] ([i915#2411]) -> [DMESG-WARN][26] ([i915#1982] / [i915#2411])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/fi-tgl-y/igt@i915_pm_rpm@basic-rte.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/fi-tgl-y/igt@i915_pm_rpm@basic-rte.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
Participating hosts (45 -> 40)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-glk-dsi fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9350 -> Patchwork_18928
CI-20190529: 20190529
CI_DRM_9350: 3161d1b26b7e1a7cb9146e3f8bd613f901ff5b38 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5855: d9b3c7058efe41e5224dd1e43fac05dc6d049380 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18928: e3f81d0a69ee4cdf786f4350951497399cc4ca39 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e3f81d0a69ee drm/i915: Enable bigjoiner
1f7c0f835d55 drm/i915: Add bigjoiner state dump
40d4ac57744a drm/i915: Fix cursor src/dst rectangle with bigjoiner
7076c6782390 drm/i915: Disable legacy cursor fastpath for bigjoiner
58ce13d4bfd2 drm/i915: Add debugfs dumping for bigjoiner, v3.
5cab172f2ad0 drm/i915: Add bigjoiner aware plane clipping checks
12a124f7192b drm/i915: Get the uapi state from the correct plane when bigjoiner is used
827d41a94f1c drm/i915: Add planes affected by bigjoiner to the state
0482905e2737 drm/i915: Add crtcs affected by bigjoiner to the state
cf90185fc58a drm/i915: HW state readout for Bigjoiner case
8bd4ba682f50 drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner
2352c92d6e9d drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave
f5d68c7c35ae drm/i915: Try to make bigjoiner work in atomic check
385ac914e475 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
d8255ae03ad0 drm/i915: Copy the plane hw state directly for Y planes
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/index.html
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_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 26+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Rebased remaining big joiner series
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (17 preceding siblings ...)
2020-11-18 2:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-11-18 10:06 ` Patchwork
2020-11-18 19:49 ` [Intel-gfx] [CI 00/15] " Navare, Manasi
19 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-11-18 10:06 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
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== Series Details ==
Series: Rebased remaining big joiner series
URL : https://patchwork.freedesktop.org/series/83990/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9350_full -> Patchwork_18928_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18928_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18928_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18928_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_caching@read-writes:
- shard-snb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-snb4/igt@gem_caching@read-writes.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-snb4/igt@gem_caching@read-writes.html
* igt@gem_cs_tlb@engines@vecs0:
- shard-glk: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk4/igt@gem_cs_tlb@engines@vecs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-glk2/igt@gem_cs_tlb@engines@vecs0.html
New tests
---------
New tests have been introduced between CI_DRM_9350_full and Patchwork_18928_full:
### New CI tests (1) ###
* boot:
- Statuses : 199 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18928_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- shard-hsw: [PASS][5] -> [FAIL][6] ([i915#1888])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw2/igt@gem_exec_suspend@basic-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-hsw2/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_whisper@basic-contexts-forked:
- shard-hsw: [PASS][7] -> [TIMEOUT][8] ([i915#2502])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw2/igt@gem_exec_whisper@basic-contexts-forked.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-hsw2/igt@gem_exec_whisper@basic-contexts-forked.html
* igt@gem_exec_whisper@basic-normal-all:
- shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118] / [i915#95])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk7/igt@gem_exec_whisper@basic-normal-all.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-glk3/igt@gem_exec_whisper@basic-normal-all.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +7 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl5/igt@i915_module_load@reload-with-fault-injection.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-skl10/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982] / [i915#2295])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl7/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-skl2/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-tglb: [PASS][17] -> [FAIL][18] ([i915#2346])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-tglb7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][19] -> [FAIL][20] ([i915#2122])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk1/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ac-hdmi-a1-hdmi-a2.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-glk8/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][21] -> [FAIL][22] ([i915#79]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-kbl1/igt@kms_flip@flip-vs-suspend@b-dp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-kbl7/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#1635] / [i915#1982]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-apl8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-apl4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
- shard-iclb: [PASS][27] -> [DMESG-WARN][28] ([i915#1982])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
- shard-glk: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-glk5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
- shard-tglb: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) +6 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-skl: [PASS][35] -> [FAIL][36] ([i915#49])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][37] -> [FAIL][38] ([i915#1188]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-skl5/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-skl: [PASS][39] -> [FAIL][40] ([i915#247])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl9/igt@kms_plane@plane-position-covered-pipe-b-planes.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-skl5/igt@kms_plane@plane-position-covered-pipe-b-planes.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][41] -> [SKIP][42] ([fdo#109441])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
* igt@perf@polling-parameterized:
- shard-glk: [PASS][43] -> [FAIL][44] ([i915#1542])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk6/igt@perf@polling-parameterized.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-glk4/igt@perf@polling-parameterized.html
#### Possible fixes ####
* igt@gem_eio@kms:
- shard-hsw: [INCOMPLETE][45] ([i915#1888] / [i915#2244]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw2/igt@gem_eio@kms.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-hsw2/igt@gem_eio@kms.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-glk: [FAIL][47] ([i915#2389]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk3/igt@gem_exec_reloc@basic-many-active@rcs0.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-glk2/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-glk: [FAIL][49] -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk6/igt@gem_exec_suspend@basic-s3.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-glk7/igt@gem_exec_suspend@basic-s3.html
- shard-kbl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-kbl2/igt@gem_exec_suspend@basic-s3.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-kbl1/igt@gem_exec_suspend@basic-s3.html
* igt@i915_module_load@reload:
- shard-iclb: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-iclb2/igt@i915_module_load@reload.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-iclb6/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@i2c:
- shard-skl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl9/igt@i915_pm_rpm@i2c.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-skl5/igt@i915_pm_rpm@i2c.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-0:
- shard-kbl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-kbl1/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-kbl6/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
- shard-skl: [FAIL][59] ([i915#54]) -> [PASS][60] +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
* igt@kms_cursor_edge_walk@pipe-a-128x128-left-edge:
- shard-glk: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk3/igt@kms_cursor_edge_walk@pipe-a-128x128-left-edge.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-glk2/igt@kms_cursor_edge_walk@pipe-a-128x128-left-edge.html
- shard-hsw: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw8/igt@kms_cursor_edge_walk@pipe-a-128x128-left-edge.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-hsw6/igt@kms_cursor_edge_walk@pipe-a-128x128-left-edge.html
* igt@kms_cursor_edge_walk@pipe-b-64x64-top-edge:
- shard-apl: [DMESG-WARN][65] ([i915#1635] / [i915#1982]) -> [PASS][66] +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-apl7/igt@kms_cursor_edge_walk@pipe-b-64x64-top-edge.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-apl3/igt@kms_cursor_edge_walk@pipe-b-64x64-top-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][67] ([i915#2346]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions:
- shard-snb: [FAIL][69] -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-snb6/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-snb5/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-tglb: [DMESG-WARN][71] ([i915#1982]) -> [PASS][72] +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [SKIP][75] ([fdo#109441]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-iclb6/igt@kms_psr@psr2_cursor_plane_onoff.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@perf_pmu@module-unload:
- shard-skl: [DMESG-WARN][77] ([i915#1982] / [i915#262]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-skl10/igt@perf_pmu@module-unload.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-skl3/igt@perf_pmu@module-unload.html
#### Warnings ####
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][79] ([i915#1226]) -> [SKIP][80] ([fdo#109349])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@runner@aborted:
- shard-hsw: [FAIL][81] ([i915#2295] / [i915#2439] / [i915#483]) -> [FAIL][82] ([i915#2295] / [i915#2439])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-hsw1/igt@runner@aborted.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-hsw7/igt@runner@aborted.html
- shard-glk: ([FAIL][83], [FAIL][84]) ([i915#1611] / [i915#2295] / [i915#2439] / [i915#86] / [k.org#202321]) -> ([FAIL][85], [FAIL][86]) ([i915#1611] / [i915#2295] / [i915#2439] / [i915#483] / [i915#86] / [k.org#202321])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk2/igt@runner@aborted.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9350/shard-glk6/igt@runner@aborted.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-glk3/igt@runner@aborted.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/shard-glk7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2244]: https://gitlab.freedesktop.org/drm/intel/issues/2244
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#247]: https://gitlab.freedesktop.org/drm/intel/issues/247
[i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#86]: https://gitlab.freedesktop.org/drm/intel/issues/86
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 8)
------------------------------
Missing (2): pig-skl-6260u pig-glk-j5005
Build changes
-------------
* Linux: CI_DRM_9350 -> Patchwork_18928
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_9350: 3161d1b26b7e1a7cb9146e3f8bd613f901ff5b38 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5855: d9b3c7058efe41e5224dd1e43fac05dc6d049380 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18928: e3f81d0a69ee4cdf786f4350951497399cc4ca39 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18928/index.html
[-- Attachment #1.2: Type: text/html, Size: 23879 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [Intel-gfx] [CI 00/15] Rebased remaining big joiner series
2020-11-17 19:47 [Intel-gfx] [CI 00/15] Rebased remaining big joiner series Manasi Navare
` (18 preceding siblings ...)
2020-11-18 10:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-11-18 19:49 ` Navare, Manasi
2020-11-19 0:04 ` Chris Wilson
2020-11-19 5:58 ` Navare, Manasi
19 siblings, 2 replies; 26+ messages in thread
From: Navare, Manasi @ 2020-11-18 19:49 UTC (permalink / raw)
To: intel-gfx
Series pushed to dinq
Manasi
On Tue, Nov 17, 2020 at 11:47:03AM -0800, Manasi Navare wrote:
>
>
> Maarten Lankhorst (4):
> drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
> drm/i915: Try to make bigjoiner work in atomic check
> drm/i915: Add bigjoiner aware plane clipping checks
> drm/i915: Add debugfs dumping for bigjoiner, v3.
>
> Manasi Navare (3):
> drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave
> drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner
> drm/i915: HW state readout for Bigjoiner case
>
> Ville Syrjälä (8):
> drm/i915: Copy the plane hw state directly for Y planes
> drm/i915: Add crtcs affected by bigjoiner to the state
> drm/i915: Add planes affected by bigjoiner to the state
> drm/i915: Get the uapi state from the correct plane when bigjoiner is
> used
> drm/i915: Disable legacy cursor fastpath for bigjoiner
> drm/i915: Fix cursor src/dst rectangle with bigjoiner
> drm/i915: Add bigjoiner state dump
> drm/i915: Enable bigjoiner
>
> drivers/gpu/drm/i915/display/icl_dsi.c | 2 -
> .../gpu/drm/i915/display/intel_atomic_plane.c | 131 +++-
> .../gpu/drm/i915/display/intel_atomic_plane.h | 9 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 69 +-
> drivers/gpu/drm/i915/display/intel_display.c | 696 ++++++++++++++----
> drivers/gpu/drm/i915/display/intel_display.h | 3 +-
> .../drm/i915/display/intel_display_debugfs.c | 25 +-
> .../drm/i915/display/intel_display_types.h | 10 +
> drivers/gpu/drm/i915/display/intel_dp.c | 100 ++-
> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 201 ++---
> drivers/gpu/drm/i915/display/intel_vdsc.h | 6 +-
> 16 files changed, 953 insertions(+), 327 deletions(-)
>
> --
> 2.19.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [Intel-gfx] [CI 00/15] Rebased remaining big joiner series
2020-11-18 19:49 ` [Intel-gfx] [CI 00/15] " Navare, Manasi
@ 2020-11-19 0:04 ` Chris Wilson
2020-11-19 5:58 ` Navare, Manasi
1 sibling, 0 replies; 26+ messages in thread
From: Chris Wilson @ 2020-11-19 0:04 UTC (permalink / raw)
To: Navare, Manasi, intel-gfx
Quoting Navare, Manasi (2020-11-18 19:49:25)
> Series pushed to dinq
Oops on boot:
<1>[ 44.315382] BUG: unable to handle page fault for address: ffffc90049e02100
<1>[ 44.315422] #PF: supervisor read access in kernel mode
<1>[ 44.315442] #PF: error_code(0x0000) - not-present page
<6>[ 44.315462] PGD 100000067 P4D 100000067 PUD 0
<4>[ 44.315497] Oops: 0000 [#1] PREEMPT SMP NOPTI
<4>[ 44.315522] CPU: 7 PID: 276 Comm: systemd-udevd Tainted: G U 5.10.0-rc3-CI-CI_DRM_9355+ #1
<4>[ 44.315552] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake Y LPDDR4x T4 Crb, BIOS TGLSFWI1.R00.2527.A03.2001170231 01/17/2020
<4>[ 44.315981] RIP: 0010:gen12_fwtable_read32+0x6f/0x2f0 [i915]
<4>[ 44.316016] Code: c6 48 8b 43 08 8b b0 98 0d 00 00 85 f6 0f 85 53 01 00 00 89 ee 48 89 df e8 fe a6 ff ff 85 c0 0f 85 bc 00 00 00 89 e8 48 03 03 <44> 8b 38 48 8b 43 08 8b 90 98 0d 00 00 85 d2 0f 85 a8 01 00 00 4c
16893] hsw_crtc_enable+0x188/0x780 [i915]
<4>[ 44.317423] intel_enable_crtc+0x56/0x70 [i915]
<4>[ 44.317931] skl_commit_modeset_enables+0x34a/0x530 [i915]
<4>[ 44.318444] intel_atomic_commit_tail+0x3a0/0x1330 [i915]
<4>[ 44.318488] ? queue_work_on+0x5e/0x70
<4>[ 44.318965] intel_atomic_commit+0x371/0x3f0 [i915]
<4>[ 44.319458] intel_initial_commit+0x156/0x1e0 [i915]
<4>[ 44.319949] intel_modeset_init_nogem+0xb59/0x1c00 [i915]
<4>[ 44.320336] i915_driver_probe+0x79c/0xd90 [i915]
<4>[ 44.320374] ? __pm_runtime_resume+0x4f/0x80
<4>[ 44.320741] i915_pci_probe+0x43/0x1d0 [i915]
<4>[ 44.320772] ? _raw_spin_unlock_irqrestore+0x2f/0x50
<4>[ 44.320804] pci_device_probe+0x9e/0x110
<4>[ 44.320830] really_probe+0x1c4/0x430
<4>[ 44.320852] driver_probe_device+0xd9/0x140
<4>[ 44.320875] device_driver_attach+0x4a/0x50
<4>[ 44.320897] __driver_attach+0x83/0x140
<4>[ 44.320917] ? device_driver_attach+0x50/0x50
<4>[ 44.320938] ? device_driver_attach+0x50/0x50
89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48
<4>[ 44.321749] RSP: 002b:00007ffda8ea9358 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
<4>[ 44.321782] RAX: ffffffffffffffda RBX: 000056004d10ffc0 RCX: 00007fad885f5839
<4>[ 44.321808] RDX: 0000000000000000 RSI: 000056004d0f5490 RDI: 000000000000000f
<4>[ 44.321834] RBP: 000056004d0f5490 R08: 0000000000000000 R09: 00007ffda8ea9470
<4>[ 44.321859] R10: 000000000000000f R11: 0000000000000246 R12: 0000000000000000
<4>[ 44.321884] R13: 000056004d0f20c0 R14: 0000000000020000 R15: 0000000000000000
<4>[ 44.321921] Modules linked in: i915(+) mei_hdcp x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul snd_hda_intel snd_intel_dspcfg ghash_clmulni_intel snd_hda_codec cdc_ether snd_hwdep usbnet snd_hda_core mii e1000e ptp snd_pcm pps_core mei_me mei prime_numbers intel_lpss_pci(+)
<4>[ 44.322105] CR2: ffffc90049e02100
<4>[ 44.322130] ---[ end trace 87c6ef683da5ac08 ]---
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [CI 00/15] Rebased remaining big joiner series
2020-11-18 19:49 ` [Intel-gfx] [CI 00/15] " Navare, Manasi
2020-11-19 0:04 ` Chris Wilson
@ 2020-11-19 5:58 ` Navare, Manasi
2020-11-19 8:00 ` Chris Wilson
2020-11-19 8:13 ` Saarinen, Jani
1 sibling, 2 replies; 26+ messages in thread
From: Navare, Manasi @ 2020-11-19 5:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
On Wed, Nov 18, 2020 at 11:49:25AM -0800, Navare, Manasi wrote:
> Series pushed to dinq
>
> Manasi
By Chris Wilson:
Oops on boot:
<1>[ 44.315382] BUG: unable to handle page fault for address: ffffc90049e02100
<1>[ 44.315422] #PF: supervisor read access in kernel mode
<1>[ 44.315442] #PF: error_code(0x0000) - not-present page
<6>[ 44.315462] PGD 100000067 P4D 100000067 PUD 0
<4>[ 44.315497] Oops: 0000 [#1] PREEMPT SMP NOPTI
<4>[ 44.315522] CPU: 7 PID: 276 Comm: systemd-udevd Tainted: G U 5.10.0-rc3-CI-CI_DRM_9355+ #1
<4>[ 44.315552] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake Y LPDDR4x T4 Crb, BIOS TGLSFWI1.R00.2527.A03.2001170231 01/17/2020
<4>[ 44.315981] RIP: 0010:gen12_fwtable_read32+0x6f/0x2f0 [i915]
<4>[ 44.316016] Code: c6 48 8b 43 08 8b b0 98 0d 00 00 85 f6 0f 85 53 01 00 00 89 ee 48 89 df e8 fe a6 ff ff 85 c0 0f 85 bc 00 00 00 89 e8 48 03 03 <44> 8b 38 48 8b 43 08 8b 90 98 0d 00 00 85 d2 0f 85 a8 01 00 00 4c
16893] hsw_crtc_enable+0x188/0x780 [i915]
<4>[ 44.317423] intel_enable_crtc+0x56/0x70 [i915]
<4>[ 44.317931] skl_commit_modeset_enables+0x34a/0x530 [i915]
<4>[ 44.318444] intel_atomic_commit_tail+0x3a0/0x1330 [i915]
<4>[ 44.318488] ? queue_work_on+0x5e/0x70
<4>[ 44.318965] intel_atomic_commit+0x371/0x3f0 [i915]
<4>[ 44.319458] intel_initial_commit+0x156/0x1e0 [i915]
<4>[ 44.319949] intel_modeset_init_nogem+0xb59/0x1c00 [i915]
<4>[ 44.320336] i915_driver_probe+0x79c/0xd90 [i915]
<4>[ 44.320374] ? __pm_runtime_resume+0x4f/0x80
<4>[ 44.320741] i915_pci_probe+0x43/0x1d0 [i915]
<4>[ 44.320772] ? _raw_spin_unlock_irqrestore+0x2f/0x50
<4>[ 44.320804] pci_device_probe+0x9e/0x110
<4>[ 44.320830] really_probe+0x1c4/0x430
<4>[ 44.320852] driver_probe_device+0xd9/0x140
<4>[ 44.320875] device_driver_attach+0x4a/0x50
<4>[ 44.320897] __driver_attach+0x83/0x140
<4>[ 44.320917] ? device_driver_attach+0x50/0x50
<4>[ 44.320938] ? device_driver_attach+0x50/0x50
89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48
<4>[ 44.321749] RSP: 002b:00007ffda8ea9358 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
<4>[ 44.321782] RAX: ffffffffffffffda RBX: 000056004d10ffc0 RCX: 00007fad885f5839
<4>[ 44.321808] RDX: 0000000000000000 RSI: 000056004d0f5490 RDI: 000000000000000f
<4>[ 44.321834] RBP: 000056004d0f5490 R08: 0000000000000000 R09: 00007ffda8ea9470
<4>[ 44.321859] R10: 000000000000000f R11: 0000000000000246 R12: 0000000000000000
<4>[ 44.321884] R13: 000056004d0f20c0 R14: 0000000000020000 R15: 0000000000000000
<4>[ 44.321921] Modules linked in: i915(+) mei_hdcp x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul snd_hda_intel snd_intel_dspcfg ghash_clmulni_intel snd_hda_codec cdc_ether snd_hwdep usbnet snd_hda_core mii e1000e ptp snd_pcm pps_core mei_me mei prime_numbers intel_lpss_pci(+)
<4>[ 44.322105] CR2: ffffc90049e02100
<4>[ 44.322130] ---[ end trace 87c6ef683da5ac08 ]---
But Chris, we havent seen this on CI nor in our testing.
Manasi
>
> On Tue, Nov 17, 2020 at 11:47:03AM -0800, Manasi Navare wrote:
> >
> >
> > Maarten Lankhorst (4):
> > drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
> > drm/i915: Try to make bigjoiner work in atomic check
> > drm/i915: Add bigjoiner aware plane clipping checks
> > drm/i915: Add debugfs dumping for bigjoiner, v3.
> >
> > Manasi Navare (3):
> > drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave
> > drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner
> > drm/i915: HW state readout for Bigjoiner case
> >
> > Ville Syrjälä (8):
> > drm/i915: Copy the plane hw state directly for Y planes
> > drm/i915: Add crtcs affected by bigjoiner to the state
> > drm/i915: Add planes affected by bigjoiner to the state
> > drm/i915: Get the uapi state from the correct plane when bigjoiner is
> > used
> > drm/i915: Disable legacy cursor fastpath for bigjoiner
> > drm/i915: Fix cursor src/dst rectangle with bigjoiner
> > drm/i915: Add bigjoiner state dump
> > drm/i915: Enable bigjoiner
> >
> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 -
> > .../gpu/drm/i915/display/intel_atomic_plane.c | 131 +++-
> > .../gpu/drm/i915/display/intel_atomic_plane.h | 9 +-
> > drivers/gpu/drm/i915/display/intel_ddi.c | 69 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 696 ++++++++++++++----
> > drivers/gpu/drm/i915/display/intel_display.h | 3 +-
> > .../drm/i915/display/intel_display_debugfs.c | 25 +-
> > .../drm/i915/display/intel_display_types.h | 10 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 100 ++-
> > drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 201 ++---
> > drivers/gpu/drm/i915/display/intel_vdsc.h | 6 +-
> > 16 files changed, 953 insertions(+), 327 deletions(-)
> >
> > --
> > 2.19.1
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [CI 00/15] Rebased remaining big joiner series
2020-11-19 5:58 ` Navare, Manasi
@ 2020-11-19 8:00 ` Chris Wilson
2020-11-19 8:13 ` Saarinen, Jani
1 sibling, 0 replies; 26+ messages in thread
From: Chris Wilson @ 2020-11-19 8:00 UTC (permalink / raw)
To: Navare, Manasi, intel-gfx
Quoting Navare, Manasi (2020-11-19 05:58:03)
> On Wed, Nov 18, 2020 at 11:49:25AM -0800, Navare, Manasi wrote:
> > Series pushed to dinq
> >
> > Manasi
>
> By Chris Wilson:
>
> Oops on boot:
>
> <1>[ 44.315382] BUG: unable to handle page fault for address: ffffc90049e02100
> <1>[ 44.315422] #PF: supervisor read access in kernel mode
> <1>[ 44.315442] #PF: error_code(0x0000) - not-present page
> <6>[ 44.315462] PGD 100000067 P4D 100000067 PUD 0
> <4>[ 44.315497] Oops: 0000 [#1] PREEMPT SMP NOPTI
> <4>[ 44.315522] CPU: 7 PID: 276 Comm: systemd-udevd Tainted: G U 5.10.0-rc3-CI-CI_DRM_9355+ #1
> <4>[ 44.315552] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake Y LPDDR4x T4 Crb, BIOS TGLSFWI1.R00.2527.A03.2001170231 01/17/2020
> <4>[ 44.315981] RIP: 0010:gen12_fwtable_read32+0x6f/0x2f0 [i915]
> <4>[ 44.316016] Code: c6 48 8b 43 08 8b b0 98 0d 00 00 85 f6 0f 85 53 01 00 00 89 ee 48 89 df e8 fe a6 ff ff 85 c0 0f 85 bc 00 00 00 89 e8 48 03 03 <44> 8b 38 48 8b 43 08 8b 90 98 0d 00 00 85 d2 0f 85 a8 01 00 00 4c
> 16893] hsw_crtc_enable+0x188/0x780 [i915]
> <4>[ 44.317423] intel_enable_crtc+0x56/0x70 [i915]
> <4>[ 44.317931] skl_commit_modeset_enables+0x34a/0x530 [i915]
> <4>[ 44.318444] intel_atomic_commit_tail+0x3a0/0x1330 [i915]
> <4>[ 44.318488] ? queue_work_on+0x5e/0x70
> <4>[ 44.318965] intel_atomic_commit+0x371/0x3f0 [i915]
> <4>[ 44.319458] intel_initial_commit+0x156/0x1e0 [i915]
> <4>[ 44.319949] intel_modeset_init_nogem+0xb59/0x1c00 [i915]
> <4>[ 44.320336] i915_driver_probe+0x79c/0xd90 [i915]
> <4>[ 44.320374] ? __pm_runtime_resume+0x4f/0x80
> <4>[ 44.320741] i915_pci_probe+0x43/0x1d0 [i915]
> <4>[ 44.320772] ? _raw_spin_unlock_irqrestore+0x2f/0x50
> <4>[ 44.320804] pci_device_probe+0x9e/0x110
> <4>[ 44.320830] really_probe+0x1c4/0x430
> <4>[ 44.320852] driver_probe_device+0xd9/0x140
> <4>[ 44.320875] device_driver_attach+0x4a/0x50
> <4>[ 44.320897] __driver_attach+0x83/0x140
> <4>[ 44.320917] ? device_driver_attach+0x50/0x50
> <4>[ 44.320938] ? device_driver_attach+0x50/0x50
> 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48
> <4>[ 44.321749] RSP: 002b:00007ffda8ea9358 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
> <4>[ 44.321782] RAX: ffffffffffffffda RBX: 000056004d10ffc0 RCX: 00007fad885f5839
> <4>[ 44.321808] RDX: 0000000000000000 RSI: 000056004d0f5490 RDI: 000000000000000f
> <4>[ 44.321834] RBP: 000056004d0f5490 R08: 0000000000000000 R09: 00007ffda8ea9470
> <4>[ 44.321859] R10: 000000000000000f R11: 0000000000000246 R12: 0000000000000000
> <4>[ 44.321884] R13: 000056004d0f20c0 R14: 0000000000020000 R15: 0000000000000000
> <4>[ 44.321921] Modules linked in: i915(+) mei_hdcp x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul snd_hda_intel snd_intel_dspcfg ghash_clmulni_intel snd_hda_codec cdc_ether snd_hwdep usbnet snd_hda_core mii e1000e ptp snd_pcm pps_core mei_me mei prime_numbers intel_lpss_pci(+)
> <4>[ 44.322105] CR2: ffffc90049e02100
> <4>[ 44.322130] ---[ end trace 87c6ef683da5ac08 ]---
>
>
> But Chris, we havent seen this on CI nor in our testing.
This is CI. CI is also reporting massive display powerwell breakage.
-Chris
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [CI 00/15] Rebased remaining big joiner series
2020-11-19 5:58 ` Navare, Manasi
2020-11-19 8:00 ` Chris Wilson
@ 2020-11-19 8:13 ` Saarinen, Jani
1 sibling, 0 replies; 26+ messages in thread
From: Saarinen, Jani @ 2020-11-19 8:13 UTC (permalink / raw)
To: Navare, Manasi D, intel-gfx; +Cc: Chris Wilson
Hi,
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Navare,
> Manasi
> Sent: torstai 19. marraskuuta 2020 7.58
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Subject: Re: [Intel-gfx] [CI 00/15] Rebased remaining big joiner series
>
> On Wed, Nov 18, 2020 at 11:49:25AM -0800, Navare, Manasi wrote:
> > Series pushed to dinq
> >
> > Manasi
>
> By Chris Wilson:
>
> Oops on boot:
>
> <1>[ 44.315382] BUG: unable to handle page fault for address: ffffc90049e02100
> <1>[ 44.315422] #PF: supervisor read access in kernel mode
> <1>[ 44.315442] #PF: error_code(0x0000) - not-present page
> <6>[ 44.315462] PGD 100000067 P4D 100000067 PUD 0
> <4>[ 44.315497] Oops: 0000 [#1] PREEMPT SMP NOPTI
> <4>[ 44.315522] CPU: 7 PID: 276 Comm: systemd-udevd Tainted: G U
> 5.10.0-rc3-CI-CI_DRM_9355+ #1
> <4>[ 44.315552] Hardware name: Intel Corporation Tiger Lake Client
> Platform/TigerLake Y LPDDR4x T4 Crb, BIOS TGLSFWI1.R00.2527.A03.2001170231
> 01/17/2020
> <4>[ 44.315981] RIP: 0010:gen12_fwtable_read32+0x6f/0x2f0 [i915]
> <4>[ 44.316016] Code: c6 48 8b 43 08 8b b0 98 0d 00 00 85 f6 0f 85 53 01 00 00 89
> ee 48 89 df e8 fe a6 ff ff 85 c0 0f 85 bc 00 00 00 89 e8 48 03 03 <44> 8b 38 48 8b 43
> 08 8b 90 98 0d 00 00 85 d2 0f 85 a8 01 00 00 4c
> 16893] hsw_crtc_enable+0x188/0x780 [i915]
> <4>[ 44.317423] intel_enable_crtc+0x56/0x70 [i915]
> <4>[ 44.317931] skl_commit_modeset_enables+0x34a/0x530 [i915]
> <4>[ 44.318444] intel_atomic_commit_tail+0x3a0/0x1330 [i915]
> <4>[ 44.318488] ? queue_work_on+0x5e/0x70
> <4>[ 44.318965] intel_atomic_commit+0x371/0x3f0 [i915]
> <4>[ 44.319458] intel_initial_commit+0x156/0x1e0 [i915]
> <4>[ 44.319949] intel_modeset_init_nogem+0xb59/0x1c00 [i915]
> <4>[ 44.320336] i915_driver_probe+0x79c/0xd90 [i915]
> <4>[ 44.320374] ? __pm_runtime_resume+0x4f/0x80
> <4>[ 44.320741] i915_pci_probe+0x43/0x1d0 [i915]
> <4>[ 44.320772] ? _raw_spin_unlock_irqrestore+0x2f/0x50
> <4>[ 44.320804] pci_device_probe+0x9e/0x110
> <4>[ 44.320830] really_probe+0x1c4/0x430
> <4>[ 44.320852] driver_probe_device+0xd9/0x140
> <4>[ 44.320875] device_driver_attach+0x4a/0x50
> <4>[ 44.320897] __driver_attach+0x83/0x140
> <4>[ 44.320917] ? device_driver_attach+0x50/0x50
> <4>[ 44.320938] ? device_driver_attach+0x50/0x50
> 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f
> f6 2c 00 f7 d8 64 89 01 48
> <4>[ 44.321749] RSP: 002b:00007ffda8ea9358 EFLAGS: 00000246 ORIG_RAX:
> 0000000000000139
> <4>[ 44.321782] RAX: ffffffffffffffda RBX: 000056004d10ffc0 RCX:
> 00007fad885f5839
> <4>[ 44.321808] RDX: 0000000000000000 RSI: 000056004d0f5490 RDI:
> 000000000000000f
> <4>[ 44.321834] RBP: 000056004d0f5490 R08: 0000000000000000 R09:
> 00007ffda8ea9470
> <4>[ 44.321859] R10: 000000000000000f R11: 0000000000000246 R12:
> 0000000000000000
> <4>[ 44.321884] R13: 000056004d0f20c0 R14: 0000000000020000 R15:
> 0000000000000000
> <4>[ 44.321921] Modules linked in: i915(+) mei_hdcp x86_pkg_temp_thermal
> coretemp crct10dif_pclmul crc32_pclmul snd_hda_intel snd_intel_dspcfg
> ghash_clmulni_intel snd_hda_codec cdc_ether snd_hwdep usbnet snd_hda_core mii
> e1000e ptp snd_pcm pps_core mei_me mei prime_numbers intel_lpss_pci(+)
> <4>[ 44.322105] CR2: ffffc90049e02100
> <4>[ 44.322130] ---[ end trace 87c6ef683da5ac08 ]---
>
>
> But Chris, we havent seen this on CI nor in our testing.
It was at least on https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/index.html?testfilter=boot
>
> Manasi
>
> >
> > On Tue, Nov 17, 2020 at 11:47:03AM -0800, Manasi Navare wrote:
> > >
> > >
> > > Maarten Lankhorst (4):
> > > drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
> > > drm/i915: Try to make bigjoiner work in atomic check
> > > drm/i915: Add bigjoiner aware plane clipping checks
> > > drm/i915: Add debugfs dumping for bigjoiner, v3.
> > >
> > > Manasi Navare (3):
> > > drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave
> > > drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner
> > > drm/i915: HW state readout for Bigjoiner case
> > >
> > > Ville Syrjälä (8):
> > > drm/i915: Copy the plane hw state directly for Y planes
> > > drm/i915: Add crtcs affected by bigjoiner to the state
> > > drm/i915: Add planes affected by bigjoiner to the state
> > > drm/i915: Get the uapi state from the correct plane when bigjoiner is
> > > used
> > > drm/i915: Disable legacy cursor fastpath for bigjoiner
> > > drm/i915: Fix cursor src/dst rectangle with bigjoiner
> > > drm/i915: Add bigjoiner state dump
> > > drm/i915: Enable bigjoiner
> > >
> > > drivers/gpu/drm/i915/display/icl_dsi.c | 2 -
> > > .../gpu/drm/i915/display/intel_atomic_plane.c | 131 +++-
> > > .../gpu/drm/i915/display/intel_atomic_plane.h | 9 +-
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 69 +-
> > > drivers/gpu/drm/i915/display/intel_display.c | 696 ++++++++++++++----
> > > drivers/gpu/drm/i915/display/intel_display.h | 3 +-
> > > .../drm/i915/display/intel_display_debugfs.c | 25 +-
> > > .../drm/i915/display/intel_display_types.h | 10 +
> > > drivers/gpu/drm/i915/display/intel_dp.c | 100 ++-
> > > drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> > > drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
> > > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> > > drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
> > > drivers/gpu/drm/i915/display/intel_vdsc.c | 201 ++---
> > > drivers/gpu/drm/i915/display/intel_vdsc.h | 6 +-
> > > 16 files changed, 953 insertions(+), 327 deletions(-)
> > >
> > > --
> > > 2.19.1
> > >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 26+ messages in thread