Re: [Intel-gfx] [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2

Re: [Intel-gfx] [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Ville Syrjälä]

On Thu, Nov 19, 2020 at 09:20:49PM +0530, Uma Shankar wrote:
> There are some corner cases wrt underrun when we enable
> FBC with PSR2 on TGL. Recommendation from hardware is to
> keep this combination disabled.
> 
> Bspec: 50422 HSD: 14010260002
> 
> v2: Added psr2 enabled check from crtc_state (Anshuman)
> Added Bspec link and HSD referneces (Jose)
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index a5b072816a7b..c64ed1cd29b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -799,6 +799,17 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
>  	struct intel_fbc *fbc = &dev_priv->fbc;
>  	struct intel_fbc_state_cache *cache = &fbc->state_cache;
>  
> +	/*
> +	 * Tigerlake is not supporting FBC with PSR2.
> +	 * Recommendation is to keep this combination disabled
> +	 * Bspec: 50422 HSD: 14010260002
> +	 */
> +	if (crtc->config && crtc->config->has_psr2 &&

Please don't add more crtc->config usages. After several years
we've almost reached the point where we can finally remove it.
I should porbably take a look at how much work would be required
to at least make it always NULL on g4x+.

The fbc state tracking is a total mess atm, but I think you can
stuff this into intel_fbc_update_state_cache() and either just
set cache->plane.visible=false (which is a bit of a lie but would
work), or add a new thing into the params/cache.

My plan is to eliminate most of the this params/cache mess
and just cache the things fbc really needs for hw
activate/deactivate. I do have a wip branch but haven't had
time recently to continue the work.

> +	    IS_TIGERLAKE(dev_priv)) {
> +		fbc->no_fbc_reason = "not supported with PSR2";
> +		return false;
> +	}
> +
>  	if (!intel_fbc_can_enable(dev_priv))
>  		return false;
>  
> -- 
> 2.26.2

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [v2 0/2] Re-enable FBC on TGL

[Uma Shankar]

FBC was disabled on TGL due to random underruns. It has
been determined that FBC will not work reliably with PSR2.
This series re-enables fbc along with taking care of the
PSR2 limitations for TGL.

Bspec: 50422 HSD: 14010260002

v2: Addressed review comments and added bspec links

Uma Shankar (2):
  drm/i915/display/tgl: Disable FBC with PSR2
  Revert "drm/i915/display/fbc: Disable fbc by default on TGL"

 drivers/gpu/drm/i915/display/intel_fbc.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Uma Shankar]

There are some corner cases wrt underrun when we enable
FBC with PSR2 on TGL. Recommendation from hardware is to
keep this combination disabled.

Bspec: 50422 HSD: 14010260002

v2: Added psr2 enabled check from crtc_state (Anshuman)
Added Bspec link and HSD referneces (Jose)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index a5b072816a7b..c64ed1cd29b1 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -799,6 +799,17 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 	struct intel_fbc *fbc = &dev_priv->fbc;
 	struct intel_fbc_state_cache *cache = &fbc->state_cache;
 
+	/*
+	 * Tigerlake is not supporting FBC with PSR2.
+	 * Recommendation is to keep this combination disabled
+	 * Bspec: 50422 HSD: 14010260002
+	 */
+	if (crtc->config && crtc->config->has_psr2 &&
+	    IS_TIGERLAKE(dev_priv)) {
+		fbc->no_fbc_reason = "not supported with PSR2";
+		return false;
+	}
+
 	if (!intel_fbc_can_enable(dev_priv))
 		return false;
 
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [v2 2/2] Revert "drm/i915/display/fbc: Disable fbc by default on TGL"

[Uma Shankar]

FBC can be re-enabled on TGL with WA of keeping it disabled
while PSR2 is enabled.

This reverts commit 2982ded2ff5ce0cf1a49bc39a526da182782b664.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index c64ed1cd29b1..7a5783564a0f 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1444,13 +1444,6 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
 	if (!HAS_FBC(dev_priv))
 		return 0;
 
-	/*
-	 * Fbc is causing random underruns in CI execution on TGL platforms.
-	 * Disabling the same while the problem is being debugged and analyzed.
-	 */
-	if (IS_TIGERLAKE(dev_priv))
-		return 0;
-
 	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
 		return 1;
 
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for Re-enable FBC on TGL (rev2)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 4247 bytes --]

== Series Details ==

Series: Re-enable FBC on TGL (rev2)
URL   : https://patchwork.freedesktop.org/series/83510/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9362 -> Patchwork_18941
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18941 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18941, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18941:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-glk-dsi:         NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/fi-glk-dsi/igt@gem_exec_suspend@basic-s3.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9362 and Patchwork_18941:

### New CI tests (1) ###

  * boot:
    - Statuses : 1 fail(s) 38 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18941 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_busy@basic@flip:
    - fi-kbl-soraka:      [PASS][2] -> [DMESG-WARN][3] ([i915#1982])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-kbl-soraka/igt@kms_busy@basic@flip.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/fi-kbl-soraka/igt@kms_busy@basic@flip.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-tgl-u2:          [DMESG-WARN][4] ([i915#1982]) -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
    - fi-icl-u2:          [DMESG-WARN][6] ([i915#1982]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-byt-j1900:       [DMESG-WARN][8] ([i915#1982]) -> [PASS][9] +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - {fi-kbl-7560u}:     [DMESG-WARN][10] ([i915#1982]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982


Participating hosts (42 -> 39)
------------------------------

  Additional (2): fi-glk-dsi fi-cfl-guc 
  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-tgl-y fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9362 -> Patchwork_18941

  CI-20190529: 20190529
  CI_DRM_9362: 374246282b84ca52149ecb9a83a4ad7a515d01d9 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5859: 5bc1047cc8f38a9e0c5a914b6511a639b15a740e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18941: fef9c94372d16d2bf3d5289d44264b292922250a @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

fef9c94372d1 Revert "drm/i915/display/fbc: Disable fbc by default on TGL"
489e02f189b4 drm/i915/display/tgl: Disable FBC with PSR2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/index.html

[-- Attachment #1.2: Type: text/html, Size: 5309 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Shankar, Uma]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Thursday, November 19, 2020 9:12 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2
> 
> On Thu, Nov 19, 2020 at 09:20:49PM +0530, Uma Shankar wrote:
> > There are some corner cases wrt underrun when we enable FBC with PSR2
> > on TGL. Recommendation from hardware is to keep this combination
> > disabled.
> >
> > Bspec: 50422 HSD: 14010260002
> >
> > v2: Added psr2 enabled check from crtc_state (Anshuman) Added Bspec
> > link and HSD referneces (Jose)
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_fbc.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index a5b072816a7b..c64ed1cd29b1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -799,6 +799,17 @@ static bool intel_fbc_can_activate(struct intel_crtc
> *crtc)
> >  	struct intel_fbc *fbc = &dev_priv->fbc;
> >  	struct intel_fbc_state_cache *cache = &fbc->state_cache;
> >
> > +	/*
> > +	 * Tigerlake is not supporting FBC with PSR2.
> > +	 * Recommendation is to keep this combination disabled
> > +	 * Bspec: 50422 HSD: 14010260002
> > +	 */
> > +	if (crtc->config && crtc->config->has_psr2 &&
> 
> Please don't add more crtc->config usages. After several years we've almost
> reached the point where we can finally remove it.
> I should porbably take a look at how much work would be required to at least
> make it always NULL on g4x+.
> 
> The fbc state tracking is a total mess atm, but I think you can stuff this into
> intel_fbc_update_state_cache() and either just set cache->plane.visible=false
> (which is a bit of a lie but would work), or add a new thing into the
> params/cache.

Ok sure, so I hope below logic will keep this disabled:
  if (crtc_state->has_psr2 && IS_TIGERLAKE(dev_priv))
                cache->plane.visible = false;

        if (!cache->plane.visible)
                return;

Will update and re-send the patch.

Thanks & Regards,
Uma Shankar

> My plan is to eliminate most of the this params/cache mess and just cache the
> things fbc really needs for hw activate/deactivate. I do have a wip branch but
> haven't had time recently to continue the work.
> 
> > +	    IS_TIGERLAKE(dev_priv)) {
> > +		fbc->no_fbc_reason = "not supported with PSR2";
> > +		return false;
> > +	}
> > +
> >  	if (!intel_fbc_can_enable(dev_priv))
> >  		return false;
> >
> > --
> > 2.26.2
> 
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [v3 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Uma Shankar]

There are some corner cases wrt underrun when we enable
FBC with PSR2 on TGL. Recommendation from hardware is to
keep this combination disabled.

Bspec: 50422 HSD: 14010260002

v2: Added psr2 enabled check from crtc_state (Anshuman)
Added Bspec link and HSD referneces (Jose)

v3: Moved the logic to disable fbc to intel_fbc_update_state_cache
and removed the crtc->config usages, as per Ville's recommendation.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index a5b072816a7b..cb29c6f068f9 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -701,6 +701,15 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 	struct drm_framebuffer *fb = plane_state->hw.fb;
 
 	cache->plane.visible = plane_state->uapi.visible;
+
+	/*
+	 * Tigerlake is not supporting FBC with PSR2.
+	 * Recommendation is to keep this combination disabled
+	 * Bspec: 50422 HSD: 14010260002
+	 */
+	if (crtc_state->has_psr2 && IS_TIGERLAKE(dev_priv))
+		cache->plane.visible = false;
+
 	if (!cache->plane.visible)
 		return;
 
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for Re-enable FBC on TGL (rev3)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 6440 bytes --]

== Series Details ==

Series: Re-enable FBC on TGL (rev3)
URL   : https://patchwork.freedesktop.org/series/83510/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9364 -> Patchwork_18945
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/index.html

New tests
---------

  New tests have been introduced between CI_DRM_9364 and Patchwork_18945:

### New CI tests (1) ###

  * boot:
    - Statuses : 1 fail(s) 38 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18945 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_parallel@engines@fds:
    - fi-icl-u2:          [PASS][1] -> [INCOMPLETE][2] ([i915#2295])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-icl-u2/igt@gem_exec_parallel@engines@fds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-icl-u2/igt@gem_exec_parallel@engines@fds.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-byt-j1900:       [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-apl-guc:         [PASS][5] -> [DMESG-WARN][6] ([i915#1635] / [i915#1982])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-apl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-apl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-soraka:      [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-kbl-soraka/igt@i915_pm_rpm@module-reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-kbl-soraka/igt@i915_pm_rpm@module-reload.html

  * igt@kms_busy@basic@flip:
    - fi-tgl-y:           [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@kms_busy@basic@flip.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-tgl-y/igt@kms_busy@basic@flip.html

  * igt@prime_self_import@basic-with_two_bos:
    - fi-tgl-y:           [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html

  
#### Possible fixes ####

  * igt@debugfs_test@read_all_entries:
    - fi-tgl-y:           [DMESG-WARN][13] ([i915#402]) -> [PASS][14] +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-bsw-kefka:       [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@kms_busy@basic@flip:
    - {fi-kbl-7560u}:     [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-kbl-7560u/igt@kms_busy@basic@flip.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-kbl-7560u/igt@kms_busy@basic@flip.html

  * igt@kms_psr@cursor_plane_move:
    - fi-tgl-y:           [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@kms_psr@cursor_plane_move.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-tgl-y/igt@kms_psr@cursor_plane_move.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-tgl-y:           [DMESG-WARN][21] ([i915#2411]) -> [DMESG-WARN][22] ([i915#1982] / [i915#2411])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@i915_pm_rpm@basic-pci-d3-state.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-tgl-y/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@runner@aborted:
    - fi-kbl-8809g:       [FAIL][23] ([i915#1186] / [i915#1784] / [i915#2426] / [i915#2439]) -> [FAIL][24] ([i915#1186] / [i915#2426] / [i915#2439])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-kbl-8809g/igt@runner@aborted.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-kbl-8809g/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1186]: https://gitlab.freedesktop.org/drm/intel/issues/1186
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1784]: https://gitlab.freedesktop.org/drm/intel/issues/1784
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (43 -> 39)
------------------------------

  Missing    (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u 


Build changes
-------------

  * Linux: CI_DRM_9364 -> Patchwork_18945

  CI-20190529: 20190529
  CI_DRM_9364: c7321011fe308f5bc466293213b01e5a86d6ff52 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5861: 71f45998b2819b2d473277d91fc3c63eef5c4a99 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18945: 91d69d8b69b25272fdecf40a9147dfd721d6aa19 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

91d69d8b69b2 Revert "drm/i915/display/fbc: Disable fbc by default on TGL"
df19de6badbd drm/i915/display/tgl: Disable FBC with PSR2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/index.html

[-- Attachment #1.2: Type: text/html, Size: 8171 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for Re-enable FBC on TGL (rev3)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 15054 bytes --]

== Series Details ==

Series: Re-enable FBC on TGL (rev3)
URL   : https://patchwork.freedesktop.org/series/83510/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9364_full -> Patchwork_18945_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

New tests
---------

  New tests have been introduced between CI_DRM_9364_full and Patchwork_18945_full:

### New CI tests (1) ###

  * boot:
    - Statuses : 175 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18945_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_whisper@basic-contexts-priority:
    - shard-glk:          [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-glk6/igt@gem_exec_whisper@basic-contexts-priority.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-glk4/igt@gem_exec_whisper@basic-contexts-priority.html

  * igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge:
    - shard-skl:          [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +8 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl9/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl6/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - shard-apl:          [PASS][5] -> [DMESG-WARN][6] ([i915#1635] / [i915#1982]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-apl1/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-apl6/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
    - shard-tglb:         [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-tglb7/igt@kms_flip@basic-plain-flip@a-edp1.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-tglb7/igt@kms_flip@basic-plain-flip@a-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
    - shard-kbl:          [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([i915#49])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl8/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html

  * igt@kms_plane@plane-panning-top-left-pipe-a-planes:
    - shard-glk:          [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-glk1/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-glk2/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_render:
    - shard-iclb:         [PASS][17] -> [SKIP][18] ([fdo#109441])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-iclb3/igt@kms_psr@psr2_sprite_render.html

  * igt@kms_universal_plane@universal-plane-gen9-features-pipe-a:
    - shard-iclb:         [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-iclb1/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-iclb4/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - shard-iclb:         [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-iclb8/igt@core_hotunplug@unbind-rebind.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-iclb8/igt@core_hotunplug@unbind-rebind.html

  * igt@drm_mm@all@color_evict_range:
    - shard-skl:          [INCOMPLETE][23] ([i915#198] / [i915#2485]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl10/igt@drm_mm@all@color_evict_range.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl1/igt@drm_mm@all@color_evict_range.html

  * igt@gem_blits@basic:
    - shard-skl:          [TIMEOUT][25] ([i915#2502]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl8/igt@gem_blits@basic.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl4/igt@gem_blits@basic.html

  * {igt@kms_async_flips@alternate-sync-async-flip}:
    - shard-tglb:         [FAIL][27] ([i915#2521]) -> [PASS][28] +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-tglb3/igt@kms_async_flips@alternate-sync-async-flip.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-tglb7/igt@kms_async_flips@alternate-sync-async-flip.html

  * {igt@kms_async_flips@async-flip-with-page-flip-events}:
    - shard-kbl:          [FAIL][29] ([i915#2521]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-kbl3/igt@kms_async_flips@async-flip-with-page-flip-events.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-kbl4/igt@kms_async_flips@async-flip-with-page-flip-events.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-90:
    - shard-kbl:          [DMESG-WARN][31] ([i915#1982]) -> [PASS][32] +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-kbl4/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-kbl2/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
    - shard-skl:          [FAIL][33] ([i915#54]) -> [PASS][34] +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - shard-apl:          [DMESG-WARN][35] ([i915#1635] / [i915#1982]) -> [PASS][36] +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-apl8/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-apl4/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-tglb:         [FAIL][37] ([i915#2346]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-tglb8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][39] ([i915#2122]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-glk1/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-glk2/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
    - shard-glk:          [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +3 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-glk5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-glk5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt:
    - shard-tglb:         [DMESG-WARN][43] ([i915#1982]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-tglb1/igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-tglb1/igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][45] ([i915#1188]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [SKIP][47] ([fdo#109441]) -> [PASS][48] +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-iclb3/igt@kms_psr@psr2_cursor_blt.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html

  * igt@perf_pmu@invalid-init:
    - shard-skl:          [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +4 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl2/igt@perf_pmu@invalid-init.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl4/igt@perf_pmu@invalid-init.html

  
#### Warnings ####

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-tglb:         [INCOMPLETE][51] ([i915#1436] / [i915#1602] / [i915#1887] / [i915#2411] / [i915#456]) -> [DMESG-WARN][52] ([i915#1436] / [i915#1602] / [i915#1887] / [i915#2411])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-tglb1/igt@gem_workarounds@suspend-resume-fd.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-tglb3/igt@gem_workarounds@suspend-resume-fd.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [DMESG-WARN][53] ([i915#1226]) -> [SKIP][54] ([fdo#109349])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-iclb7/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
    - shard-skl:          [DMESG-FAIL][55] ([i915#1982]) -> [DMESG-WARN][56] ([i915#1982])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
    - shard-apl:          [DMESG-FAIL][57] ([fdo#108145] / [i915#1635] / [i915#1982]) -> [FAIL][58] ([fdo#108145] / [i915#1635] / [i915#265])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html

  * igt@runner@aborted:
    - shard-skl:          [FAIL][59] ([i915#2295] / [i915#483]) -> ([FAIL][60], [FAIL][61]) ([i915#2029] / [i915#2295] / [i915#483])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl7/igt@runner@aborted.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl3/igt@runner@aborted.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl3/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2485]: https://gitlab.freedesktop.org/drm/intel/issues/2485
  [i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9364 -> Patchwork_18945

  CI-20190529: 20190529
  CI_DRM_9364: c7321011fe308f5bc466293213b01e5a86d6ff52 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5861: 71f45998b2819b2d473277d91fc3c63eef5c4a99 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18945: 91d69d8b69b25272fdecf40a9147dfd721d6aa19 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/index.html

[-- Attachment #1.2: Type: text/html, Size: 18513 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [v3 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Ville Syrjälä]

On Fri, Nov 20, 2020 at 01:06:14AM +0530, Uma Shankar wrote:
> There are some corner cases wrt underrun when we enable
> FBC with PSR2 on TGL. Recommendation from hardware is to
> keep this combination disabled.
> 
> Bspec: 50422 HSD: 14010260002
> 
> v2: Added psr2 enabled check from crtc_state (Anshuman)
> Added Bspec link and HSD referneces (Jose)
> 
> v3: Moved the logic to disable fbc to intel_fbc_update_state_cache
> and removed the crtc->config usages, as per Ville's recommendation.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index a5b072816a7b..cb29c6f068f9 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -701,6 +701,15 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
>  	struct drm_framebuffer *fb = plane_state->hw.fb;
>  
>  	cache->plane.visible = plane_state->uapi.visible;
> +
> +	/*
> +	 * Tigerlake is not supporting FBC with PSR2.
> +	 * Recommendation is to keep this combination disabled
> +	 * Bspec: 50422 HSD: 14010260002
> +	 */
> +	if (crtc_state->has_psr2 && IS_TIGERLAKE(dev_priv))
> +		cache->plane.visible = false;
> +
>  	if (!cache->plane.visible)
>  		return;
>  
> -- 
> 2.26.2

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [v3 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Souza, Jose]

On Fri, 2020-11-20 at 01:06 +0530, Uma Shankar wrote:
> There are some corner cases wrt underrun when we enable
> FBC with PSR2 on TGL. Recommendation from hardware is to
> keep this combination disabled.
> 
> Bspec: 50422 HSD: 14010260002
> 
> v2: Added psr2 enabled check from crtc_state (Anshuman)
> Added Bspec link and HSD referneces (Jose)
> 
> v3: Moved the logic to disable fbc to intel_fbc_update_state_cache
> and removed the crtc->config usages, as per Ville's recommendation.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index a5b072816a7b..cb29c6f068f9 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -701,6 +701,15 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
>  	struct drm_framebuffer *fb = plane_state->hw.fb;
>  
> 
> 
> 
>  	cache->plane.visible = plane_state->uapi.visible;
> +
> +	/*
> +	 * Tigerlake is not supporting FBC with PSR2.
> +	 * Recommendation is to keep this combination disabled
> +	 * Bspec: 50422 HSD: 14010260002
> +	 */
> +	if (crtc_state->has_psr2 && IS_TIGERLAKE(dev_priv))
> +		cache->plane.visible = false;

Looks like a hack to me, would be better add a psr2 variable in intel_fbc_state_cache.
We also would need have a PSR2 reason set in no_fbc_reason and handle it in IGT.

> +
>  	if (!cache->plane.visible)
>  		return;
>  
> 
> 
> 

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [v3 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Ville Syrjälä]

On Tue, Nov 24, 2020 at 10:03:35PM +0000, Souza, Jose wrote:
> On Fri, 2020-11-20 at 01:06 +0530, Uma Shankar wrote:
> > There are some corner cases wrt underrun when we enable
> > FBC with PSR2 on TGL. Recommendation from hardware is to
> > keep this combination disabled.
> > 
> > Bspec: 50422 HSD: 14010260002
> > 
> > v2: Added psr2 enabled check from crtc_state (Anshuman)
> > Added Bspec link and HSD referneces (Jose)
> > 
> > v3: Moved the logic to disable fbc to intel_fbc_update_state_cache
> > and removed the crtc->config usages, as per Ville's recommendation.
> > 
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index a5b072816a7b..cb29c6f068f9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -701,6 +701,15 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> >  	struct drm_framebuffer *fb = plane_state->hw.fb;
> >  
> > 
> > 
> > 
> >  	cache->plane.visible = plane_state->uapi.visible;
> > +
> > +	/*
> > +	 * Tigerlake is not supporting FBC with PSR2.
> > +	 * Recommendation is to keep this combination disabled
> > +	 * Bspec: 50422 HSD: 14010260002
> > +	 */
> > +	if (crtc_state->has_psr2 && IS_TIGERLAKE(dev_priv))
> > +		cache->plane.visible = false;
> 
> Looks like a hack to me, would be better add a psr2 variable in intel_fbc_state_cache.

The plan is to remove most things from that cache anyway since it's
mostly pointless stuff that should just be handled directly via
the plane/crtc states. Not really convinced it makes sense to add
more crap to it at this time. So IMO this is good enough for now.

> We also would need have a PSR2 reason set in no_fbc_reason and handle it in IGT.

I think that no_fbc_reason is rather pointless as well. Would make
life a lot simpler if we didn't have to worry about it. So tempted
to just nuke it.

> 
> > +
> >  	if (!cache->plane.visible)
> >  		return;
> >  
> > 
> > 
> > 
> 

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [v2 2/2] Revert "drm/i915/display/fbc: Disable fbc by default on TGL"

[Ville Syrjälä]

On Thu, Nov 19, 2020 at 09:20:50PM +0530, Uma Shankar wrote:
> FBC can be re-enabled on TGL with WA of keeping it disabled
> while PSR2 is enabled.
> 
> This reverts commit 2982ded2ff5ce0cf1a49bc39a526da182782b664.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Sorry, forgot to review this one.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 7 -------
>  1 file changed, 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index c64ed1cd29b1..7a5783564a0f 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1444,13 +1444,6 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
>  	if (!HAS_FBC(dev_priv))
>  		return 0;
>  
> -	/*
> -	 * Fbc is causing random underruns in CI execution on TGL platforms.
> -	 * Disabling the same while the problem is being debugged and analyzed.
> -	 */
> -	if (IS_TIGERLAKE(dev_priv))
> -		return 0;
> -
>  	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
>  		return 1;
>  
> -- 
> 2.26.2

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [v3 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Souza, Jose]

On Wed, 2020-11-25 at 18:17 +0200, Ville Syrjälä wrote:
> On Tue, Nov 24, 2020 at 10:03:35PM +0000, Souza, Jose wrote:
> > On Fri, 2020-11-20 at 01:06 +0530, Uma Shankar wrote:
> > > There are some corner cases wrt underrun when we enable
> > > FBC with PSR2 on TGL. Recommendation from hardware is to
> > > keep this combination disabled.
> > > 
> > > Bspec: 50422 HSD: 14010260002
> > > 
> > > v2: Added psr2 enabled check from crtc_state (Anshuman)
> > > Added Bspec link and HSD referneces (Jose)
> > > 
> > > v3: Moved the logic to disable fbc to intel_fbc_update_state_cache
> > > and removed the crtc->config usages, as per Ville's recommendation.
> > > 
> > > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index a5b072816a7b..cb29c6f068f9 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -701,6 +701,15 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> > >  	struct drm_framebuffer *fb = plane_state->hw.fb;
> > >  
> > > 
> > > 
> > > 
> > >  	cache->plane.visible = plane_state->uapi.visible;
> > > +
> > > +	/*
> > > +	 * Tigerlake is not supporting FBC with PSR2.
> > > +	 * Recommendation is to keep this combination disabled
> > > +	 * Bspec: 50422 HSD: 14010260002
> > > +	 */
> > > +	if (crtc_state->has_psr2 && IS_TIGERLAKE(dev_priv))
> > > +		cache->plane.visible = false;
> > 
> > Looks like a hack to me, would be better add a psr2 variable in intel_fbc_state_cache.
> 
> The plan is to remove most things from that cache anyway since it's
> mostly pointless stuff that should just be handled directly via
> the plane/crtc states. Not really convinced it makes sense to add
> more crap to it at this time. So IMO this is good enough for now.

When this will happen? if soon okay.
If there is no ETA IMHO is better do the right thing.

> 
> > We also would need have a PSR2 reason set in no_fbc_reason and handle it in IGT.
> 
> I think that no_fbc_reason is rather pointless as well. Would make
> life a lot simpler if we didn't have to worry about it. So tempted
> to just nuke it.
> 
> > 
> > > +
> > >  	if (!cache->plane.visible)
> > >  		return;
> > >  
> > > 
> > > 
> > > 
> > 
> 

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [v3 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Ville Syrjälä]

On Wed, Nov 25, 2020 at 05:52:10PM +0000, Souza, Jose wrote:
> On Wed, 2020-11-25 at 18:17 +0200, Ville Syrjälä wrote:
> > On Tue, Nov 24, 2020 at 10:03:35PM +0000, Souza, Jose wrote:
> > > On Fri, 2020-11-20 at 01:06 +0530, Uma Shankar wrote:
> > > > There are some corner cases wrt underrun when we enable
> > > > FBC with PSR2 on TGL. Recommendation from hardware is to
> > > > keep this combination disabled.
> > > > 
> > > > Bspec: 50422 HSD: 14010260002
> > > > 
> > > > v2: Added psr2 enabled check from crtc_state (Anshuman)
> > > > Added Bspec link and HSD referneces (Jose)
> > > > 
> > > > v3: Moved the logic to disable fbc to intel_fbc_update_state_cache
> > > > and removed the crtc->config usages, as per Ville's recommendation.
> > > > 
> > > > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++++
> > > >  1 file changed, 9 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > index a5b072816a7b..cb29c6f068f9 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > @@ -701,6 +701,15 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> > > >  	struct drm_framebuffer *fb = plane_state->hw.fb;
> > > >  
> > > > 
> > > > 
> > > > 
> > > >  	cache->plane.visible = plane_state->uapi.visible;
> > > > +
> > > > +	/*
> > > > +	 * Tigerlake is not supporting FBC with PSR2.
> > > > +	 * Recommendation is to keep this combination disabled
> > > > +	 * Bspec: 50422 HSD: 14010260002
> > > > +	 */
> > > > +	if (crtc_state->has_psr2 && IS_TIGERLAKE(dev_priv))
> > > > +		cache->plane.visible = false;
> > > 
> > > Looks like a hack to me, would be better add a psr2 variable in intel_fbc_state_cache.
> > 
> > The plan is to remove most things from that cache anyway since it's
> > mostly pointless stuff that should just be handled directly via
> > the plane/crtc states. Not really convinced it makes sense to add
> > more crap to it at this time. So IMO this is good enough for now.
> 
> When this will happen? if soon okay.
> If there is no ETA IMHO is better do the right thing.

I was hoping to get back to it soon, but looks like there's
quite a bit more urgent work ahead for the moment. So don't
know when I'll get back to this.

So I guess path of least resitance would be for Uma to respin
with your suggested approach. It was one of the solutions I
also suggested originally, but I did also suggest this simpler
version Uma actually did.

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [v3 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Shankar, Uma]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Friday, November 27, 2020 8:16 PM
> To: Souza, Jose <jose.souza@intel.com>
> Cc: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [v3 1/2] drm/i915/display/tgl: Disable FBC with PSR2
> 
> On Wed, Nov 25, 2020 at 05:52:10PM +0000, Souza, Jose wrote:
> > On Wed, 2020-11-25 at 18:17 +0200, Ville Syrjälä wrote:
> > > On Tue, Nov 24, 2020 at 10:03:35PM +0000, Souza, Jose wrote:
> > > > On Fri, 2020-11-20 at 01:06 +0530, Uma Shankar wrote:
> > > > > There are some corner cases wrt underrun when we enable FBC with
> > > > > PSR2 on TGL. Recommendation from hardware is to keep this
> > > > > combination disabled.
> > > > >
> > > > > Bspec: 50422 HSD: 14010260002
> > > > >
> > > > > v2: Added psr2 enabled check from crtc_state (Anshuman) Added
> > > > > Bspec link and HSD referneces (Jose)
> > > > >
> > > > > v3: Moved the logic to disable fbc to
> > > > > intel_fbc_update_state_cache and removed the crtc->config usages, as
> per Ville's recommendation.
> > > > >
> > > > > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++++
> > > > >  1 file changed, 9 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > index a5b072816a7b..cb29c6f068f9 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > @@ -701,6 +701,15 @@ static void intel_fbc_update_state_cache(struct
> intel_crtc *crtc,
> > > > >  	struct drm_framebuffer *fb = plane_state->hw.fb;
> > > > >
> > > > >
> > > > >
> > > > >
> > > > >  	cache->plane.visible = plane_state->uapi.visible;
> > > > > +
> > > > > +	/*
> > > > > +	 * Tigerlake is not supporting FBC with PSR2.
> > > > > +	 * Recommendation is to keep this combination disabled
> > > > > +	 * Bspec: 50422 HSD: 14010260002
> > > > > +	 */
> > > > > +	if (crtc_state->has_psr2 && IS_TIGERLAKE(dev_priv))
> > > > > +		cache->plane.visible = false;
> > > >
> > > > Looks like a hack to me, would be better add a psr2 variable in
> intel_fbc_state_cache.
> > >
> > > The plan is to remove most things from that cache anyway since it's
> > > mostly pointless stuff that should just be handled directly via the
> > > plane/crtc states. Not really convinced it makes sense to add more
> > > crap to it at this time. So IMO this is good enough for now.
> >
> > When this will happen? if soon okay.
> > If there is no ETA IMHO is better do the right thing.
> 
> I was hoping to get back to it soon, but looks like there's quite a bit more urgent
> work ahead for the moment. So don't know when I'll get back to this.
> 
> So I guess path of least resitance would be for Uma to respin with your
> suggested approach. It was one of the solutions I also suggested originally, but I
> did also suggest this simpler version Uma actually did.

Ok, let me send out a version with psr2 variable in state cache. Please review if that looks
better.

Regards,
Uma Shankar

> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx