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From: remi.denis.courmont@huawei.com
To: qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org
Subject: [PATCH 11/17] target/arm: do S1_ptw_translate() before address space lookup
Date: Mon, 23 Nov 2020 10:02:31 +0200	[thread overview]
Message-ID: <20201123080237.18465-11-remi.denis.courmont@huawei.com> (raw)
In-Reply-To: <3333301.iIbC2pHGDl@basile.remlab.net>

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

In the secure stage 2 translation regime, the VSTCR.SW and VTCR.NSW
bits can invert the secure flag for pagetable walks. This patchset
allows S1_ptw_translate() to change the non-secure bit.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9683f5aadc..e4681b1397 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10391,7 +10391,7 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
 
 /* Translate a S1 pagetable walk through S2 if needed.  */
 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
-                               hwaddr addr, MemTxAttrs txattrs,
+                               hwaddr addr, bool *is_secure,
                                ARMMMUFaultInfo *fi)
 {
     ARMMMUIdx s2_mmu_idx;
@@ -10403,6 +10403,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
         int s2prot;
         int ret;
         ARMCacheAttrs cacheattrs = {};
+        MemTxAttrs txattrs = {};
+
+        assert(!*is_secure); /* TODO: S-EL2 */
 
         ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
                                  &s2pa, &txattrs, &s2prot, &s2size, fi,
@@ -10442,9 +10445,9 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
     AddressSpace *as;
     uint32_t data;
 
+    addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
     attrs.secure = is_secure;
     as = arm_addressspace(cs, attrs);
-    addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
     if (fi->s1ptw) {
         return 0;
     }
@@ -10471,9 +10474,9 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
     AddressSpace *as;
     uint64_t data;
 
+    addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
     attrs.secure = is_secure;
     as = arm_addressspace(cs, attrs);
-    addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
     if (fi->s1ptw) {
         return 0;
     }
-- 
2.29.2



  parent reply	other threads:[~2020-11-23  8:13 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-23  8:01 [PATCHv3 00/17] ARMv8.4 Secure EL2 Rémi Denis-Courmont
2020-11-23  8:02 ` [PATCH 01/17] target/arm: remove redundant tests remi.denis.courmont
2020-11-23  8:02 ` [PATCH 02/17] target/arm: add arm_is_el2_enabled() helper remi.denis.courmont
2020-11-23  8:02 ` [PATCH 03/17] target/arm: use arm_is_el2_enabled() where applicable remi.denis.courmont
2020-11-23  8:02 ` [PATCH 04/17] target/arm: use arm_hcr_el2_eff() " remi.denis.courmont
2020-11-23  8:02 ` [PATCH 05/17] target/arm: factor MDCR_EL2 common handling remi.denis.courmont
2020-11-23  8:02 ` [PATCH 06/17] target/arm: declare new AA64PFR0 bit-fields remi.denis.courmont
2020-11-23  8:02 ` [PATCH 07/17] target/arm: add 64-bit S-EL2 to EL exception table remi.denis.courmont
2020-11-23  8:02 ` [PATCH 08/17] target/arm: return the stage 2 index for stage 1 remi.denis.courmont
2020-11-23  8:02 ` [PATCH 09/17] target/arm: add MMU stage 1 for Secure EL2 remi.denis.courmont
2020-11-23  8:02 ` [PATCH 10/17] target/arm: add ARMv8.4-SEL2 system registers remi.denis.courmont
2020-11-23  8:02 ` remi.denis.courmont [this message]
2020-11-23  8:02 ` [PATCH 12/17] target/arm: secure stage 2 translation regime remi.denis.courmont
2020-11-23  8:02 ` [PATCH 13/17] target/arm: handle VMID change in secure state remi.denis.courmont
2020-11-23  8:02 ` [PATCH 14/17] target/arm: set HPFAR_EL2.NS on secure stage 2 faults remi.denis.courmont
2020-11-23  8:02 ` [PATCH 15/17] target/arm: add ARMv8.4-SEL2 extension remi.denis.courmont
2020-11-23  8:02 ` [PATCH 16/17] target/arm: enable Secure EL2 in max CPU remi.denis.courmont
2020-11-23  8:02 ` [PATCH 17/17] target/arm: refactor vae1_tlbmask() remi.denis.courmont
2020-12-01 16:54 ` [PATCHv3 00/17] ARMv8.4 Secure EL2 Peter Maydell
2020-12-01 17:20   ` Rémi Denis-Courmont
2020-12-01 18:23     ` Peter Maydell
2020-12-01 18:37       ` Rémi Denis-Courmont
2020-12-08 14:11         ` Alex Bennée
2020-12-18  9:45           ` Rémi Denis-Courmont
  -- strict thread matches above, loose matches on Subject: below --
2020-11-09 13:56 [PATCHv2 00/17] ARM Secure EL2 extension Rémi Denis-Courmont
2020-11-09 14:10 ` [PATCH 11/17] target/arm: do S1_ptw_translate() before address space lookup remi.denis.courmont
2020-11-13 21:28   ` Richard Henderson

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