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From: remi.denis.courmont@huawei.com
To: qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org
Subject: [PATCH 06/17] target/arm: declare new AA64PFR0 bit-fields
Date: Mon, 23 Nov 2020 10:02:26 +0200	[thread overview]
Message-ID: <20201123080237.18465-6-remi.denis.courmont@huawei.com> (raw)
In-Reply-To: <3333301.iIbC2pHGDl@basile.remlab.net>

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9617e39004..1166bd8731 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1849,6 +1849,12 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
 FIELD(ID_AA64PFR0, GIC, 24, 4)
 FIELD(ID_AA64PFR0, RAS, 28, 4)
 FIELD(ID_AA64PFR0, SVE, 32, 4)
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
+FIELD(ID_AA64PFR0, AMU, 44, 4)
+FIELD(ID_AA64PFR0, DIT, 48, 4)
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
 
 FIELD(ID_AA64PFR1, BT, 0, 4)
 FIELD(ID_AA64PFR1, SBSS, 4, 4)
@@ -3882,6 +3888,11 @@ static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
 }
 
+static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
+}
+
 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
-- 
2.29.2



  parent reply	other threads:[~2020-11-23  8:12 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-23  8:01 [PATCHv3 00/17] ARMv8.4 Secure EL2 Rémi Denis-Courmont
2020-11-23  8:02 ` [PATCH 01/17] target/arm: remove redundant tests remi.denis.courmont
2020-11-23  8:02 ` [PATCH 02/17] target/arm: add arm_is_el2_enabled() helper remi.denis.courmont
2020-11-23  8:02 ` [PATCH 03/17] target/arm: use arm_is_el2_enabled() where applicable remi.denis.courmont
2020-11-23  8:02 ` [PATCH 04/17] target/arm: use arm_hcr_el2_eff() " remi.denis.courmont
2020-11-23  8:02 ` [PATCH 05/17] target/arm: factor MDCR_EL2 common handling remi.denis.courmont
2020-11-23  8:02 ` remi.denis.courmont [this message]
2020-11-23  8:02 ` [PATCH 07/17] target/arm: add 64-bit S-EL2 to EL exception table remi.denis.courmont
2020-11-23  8:02 ` [PATCH 08/17] target/arm: return the stage 2 index for stage 1 remi.denis.courmont
2020-11-23  8:02 ` [PATCH 09/17] target/arm: add MMU stage 1 for Secure EL2 remi.denis.courmont
2020-11-23  8:02 ` [PATCH 10/17] target/arm: add ARMv8.4-SEL2 system registers remi.denis.courmont
2020-11-23  8:02 ` [PATCH 11/17] target/arm: do S1_ptw_translate() before address space lookup remi.denis.courmont
2020-11-23  8:02 ` [PATCH 12/17] target/arm: secure stage 2 translation regime remi.denis.courmont
2020-11-23  8:02 ` [PATCH 13/17] target/arm: handle VMID change in secure state remi.denis.courmont
2020-11-23  8:02 ` [PATCH 14/17] target/arm: set HPFAR_EL2.NS on secure stage 2 faults remi.denis.courmont
2020-11-23  8:02 ` [PATCH 15/17] target/arm: add ARMv8.4-SEL2 extension remi.denis.courmont
2020-11-23  8:02 ` [PATCH 16/17] target/arm: enable Secure EL2 in max CPU remi.denis.courmont
2020-11-23  8:02 ` [PATCH 17/17] target/arm: refactor vae1_tlbmask() remi.denis.courmont
2020-12-01 16:54 ` [PATCHv3 00/17] ARMv8.4 Secure EL2 Peter Maydell
2020-12-01 17:20   ` Rémi Denis-Courmont
2020-12-01 18:23     ` Peter Maydell
2020-12-01 18:37       ` Rémi Denis-Courmont
2020-12-08 14:11         ` Alex Bennée
2020-12-18  9:45           ` Rémi Denis-Courmont
  -- strict thread matches above, loose matches on Subject: below --
2020-11-09 13:56 [PATCHv2 00/17] ARM Secure EL2 extension Rémi Denis-Courmont
2020-11-09 14:10 ` [PATCH 06/17] target/arm: declare new AA64PFR0 bit-fields remi.denis.courmont

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