* [PATCH v2 01/29] ccs: Add the generator for CCS register definitions and limits
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
@ 2020-11-27 10:32 ` Sakari Ailus
2020-12-02 14:17 ` Mauro Carvalho Chehab
2020-11-27 10:32 ` [PATCH v2 02/29] Documentation: ccs: Add CCS driver documentation Sakari Ailus
` (27 subsequent siblings)
28 siblings, 1 reply; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:32 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Add register definitions of the MIPI CCS 1.1 standard.
The CCS driver makes extended use of device's capability registers that
are dependent on CCS version. This involves having an in-memory data
structure for limit and capability information, creating that data
structure and accessing it.
The register definitions as well as the definitions of this data structure
are generated from a text file using a Perl script. Add the generator
script to make it easy to update the generated files.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
.../driver-api/media/drivers/ccs/ccs-regs.txt | 1041 +++++++++++++++++
.../driver-api/media/drivers/ccs/mk-ccs-regs | 433 +++++++
MAINTAINERS | 1 +
3 files changed, 1475 insertions(+)
create mode 100644 Documentation/driver-api/media/drivers/ccs/ccs-regs.txt
create mode 100755 Documentation/driver-api/media/drivers/ccs/mk-ccs-regs
diff --git a/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt b/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt
new file mode 100644
index 000000000000..93f0131aa304
--- /dev/null
+++ b/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt
@@ -0,0 +1,1041 @@
+# Copyright (C) 2019--2020 Intel Corporation
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
+
+# register rflags
+# - f field LSB MSB rflags
+# - e enum value # after a field
+# - e enum value [LSB MSB]
+# - b bool bit
+# - l arg name min max elsize [discontig...]
+#
+# rflags
+# 8, 16, 32 register bits (default is 8)
+# v1.1 defined in version 1.1
+# f formula
+# float_ireal iReal or IEEE 754; 32 bits
+# ireal unsigned iReal
+
+# general status registers
+module_model_id 0x0000 16
+module_revision_number_major 0x0002 8
+frame_count 0x0005 8
+pixel_order 0x0006 8
+- e GRBG 0
+- e RGGB 1
+- e BGGR 2
+- e GBRG 3
+MIPI_CCS_version 0x0007 8
+- e v1_0 0x10
+- e v1_1 0x11
+- f major 4 7
+- f minor 0 3
+data_pedestal 0x0008 16
+module_manufacturer_id 0x000e 16
+module_revision_number_minor 0x0010 8
+module_date_year 0x0012 8
+module_date_month 0x0013 8
+module_date_day 0x0014 8
+module_date_phase 0x0015 8
+- f 0 2
+- e ts 0
+- e es 1
+- e cs 2
+- e mp 3
+sensor_model_id 0x0016 16
+sensor_revision_number 0x0018 8
+sensor_firmware_version 0x001a 8
+serial_number 0x001c 32
+sensor_manufacturer_id 0x0020 16
+sensor_revision_number_16 0x0022 16
+
+# frame format description registers
+frame_format_model_type 0x0040 8
+- e 2-byte 1
+- e 4-byte 2
+frame_format_model_subtype 0x0041 8
+- f rows 0 3
+- f columns 4 7
+frame_format_descriptor(n) 0x0042 16 f
+- l n 0 14 2
+- f pixels 0 11
+- f pcode 12 15
+- e embedded 1
+- e dummy_pixel 2
+- e black_pixel 3
+- e dark_pixel 4
+- e visible_pixel 5
+- e manuf_specific_0 8
+- e manuf_specific_1 9
+- e manuf_specific_2 10
+- e manuf_specific_3 11
+- e manuf_specific_4 12
+- e manuf_specific_5 13
+- e manuf_specific_6 14
+frame_format_descriptor_4(n) 0x0060 32 f
+- l n 0 7 4
+- f pixels 0 15
+- f pcode 28 31
+- e embedded 1
+- e dummy_pixel 2
+- e black_pixel 3
+- e dark_pixel 4
+- e visible_pixel 5
+- e manuf_specific_0 8
+- e manuf_specific_1 9
+- e manuf_specific_2 10
+- e manuf_specific_3 11
+- e manuf_specific_4 12
+- e manuf_specific_5 13
+- e manuf_specific_6 14
+
+# analog gain description registers
+analog_gain_capability 0x0080 16
+- e global 0
+- e alternate_global 2
+analog_gain_code_min 0x0084 16
+analog_gain_code_max 0x0086 16
+analog_gain_code_step 0x0088 16
+analog_gain_type 0x008a 16
+analog_gain_m0 0x008c 16
+analog_gain_c0 0x008e 16
+analog_gain_m1 0x0090 16
+analog_gain_c1 0x0092 16
+analog_linear_gain_min 0x0094 16 v1.1
+analog_linear_gain_max 0x0096 16 v1.1
+analog_linear_gain_step_size 0x0098 16 v1.1
+analog_exponential_gain_min 0x009a 16 v1.1
+analog_exponential_gain_max 0x009c 16 v1.1
+analog_exponential_gain_step_size 0x009e 16 v1.1
+
+# data format description registers
+data_format_model_type 0x00c0 8
+- e normal 1
+- e extended 2
+data_format_model_subtype 0x00c1 8
+- f rows 0 3
+- f columns 4 7
+data_format_descriptor(n) 0x00c2 16 f
+- l n 0 15 2
+- f compressed 0 7
+- f uncompressed 8 15
+
+# general set-up registers
+mode_select 0x0100 8
+- e software_standby 0
+- e streaming 1
+image_orientation 0x0101 8
+- b horizontal_mirror 0
+- b vertical_flip 1
+software_reset 0x0103 8
+- e off 0
+- e on 1
+grouped_parameter_hold 0x0104 8
+mask_corrupted_frames 0x0105 8
+- e allow 0
+- e mask 1
+fast_standby_ctrl 0x0106 8
+- e complete_frames 0
+- e frame_truncation 1
+CCI_address_ctrl 0x0107 8
+2nd_CCI_if_ctrl 0x0108 8
+- b enable 0
+- b ack 1
+2nd_CCI_address_ctrl 0x0109 8
+CSI_channel_identifier 0x0110 8
+CSI_signaling_mode 0x0111 8
+- e csi_2_dphy 2
+- e csi_2_cphy 3
+CSI_data_format 0x0112 16
+CSI_lane_mode 0x0114 8
+DPCM_Frame_DT 0x011d 8
+Bottom_embedded_data_DT 0x011e 8
+Bottom_embedded_data_VC 0x011f 8
+
+gain_mode 0x0120 8
+- e global 0
+- e alternate 1
+ADC_bit_depth 0x0121 8
+emb_data_ctrl 0x0122 v1.1
+- b raw8_packing_for_raw16 0
+- b raw10_packing_for_raw20 1
+- b raw12_packing_for_raw24 2
+
+GPIO_TRIG_mode 0x0130 8
+extclk_frequency_mhz 0x0136 16 ireal
+temp_sensor_ctrl 0x0138 8
+- b enable 0
+temp_sensor_mode 0x0139 8
+temp_sensor_output 0x013a 8
+
+# integration time registers
+fine_integration_time 0x0200 16
+coarse_integration_time 0x0202 16
+
+# analog gain registers
+analog_gain_code_global 0x0204 16
+analog_linear_gain_global 0x0206 16 v1.1
+analog_exponential_gain_global 0x0208 16 v1.1
+
+# digital gain registers
+digital_gain_global 0x020e 16
+
+# hdr control registers
+Short_analog_gain_global 0x0216 16
+Short_digital_gain_global 0x0218 16
+
+HDR_mode 0x0220 8
+- b enabled 0
+- b separate_analog_gain 1
+- b upscaling 2
+- b reset_sync 3
+- b timing_mode 4
+- b exposure_ctrl_direct 5
+- b separate_digital_gain 6
+HDR_resolution_reduction 0x0221 8
+- f row 0 3
+- f column 4 7
+Exposure_ratio 0x0222 8
+HDR_internal_bit_depth 0x0223 8
+Direct_short_integration_time 0x0224 16
+Short_analog_linear_gain_global 0x0226 16 v1.1
+Short_analog_exponential_gain_global 0x0228 16 v1.1
+
+# clock set-up registers
+vt_pix_clk_div 0x0300 16
+vt_sys_clk_div 0x0302 16
+pre_pll_clk_div 0x0304 16
+#vt_pre_pll_clk_div 0x0304 16
+pll_multiplier 0x0306 16
+#vt_pll_multiplier 0x0306 16
+op_pix_clk_div 0x0308 16
+op_sys_clk_div 0x030a 16
+op_pre_pll_clk_div 0x030c 16
+op_pll_multiplier 0x031e 16
+pll_mode 0x0310 8
+- f 0 0
+- e single 0
+- e dual 1
+op_pix_clk_div_rev 0x0312 16 v1.1
+op_sys_clk_div_rev 0x0314 16 v1.1
+
+# frame timing registers
+frame_length_lines 0x0340 16
+line_length_pck 0x0342 16
+
+# image size registers
+x_addr_start 0x0344 16
+y_addr_start 0x0346 16
+x_addr_end 0x0348 16
+y_addr_end 0x034a 16
+x_output_size 0x034c 16
+y_output_size 0x034e 16
+
+# timing mode registers
+Frame_length_ctrl 0x0350 8
+- b automatic 0
+Timing_mode_ctrl 0x0352 8
+- b manual_readout 0
+- b delayed_exposure 1
+Start_readout_rs 0x0353 8
+- b manual_readout_start 0
+Frame_margin 0x0354 16
+
+# sub-sampling registers
+x_even_inc 0x0380 16
+x_odd_inc 0x0382 16
+y_even_inc 0x0384 16
+y_odd_inc 0x0386 16
+
+# monochrome readout registers
+monochrome_en 0x0390 v1.1
+- e enabled 0
+
+# image scaling registers
+Scaling_mode 0x0400 16
+- e no_scaling 0
+- e horizontal 1
+scale_m 0x0404 16
+scale_n 0x0406 16
+digital_crop_x_offset 0x0408 16
+digital_crop_y_offset 0x040a 16
+digital_crop_image_width 0x040c 16
+digital_crop_image_height 0x040e 16
+
+# image compression registers
+compression_mode 0x0500 16
+- e none 0
+- e dpcm_pcm_simple 1
+
+# test pattern registers
+test_pattern_mode 0x0600 16
+- e none 0
+- e solid_color 1
+- e color_bars 2
+- e fade_to_grey 3
+- e pn9 4
+- e color_tile 5
+test_data_red 0x0602 16
+test_data_greenR 0x0604 16
+test_data_blue 0x0606 16
+test_data_greenB 0x0608 16
+value_step_size_smooth 0x060a 8
+value_step_size_quantised 0x060b 8
+
+# phy configuration registers
+tclk_post 0x0800 8
+ths_prepare 0x0801 8
+ths_zero_min 0x0802 8
+ths_trail 0x0803 8
+tclk_trail_min 0x0804 8
+tclk_prepare 0x0805 8
+tclk_zero 0x0806 8
+tlpx 0x0807 8
+phy_ctrl 0x0808 8
+- e auto 0
+- e UI 1
+- e manual 2
+tclk_post_ex 0x080a 16
+ths_prepare_ex 0x080c 16
+ths_zero_min_ex 0x080e 16
+ths_trail_ex 0x0810 16
+tclk_trail_min_ex 0x0812 16
+tclk_prepare_ex 0x0814 16
+tclk_zero_ex 0x0816 16
+tlpx_ex 0x0818 16
+
+# link rate register
+requested_link_rate 0x0820 32 u16.16
+
+# equalization control registers
+DPHY_equalization_mode 0x0824 8 v1.1
+- b eq2 0
+PHY_equalization_ctrl 0x0825 8 v1.1
+- b enable 0
+
+# d-phy preamble control registers
+DPHY_preamble_ctrl 0x0826 8 v1.1
+- b enable 0
+DPHY_preamble_length 0x0826 8 v1.1
+
+# d-phy spread spectrum control registers
+PHY_SSC_ctrl 0x0828 8 v1.1
+- b enable 0
+
+# manual lp control register
+manual_LP_ctrl 0x0829 8 v1.1
+- b enable 0
+
+# additional phy configuration registers
+twakeup 0x082a v1.1
+tinit 0x082b v1.1
+ths_exit 0x082c v1.1
+ths_exit_ex 0x082e 16 v1.1
+
+# phy calibration configuration registers
+PHY_periodic_calibration_ctrl 0x0830 8
+- b frame_blanking 0
+PHY_periodic_calibration_interval 0x0831 8
+PHY_init_calibration_ctrl 0x0832 8
+- b stream_start 0
+DPHY_calibration_mode 0x0833 8 v1.1
+- b also_alternate 0
+CPHY_calibration_mode 0x0834 8 v1.1
+- e format_1 0
+- e format_2 1
+- e format_3 2
+t3_calpreamble_length 0x0835 8 v1.1
+t3_calpreamble_length_per 0x0836 8 v1.1
+t3_calaltseq_length 0x0837 8 v1.1
+t3_calaltseq_length_per 0x0838 8 v1.1
+FM2_init_seed 0x083a 16 v1.1
+t3_caludefseq_length 0x083c 16 v1.1
+t3_caludefseq_length_per 0x083e 16 v1.1
+
+# c-phy manual control registers
+TGR_Preamble_Length 0x0841 8
+- b preamable_prog_seq 7
+- f begin_preamble_length 0 5
+TGR_Post_Length 0x0842 8
+- f post_length 0 4
+TGR_Preamble_Prog_Sequence(n2) 0x0843
+- l n2 0 6 1
+- f symbol_n_1 3 5
+- f symbol_n 0 2
+t3_prepare 0x084e 16
+t3_lpx 0x0850 16
+
+# alps control register
+ALPS_ctrl 0x085a 8
+- b lvlp_dphy 0
+- b lvlp_cphy 1
+- b alp_cphy 2
+
+# lrte control registers
+TX_REG_CSI_EPD_EN_SSP_cphy 0x0860 16
+TX_REG_CSI_EPD_OP_SLP_cphy 0x0862 16
+TX_REG_CSI_EPD_EN_SSP_dphy 0x0864 16
+TX_REG_CSI_EPD_OP_SLP_dphy 0x0866 16
+TX_REG_CSI_EPD_MISC_OPTION_cphy 0x0868 v1.1
+TX_REG_CSI_EPD_MISC_OPTION_dphy 0x0869 v1.1
+
+# scrambling control registers
+Scrambling_ctrl 0x0870
+- b enabled 0
+- f 2 3
+- e 1_seed_cphy 0
+- e 4_seed_cphy 3
+lane_seed_value(seed, lane) 0x0872 16
+- l seed 0 3 0x10
+- l lane 0 7 0x2
+
+# usl control registers
+TX_USL_REV_ENTRY 0x08c0 16 v1.1
+TX_USL_REV_Clock_Counter 0x08c2 16 v1.1
+TX_USL_REV_LP_Counter 0x08c4 16 v1.1
+TX_USL_REV_Frame_Counter 0x08c6 16 v1.1
+TX_USL_REV_Chronological_Timer 0x08c8 16 v1.1
+TX_USL_FWD_ENTRY 0x08ca 16 v1.1
+TX_USL_GPIO 0x08cc 16 v1.1
+TX_USL_Operation 0x08ce 16 v1.1
+- b reset 0
+TX_USL_ALP_ctrl 0x08d0 16 v1.1
+- b clock_pause 0
+TX_USL_APP_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
+TX_USL_SNS_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
+USL_Clock_Mode_d_ctrl 0x08d2 v1.1
+- b cont_clock_standby 0
+- b cont_clock_vblank 1
+- b cont_clock_hblank 2
+
+# binning configuration registers
+binning_mode 0x0900 8
+binning_type 0x0901 8
+binning_weighting 0x0902 8
+
+# data transfer interface registers
+data_transfer_if_1_ctrl 0x0a00 8
+- b enable 0
+- b write 1
+- b clear_error 2
+data_transfer_if_1_status 0x0a01 8
+- b read_if_ready 0
+- b write_if_ready 1
+- b data_corrupted 2
+- b improper_if_usage 3
+data_transfer_if_1_page_select 0x0a02 8
+data_transfer_if_1_data(p) 0x0a04 8 f
+- l p 0 63 1
+
+# image processing and sensor correction configuration registers
+shading_correction_en 0x0b00 8
+- b enable 0
+luminance_correction_level 0x0b01 8
+green_imbalance_filter_en 0x0b02 8
+- b enable 0
+mapped_defect_correct_en 0x0b05 8
+- b enable 0
+single_defect_correct_en 0x0b06 8
+- b enable 0
+dynamic_couplet_correct_en 0x0b08 8
+- b enable 0
+combined_defect_correct_en 0x0b0a 8
+- b enable 0
+module_specific_correction_en 0x0b0c 8
+- b enable 0
+dynamic_triplet_defect_correct_en 0x0b13 8
+- b enable 0
+NF_ctrl 0x0b15 8
+- b luma 0
+- b chroma 1
+- b combined 2
+
+# optical black pixel readout registers
+OB_readout_control 0x0b30 8
+- b enable 0
+- b interleaving 1
+OB_virtual_channel 0x0b31 8
+OB_DT 0x0b32 8
+OB_data_format 0x0b33 8
+
+# color temperature feedback registers
+color_temperature 0x0b8c 16
+absolute_gain_greenr 0x0b8e 16
+absolute_gain_red 0x0b90 16
+absolute_gain_blue 0x0b92 16
+absolute_gain_greenb 0x0b94 16
+
+# cfa conversion registers
+CFA_conversion_ctrl 0x0ba0 v1.1
+- b bayer_conversion_enable 0
+
+# flash strobe and sa strobe control registers
+flash_strobe_adjustment 0x0c12 8
+flash_strobe_start_point 0x0c14 16
+tflash_strobe_delay_rs_ctrl 0x0c16 16
+tflash_strobe_width_high_rs_ctrl 0x0c18 16
+flash_mode_rs 0x0c1a 8
+- b continuous 0
+- b truncate 1
+- b async 3
+flash_trigger_rs 0x0c1b 8
+flash_status 0x0c1c 8
+- b retimed 0
+sa_strobe_mode 0x0c1d 8
+- b continuous 0
+- b truncate 1
+- b async 3
+- b adjust_edge 4
+sa_strobe_start_point 0x0c1e 16
+tsa_strobe_delay_ctrl 0x0c20 16
+tsa_strobe_width_ctrl 0x0c22 16
+sa_strobe_trigger 0x0c24 8
+sa_strobe_status 0x0c25 8
+- b retimed 0
+tSA_strobe_re_delay_ctrl 0x0c30 16
+tSA_strobe_fe_delay_ctrl 0x0c32 16
+
+# pdaf control registers
+PDAF_ctrl 0x0d00 16
+- b enable 0
+- b processed 1
+- b interleaved 2
+- b visible_pdaf_correction 3
+PDAF_VC 0x0d02 8
+PDAF_DT 0x0d03 8
+pd_x_addr_start 0x0d04 16
+pd_y_addr_start 0x0d06 16
+pd_x_addr_end 0x0d08 16
+pd_y_addr_end 0x0d0a 16
+
+# bracketing interface configuration registers
+bracketing_LUT_ctrl 0x0e00 8
+bracketing_LUT_mode 0x0e01 8
+- b continue_streaming 0
+- b loop_mode 1
+bracketing_LUT_entry_ctrl 0x0e02 8
+bracketing_LUT_frame(n) 0x0e10 v1.1 f
+- l n 0 0xef 1
+
+# integration time and gain parameter limit registers
+integration_time_capability 0x1000 16
+- b fine 0
+coarse_integration_time_min 0x1004 16
+coarse_integration_time_max_margin 0x1006 16
+fine_integration_time_min 0x1008 16
+fine_integration_time_max_margin 0x100a 16
+
+# digital gain parameter limit registers
+digital_gain_capability 0x1081
+- e none 0
+- e global 2
+digital_gain_min 0x1084 16
+digital_gain_max 0x1086 16
+digital_gain_step_size 0x1088 16
+
+# data pedestal capability registers
+Pedestal_capability 0x10e0 8 v1.1
+
+# adc capability registers
+ADC_capability 0x10f0 8
+- b bit_depth_ctrl 0
+ADC_bit_depth_capability 0x10f4 32 v1.1
+
+# video timing parameter limit registers
+min_ext_clk_freq_mhz 0x1100 32 float_ireal
+max_ext_clk_freq_mhz 0x1104 32 float_ireal
+min_pre_pll_clk_div 0x1108 16
+# min_vt_pre_pll_clk_div 0x1108 16
+max_pre_pll_clk_div 0x110a 16
+# max_vt_pre_pll_clk_div 0x110a 16
+min_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
+# min_vt_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
+max_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
+# max_vt_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
+min_pll_multiplier 0x1114 16
+# min_vt_pll_multiplier 0x1114 16
+max_pll_multiplier 0x1116 16
+# max_vt_pll_multiplier 0x1116 16
+min_pll_op_clk_freq_mhz 0x1118 32 float_ireal
+max_pll_op_clk_freq_mhz 0x111c 32 float_ireal
+
+# video timing set-up capability registers
+min_vt_sys_clk_div 0x1120 16
+max_vt_sys_clk_div 0x1122 16
+min_vt_sys_clk_freq_mhz 0x1124 32 float_ireal
+max_vt_sys_clk_freq_mhz 0x1128 32 float_ireal
+min_vt_pix_clk_freq_mhz 0x112c 32 float_ireal
+max_vt_pix_clk_freq_mhz 0x1130 32 float_ireal
+min_vt_pix_clk_div 0x1134 16
+max_vt_pix_clk_div 0x1136 16
+clock_calculation 0x1138
+- b lane_speed 0
+- b link_decoupled 1
+- b dual_pll_op_sys_ddr 2
+- b dual_pll_op_pix_ddr 3
+num_of_vt_lanes 0x1139
+num_of_op_lanes 0x113a
+op_bits_per_lane 0x113b 8 v1.1
+
+# frame timing parameter limits
+min_frame_length_lines 0x1140 16
+max_frame_length_lines 0x1142 16
+min_line_length_pck 0x1144 16
+max_line_length_pck 0x1146 16
+min_line_blanking_pck 0x1148 16
+min_frame_blanking_lines 0x114a 16
+min_line_length_pck_step_size 0x114c
+timing_mode_capability 0x114d
+- b auto_frame_length 0
+- b rolling_shutter_manual_readout 2
+- b delayed_exposure_start 3
+- b manual_exposure_embedded_data 4
+frame_margin_max_value 0x114e 16
+frame_margin_min_value 0x1150
+gain_delay_type 0x1151
+- e fixed 0
+- e variable 1
+
+# output clock set-up capability registers
+min_op_sys_clk_div 0x1160 16
+max_op_sys_clk_div 0x1162 16
+min_op_sys_clk_freq_mhz 0x1164 32 float_ireal
+max_op_sys_clk_freq_mhz 0x1168 32 float_ireal
+min_op_pix_clk_div 0x116c 16
+max_op_pix_clk_div 0x116e 16
+min_op_pix_clk_freq_mhz 0x1170 32 float_ireal
+max_op_pix_clk_freq_mhz 0x1174 32 float_ireal
+
+# image size parameter limit registers
+x_addr_min 0x1180 16
+y_addr_min 0x1182 16
+x_addr_max 0x1184 16
+y_addr_max 0x1186 16
+min_x_output_size 0x1188 16
+min_y_output_size 0x118a 16
+max_x_output_size 0x118c 16
+max_y_output_size 0x118e 16
+
+x_addr_start_div_constant 0x1190 v1.1
+y_addr_start_div_constant 0x1191 v1.1
+x_addr_end_div_constant 0x1192 v1.1
+y_addr_end_div_constant 0x1193 v1.1
+x_size_div 0x1194 v1.1
+y_size_div 0x1195 v1.1
+x_output_div 0x1196 v1.1
+y_output_div 0x1197 v1.1
+non_flexible_resolution_support 0x1198 v1.1
+- b new_pix_addr 0
+- b new_output_res 1
+- b output_crop_no_pad 2
+- b output_size_lane_dep 3
+
+min_op_pre_pll_clk_div 0x11a0 16
+max_op_pre_pll_clk_div 0x11a2 16
+min_op_pll_ip_clk_freq_mhz 0x11a4 32 float_ireal
+max_op_pll_ip_clk_freq_mhz 0x11a8 32 float_ireal
+min_op_pll_multiplier 0x11ac 16
+max_op_pll_multiplier 0x11ae 16
+min_op_pll_op_clk_freq_mhz 0x11b0 32 float_ireal
+max_op_pll_op_clk_freq_mhz 0x11b4 32 float_ireal
+clock_tree_pll_capability 0x11b8 8
+- b dual_pll 0
+- b single_pll 1
+- b ext_divider 2
+- b flexible_op_pix_clk_div 3
+clock_capa_type_capability 0x11b9 v1.1
+- b ireal 0
+
+# sub-sampling parameters limit registers
+min_even_inc 0x11c0 16
+min_odd_inc 0x11c2 16
+max_even_inc 0x11c4 16
+max_odd_inc 0x11c6 16
+aux_subsamp_capability 0x11c8 v1.1
+- b factor_power_of_2 1
+aux_subsamp_mono_capability 0x11c9 v1.1
+- b factor_power_of_2 1
+monochrome_capability 0x11ca v1.1
+- e inc_odd 0
+- e inc_even 1
+pixel_readout_capability 0x11cb v1.1
+- e bayer 0
+- e monochrome 1
+- e bayer_and_mono 2
+min_even_inc_mono 0x11cc 16 v1.1
+max_even_inc_mono 0x11ce 16 v1.1
+min_odd_inc_mono 0x11d0 16 v1.1
+max_odd_inc_mono 0x11d2 16 v1.1
+min_even_inc_bc2 0x11d4 16 v1.1
+max_even_inc_bc2 0x11d6 16 v1.1
+min_odd_inc_bc2 0x11d8 16 v1.1
+max_odd_inc_bc2 0x11da 16 v1.1
+min_even_inc_mono_bc2 0x11dc 16 v1.1
+max_even_inc_mono_bc2 0x11de 16 v1.1
+min_odd_inc_mono_bc2 0x11f0 16 v1.1
+max_odd_inc_mono_bc2 0x11f2 16 v1.1
+
+# image scaling limit parameters
+scaling_capability 0x1200 16
+- e none 0
+- e horizontal 1
+- e reserved 2
+scaler_m_min 0x1204 16
+scaler_m_max 0x1206 16
+scaler_n_min 0x1208 16
+scaler_n_max 0x120a 16
+digital_crop_capability 0x120e
+- e none 0
+- e input_crop 1
+
+# hdr limit registers
+hdr_capability_1 0x1210
+- b 2x2_binning 0
+- b combined_analog_gain 1
+- b separate_analog_gain 2
+- b upscaling 3
+- b reset_sync 4
+- b direct_short_exp_timing 5
+- b direct_short_exp_synthesis 6
+min_hdr_bit_depth 0x1211
+hdr_resolution_sub_types 0x1212
+hdr_resolution_sub_type(n) 0x1213
+- l n 0 1 1
+- f row 0 3
+- f column 4 7
+hdr_capability_2 0x121b
+- b combined_digital_gain 0
+- b separate_digital_gain 1
+- b timing_mode 3
+- b synthesis_mode 4
+max_hdr_bit_depth 0x121c
+
+# usl capability register
+usl_support_capability 0x1230 v1.1
+- b clock_tree 0
+- b rev_clock_tree 1
+- b rev_clock_calc 2
+usl_clock_mode_d_capability 0x1231 v1.1
+- b cont_clock_standby 0
+- b cont_clock_vblank 1
+- b cont_clock_hblank 2
+- b noncont_clock_standby 3
+- b noncont_clock_vblank 4
+- b noncont_clock_hblank 5
+min_op_sys_clk_div_rev 0x1234 v1.1
+max_op_sys_clk_div_rev 0x1236 v1.1
+min_op_pix_clk_div_rev 0x1238 v1.1
+max_op_pix_clk_div_rev 0x123a v1.1
+min_op_sys_clk_freq_rev_mhz 0x123c 32 v1.1 float_ireal
+max_op_sys_clk_freq_rev_mhz 0x1240 32 v1.1 float_ireal
+min_op_pix_clk_freq_rev_mhz 0x1244 32 v1.1 float_ireal
+max_op_pix_clk_freq_rev_mhz 0x1248 32 v1.1 float_ireal
+max_bitrate_rev_d_mode_mbps 0x124c 32 v1.1 ireal
+max_symrate_rev_c_mode_msps 0x1250 32 v1.1 ireal
+
+# image compression capability registers
+compression_capability 0x1300
+- b dpcm_pcm_simple 0
+
+# test mode capability registers
+test_mode_capability 0x1310 16
+- b solid_color 0
+- b color_bars 1
+- b fade_to_grey 2
+- b pn9 3
+- b color_tile 5
+pn9_data_format1 0x1312
+pn9_data_format2 0x1313
+pn9_data_format3 0x1314
+pn9_data_format4 0x1315
+pn9_misc_capability 0x1316
+- f num_pixels 0 2
+- b compression 3
+test_pattern_capability 0x1317 v1.1
+- b no_repeat 1
+pattern_size_div_m1 0x1318 v1.1
+
+# fifo capability registers
+fifo_support_capability 0x1502
+- e none 0
+- e derating 1
+- e derating_overrating 2
+
+# csi-2 capability registers
+phy_ctrl_capability 0x1600
+- b auto_phy_ctl 0
+- b ui_phy_ctl 1
+- b dphy_time_ui_reg_1_ctl 2
+- b dphy_time_ui_reg_2_ctl 3
+- b dphy_time_ctl 4
+- b dphy_ext_time_ui_reg_1_ctl 5
+- b dphy_ext_time_ui_reg_2_ctl 6
+- b dphy_ext_time_ctl 7
+csi_dphy_lane_mode_capability 0x1601
+- b 1_lane 0
+- b 2_lane 1
+- b 3_lane 2
+- b 4_lane 3
+- b 5_lane 4
+- b 6_lane 5
+- b 7_lane 6
+- b 8_lane 7
+csi_signaling_mode_capability 0x1602
+- b csi_dphy 2
+- b csi_cphy 3
+fast_standby_capability 0x1603
+- e no_frame_truncation 0
+- e frame_truncation 1
+csi_address_control_capability 0x1604
+- b cci_addr_change 0
+- b 2nd_cci_addr 1
+- b sw_changeable_2nd_cci_addr 2
+data_type_capability 0x1605
+- b dpcm_programmable 0
+- b bottom_embedded_dt_programmable 1
+- b bottom_embedded_vc_programmable 2
+- b ext_vc_range 3
+csi_cphy_lane_mode_capability 0x1606
+- b 1_lane 0
+- b 2_lane 1
+- b 3_lane 2
+- b 4_lane 3
+- b 5_lane 4
+- b 6_lane 5
+- b 7_lane 6
+- b 8_lane 7
+emb_data_capability 0x1607 v1.1
+- b two_bytes_per_raw16 0
+- b two_bytes_per_raw20 1
+- b two_bytes_per_raw24 2
+- b no_one_byte_per_raw16 3
+- b no_one_byte_per_raw20 4
+- b no_one_byte_per_raw24 5
+max_per_lane_bitrate_lane_d_mode_mbps(n) 0x1608 32 ireal
+- l n 0 7 4 4,0x32
+temp_sensor_capability 0x1618
+- b supported 0
+- b CCS_format 1
+- b reset_0x80 2
+max_per_lane_bitrate_lane_c_mode_mbps(n) 0x161a 32 ireal
+- l n 0 7 4 4,0x30
+dphy_equalization_capability 0x162b
+- b equalization_ctrl 0
+- b eq1 1
+- b eq2 2
+cphy_equalization_capability 0x162c
+- b equalization_ctrl 0
+dphy_preamble_capability 0x162d
+- b preamble_seq_ctrl 0
+dphy_ssc_capability 0x162e
+- b supported 0
+cphy_calibration_capability 0x162f
+- b manual 0
+- b manual_streaming 1
+- b format_1_ctrl 2
+- b format_2_ctrl 3
+- b format_3_ctrl 4
+dphy_calibration_capability 0x1630
+- b manual 0
+- b manual_streaming 1
+- b alternate_seq 2
+phy_ctrl_capability_2 0x1631
+- b tgr_length 0
+- b tgr_preamble_prog_seq 1
+- b extra_cphy_manual_timing 2
+- b clock_based_manual_cdphy 3
+- b clock_based_manual_dphy 4
+- b clock_based_manual_cphy 5
+- b manual_lp_dphy 6
+- b manual_lp_cphy 7
+lrte_cphy_capability 0x1632
+- b pdq_short 0
+- b spacer_short 1
+- b pdq_long 2
+- b spacer_long 3
+- b spacer_no_pdq 4
+lrte_dphy_capability 0x1633
+- b pdq_short_opt1 0
+- b spacer_short_opt1 1
+- b pdq_long_opt1 2
+- b spacer_long_opt1 3
+- b spacer_short_opt2 4
+- b spacer_long_opt2 5
+- b spacer_no_pdq_opt1 6
+- b spacer_variable_opt2 7
+alps_capability_dphy 0x1634
+- e lvlp_not_supported 0 0x3
+- e lvlp_supported 1 0x3
+- e controllable_lvlp 2 0x3
+alps_capability_cphy 0x1635
+- e lvlp_not_supported 0 0x3
+- e lvlp_supported 1 0x3
+- e controllable_lvlp 2 0x3
+- e alp_not_supported 0xc 0xc
+- e alp_supported 0xd 0xc
+- e controllable_alp 0xe 0xc
+scrambling_capability 0x1636
+- b scrambling_supported 0
+- f max_seeds_per_lane_c 1 2
+- e 1 0
+- e 4 3
+- f num_seed_regs 3 5
+- e 0 0
+- e 1 1
+- e 4 4
+- b num_seed_per_lane 6
+dphy_manual_constant 0x1637
+cphy_manual_constant 0x1638
+CSI2_interface_capability_misc 0x1639 v1.1
+- b eotp_short_pkt_opt2 0
+PHY_ctrl_capability_3 0x165c v1.1
+- b dphy_timing_not_multiple 0
+- b dphy_min_timing_value_1 1
+- b twakeup_supported 2
+- b tinit_supported 3
+- b ths_exit_supported 4
+- b cphy_timing_not_multiple 5
+- b cphy_min_timing_value_1 6
+dphy_sf 0x165d v1.1
+cphy_sf 0x165e v1.1
+- f twakeup 0 3
+- f tinit 4 7
+dphy_limits_1 0x165f v1.1
+- f ths_prepare 0 3
+- f ths_zero 4 7
+dphy_limits_2 0x1660 v1.1
+- f ths_trail 0 3
+- f tclk_trail_min 4 7
+dphy_limits_3 0x1661 v1.1
+- f tclk_prepare 0 3
+- f tclk_zero 4 7
+dphy_limits_4 0x1662 v1.1
+- f tclk_post 0 3
+- f tlpx 4 7
+dphy_limits_5 0x1663 v1.1
+- f ths_exit 0 3
+- f twakeup 4 7
+dphy_limits_6 0x1664 v1.1
+- f tinit 0 3
+cphy_limits_1 0x1665 v1.1
+- f t3_prepare_max 0 3
+- f t3_lpx_max 4 7
+cphy_limits_2 0x1666 v1.1
+- f ths_exit_max 0 3
+- f twakeup_max 4 7
+cphy_limits_3 0x1667 v1.1
+- f tinit_max 0 3
+
+# binning capability registers
+min_frame_length_lines_bin 0x1700 16
+max_frame_length_lines_bin 0x1702 16
+min_line_length_pck_bin 0x1704 16
+max_line_length_pck_bin 0x1706 16
+min_line_blanking_pck_bin 0x1708 16
+fine_integration_time_min_bin 0x170a 16
+fine_integration_time_max_margin_bin 0x170c 16
+binning_capability 0x1710
+- e unsupported 0
+- e binning_then_subsampling 1
+- e subsampling_then_binning 2
+binning_weighting_capability 0x1711
+- b averaged 0
+- b summed 1
+- b bayer_corrected 2
+- b module_specific_weight 3
+binning_sub_types 0x1712
+binning_sub_type(n) 0x1713
+- l n 0 63 1
+- f row 0 3
+- f column 4 7
+binning_weighting_mono_capability 0x1771 v1.1
+- b averaged 0
+- b summed 1
+- b bayer_corrected 2
+- b module_specific_weight 3
+binning_sub_types_mono 0x1772 v1.1
+binning_sub_type_mono(n) 0x1773 v1.1 f
+- l n 0 63 1
+
+# data transfer interface capability registers
+data_transfer_if_capability 0x1800
+- b supported 0
+- b polling 2
+
+# sensor correction capability registers
+shading_correction_capability 0x1900
+- b color_shading 0
+- b luminance_correction 1
+green_imbalance_capability 0x1901
+- b supported 0
+module_specific_correction_capability 0x1903
+defect_correction_capability 0x1904 16
+- b mapped_defect 0
+- b dynamic_couplet 2
+- b dynamic_single 5
+- b combined_dynamic 8
+defect_correction_capability_2 0x1906 16
+- b dynamic_triplet 3
+nf_capability 0x1908
+- b luma 0
+- b chroma 1
+- b combined 2
+
+# optical black readout capability registers
+ob_readout_capability 0x1980
+- b controllable_readout 0
+- b visible_pixel_readout 1
+- b different_vc_readout 2
+- b different_dt_readout 3
+- b prog_data_format 4
+
+# color feedback capability registers
+color_feedback_capability 0x1987
+- b kelvin 0
+- b awb_gain 1
+
+# cfa pattern capability registers
+CFA_pattern_capability 0x1990 v1.1
+- e bayer 0
+- e monochrome 1
+- e 4x4_quad_bayer 2
+- e vendor_specific 3
+CFA_pattern_conversion_capability 0x1991 v1.1
+- b bayer 0
+
+# timer capability registers
+flash_mode_capability 0x1a02
+- b single_strobe 0
+sa_strobe_mode_capability 0x1a03
+- b fixed_width 0
+- b edge_ctrl 1
+
+# soft reset capability registers
+reset_max_delay 0x1a10 v1.1
+reset_min_time 0x1a11 v1.1
+
+# pdaf capability registers
+pdaf_capability_1 0x1b80
+- b supported 0
+- b processed_bottom_embedded 1
+- b processed_interleaved 2
+- b raw_bottom_embedded 3
+- b raw_interleaved 4
+- b visible_pdaf_correction 5
+- b vc_interleaving 6
+- b dt_interleaving 7
+pdaf_capability_2 0x1b81
+- b ROI 0
+- b after_digital_crop 1
+- b ctrl_retimed 2
+
+# bracketing interface capability registers
+bracketing_lut_capability_1 0x1c00
+- b coarse_integration 0
+- b global_analog_gain 1
+- b flash 4
+- b global_digital_gain 5
+- b alternate_global_analog_gain 6
+bracketing_lut_capability_2 0x1c01
+- b single_bracketing_mode 0
+- b looped_bracketing_mode 1
+bracketing_lut_size 0x1c02
diff --git a/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs b/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs
new file mode 100755
index 000000000000..3d6a2a7aac3a
--- /dev/null
+++ b/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs
@@ -0,0 +1,433 @@
+#!/usr/bin/perl -w
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
+# Copyright (C) 2019--2020 Intel Corporation
+
+use Getopt::Long qw(:config no_ignore_case);
+use File::Basename;
+
+my $ccsregs = "ccs-regs.txt";
+my $header;
+my $regarray;
+my $limitc;
+my $limith;
+my $kernel;
+my $help;
+
+GetOptions("ccsregs|c=s" => \$ccsregs,
+ "header|e=s" => \$header,
+ "regarray|r=s" => \$regarray,
+ "limitc|l=s" => \$limitc,
+ "limith|L=s" => \$limith,
+ "kernel|k" => \$kernel,
+ "help|h" => \$help) or die "can't parse options";
+
+$help = 1 if ! defined $header || ! defined $limitc || ! defined $limith;
+
+if (defined $help) {
+ print <<EOH
+$0 - Create CCS register definitions for C
+
+usage: $0 -c ccs-regs.txt -e header -r regarray -l limit-c -L limit-header [-k]
+
+ -c ccs register file
+ -e header file name
+ -r register description array file name
+ -l limit and capability array file name
+ -L limit and capability header file name
+ -k generate files for kernel space consumption
+EOH
+ ;
+ exit 0;
+}
+
+my $lh_hdr = ! defined $kernel
+ ? '#include "ccs-os.h"' . "\n"
+ : "#include <linux/bits.h>\n#include <linux/types.h>\n";
+my $uint32_t = ! defined $kernel ? 'uint32_t' : 'u32';
+my $uint16_t = ! defined $kernel ? 'uint16_t' : 'u16';
+
+open(my $R, "< $ccsregs") or die "can't open $ccsregs";
+
+open(my $H, "> $header") or die "can't open $header";
+my $A;
+if (defined $regarray) {
+ open($A, "> $regarray") or die "can't open $regarray";
+}
+open(my $LC, "> $limitc") or die "can't open $limitc";
+open(my $LH, "> $limith") or die "can't open $limith";
+
+my %this;
+
+sub is_limit_reg($) {
+ my $addr = hex $_[0];
+
+ return 0 if $addr < 0x40; # weed out status registers
+ return 0 if $addr >= 0x100 && $addr < 0xfff; # weed out configuration registers
+
+ return 1;
+}
+
+my $uc_header = basename uc $header;
+$uc_header =~ s/[^A-Z0-9]/_/g;
+
+my $copyright = "/* Copyright (C) 2019--2020 Intel Corporation */\n";
+my $license = "SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause";
+
+for my $fh ($A, $LC) {
+ print $fh "// $license\n$copyright\n" if defined $fh;
+}
+
+for my $fh ($H, $LH) {
+ print $fh "/* $license */\n$copyright\n";
+}
+
+sub bit_def($) {
+ my $bit = shift @_;
+
+ return "BIT($bit)" if defined $kernel;
+ return "(1U << $bit)" if $bit =~ /^[a-zA-Z0-9_]+$/;
+ return "(1U << ($bit))";
+}
+
+print $H <<EOF
+#ifndef __${uc_header}__
+#define __${uc_header}__
+
+EOF
+ ;
+
+print $H "#include <linux/bits.h>\n\n" if defined $kernel;
+
+print $H <<EOF
+#define CCS_FL_BASE 16
+EOF
+ ;
+
+print $H "#define CCS_FL_16BIT " . bit_def("CCS_FL_BASE") . "\n";
+print $H "#define CCS_FL_32BIT " . bit_def("CCS_FL_BASE + 1") . "\n";
+print $H "#define CCS_FL_FLOAT_IREAL " . bit_def("CCS_FL_BASE + 2") . "\n";
+print $H "#define CCS_FL_IREAL " . bit_def("CCS_FL_BASE + 3") . "\n";
+
+print $H <<EOF
+#define CCS_R_ADDR(r) ((r) & 0xffff)
+
+EOF
+ ;
+
+print $A <<EOF
+#include <stdint.h>
+#include <stdio.h>
+#include "ccs-extra.h"
+#include "ccs-regs.h"
+
+EOF
+ if defined $A;
+
+my $uc_limith = basename uc $limith;
+$uc_limith =~ s/[^A-Z0-9]/_/g;
+
+print $LH <<EOF
+#ifndef __${uc_limith}__
+#define __${uc_limith}__
+
+$lh_hdr
+struct ccs_limit {
+ $uint32_t reg;
+ $uint16_t size;
+ $uint16_t flags;
+ const char *name;
+};
+
+EOF
+ ;
+print $LH "#define CCS_L_FL_SAME_REG " . bit_def(0) . "\n\n";
+
+print $LH <<EOF
+extern const struct ccs_limit ccs_limits[];
+
+EOF
+ ;
+
+print $LC <<EOF
+#include "ccs-limits.h"
+#include "ccs-regs.h"
+
+const struct ccs_limit ccs_limits[] = {
+EOF
+ ;
+
+my $limitcount = 0;
+my $argdescs;
+my $reglist = "const struct ccs_reg_desc ccs_reg_desc[] = {\n";
+
+sub name_split($$) {
+ my ($name, $addr) = @_;
+ my $args;
+
+ $name =~ /([^\(]+?)(\(.*)/;
+ ($name, $args) = ($1, $2);
+ $args = [split /,\s*/, $args];
+ foreach my $t (@$args) {
+ $t =~ s/[\(\)]//g;
+ $t =~ s/\//\\\//g;
+ }
+
+ return ($name, $addr, $args);
+}
+
+sub tabconv($) {
+ $_ = shift;
+
+ my @l = split "\n", $_;
+
+ map {
+ s/ {8,8}/\t/g;
+ s/\t\K +//;
+ } @l;
+
+ return (join "\n", @l) . "\n";
+}
+
+sub elem_size(@) {
+ my @flags = @_;
+
+ return 2 if grep /^16$/, @flags;
+ return 4 if grep /^32$/, @flags;
+ return 1;
+}
+
+sub arr_size($) {
+ my $this = $_[0];
+ my $size = $this->{elsize};
+ my $h = $this->{argparams};
+
+ foreach my $arg (@{$this->{args}}) {
+ my $apref = $h->{$arg};
+
+ $size *= $apref->{max} - $apref->{min} + 1;
+ }
+
+ return $size;
+}
+
+sub print_args($$$) {
+ my ($this, $postfix, $is_same_reg) = @_;
+ my ($args, $argparams, $name) =
+ ($this->{args}, $this->{argparams}, $this->{name});
+ my $varname = "ccs_reg_arg_" . (lc $name) . $postfix;
+ my @mins;
+ my @sorted_args = @{$this->{sorted_args}};
+ my $lim_arg;
+ my $size = arr_size($this);
+
+ $argdescs .= "static const struct ccs_reg_arg " . $varname . "[] = {\n";
+
+ foreach my $sorted_arg (@sorted_args) {
+ push @mins, $argparams->{$sorted_arg}->{min};
+ }
+
+ foreach my $sorted_arg (@sorted_args) {
+ my $h = $argparams->{$sorted_arg};
+
+ $argdescs .= "\t{ \"$sorted_arg\", $h->{min}, $h->{max}, $h->{elsize} },\n";
+
+ $lim_arg .= defined $lim_arg ? ", $h->{min}" : "$h->{min}";
+ }
+
+ $argdescs .= "};\n\n";
+
+ $reglist .= "\t{ CCS_R_" . (uc $name) . "(" . (join ",", (@mins)) .
+ "), $size, sizeof($varname) / sizeof(*$varname)," .
+ " \"" . (lc $name) . "\", $varname },\n";
+
+ print $LC tabconv sprintf "\t{ CCS_R_" . (uc $name) . "($lim_arg), " .
+ $size . ", " . ($is_same_reg ? "CCS_L_FL_SAME_REG" : "0") .
+ ", \"$name" . (defined $this->{discontig} ? " $lim_arg" : "") . "\" },\n"
+ if is_limit_reg $this->{base_addr};
+}
+
+my $hdr_data;
+
+while (<$R>) {
+ chop;
+ s/^\s*//;
+ next if /^[#;]/ || /^$/;
+ if (s/^-\s*//) {
+ if (s/^b\s*//) {
+ my ($bit, $addr) = split /\t+/;
+ $bit = uc $bit;
+ $hdr_data .= sprintf "#define %-62s %s", "CCS_" . (uc ${this{name}}) ."_$bit", bit_def($addr) . "\n";
+ } elsif (s/^f\s*//) {
+ s/[,\.-]/_/g;
+ my @a = split /\s+/;
+ my ($msb, $lsb, $this_field) = reverse @a;
+ @a = ( { "name" => "SHIFT", "addr" => $lsb, "fmt" => "%uU", },
+ { "name" => "MASK", "addr" => (1 << ($msb + 1)) - 1 - ((1 << $lsb) - 1), "fmt" => "0x%" . join(".", ($this{"elsize"} >> 2) x 2) . "x" } );
+ $this{"field"} = $this_field;
+ foreach my $ar (@a) {
+ #print $ar->{fmt}."\n";
+ $hdr_data .= sprintf "#define %-62s " . $ar->{"fmt"} . "\n", "CCS_" . (uc $this{"name"}) . (defined $this_field ? "_" . uc $this_field : "") . "_" . $ar->{"name"}, $ar->{"addr"} . "\n";
+ }
+ } elsif (s/^e\s*//) {
+ s/[,\.-]/_/g;
+ my ($enum, $addr) = split /\s+/;
+ $enum = uc $enum;
+ $hdr_data .= sprintf "#define %-62s %s", "CCS_" . (uc ${this{name}}) . (defined $this{"field"} ? "_" . uc $this{"field"} : "") ."_$enum", $addr . ($addr =~ /0x/i ? "" : "U") . "\n";
+ } elsif (s/^l\s*//) {
+ my ($arg, $min, $max, $elsize, @discontig) = split /\s+/;
+ my $size;
+
+ foreach my $num ($min, $max) {
+ $num = hex $num if $num =~ /0x/i;
+ }
+
+ $hdr_data .= sprintf "#define %-62s %s", "CCS_LIM_" . (uc ${this{name}} . "_MIN_$arg"), $min . ($min =~ /0x/i ? "" : "U") . "\n";
+ $hdr_data .= sprintf "#define %-62s %s", "CCS_LIM_" . (uc ${this{name}} . "_MAX_$arg"), $max . ($max =~ /0x/i ? "" : "U") . "\n";
+
+ my $h = $this{argparams};
+
+ $h->{$arg} = { "min" => $min,
+ "max" => $max,
+ "elsize" => $elsize =~ /^0x/ ? hex $elsize : $elsize,
+ "discontig" => \@discontig };
+
+ $this{discontig} = $arg if @discontig;
+
+ next if $#{$this{args}} + 1 != scalar keys %{$this{argparams}};
+
+ my $reg_formula = "($this{addr}";
+ my $lim_formula;
+
+ foreach my $arg (@{$this{args}}) {
+ my $d = $h->{$arg}->{discontig};
+ my $times = $h->{$arg}->{elsize} != 1 ?
+ " * " . $h->{$arg}->{elsize} : "";
+
+ if (@$d) {
+ my ($lim, $offset) = split /,/, $d->[0];
+
+ $reg_formula .= " + (($arg) < $lim ? ($arg)$times : $offset + (($arg) - $lim)$times)";
+ } else {
+ $reg_formula .= " + ($arg)$times";
+ }
+
+ $lim_formula .= (defined $lim_formula ? " + " : "") . "($arg)$times";
+ }
+
+ $reg_formula .= ")\n";
+ $lim_formula =~ s/^\(([a-z0-9]+)\)$/$1/i;
+
+ print $H tabconv sprintf("#define %-62s %s", "CCS_R_" . (uc $this{name}) .
+ $this{arglist}, $reg_formula);
+
+ print $H tabconv $hdr_data;
+ undef $hdr_data;
+
+ # Sort arguments in descending order by size
+ @{$this{sorted_args}} = sort {
+ $h->{$a}->{elsize} <= $h->{$b}->{elsize}
+ } @{$this{args}};
+
+ if (defined $this{discontig}) {
+ my $da = $this{argparams}->{$this{discontig}};
+ my ($first_discontig) = split /,/, $da->{discontig}->[0];
+ my $max = $da->{max};
+
+ $da->{max} = $first_discontig - 1;
+ print_args(\%this, "", 0);
+
+ $da->{min} = $da->{max} + 1;
+ $da->{max} = $max;
+ print_args(\%this, $first_discontig, 1);
+ } else {
+ print_args(\%this, "", 0);
+ }
+
+ next unless is_limit_reg $this{base_addr};
+
+ print $LH tabconv sprintf "#define %-63s%s\n",
+ "CCS_L_" . (uc $this{name}) . "_OFFSET(" .
+ (join ", ", @{$this{args}}) . ")", "($lim_formula)";
+ }
+
+ if (! @{$this{args}}) {
+ print $H tabconv($hdr_data);
+ undef $hdr_data;
+ }
+
+ next;
+ }
+
+ my ($name, $addr, @flags) = split /\t+/, $_;
+ my $args = [];
+
+ my $sp;
+
+ ($name, $addr, $args) = name_split($name, $addr) if /\(.*\)/;
+
+ $name =~ s/[,\.-]/_/g;
+
+ my $flagstring = "";
+ my $size = elem_size(@flags);
+ $flagstring .= "| CCS_FL_16BIT " if $size eq "2";
+ $flagstring .= "| CCS_FL_32BIT " if $size eq "4";
+ $flagstring .= "| CCS_FL_FLOAT_IREAL " if grep /^float_ireal$/, @flags;
+ $flagstring .= "| CCS_FL_IREAL " if grep /^ireal$/, @flags;
+ $flagstring =~ s/^\| //;
+ $flagstring =~ s/ $//;
+ $flagstring = "($flagstring)" if $flagstring =~ /\|/;
+ my $base_addr = $addr;
+ $addr = "($addr | $flagstring)" if $flagstring ne "";
+
+ my $arglist = @$args ? "(" . (join ", ", @$args) . ")" : "";
+ $hdr_data .= sprintf "#define %-62s %s\n", "CCS_R_" . (uc $name), $addr
+ if !@$args;
+
+ $name =~ s/\(.*//;
+
+ %this = ( name => $name,
+ addr => $addr,
+ base_addr => $base_addr,
+ argparams => {},
+ args => $args,
+ arglist => $arglist,
+ elsize => $size,
+ );
+
+ if (!@$args) {
+ $reglist .= "\t{ CCS_R_" . (uc $name) . ", 1, 0, \"" . (lc $name) . "\", NULL },\n";
+ print $H tabconv $hdr_data;
+ undef $hdr_data;
+
+ print $LC tabconv sprintf "\t{ CCS_R_" . (uc $name) . ", " .
+ $this{elsize} . ", 0, \"$name\" },\n"
+ if is_limit_reg $this{base_addr};
+ }
+
+ print $LH tabconv sprintf "#define %-63s%s\n",
+ "CCS_L_" . (uc $this{name}), $limitcount++
+ if is_limit_reg $this{base_addr};
+}
+
+if (defined $A) {
+ print $A $argdescs, $reglist;
+
+ print $A "\t{ 0 }\n";
+
+ print $A "};\n";
+}
+
+print $H "\n#endif /* __${uc_header}__ */\n";
+
+print $LH tabconv sprintf "#define %-63s%s\n", "CCS_L_LAST", $limitcount;
+
+print $LH "\n#endif /* __${uc_limith}__ */\n";
+
+print $LC "\t{ 0 } /* Guardian */\n";
+print $LC "};\n";
+
+close($R);
+close($H);
+close($A) if defined $A;
+close($LC);
+close($LH);
diff --git a/MAINTAINERS b/MAINTAINERS
index 352b8eaa21f7..1a5455e1c664 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16135,6 +16135,7 @@ M: Sakari Ailus <sakari.ailus@linux.intel.com>
L: linux-media@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
+F: Documentation/driver-api/media/drivers/ccs/
F: drivers/media/i2c/smiapp-pll.c
F: drivers/media/i2c/smiapp-pll.h
F: drivers/media/i2c/smiapp/
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v2 01/29] ccs: Add the generator for CCS register definitions and limits
2020-11-27 10:32 ` [PATCH v2 01/29] ccs: Add the generator for CCS register definitions and limits Sakari Ailus
@ 2020-12-02 14:17 ` Mauro Carvalho Chehab
2020-12-02 14:46 ` Sakari Ailus
0 siblings, 1 reply; 32+ messages in thread
From: Mauro Carvalho Chehab @ 2020-12-02 14:17 UTC (permalink / raw)
To: Sakari Ailus; +Cc: linux-media, hverkuil
Em Fri, 27 Nov 2020 12:32:57 +0200
Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
> Add register definitions of the MIPI CCS 1.1 standard.
>
> The CCS driver makes extended use of device's capability registers that
> are dependent on CCS version. This involves having an in-memory data
> structure for limit and capability information, creating that data
> structure and accessing it.
>
> The register definitions as well as the definitions of this data structure
> are generated from a text file using a Perl script. Add the generator
> script to make it easy to update the generated files.
>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
> .../driver-api/media/drivers/ccs/ccs-regs.txt | 1041 +++++++++++++++++
> .../driver-api/media/drivers/ccs/mk-ccs-regs | 433 +++++++
> MAINTAINERS | 1 +
> 3 files changed, 1475 insertions(+)
> create mode 100644 Documentation/driver-api/media/drivers/ccs/ccs-regs.txt
> create mode 100755 Documentation/driver-api/media/drivers/ccs/mk-ccs-regs
>
> diff --git a/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt b/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt
> new file mode 100644
> index 000000000000..93f0131aa304
> --- /dev/null
> +++ b/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt
> @@ -0,0 +1,1041 @@
> +# Copyright (C) 2019--2020 Intel Corporation
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
Whenever technically possible, the SPDX header should be the first
line.
-
With regards to css-regs.txt file itself, I think it should be
added on a css-specific ReST file (index.rst?) using the
.. include
directive (or a similar one).
Regards,
Mauro
> +
> +# register rflags
> +# - f field LSB MSB rflags
> +# - e enum value # after a field
> +# - e enum value [LSB MSB]
> +# - b bool bit
> +# - l arg name min max elsize [discontig...]
> +#
> +# rflags
> +# 8, 16, 32 register bits (default is 8)
> +# v1.1 defined in version 1.1
> +# f formula
> +# float_ireal iReal or IEEE 754; 32 bits
> +# ireal unsigned iReal
> +
> +# general status registers
> +module_model_id 0x0000 16
> +module_revision_number_major 0x0002 8
> +frame_count 0x0005 8
> +pixel_order 0x0006 8
For instance, the above could be, instead:
.. general status registers
::
module_model_id 0x0000 16
module_revision_number_major 0x0002 8
frame_count 0x0005 8
pixel_order 0x0006 8
(which should be easy to parse)
or, even better:
general status registers:
==================================== ====== ==
module_model_id 0x0000 16
module_revision_number_major 0x0002 8
frame_count 0x0005 8
pixel_order 0x0006 8
==================================== ====== ==
Parsing the later could be a little harder, although it would allow
placing the file inside the documentation, with could be interesting.
> +- e GRBG 0
> +- e RGGB 1
> +- e BGGR 2
> +- e GBRG 3
> +MIPI_CCS_version 0x0007 8
> +- e v1_0 0x10
> +- e v1_1 0x11
> +- f major 4 7
> +- f minor 0 3
> +data_pedestal 0x0008 16
> +module_manufacturer_id 0x000e 16
> +module_revision_number_minor 0x0010 8
> +module_date_year 0x0012 8
> +module_date_month 0x0013 8
> +module_date_day 0x0014 8
> +module_date_phase 0x0015 8
> +- f 0 2
> +- e ts 0
> +- e es 1
> +- e cs 2
> +- e mp 3
> +sensor_model_id 0x0016 16
> +sensor_revision_number 0x0018 8
> +sensor_firmware_version 0x001a 8
> +serial_number 0x001c 32
> +sensor_manufacturer_id 0x0020 16
> +sensor_revision_number_16 0x0022 16
> +
> +# frame format description registers
> +frame_format_model_type 0x0040 8
> +- e 2-byte 1
> +- e 4-byte 2
> +frame_format_model_subtype 0x0041 8
> +- f rows 0 3
> +- f columns 4 7
> +frame_format_descriptor(n) 0x0042 16 f
> +- l n 0 14 2
> +- f pixels 0 11
> +- f pcode 12 15
> +- e embedded 1
> +- e dummy_pixel 2
> +- e black_pixel 3
> +- e dark_pixel 4
> +- e visible_pixel 5
> +- e manuf_specific_0 8
> +- e manuf_specific_1 9
> +- e manuf_specific_2 10
> +- e manuf_specific_3 11
> +- e manuf_specific_4 12
> +- e manuf_specific_5 13
> +- e manuf_specific_6 14
> +frame_format_descriptor_4(n) 0x0060 32 f
> +- l n 0 7 4
> +- f pixels 0 15
> +- f pcode 28 31
> +- e embedded 1
> +- e dummy_pixel 2
> +- e black_pixel 3
> +- e dark_pixel 4
> +- e visible_pixel 5
> +- e manuf_specific_0 8
> +- e manuf_specific_1 9
> +- e manuf_specific_2 10
> +- e manuf_specific_3 11
> +- e manuf_specific_4 12
> +- e manuf_specific_5 13
> +- e manuf_specific_6 14
> +
> +# analog gain description registers
> +analog_gain_capability 0x0080 16
> +- e global 0
> +- e alternate_global 2
> +analog_gain_code_min 0x0084 16
> +analog_gain_code_max 0x0086 16
> +analog_gain_code_step 0x0088 16
> +analog_gain_type 0x008a 16
> +analog_gain_m0 0x008c 16
> +analog_gain_c0 0x008e 16
> +analog_gain_m1 0x0090 16
> +analog_gain_c1 0x0092 16
> +analog_linear_gain_min 0x0094 16 v1.1
> +analog_linear_gain_max 0x0096 16 v1.1
> +analog_linear_gain_step_size 0x0098 16 v1.1
> +analog_exponential_gain_min 0x009a 16 v1.1
> +analog_exponential_gain_max 0x009c 16 v1.1
> +analog_exponential_gain_step_size 0x009e 16 v1.1
> +
> +# data format description registers
> +data_format_model_type 0x00c0 8
> +- e normal 1
> +- e extended 2
> +data_format_model_subtype 0x00c1 8
> +- f rows 0 3
> +- f columns 4 7
> +data_format_descriptor(n) 0x00c2 16 f
> +- l n 0 15 2
> +- f compressed 0 7
> +- f uncompressed 8 15
> +
> +# general set-up registers
> +mode_select 0x0100 8
> +- e software_standby 0
> +- e streaming 1
> +image_orientation 0x0101 8
> +- b horizontal_mirror 0
> +- b vertical_flip 1
> +software_reset 0x0103 8
> +- e off 0
> +- e on 1
> +grouped_parameter_hold 0x0104 8
> +mask_corrupted_frames 0x0105 8
> +- e allow 0
> +- e mask 1
> +fast_standby_ctrl 0x0106 8
> +- e complete_frames 0
> +- e frame_truncation 1
> +CCI_address_ctrl 0x0107 8
> +2nd_CCI_if_ctrl 0x0108 8
> +- b enable 0
> +- b ack 1
> +2nd_CCI_address_ctrl 0x0109 8
> +CSI_channel_identifier 0x0110 8
> +CSI_signaling_mode 0x0111 8
> +- e csi_2_dphy 2
> +- e csi_2_cphy 3
> +CSI_data_format 0x0112 16
> +CSI_lane_mode 0x0114 8
> +DPCM_Frame_DT 0x011d 8
> +Bottom_embedded_data_DT 0x011e 8
> +Bottom_embedded_data_VC 0x011f 8
> +
> +gain_mode 0x0120 8
> +- e global 0
> +- e alternate 1
> +ADC_bit_depth 0x0121 8
> +emb_data_ctrl 0x0122 v1.1
> +- b raw8_packing_for_raw16 0
> +- b raw10_packing_for_raw20 1
> +- b raw12_packing_for_raw24 2
> +
> +GPIO_TRIG_mode 0x0130 8
> +extclk_frequency_mhz 0x0136 16 ireal
> +temp_sensor_ctrl 0x0138 8
> +- b enable 0
> +temp_sensor_mode 0x0139 8
> +temp_sensor_output 0x013a 8
> +
> +# integration time registers
> +fine_integration_time 0x0200 16
> +coarse_integration_time 0x0202 16
> +
> +# analog gain registers
> +analog_gain_code_global 0x0204 16
> +analog_linear_gain_global 0x0206 16 v1.1
> +analog_exponential_gain_global 0x0208 16 v1.1
> +
> +# digital gain registers
> +digital_gain_global 0x020e 16
> +
> +# hdr control registers
> +Short_analog_gain_global 0x0216 16
> +Short_digital_gain_global 0x0218 16
> +
> +HDR_mode 0x0220 8
> +- b enabled 0
> +- b separate_analog_gain 1
> +- b upscaling 2
> +- b reset_sync 3
> +- b timing_mode 4
> +- b exposure_ctrl_direct 5
> +- b separate_digital_gain 6
> +HDR_resolution_reduction 0x0221 8
> +- f row 0 3
> +- f column 4 7
> +Exposure_ratio 0x0222 8
> +HDR_internal_bit_depth 0x0223 8
> +Direct_short_integration_time 0x0224 16
> +Short_analog_linear_gain_global 0x0226 16 v1.1
> +Short_analog_exponential_gain_global 0x0228 16 v1.1
> +
> +# clock set-up registers
> +vt_pix_clk_div 0x0300 16
> +vt_sys_clk_div 0x0302 16
> +pre_pll_clk_div 0x0304 16
> +#vt_pre_pll_clk_div 0x0304 16
> +pll_multiplier 0x0306 16
> +#vt_pll_multiplier 0x0306 16
> +op_pix_clk_div 0x0308 16
> +op_sys_clk_div 0x030a 16
> +op_pre_pll_clk_div 0x030c 16
> +op_pll_multiplier 0x031e 16
> +pll_mode 0x0310 8
> +- f 0 0
> +- e single 0
> +- e dual 1
> +op_pix_clk_div_rev 0x0312 16 v1.1
> +op_sys_clk_div_rev 0x0314 16 v1.1
> +
> +# frame timing registers
> +frame_length_lines 0x0340 16
> +line_length_pck 0x0342 16
> +
> +# image size registers
> +x_addr_start 0x0344 16
> +y_addr_start 0x0346 16
> +x_addr_end 0x0348 16
> +y_addr_end 0x034a 16
> +x_output_size 0x034c 16
> +y_output_size 0x034e 16
> +
> +# timing mode registers
> +Frame_length_ctrl 0x0350 8
> +- b automatic 0
> +Timing_mode_ctrl 0x0352 8
> +- b manual_readout 0
> +- b delayed_exposure 1
> +Start_readout_rs 0x0353 8
> +- b manual_readout_start 0
> +Frame_margin 0x0354 16
> +
> +# sub-sampling registers
> +x_even_inc 0x0380 16
> +x_odd_inc 0x0382 16
> +y_even_inc 0x0384 16
> +y_odd_inc 0x0386 16
> +
> +# monochrome readout registers
> +monochrome_en 0x0390 v1.1
> +- e enabled 0
> +
> +# image scaling registers
> +Scaling_mode 0x0400 16
> +- e no_scaling 0
> +- e horizontal 1
> +scale_m 0x0404 16
> +scale_n 0x0406 16
> +digital_crop_x_offset 0x0408 16
> +digital_crop_y_offset 0x040a 16
> +digital_crop_image_width 0x040c 16
> +digital_crop_image_height 0x040e 16
> +
> +# image compression registers
> +compression_mode 0x0500 16
> +- e none 0
> +- e dpcm_pcm_simple 1
> +
> +# test pattern registers
> +test_pattern_mode 0x0600 16
> +- e none 0
> +- e solid_color 1
> +- e color_bars 2
> +- e fade_to_grey 3
> +- e pn9 4
> +- e color_tile 5
> +test_data_red 0x0602 16
> +test_data_greenR 0x0604 16
> +test_data_blue 0x0606 16
> +test_data_greenB 0x0608 16
> +value_step_size_smooth 0x060a 8
> +value_step_size_quantised 0x060b 8
> +
> +# phy configuration registers
> +tclk_post 0x0800 8
> +ths_prepare 0x0801 8
> +ths_zero_min 0x0802 8
> +ths_trail 0x0803 8
> +tclk_trail_min 0x0804 8
> +tclk_prepare 0x0805 8
> +tclk_zero 0x0806 8
> +tlpx 0x0807 8
> +phy_ctrl 0x0808 8
> +- e auto 0
> +- e UI 1
> +- e manual 2
> +tclk_post_ex 0x080a 16
> +ths_prepare_ex 0x080c 16
> +ths_zero_min_ex 0x080e 16
> +ths_trail_ex 0x0810 16
> +tclk_trail_min_ex 0x0812 16
> +tclk_prepare_ex 0x0814 16
> +tclk_zero_ex 0x0816 16
> +tlpx_ex 0x0818 16
> +
> +# link rate register
> +requested_link_rate 0x0820 32 u16.16
> +
> +# equalization control registers
> +DPHY_equalization_mode 0x0824 8 v1.1
> +- b eq2 0
> +PHY_equalization_ctrl 0x0825 8 v1.1
> +- b enable 0
> +
> +# d-phy preamble control registers
> +DPHY_preamble_ctrl 0x0826 8 v1.1
> +- b enable 0
> +DPHY_preamble_length 0x0826 8 v1.1
> +
> +# d-phy spread spectrum control registers
> +PHY_SSC_ctrl 0x0828 8 v1.1
> +- b enable 0
> +
> +# manual lp control register
> +manual_LP_ctrl 0x0829 8 v1.1
> +- b enable 0
> +
> +# additional phy configuration registers
> +twakeup 0x082a v1.1
> +tinit 0x082b v1.1
> +ths_exit 0x082c v1.1
> +ths_exit_ex 0x082e 16 v1.1
> +
> +# phy calibration configuration registers
> +PHY_periodic_calibration_ctrl 0x0830 8
> +- b frame_blanking 0
> +PHY_periodic_calibration_interval 0x0831 8
> +PHY_init_calibration_ctrl 0x0832 8
> +- b stream_start 0
> +DPHY_calibration_mode 0x0833 8 v1.1
> +- b also_alternate 0
> +CPHY_calibration_mode 0x0834 8 v1.1
> +- e format_1 0
> +- e format_2 1
> +- e format_3 2
> +t3_calpreamble_length 0x0835 8 v1.1
> +t3_calpreamble_length_per 0x0836 8 v1.1
> +t3_calaltseq_length 0x0837 8 v1.1
> +t3_calaltseq_length_per 0x0838 8 v1.1
> +FM2_init_seed 0x083a 16 v1.1
> +t3_caludefseq_length 0x083c 16 v1.1
> +t3_caludefseq_length_per 0x083e 16 v1.1
> +
> +# c-phy manual control registers
> +TGR_Preamble_Length 0x0841 8
> +- b preamable_prog_seq 7
> +- f begin_preamble_length 0 5
> +TGR_Post_Length 0x0842 8
> +- f post_length 0 4
> +TGR_Preamble_Prog_Sequence(n2) 0x0843
> +- l n2 0 6 1
> +- f symbol_n_1 3 5
> +- f symbol_n 0 2
> +t3_prepare 0x084e 16
> +t3_lpx 0x0850 16
> +
> +# alps control register
> +ALPS_ctrl 0x085a 8
> +- b lvlp_dphy 0
> +- b lvlp_cphy 1
> +- b alp_cphy 2
> +
> +# lrte control registers
> +TX_REG_CSI_EPD_EN_SSP_cphy 0x0860 16
> +TX_REG_CSI_EPD_OP_SLP_cphy 0x0862 16
> +TX_REG_CSI_EPD_EN_SSP_dphy 0x0864 16
> +TX_REG_CSI_EPD_OP_SLP_dphy 0x0866 16
> +TX_REG_CSI_EPD_MISC_OPTION_cphy 0x0868 v1.1
> +TX_REG_CSI_EPD_MISC_OPTION_dphy 0x0869 v1.1
> +
> +# scrambling control registers
> +Scrambling_ctrl 0x0870
> +- b enabled 0
> +- f 2 3
> +- e 1_seed_cphy 0
> +- e 4_seed_cphy 3
> +lane_seed_value(seed, lane) 0x0872 16
> +- l seed 0 3 0x10
> +- l lane 0 7 0x2
> +
> +# usl control registers
> +TX_USL_REV_ENTRY 0x08c0 16 v1.1
> +TX_USL_REV_Clock_Counter 0x08c2 16 v1.1
> +TX_USL_REV_LP_Counter 0x08c4 16 v1.1
> +TX_USL_REV_Frame_Counter 0x08c6 16 v1.1
> +TX_USL_REV_Chronological_Timer 0x08c8 16 v1.1
> +TX_USL_FWD_ENTRY 0x08ca 16 v1.1
> +TX_USL_GPIO 0x08cc 16 v1.1
> +TX_USL_Operation 0x08ce 16 v1.1
> +- b reset 0
> +TX_USL_ALP_ctrl 0x08d0 16 v1.1
> +- b clock_pause 0
> +TX_USL_APP_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
> +TX_USL_SNS_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
> +USL_Clock_Mode_d_ctrl 0x08d2 v1.1
> +- b cont_clock_standby 0
> +- b cont_clock_vblank 1
> +- b cont_clock_hblank 2
> +
> +# binning configuration registers
> +binning_mode 0x0900 8
> +binning_type 0x0901 8
> +binning_weighting 0x0902 8
> +
> +# data transfer interface registers
> +data_transfer_if_1_ctrl 0x0a00 8
> +- b enable 0
> +- b write 1
> +- b clear_error 2
> +data_transfer_if_1_status 0x0a01 8
> +- b read_if_ready 0
> +- b write_if_ready 1
> +- b data_corrupted 2
> +- b improper_if_usage 3
> +data_transfer_if_1_page_select 0x0a02 8
> +data_transfer_if_1_data(p) 0x0a04 8 f
> +- l p 0 63 1
> +
> +# image processing and sensor correction configuration registers
> +shading_correction_en 0x0b00 8
> +- b enable 0
> +luminance_correction_level 0x0b01 8
> +green_imbalance_filter_en 0x0b02 8
> +- b enable 0
> +mapped_defect_correct_en 0x0b05 8
> +- b enable 0
> +single_defect_correct_en 0x0b06 8
> +- b enable 0
> +dynamic_couplet_correct_en 0x0b08 8
> +- b enable 0
> +combined_defect_correct_en 0x0b0a 8
> +- b enable 0
> +module_specific_correction_en 0x0b0c 8
> +- b enable 0
> +dynamic_triplet_defect_correct_en 0x0b13 8
> +- b enable 0
> +NF_ctrl 0x0b15 8
> +- b luma 0
> +- b chroma 1
> +- b combined 2
> +
> +# optical black pixel readout registers
> +OB_readout_control 0x0b30 8
> +- b enable 0
> +- b interleaving 1
> +OB_virtual_channel 0x0b31 8
> +OB_DT 0x0b32 8
> +OB_data_format 0x0b33 8
> +
> +# color temperature feedback registers
> +color_temperature 0x0b8c 16
> +absolute_gain_greenr 0x0b8e 16
> +absolute_gain_red 0x0b90 16
> +absolute_gain_blue 0x0b92 16
> +absolute_gain_greenb 0x0b94 16
> +
> +# cfa conversion registers
> +CFA_conversion_ctrl 0x0ba0 v1.1
> +- b bayer_conversion_enable 0
> +
> +# flash strobe and sa strobe control registers
> +flash_strobe_adjustment 0x0c12 8
> +flash_strobe_start_point 0x0c14 16
> +tflash_strobe_delay_rs_ctrl 0x0c16 16
> +tflash_strobe_width_high_rs_ctrl 0x0c18 16
> +flash_mode_rs 0x0c1a 8
> +- b continuous 0
> +- b truncate 1
> +- b async 3
> +flash_trigger_rs 0x0c1b 8
> +flash_status 0x0c1c 8
> +- b retimed 0
> +sa_strobe_mode 0x0c1d 8
> +- b continuous 0
> +- b truncate 1
> +- b async 3
> +- b adjust_edge 4
> +sa_strobe_start_point 0x0c1e 16
> +tsa_strobe_delay_ctrl 0x0c20 16
> +tsa_strobe_width_ctrl 0x0c22 16
> +sa_strobe_trigger 0x0c24 8
> +sa_strobe_status 0x0c25 8
> +- b retimed 0
> +tSA_strobe_re_delay_ctrl 0x0c30 16
> +tSA_strobe_fe_delay_ctrl 0x0c32 16
> +
> +# pdaf control registers
> +PDAF_ctrl 0x0d00 16
> +- b enable 0
> +- b processed 1
> +- b interleaved 2
> +- b visible_pdaf_correction 3
> +PDAF_VC 0x0d02 8
> +PDAF_DT 0x0d03 8
> +pd_x_addr_start 0x0d04 16
> +pd_y_addr_start 0x0d06 16
> +pd_x_addr_end 0x0d08 16
> +pd_y_addr_end 0x0d0a 16
> +
> +# bracketing interface configuration registers
> +bracketing_LUT_ctrl 0x0e00 8
> +bracketing_LUT_mode 0x0e01 8
> +- b continue_streaming 0
> +- b loop_mode 1
> +bracketing_LUT_entry_ctrl 0x0e02 8
> +bracketing_LUT_frame(n) 0x0e10 v1.1 f
> +- l n 0 0xef 1
> +
> +# integration time and gain parameter limit registers
> +integration_time_capability 0x1000 16
> +- b fine 0
> +coarse_integration_time_min 0x1004 16
> +coarse_integration_time_max_margin 0x1006 16
> +fine_integration_time_min 0x1008 16
> +fine_integration_time_max_margin 0x100a 16
> +
> +# digital gain parameter limit registers
> +digital_gain_capability 0x1081
> +- e none 0
> +- e global 2
> +digital_gain_min 0x1084 16
> +digital_gain_max 0x1086 16
> +digital_gain_step_size 0x1088 16
> +
> +# data pedestal capability registers
> +Pedestal_capability 0x10e0 8 v1.1
> +
> +# adc capability registers
> +ADC_capability 0x10f0 8
> +- b bit_depth_ctrl 0
> +ADC_bit_depth_capability 0x10f4 32 v1.1
> +
> +# video timing parameter limit registers
> +min_ext_clk_freq_mhz 0x1100 32 float_ireal
> +max_ext_clk_freq_mhz 0x1104 32 float_ireal
> +min_pre_pll_clk_div 0x1108 16
> +# min_vt_pre_pll_clk_div 0x1108 16
> +max_pre_pll_clk_div 0x110a 16
> +# max_vt_pre_pll_clk_div 0x110a 16
> +min_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
> +# min_vt_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
> +max_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
> +# max_vt_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
> +min_pll_multiplier 0x1114 16
> +# min_vt_pll_multiplier 0x1114 16
> +max_pll_multiplier 0x1116 16
> +# max_vt_pll_multiplier 0x1116 16
> +min_pll_op_clk_freq_mhz 0x1118 32 float_ireal
> +max_pll_op_clk_freq_mhz 0x111c 32 float_ireal
> +
> +# video timing set-up capability registers
> +min_vt_sys_clk_div 0x1120 16
> +max_vt_sys_clk_div 0x1122 16
> +min_vt_sys_clk_freq_mhz 0x1124 32 float_ireal
> +max_vt_sys_clk_freq_mhz 0x1128 32 float_ireal
> +min_vt_pix_clk_freq_mhz 0x112c 32 float_ireal
> +max_vt_pix_clk_freq_mhz 0x1130 32 float_ireal
> +min_vt_pix_clk_div 0x1134 16
> +max_vt_pix_clk_div 0x1136 16
> +clock_calculation 0x1138
> +- b lane_speed 0
> +- b link_decoupled 1
> +- b dual_pll_op_sys_ddr 2
> +- b dual_pll_op_pix_ddr 3
> +num_of_vt_lanes 0x1139
> +num_of_op_lanes 0x113a
> +op_bits_per_lane 0x113b 8 v1.1
> +
> +# frame timing parameter limits
> +min_frame_length_lines 0x1140 16
> +max_frame_length_lines 0x1142 16
> +min_line_length_pck 0x1144 16
> +max_line_length_pck 0x1146 16
> +min_line_blanking_pck 0x1148 16
> +min_frame_blanking_lines 0x114a 16
> +min_line_length_pck_step_size 0x114c
> +timing_mode_capability 0x114d
> +- b auto_frame_length 0
> +- b rolling_shutter_manual_readout 2
> +- b delayed_exposure_start 3
> +- b manual_exposure_embedded_data 4
> +frame_margin_max_value 0x114e 16
> +frame_margin_min_value 0x1150
> +gain_delay_type 0x1151
> +- e fixed 0
> +- e variable 1
> +
> +# output clock set-up capability registers
> +min_op_sys_clk_div 0x1160 16
> +max_op_sys_clk_div 0x1162 16
> +min_op_sys_clk_freq_mhz 0x1164 32 float_ireal
> +max_op_sys_clk_freq_mhz 0x1168 32 float_ireal
> +min_op_pix_clk_div 0x116c 16
> +max_op_pix_clk_div 0x116e 16
> +min_op_pix_clk_freq_mhz 0x1170 32 float_ireal
> +max_op_pix_clk_freq_mhz 0x1174 32 float_ireal
> +
> +# image size parameter limit registers
> +x_addr_min 0x1180 16
> +y_addr_min 0x1182 16
> +x_addr_max 0x1184 16
> +y_addr_max 0x1186 16
> +min_x_output_size 0x1188 16
> +min_y_output_size 0x118a 16
> +max_x_output_size 0x118c 16
> +max_y_output_size 0x118e 16
> +
> +x_addr_start_div_constant 0x1190 v1.1
> +y_addr_start_div_constant 0x1191 v1.1
> +x_addr_end_div_constant 0x1192 v1.1
> +y_addr_end_div_constant 0x1193 v1.1
> +x_size_div 0x1194 v1.1
> +y_size_div 0x1195 v1.1
> +x_output_div 0x1196 v1.1
> +y_output_div 0x1197 v1.1
> +non_flexible_resolution_support 0x1198 v1.1
> +- b new_pix_addr 0
> +- b new_output_res 1
> +- b output_crop_no_pad 2
> +- b output_size_lane_dep 3
> +
> +min_op_pre_pll_clk_div 0x11a0 16
> +max_op_pre_pll_clk_div 0x11a2 16
> +min_op_pll_ip_clk_freq_mhz 0x11a4 32 float_ireal
> +max_op_pll_ip_clk_freq_mhz 0x11a8 32 float_ireal
> +min_op_pll_multiplier 0x11ac 16
> +max_op_pll_multiplier 0x11ae 16
> +min_op_pll_op_clk_freq_mhz 0x11b0 32 float_ireal
> +max_op_pll_op_clk_freq_mhz 0x11b4 32 float_ireal
> +clock_tree_pll_capability 0x11b8 8
> +- b dual_pll 0
> +- b single_pll 1
> +- b ext_divider 2
> +- b flexible_op_pix_clk_div 3
> +clock_capa_type_capability 0x11b9 v1.1
> +- b ireal 0
> +
> +# sub-sampling parameters limit registers
> +min_even_inc 0x11c0 16
> +min_odd_inc 0x11c2 16
> +max_even_inc 0x11c4 16
> +max_odd_inc 0x11c6 16
> +aux_subsamp_capability 0x11c8 v1.1
> +- b factor_power_of_2 1
> +aux_subsamp_mono_capability 0x11c9 v1.1
> +- b factor_power_of_2 1
> +monochrome_capability 0x11ca v1.1
> +- e inc_odd 0
> +- e inc_even 1
> +pixel_readout_capability 0x11cb v1.1
> +- e bayer 0
> +- e monochrome 1
> +- e bayer_and_mono 2
> +min_even_inc_mono 0x11cc 16 v1.1
> +max_even_inc_mono 0x11ce 16 v1.1
> +min_odd_inc_mono 0x11d0 16 v1.1
> +max_odd_inc_mono 0x11d2 16 v1.1
> +min_even_inc_bc2 0x11d4 16 v1.1
> +max_even_inc_bc2 0x11d6 16 v1.1
> +min_odd_inc_bc2 0x11d8 16 v1.1
> +max_odd_inc_bc2 0x11da 16 v1.1
> +min_even_inc_mono_bc2 0x11dc 16 v1.1
> +max_even_inc_mono_bc2 0x11de 16 v1.1
> +min_odd_inc_mono_bc2 0x11f0 16 v1.1
> +max_odd_inc_mono_bc2 0x11f2 16 v1.1
> +
> +# image scaling limit parameters
> +scaling_capability 0x1200 16
> +- e none 0
> +- e horizontal 1
> +- e reserved 2
> +scaler_m_min 0x1204 16
> +scaler_m_max 0x1206 16
> +scaler_n_min 0x1208 16
> +scaler_n_max 0x120a 16
> +digital_crop_capability 0x120e
> +- e none 0
> +- e input_crop 1
> +
> +# hdr limit registers
> +hdr_capability_1 0x1210
> +- b 2x2_binning 0
> +- b combined_analog_gain 1
> +- b separate_analog_gain 2
> +- b upscaling 3
> +- b reset_sync 4
> +- b direct_short_exp_timing 5
> +- b direct_short_exp_synthesis 6
> +min_hdr_bit_depth 0x1211
> +hdr_resolution_sub_types 0x1212
> +hdr_resolution_sub_type(n) 0x1213
> +- l n 0 1 1
> +- f row 0 3
> +- f column 4 7
> +hdr_capability_2 0x121b
> +- b combined_digital_gain 0
> +- b separate_digital_gain 1
> +- b timing_mode 3
> +- b synthesis_mode 4
> +max_hdr_bit_depth 0x121c
> +
> +# usl capability register
> +usl_support_capability 0x1230 v1.1
> +- b clock_tree 0
> +- b rev_clock_tree 1
> +- b rev_clock_calc 2
> +usl_clock_mode_d_capability 0x1231 v1.1
> +- b cont_clock_standby 0
> +- b cont_clock_vblank 1
> +- b cont_clock_hblank 2
> +- b noncont_clock_standby 3
> +- b noncont_clock_vblank 4
> +- b noncont_clock_hblank 5
> +min_op_sys_clk_div_rev 0x1234 v1.1
> +max_op_sys_clk_div_rev 0x1236 v1.1
> +min_op_pix_clk_div_rev 0x1238 v1.1
> +max_op_pix_clk_div_rev 0x123a v1.1
> +min_op_sys_clk_freq_rev_mhz 0x123c 32 v1.1 float_ireal
> +max_op_sys_clk_freq_rev_mhz 0x1240 32 v1.1 float_ireal
> +min_op_pix_clk_freq_rev_mhz 0x1244 32 v1.1 float_ireal
> +max_op_pix_clk_freq_rev_mhz 0x1248 32 v1.1 float_ireal
> +max_bitrate_rev_d_mode_mbps 0x124c 32 v1.1 ireal
> +max_symrate_rev_c_mode_msps 0x1250 32 v1.1 ireal
> +
> +# image compression capability registers
> +compression_capability 0x1300
> +- b dpcm_pcm_simple 0
> +
> +# test mode capability registers
> +test_mode_capability 0x1310 16
> +- b solid_color 0
> +- b color_bars 1
> +- b fade_to_grey 2
> +- b pn9 3
> +- b color_tile 5
> +pn9_data_format1 0x1312
> +pn9_data_format2 0x1313
> +pn9_data_format3 0x1314
> +pn9_data_format4 0x1315
> +pn9_misc_capability 0x1316
> +- f num_pixels 0 2
> +- b compression 3
> +test_pattern_capability 0x1317 v1.1
> +- b no_repeat 1
> +pattern_size_div_m1 0x1318 v1.1
> +
> +# fifo capability registers
> +fifo_support_capability 0x1502
> +- e none 0
> +- e derating 1
> +- e derating_overrating 2
> +
> +# csi-2 capability registers
> +phy_ctrl_capability 0x1600
> +- b auto_phy_ctl 0
> +- b ui_phy_ctl 1
> +- b dphy_time_ui_reg_1_ctl 2
> +- b dphy_time_ui_reg_2_ctl 3
> +- b dphy_time_ctl 4
> +- b dphy_ext_time_ui_reg_1_ctl 5
> +- b dphy_ext_time_ui_reg_2_ctl 6
> +- b dphy_ext_time_ctl 7
> +csi_dphy_lane_mode_capability 0x1601
> +- b 1_lane 0
> +- b 2_lane 1
> +- b 3_lane 2
> +- b 4_lane 3
> +- b 5_lane 4
> +- b 6_lane 5
> +- b 7_lane 6
> +- b 8_lane 7
> +csi_signaling_mode_capability 0x1602
> +- b csi_dphy 2
> +- b csi_cphy 3
> +fast_standby_capability 0x1603
> +- e no_frame_truncation 0
> +- e frame_truncation 1
> +csi_address_control_capability 0x1604
> +- b cci_addr_change 0
> +- b 2nd_cci_addr 1
> +- b sw_changeable_2nd_cci_addr 2
> +data_type_capability 0x1605
> +- b dpcm_programmable 0
> +- b bottom_embedded_dt_programmable 1
> +- b bottom_embedded_vc_programmable 2
> +- b ext_vc_range 3
> +csi_cphy_lane_mode_capability 0x1606
> +- b 1_lane 0
> +- b 2_lane 1
> +- b 3_lane 2
> +- b 4_lane 3
> +- b 5_lane 4
> +- b 6_lane 5
> +- b 7_lane 6
> +- b 8_lane 7
> +emb_data_capability 0x1607 v1.1
> +- b two_bytes_per_raw16 0
> +- b two_bytes_per_raw20 1
> +- b two_bytes_per_raw24 2
> +- b no_one_byte_per_raw16 3
> +- b no_one_byte_per_raw20 4
> +- b no_one_byte_per_raw24 5
> +max_per_lane_bitrate_lane_d_mode_mbps(n) 0x1608 32 ireal
> +- l n 0 7 4 4,0x32
> +temp_sensor_capability 0x1618
> +- b supported 0
> +- b CCS_format 1
> +- b reset_0x80 2
> +max_per_lane_bitrate_lane_c_mode_mbps(n) 0x161a 32 ireal
> +- l n 0 7 4 4,0x30
> +dphy_equalization_capability 0x162b
> +- b equalization_ctrl 0
> +- b eq1 1
> +- b eq2 2
> +cphy_equalization_capability 0x162c
> +- b equalization_ctrl 0
> +dphy_preamble_capability 0x162d
> +- b preamble_seq_ctrl 0
> +dphy_ssc_capability 0x162e
> +- b supported 0
> +cphy_calibration_capability 0x162f
> +- b manual 0
> +- b manual_streaming 1
> +- b format_1_ctrl 2
> +- b format_2_ctrl 3
> +- b format_3_ctrl 4
> +dphy_calibration_capability 0x1630
> +- b manual 0
> +- b manual_streaming 1
> +- b alternate_seq 2
> +phy_ctrl_capability_2 0x1631
> +- b tgr_length 0
> +- b tgr_preamble_prog_seq 1
> +- b extra_cphy_manual_timing 2
> +- b clock_based_manual_cdphy 3
> +- b clock_based_manual_dphy 4
> +- b clock_based_manual_cphy 5
> +- b manual_lp_dphy 6
> +- b manual_lp_cphy 7
> +lrte_cphy_capability 0x1632
> +- b pdq_short 0
> +- b spacer_short 1
> +- b pdq_long 2
> +- b spacer_long 3
> +- b spacer_no_pdq 4
> +lrte_dphy_capability 0x1633
> +- b pdq_short_opt1 0
> +- b spacer_short_opt1 1
> +- b pdq_long_opt1 2
> +- b spacer_long_opt1 3
> +- b spacer_short_opt2 4
> +- b spacer_long_opt2 5
> +- b spacer_no_pdq_opt1 6
> +- b spacer_variable_opt2 7
> +alps_capability_dphy 0x1634
> +- e lvlp_not_supported 0 0x3
> +- e lvlp_supported 1 0x3
> +- e controllable_lvlp 2 0x3
> +alps_capability_cphy 0x1635
> +- e lvlp_not_supported 0 0x3
> +- e lvlp_supported 1 0x3
> +- e controllable_lvlp 2 0x3
> +- e alp_not_supported 0xc 0xc
> +- e alp_supported 0xd 0xc
> +- e controllable_alp 0xe 0xc
> +scrambling_capability 0x1636
> +- b scrambling_supported 0
> +- f max_seeds_per_lane_c 1 2
> +- e 1 0
> +- e 4 3
> +- f num_seed_regs 3 5
> +- e 0 0
> +- e 1 1
> +- e 4 4
> +- b num_seed_per_lane 6
> +dphy_manual_constant 0x1637
> +cphy_manual_constant 0x1638
> +CSI2_interface_capability_misc 0x1639 v1.1
> +- b eotp_short_pkt_opt2 0
> +PHY_ctrl_capability_3 0x165c v1.1
> +- b dphy_timing_not_multiple 0
> +- b dphy_min_timing_value_1 1
> +- b twakeup_supported 2
> +- b tinit_supported 3
> +- b ths_exit_supported 4
> +- b cphy_timing_not_multiple 5
> +- b cphy_min_timing_value_1 6
> +dphy_sf 0x165d v1.1
> +cphy_sf 0x165e v1.1
> +- f twakeup 0 3
> +- f tinit 4 7
> +dphy_limits_1 0x165f v1.1
> +- f ths_prepare 0 3
> +- f ths_zero 4 7
> +dphy_limits_2 0x1660 v1.1
> +- f ths_trail 0 3
> +- f tclk_trail_min 4 7
> +dphy_limits_3 0x1661 v1.1
> +- f tclk_prepare 0 3
> +- f tclk_zero 4 7
> +dphy_limits_4 0x1662 v1.1
> +- f tclk_post 0 3
> +- f tlpx 4 7
> +dphy_limits_5 0x1663 v1.1
> +- f ths_exit 0 3
> +- f twakeup 4 7
> +dphy_limits_6 0x1664 v1.1
> +- f tinit 0 3
> +cphy_limits_1 0x1665 v1.1
> +- f t3_prepare_max 0 3
> +- f t3_lpx_max 4 7
> +cphy_limits_2 0x1666 v1.1
> +- f ths_exit_max 0 3
> +- f twakeup_max 4 7
> +cphy_limits_3 0x1667 v1.1
> +- f tinit_max 0 3
> +
> +# binning capability registers
> +min_frame_length_lines_bin 0x1700 16
> +max_frame_length_lines_bin 0x1702 16
> +min_line_length_pck_bin 0x1704 16
> +max_line_length_pck_bin 0x1706 16
> +min_line_blanking_pck_bin 0x1708 16
> +fine_integration_time_min_bin 0x170a 16
> +fine_integration_time_max_margin_bin 0x170c 16
> +binning_capability 0x1710
> +- e unsupported 0
> +- e binning_then_subsampling 1
> +- e subsampling_then_binning 2
> +binning_weighting_capability 0x1711
> +- b averaged 0
> +- b summed 1
> +- b bayer_corrected 2
> +- b module_specific_weight 3
> +binning_sub_types 0x1712
> +binning_sub_type(n) 0x1713
> +- l n 0 63 1
> +- f row 0 3
> +- f column 4 7
> +binning_weighting_mono_capability 0x1771 v1.1
> +- b averaged 0
> +- b summed 1
> +- b bayer_corrected 2
> +- b module_specific_weight 3
> +binning_sub_types_mono 0x1772 v1.1
> +binning_sub_type_mono(n) 0x1773 v1.1 f
> +- l n 0 63 1
> +
> +# data transfer interface capability registers
> +data_transfer_if_capability 0x1800
> +- b supported 0
> +- b polling 2
> +
> +# sensor correction capability registers
> +shading_correction_capability 0x1900
> +- b color_shading 0
> +- b luminance_correction 1
> +green_imbalance_capability 0x1901
> +- b supported 0
> +module_specific_correction_capability 0x1903
> +defect_correction_capability 0x1904 16
> +- b mapped_defect 0
> +- b dynamic_couplet 2
> +- b dynamic_single 5
> +- b combined_dynamic 8
> +defect_correction_capability_2 0x1906 16
> +- b dynamic_triplet 3
> +nf_capability 0x1908
> +- b luma 0
> +- b chroma 1
> +- b combined 2
> +
> +# optical black readout capability registers
> +ob_readout_capability 0x1980
> +- b controllable_readout 0
> +- b visible_pixel_readout 1
> +- b different_vc_readout 2
> +- b different_dt_readout 3
> +- b prog_data_format 4
> +
> +# color feedback capability registers
> +color_feedback_capability 0x1987
> +- b kelvin 0
> +- b awb_gain 1
> +
> +# cfa pattern capability registers
> +CFA_pattern_capability 0x1990 v1.1
> +- e bayer 0
> +- e monochrome 1
> +- e 4x4_quad_bayer 2
> +- e vendor_specific 3
> +CFA_pattern_conversion_capability 0x1991 v1.1
> +- b bayer 0
> +
> +# timer capability registers
> +flash_mode_capability 0x1a02
> +- b single_strobe 0
> +sa_strobe_mode_capability 0x1a03
> +- b fixed_width 0
> +- b edge_ctrl 1
> +
> +# soft reset capability registers
> +reset_max_delay 0x1a10 v1.1
> +reset_min_time 0x1a11 v1.1
> +
> +# pdaf capability registers
> +pdaf_capability_1 0x1b80
> +- b supported 0
> +- b processed_bottom_embedded 1
> +- b processed_interleaved 2
> +- b raw_bottom_embedded 3
> +- b raw_interleaved 4
> +- b visible_pdaf_correction 5
> +- b vc_interleaving 6
> +- b dt_interleaving 7
> +pdaf_capability_2 0x1b81
> +- b ROI 0
> +- b after_digital_crop 1
> +- b ctrl_retimed 2
> +
> +# bracketing interface capability registers
> +bracketing_lut_capability_1 0x1c00
> +- b coarse_integration 0
> +- b global_analog_gain 1
> +- b flash 4
> +- b global_digital_gain 5
> +- b alternate_global_analog_gain 6
> +bracketing_lut_capability_2 0x1c01
> +- b single_bracketing_mode 0
> +- b looped_bracketing_mode 1
> +bracketing_lut_size 0x1c02
> diff --git a/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs b/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs
> new file mode 100755
> index 000000000000..3d6a2a7aac3a
> --- /dev/null
> +++ b/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs
> @@ -0,0 +1,433 @@
> +#!/usr/bin/perl -w
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
> +# Copyright (C) 2019--2020 Intel Corporation
> +
> +use Getopt::Long qw(:config no_ignore_case);
> +use File::Basename;
> +
> +my $ccsregs = "ccs-regs.txt";
> +my $header;
> +my $regarray;
> +my $limitc;
> +my $limith;
> +my $kernel;
> +my $help;
> +
> +GetOptions("ccsregs|c=s" => \$ccsregs,
> + "header|e=s" => \$header,
> + "regarray|r=s" => \$regarray,
> + "limitc|l=s" => \$limitc,
> + "limith|L=s" => \$limith,
> + "kernel|k" => \$kernel,
> + "help|h" => \$help) or die "can't parse options";
> +
> +$help = 1 if ! defined $header || ! defined $limitc || ! defined $limith;
> +
> +if (defined $help) {
> + print <<EOH
> +$0 - Create CCS register definitions for C
> +
> +usage: $0 -c ccs-regs.txt -e header -r regarray -l limit-c -L limit-header [-k]
> +
> + -c ccs register file
> + -e header file name
> + -r register description array file name
> + -l limit and capability array file name
> + -L limit and capability header file name
> + -k generate files for kernel space consumption
> +EOH
> + ;
> + exit 0;
> +}
> +
> +my $lh_hdr = ! defined $kernel
> + ? '#include "ccs-os.h"' . "\n"
> + : "#include <linux/bits.h>\n#include <linux/types.h>\n";
> +my $uint32_t = ! defined $kernel ? 'uint32_t' : 'u32';
> +my $uint16_t = ! defined $kernel ? 'uint16_t' : 'u16';
> +
> +open(my $R, "< $ccsregs") or die "can't open $ccsregs";
> +
> +open(my $H, "> $header") or die "can't open $header";
> +my $A;
> +if (defined $regarray) {
> + open($A, "> $regarray") or die "can't open $regarray";
> +}
> +open(my $LC, "> $limitc") or die "can't open $limitc";
> +open(my $LH, "> $limith") or die "can't open $limith";
> +
> +my %this;
> +
> +sub is_limit_reg($) {
> + my $addr = hex $_[0];
> +
> + return 0 if $addr < 0x40; # weed out status registers
> + return 0 if $addr >= 0x100 && $addr < 0xfff; # weed out configuration registers
> +
> + return 1;
> +}
> +
> +my $uc_header = basename uc $header;
> +$uc_header =~ s/[^A-Z0-9]/_/g;
> +
> +my $copyright = "/* Copyright (C) 2019--2020 Intel Corporation */\n";
> +my $license = "SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause";
> +
> +for my $fh ($A, $LC) {
> + print $fh "// $license\n$copyright\n" if defined $fh;
> +}
> +
> +for my $fh ($H, $LH) {
> + print $fh "/* $license */\n$copyright\n";
> +}
> +
> +sub bit_def($) {
> + my $bit = shift @_;
> +
> + return "BIT($bit)" if defined $kernel;
> + return "(1U << $bit)" if $bit =~ /^[a-zA-Z0-9_]+$/;
> + return "(1U << ($bit))";
> +}
> +
> +print $H <<EOF
> +#ifndef __${uc_header}__
> +#define __${uc_header}__
> +
> +EOF
> + ;
> +
> +print $H "#include <linux/bits.h>\n\n" if defined $kernel;
> +
> +print $H <<EOF
> +#define CCS_FL_BASE 16
> +EOF
> + ;
> +
> +print $H "#define CCS_FL_16BIT " . bit_def("CCS_FL_BASE") . "\n";
> +print $H "#define CCS_FL_32BIT " . bit_def("CCS_FL_BASE + 1") . "\n";
> +print $H "#define CCS_FL_FLOAT_IREAL " . bit_def("CCS_FL_BASE + 2") . "\n";
> +print $H "#define CCS_FL_IREAL " . bit_def("CCS_FL_BASE + 3") . "\n";
> +
> +print $H <<EOF
> +#define CCS_R_ADDR(r) ((r) & 0xffff)
> +
> +EOF
> + ;
> +
> +print $A <<EOF
> +#include <stdint.h>
> +#include <stdio.h>
> +#include "ccs-extra.h"
> +#include "ccs-regs.h"
> +
> +EOF
> + if defined $A;
> +
> +my $uc_limith = basename uc $limith;
> +$uc_limith =~ s/[^A-Z0-9]/_/g;
> +
> +print $LH <<EOF
> +#ifndef __${uc_limith}__
> +#define __${uc_limith}__
> +
> +$lh_hdr
> +struct ccs_limit {
> + $uint32_t reg;
> + $uint16_t size;
> + $uint16_t flags;
> + const char *name;
> +};
> +
> +EOF
> + ;
> +print $LH "#define CCS_L_FL_SAME_REG " . bit_def(0) . "\n\n";
> +
> +print $LH <<EOF
> +extern const struct ccs_limit ccs_limits[];
> +
> +EOF
> + ;
> +
> +print $LC <<EOF
> +#include "ccs-limits.h"
> +#include "ccs-regs.h"
> +
> +const struct ccs_limit ccs_limits[] = {
> +EOF
> + ;
> +
> +my $limitcount = 0;
> +my $argdescs;
> +my $reglist = "const struct ccs_reg_desc ccs_reg_desc[] = {\n";
> +
> +sub name_split($$) {
> + my ($name, $addr) = @_;
> + my $args;
> +
> + $name =~ /([^\(]+?)(\(.*)/;
> + ($name, $args) = ($1, $2);
> + $args = [split /,\s*/, $args];
> + foreach my $t (@$args) {
> + $t =~ s/[\(\)]//g;
> + $t =~ s/\//\\\//g;
> + }
> +
> + return ($name, $addr, $args);
> +}
> +
> +sub tabconv($) {
> + $_ = shift;
> +
> + my @l = split "\n", $_;
> +
> + map {
> + s/ {8,8}/\t/g;
> + s/\t\K +//;
> + } @l;
> +
> + return (join "\n", @l) . "\n";
> +}
> +
> +sub elem_size(@) {
> + my @flags = @_;
> +
> + return 2 if grep /^16$/, @flags;
> + return 4 if grep /^32$/, @flags;
> + return 1;
> +}
> +
> +sub arr_size($) {
> + my $this = $_[0];
> + my $size = $this->{elsize};
> + my $h = $this->{argparams};
> +
> + foreach my $arg (@{$this->{args}}) {
> + my $apref = $h->{$arg};
> +
> + $size *= $apref->{max} - $apref->{min} + 1;
> + }
> +
> + return $size;
> +}
> +
> +sub print_args($$$) {
> + my ($this, $postfix, $is_same_reg) = @_;
> + my ($args, $argparams, $name) =
> + ($this->{args}, $this->{argparams}, $this->{name});
> + my $varname = "ccs_reg_arg_" . (lc $name) . $postfix;
> + my @mins;
> + my @sorted_args = @{$this->{sorted_args}};
> + my $lim_arg;
> + my $size = arr_size($this);
> +
> + $argdescs .= "static const struct ccs_reg_arg " . $varname . "[] = {\n";
> +
> + foreach my $sorted_arg (@sorted_args) {
> + push @mins, $argparams->{$sorted_arg}->{min};
> + }
> +
> + foreach my $sorted_arg (@sorted_args) {
> + my $h = $argparams->{$sorted_arg};
> +
> + $argdescs .= "\t{ \"$sorted_arg\", $h->{min}, $h->{max}, $h->{elsize} },\n";
> +
> + $lim_arg .= defined $lim_arg ? ", $h->{min}" : "$h->{min}";
> + }
> +
> + $argdescs .= "};\n\n";
> +
> + $reglist .= "\t{ CCS_R_" . (uc $name) . "(" . (join ",", (@mins)) .
> + "), $size, sizeof($varname) / sizeof(*$varname)," .
> + " \"" . (lc $name) . "\", $varname },\n";
> +
> + print $LC tabconv sprintf "\t{ CCS_R_" . (uc $name) . "($lim_arg), " .
> + $size . ", " . ($is_same_reg ? "CCS_L_FL_SAME_REG" : "0") .
> + ", \"$name" . (defined $this->{discontig} ? " $lim_arg" : "") . "\" },\n"
> + if is_limit_reg $this->{base_addr};
> +}
> +
> +my $hdr_data;
> +
> +while (<$R>) {
> + chop;
> + s/^\s*//;
> + next if /^[#;]/ || /^$/;
> + if (s/^-\s*//) {
> + if (s/^b\s*//) {
> + my ($bit, $addr) = split /\t+/;
> + $bit = uc $bit;
> + $hdr_data .= sprintf "#define %-62s %s", "CCS_" . (uc ${this{name}}) ."_$bit", bit_def($addr) . "\n";
> + } elsif (s/^f\s*//) {
> + s/[,\.-]/_/g;
> + my @a = split /\s+/;
> + my ($msb, $lsb, $this_field) = reverse @a;
> + @a = ( { "name" => "SHIFT", "addr" => $lsb, "fmt" => "%uU", },
> + { "name" => "MASK", "addr" => (1 << ($msb + 1)) - 1 - ((1 << $lsb) - 1), "fmt" => "0x%" . join(".", ($this{"elsize"} >> 2) x 2) . "x" } );
> + $this{"field"} = $this_field;
> + foreach my $ar (@a) {
> + #print $ar->{fmt}."\n";
> + $hdr_data .= sprintf "#define %-62s " . $ar->{"fmt"} . "\n", "CCS_" . (uc $this{"name"}) . (defined $this_field ? "_" . uc $this_field : "") . "_" . $ar->{"name"}, $ar->{"addr"} . "\n";
> + }
> + } elsif (s/^e\s*//) {
> + s/[,\.-]/_/g;
> + my ($enum, $addr) = split /\s+/;
> + $enum = uc $enum;
> + $hdr_data .= sprintf "#define %-62s %s", "CCS_" . (uc ${this{name}}) . (defined $this{"field"} ? "_" . uc $this{"field"} : "") ."_$enum", $addr . ($addr =~ /0x/i ? "" : "U") . "\n";
> + } elsif (s/^l\s*//) {
> + my ($arg, $min, $max, $elsize, @discontig) = split /\s+/;
> + my $size;
> +
> + foreach my $num ($min, $max) {
> + $num = hex $num if $num =~ /0x/i;
> + }
> +
> + $hdr_data .= sprintf "#define %-62s %s", "CCS_LIM_" . (uc ${this{name}} . "_MIN_$arg"), $min . ($min =~ /0x/i ? "" : "U") . "\n";
> + $hdr_data .= sprintf "#define %-62s %s", "CCS_LIM_" . (uc ${this{name}} . "_MAX_$arg"), $max . ($max =~ /0x/i ? "" : "U") . "\n";
> +
> + my $h = $this{argparams};
> +
> + $h->{$arg} = { "min" => $min,
> + "max" => $max,
> + "elsize" => $elsize =~ /^0x/ ? hex $elsize : $elsize,
> + "discontig" => \@discontig };
> +
> + $this{discontig} = $arg if @discontig;
> +
> + next if $#{$this{args}} + 1 != scalar keys %{$this{argparams}};
> +
> + my $reg_formula = "($this{addr}";
> + my $lim_formula;
> +
> + foreach my $arg (@{$this{args}}) {
> + my $d = $h->{$arg}->{discontig};
> + my $times = $h->{$arg}->{elsize} != 1 ?
> + " * " . $h->{$arg}->{elsize} : "";
> +
> + if (@$d) {
> + my ($lim, $offset) = split /,/, $d->[0];
> +
> + $reg_formula .= " + (($arg) < $lim ? ($arg)$times : $offset + (($arg) - $lim)$times)";
> + } else {
> + $reg_formula .= " + ($arg)$times";
> + }
> +
> + $lim_formula .= (defined $lim_formula ? " + " : "") . "($arg)$times";
> + }
> +
> + $reg_formula .= ")\n";
> + $lim_formula =~ s/^\(([a-z0-9]+)\)$/$1/i;
> +
> + print $H tabconv sprintf("#define %-62s %s", "CCS_R_" . (uc $this{name}) .
> + $this{arglist}, $reg_formula);
> +
> + print $H tabconv $hdr_data;
> + undef $hdr_data;
> +
> + # Sort arguments in descending order by size
> + @{$this{sorted_args}} = sort {
> + $h->{$a}->{elsize} <= $h->{$b}->{elsize}
> + } @{$this{args}};
> +
> + if (defined $this{discontig}) {
> + my $da = $this{argparams}->{$this{discontig}};
> + my ($first_discontig) = split /,/, $da->{discontig}->[0];
> + my $max = $da->{max};
> +
> + $da->{max} = $first_discontig - 1;
> + print_args(\%this, "", 0);
> +
> + $da->{min} = $da->{max} + 1;
> + $da->{max} = $max;
> + print_args(\%this, $first_discontig, 1);
> + } else {
> + print_args(\%this, "", 0);
> + }
> +
> + next unless is_limit_reg $this{base_addr};
> +
> + print $LH tabconv sprintf "#define %-63s%s\n",
> + "CCS_L_" . (uc $this{name}) . "_OFFSET(" .
> + (join ", ", @{$this{args}}) . ")", "($lim_formula)";
> + }
> +
> + if (! @{$this{args}}) {
> + print $H tabconv($hdr_data);
> + undef $hdr_data;
> + }
> +
> + next;
> + }
> +
> + my ($name, $addr, @flags) = split /\t+/, $_;
> + my $args = [];
> +
> + my $sp;
> +
> + ($name, $addr, $args) = name_split($name, $addr) if /\(.*\)/;
> +
> + $name =~ s/[,\.-]/_/g;
> +
> + my $flagstring = "";
> + my $size = elem_size(@flags);
> + $flagstring .= "| CCS_FL_16BIT " if $size eq "2";
> + $flagstring .= "| CCS_FL_32BIT " if $size eq "4";
> + $flagstring .= "| CCS_FL_FLOAT_IREAL " if grep /^float_ireal$/, @flags;
> + $flagstring .= "| CCS_FL_IREAL " if grep /^ireal$/, @flags;
> + $flagstring =~ s/^\| //;
> + $flagstring =~ s/ $//;
> + $flagstring = "($flagstring)" if $flagstring =~ /\|/;
> + my $base_addr = $addr;
> + $addr = "($addr | $flagstring)" if $flagstring ne "";
> +
> + my $arglist = @$args ? "(" . (join ", ", @$args) . ")" : "";
> + $hdr_data .= sprintf "#define %-62s %s\n", "CCS_R_" . (uc $name), $addr
> + if !@$args;
> +
> + $name =~ s/\(.*//;
> +
> + %this = ( name => $name,
> + addr => $addr,
> + base_addr => $base_addr,
> + argparams => {},
> + args => $args,
> + arglist => $arglist,
> + elsize => $size,
> + );
> +
> + if (!@$args) {
> + $reglist .= "\t{ CCS_R_" . (uc $name) . ", 1, 0, \"" . (lc $name) . "\", NULL },\n";
> + print $H tabconv $hdr_data;
> + undef $hdr_data;
> +
> + print $LC tabconv sprintf "\t{ CCS_R_" . (uc $name) . ", " .
> + $this{elsize} . ", 0, \"$name\" },\n"
> + if is_limit_reg $this{base_addr};
> + }
> +
> + print $LH tabconv sprintf "#define %-63s%s\n",
> + "CCS_L_" . (uc $this{name}), $limitcount++
> + if is_limit_reg $this{base_addr};
> +}
> +
> +if (defined $A) {
> + print $A $argdescs, $reglist;
> +
> + print $A "\t{ 0 }\n";
> +
> + print $A "};\n";
> +}
> +
> +print $H "\n#endif /* __${uc_header}__ */\n";
> +
> +print $LH tabconv sprintf "#define %-63s%s\n", "CCS_L_LAST", $limitcount;
> +
> +print $LH "\n#endif /* __${uc_limith}__ */\n";
> +
> +print $LC "\t{ 0 } /* Guardian */\n";
> +print $LC "};\n";
> +
> +close($R);
> +close($H);
> +close($A) if defined $A;
> +close($LC);
> +close($LH);
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 352b8eaa21f7..1a5455e1c664 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -16135,6 +16135,7 @@ M: Sakari Ailus <sakari.ailus@linux.intel.com>
> L: linux-media@vger.kernel.org
> S: Maintained
> F: Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
> +F: Documentation/driver-api/media/drivers/ccs/
> F: drivers/media/i2c/smiapp-pll.c
> F: drivers/media/i2c/smiapp-pll.h
> F: drivers/media/i2c/smiapp/
Thanks,
Mauro
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v2 01/29] ccs: Add the generator for CCS register definitions and limits
2020-12-02 14:17 ` Mauro Carvalho Chehab
@ 2020-12-02 14:46 ` Sakari Ailus
0 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-12-02 14:46 UTC (permalink / raw)
To: Mauro Carvalho Chehab; +Cc: linux-media, hverkuil
Hi Mauro,
On Wed, Dec 02, 2020 at 03:17:49PM +0100, Mauro Carvalho Chehab wrote:
> Em Fri, 27 Nov 2020 12:32:57 +0200
> Sakari Ailus <sakari.ailus@linux.intel.com> escreveu:
>
> > Add register definitions of the MIPI CCS 1.1 standard.
> >
> > The CCS driver makes extended use of device's capability registers that
> > are dependent on CCS version. This involves having an in-memory data
> > structure for limit and capability information, creating that data
> > structure and accessing it.
> >
> > The register definitions as well as the definitions of this data structure
> > are generated from a text file using a Perl script. Add the generator
> > script to make it easy to update the generated files.
> >
> > Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> > ---
> > .../driver-api/media/drivers/ccs/ccs-regs.txt | 1041 +++++++++++++++++
> > .../driver-api/media/drivers/ccs/mk-ccs-regs | 433 +++++++
> > MAINTAINERS | 1 +
> > 3 files changed, 1475 insertions(+)
> > create mode 100644 Documentation/driver-api/media/drivers/ccs/ccs-regs.txt
> > create mode 100755 Documentation/driver-api/media/drivers/ccs/mk-ccs-regs
> >
> > diff --git a/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt b/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt
> > new file mode 100644
> > index 000000000000..93f0131aa304
> > --- /dev/null
> > +++ b/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt
> > @@ -0,0 +1,1041 @@
> > +# Copyright (C) 2019--2020 Intel Corporation
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
>
>
> Whenever technically possible, the SPDX header should be the first
> line.
I sent patches addressing this, as well as renaming it as ccs-regs.asc.
>
> -
>
> With regards to css-regs.txt file itself, I think it should be
> added on a css-specific ReST file (index.rst?) using the
>
> .. include
>
> directive (or a similar one).
>
> Regards,
> Mauro
>
> > +
> > +# register rflags
> > +# - f field LSB MSB rflags
> > +# - e enum value # after a field
> > +# - e enum value [LSB MSB]
> > +# - b bool bit
> > +# - l arg name min max elsize [discontig...]
> > +#
> > +# rflags
> > +# 8, 16, 32 register bits (default is 8)
> > +# v1.1 defined in version 1.1
> > +# f formula
> > +# float_ireal iReal or IEEE 754; 32 bits
> > +# ireal unsigned iReal
>
>
> > +
> > +# general status registers
> > +module_model_id 0x0000 16
> > +module_revision_number_major 0x0002 8
> > +frame_count 0x0005 8
> > +pixel_order 0x0006 8
>
>
> For instance, the above could be, instead:
>
> .. general status registers
>
> ::
>
> module_model_id 0x0000 16
> module_revision_number_major 0x0002 8
> frame_count 0x0005 8
> pixel_order 0x0006 8
>
> (which should be easy to parse)
>
> or, even better:
>
> general status registers:
>
> ==================================== ====== ==
> module_model_id 0x0000 16
> module_revision_number_major 0x0002 8
> frame_count 0x0005 8
> pixel_order 0x0006 8
> ==================================== ====== ==
>
>
> Parsing the later could be a little harder, although it would allow
> placing the file inside the documentation, with could be interesting.
Driver implemented in C uses the macros in the generated header, so the
documentation should make use of those macro names. Generating developer
documentation to support a single driver seems overkill to me. I develop
this driver and over a decade I have received very, very few patches to
this driver, so I consider the primary audience of such document to be
myself. And I can tell I'm happy looking at the source code.
If we'd still do that, then, instead of changing the format of this file,
I'd generate the documentation using another script. Btw. mk-ccs-regs
script isn't the only script interpreting this file, so changing the format
requires changes elsewhere.
--
Kind regards,
Sakari Ailus
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 02/29] Documentation: ccs: Add CCS driver documentation
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
2020-11-27 10:32 ` [PATCH v2 01/29] ccs: Add the generator for CCS register definitions and limits Sakari Ailus
@ 2020-11-27 10:32 ` Sakari Ailus
2020-11-27 10:32 ` [PATCH v2 03/29] smiapp: Import CCS definitions Sakari Ailus
` (26 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:32 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Document the MIPI CCS driver and the C register definition generator.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
.../driver-api/media/drivers/ccs/ccs.rst | 82 +++++++++++++++++++
.../driver-api/media/drivers/index.rst | 1 +
2 files changed, 83 insertions(+)
create mode 100644 Documentation/driver-api/media/drivers/ccs/ccs.rst
diff --git a/Documentation/driver-api/media/drivers/ccs/ccs.rst b/Documentation/driver-api/media/drivers/ccs/ccs.rst
new file mode 100644
index 000000000000..9164c9fa8b42
--- /dev/null
+++ b/Documentation/driver-api/media/drivers/ccs/ccs.rst
@@ -0,0 +1,82 @@
+.. SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
+
+.. include:: <isonum.txt>
+
+MIPI CCS camera sensor driver
+=============================
+
+The MIPI CCS camera sensor driver is a generic driver for `MIPI CCS
+<https://www.mipi.org/specifications/camera-command-set>`_ compliant
+camera sensors. It exposes three sub-devices representing the pixel array,
+the binner and the scaler.
+
+As the capabilities of individual devices vary, the driver exposes
+interfaces based on the capabilities that exist in hardware.
+
+Pixel Array sub-device
+----------------------
+
+The pixel array sub-device represents the camera sensor's pixel matrix, as well
+as analogue crop functionality present in many compliant devices. The analogue
+crop is configured using the ``V4L2_SEL_TGT_CROP`` on the source pad (0) of the
+entity. The size of the pixel matrix can be obtained by getting the
+``V4L2_SEL_TGT_NATIVE_SIZE`` target.
+
+Binner
+------
+
+The binner sub-device represents the binning functionality on the sensor. For
+that purpose, selection target ``V4L2_SEL_TGT_COMPOSE`` is supported on the
+sink pad (0).
+
+Additionally, if a device has no scaler or digital crop functionality, the
+source pad (1) expses another digital crop selection rectangle that can only
+crop at the end of the lines and frames.
+
+Scaler
+------
+
+The scaler sub-device represents the digital crop and scaling functionality of
+the sensor. The V4L2 selection target ``V4L2_SEL_TGT_CROP`` is used to
+configure the digital crop on the sink pad (0) when digital crop is supported.
+Scaling is configured using selection target ``V4L2_SEL_TGT_COMPOSE`` on the
+sink pad (0) as well.
+
+Additionally, if the scaler sub-device exists, its source pad (1) exposes
+another digital crop selection rectangle that can only crop at the end of the
+lines and frames.
+
+Digital and analogue crop
+-------------------------
+
+Digital crop functionality is referred to as cropping that effectively works by
+dropping some data on the floor. Analogue crop, on the other hand, means that
+the cropped information is never retrieved. In case of camera sensors, the
+analogue data is never read from the pixel matrix that are outside the
+configured selection rectangle that designates crop. The difference has an
+effect in device timing and likely also in power consumption.
+
+Register definition generator
+-----------------------------
+
+The ccs-regs.txt file contains MIPI CCS register definitions that are used
+to produce C source code files for definitions that can be better used by
+programs written in C language. As there are many dependencies between the
+produced files, please do not modify them manually as it's error-prone and
+in vain, but instead change the script producing them.
+
+Usage
+~~~~~
+
+Conventionally the script is called this way to update the CCS driver
+definitions:
+
+.. code-block:: none
+
+ $ Documentation/driver-api/media/drivers/ccs/mk-ccs-regs -k \
+ -e drivers/media/i2c/ccs/ccs-regs.h \
+ -L drivers/media/i2c/ccs/ccs-limits.h \
+ -l drivers/media/i2c/ccs/ccs-limits.c \
+ -c Documentation/driver-api/media/drivers/ccs/ccs-regs.txt
+
+**Copyright** |copy| 2020 Intel Corporation
diff --git a/Documentation/driver-api/media/drivers/index.rst b/Documentation/driver-api/media/drivers/index.rst
index eb7011782863..426cda633bf0 100644
--- a/Documentation/driver-api/media/drivers/index.rst
+++ b/Documentation/driver-api/media/drivers/index.rst
@@ -26,6 +26,7 @@ Video4Linux (V4L) drivers
tuners
vimc-devel
zoran
+ ccs/ccs
Digital TV drivers
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 03/29] smiapp: Import CCS definitions
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
2020-11-27 10:32 ` [PATCH v2 01/29] ccs: Add the generator for CCS register definitions and limits Sakari Ailus
2020-11-27 10:32 ` [PATCH v2 02/29] Documentation: ccs: Add CCS driver documentation Sakari Ailus
@ 2020-11-27 10:32 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 04/29] smiapp: Use CCS register flags Sakari Ailus
` (25 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:32 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Import CCS register and limit definitions. These files are generated by a
Perl script based on a text-based register definition file. The generator
is added later in the series.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/ccs-limits.c | 239 +++++++
drivers/media/i2c/smiapp/ccs-limits.h | 259 +++++++
drivers/media/i2c/smiapp/ccs-regs.h | 954 ++++++++++++++++++++++++++
3 files changed, 1452 insertions(+)
create mode 100644 drivers/media/i2c/smiapp/ccs-limits.c
create mode 100644 drivers/media/i2c/smiapp/ccs-limits.h
create mode 100644 drivers/media/i2c/smiapp/ccs-regs.h
diff --git a/drivers/media/i2c/smiapp/ccs-limits.c b/drivers/media/i2c/smiapp/ccs-limits.c
new file mode 100644
index 000000000000..f5511789ac83
--- /dev/null
+++ b/drivers/media/i2c/smiapp/ccs-limits.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
+/* Copyright (C) 2019--2020 Intel Corporation */
+
+#include "ccs-limits.h"
+#include "ccs-regs.h"
+
+const struct ccs_limit ccs_limits[] = {
+ { CCS_R_FRAME_FORMAT_MODEL_TYPE, 1, 0, "frame_format_model_type" },
+ { CCS_R_FRAME_FORMAT_MODEL_SUBTYPE, 1, 0, "frame_format_model_subtype" },
+ { CCS_R_FRAME_FORMAT_DESCRIPTOR(0), 30, 0, "frame_format_descriptor" },
+ { CCS_R_FRAME_FORMAT_DESCRIPTOR_4(0), 32, 0, "frame_format_descriptor_4" },
+ { CCS_R_ANALOG_GAIN_CAPABILITY, 2, 0, "analog_gain_capability" },
+ { CCS_R_ANALOG_GAIN_CODE_MIN, 2, 0, "analog_gain_code_min" },
+ { CCS_R_ANALOG_GAIN_CODE_MAX, 2, 0, "analog_gain_code_max" },
+ { CCS_R_ANALOG_GAIN_CODE_STEP, 2, 0, "analog_gain_code_step" },
+ { CCS_R_ANALOG_GAIN_TYPE, 2, 0, "analog_gain_type" },
+ { CCS_R_ANALOG_GAIN_M0, 2, 0, "analog_gain_m0" },
+ { CCS_R_ANALOG_GAIN_C0, 2, 0, "analog_gain_c0" },
+ { CCS_R_ANALOG_GAIN_M1, 2, 0, "analog_gain_m1" },
+ { CCS_R_ANALOG_GAIN_C1, 2, 0, "analog_gain_c1" },
+ { CCS_R_ANALOG_LINEAR_GAIN_MIN, 2, 0, "analog_linear_gain_min" },
+ { CCS_R_ANALOG_LINEAR_GAIN_MAX, 2, 0, "analog_linear_gain_max" },
+ { CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE, 2, 0, "analog_linear_gain_step_size" },
+ { CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN, 2, 0, "analog_exponential_gain_min" },
+ { CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX, 2, 0, "analog_exponential_gain_max" },
+ { CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE, 2, 0, "analog_exponential_gain_step_size" },
+ { CCS_R_DATA_FORMAT_MODEL_TYPE, 1, 0, "data_format_model_type" },
+ { CCS_R_DATA_FORMAT_MODEL_SUBTYPE, 1, 0, "data_format_model_subtype" },
+ { CCS_R_DATA_FORMAT_DESCRIPTOR(0), 32, 0, "data_format_descriptor" },
+ { CCS_R_INTEGRATION_TIME_CAPABILITY, 2, 0, "integration_time_capability" },
+ { CCS_R_COARSE_INTEGRATION_TIME_MIN, 2, 0, "coarse_integration_time_min" },
+ { CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "coarse_integration_time_max_margin" },
+ { CCS_R_FINE_INTEGRATION_TIME_MIN, 2, 0, "fine_integration_time_min" },
+ { CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "fine_integration_time_max_margin" },
+ { CCS_R_DIGITAL_GAIN_CAPABILITY, 1, 0, "digital_gain_capability" },
+ { CCS_R_DIGITAL_GAIN_MIN, 2, 0, "digital_gain_min" },
+ { CCS_R_DIGITAL_GAIN_MAX, 2, 0, "digital_gain_max" },
+ { CCS_R_DIGITAL_GAIN_STEP_SIZE, 2, 0, "digital_gain_step_size" },
+ { CCS_R_PEDESTAL_CAPABILITY, 1, 0, "Pedestal_capability" },
+ { CCS_R_ADC_CAPABILITY, 1, 0, "ADC_capability" },
+ { CCS_R_ADC_BIT_DEPTH_CAPABILITY, 4, 0, "ADC_bit_depth_capability" },
+ { CCS_R_MIN_EXT_CLK_FREQ_MHZ, 4, 0, "min_ext_clk_freq_mhz" },
+ { CCS_R_MAX_EXT_CLK_FREQ_MHZ, 4, 0, "max_ext_clk_freq_mhz" },
+ { CCS_R_MIN_PRE_PLL_CLK_DIV, 2, 0, "min_pre_pll_clk_div" },
+ { CCS_R_MAX_PRE_PLL_CLK_DIV, 2, 0, "max_pre_pll_clk_div" },
+ { CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_pll_ip_clk_freq_mhz" },
+ { CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_pll_ip_clk_freq_mhz" },
+ { CCS_R_MIN_PLL_MULTIPLIER, 2, 0, "min_pll_multiplier" },
+ { CCS_R_MAX_PLL_MULTIPLIER, 2, 0, "max_pll_multiplier" },
+ { CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_pll_op_clk_freq_mhz" },
+ { CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_pll_op_clk_freq_mhz" },
+ { CCS_R_MIN_VT_SYS_CLK_DIV, 2, 0, "min_vt_sys_clk_div" },
+ { CCS_R_MAX_VT_SYS_CLK_DIV, 2, 0, "max_vt_sys_clk_div" },
+ { CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ, 4, 0, "min_vt_sys_clk_freq_mhz" },
+ { CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ, 4, 0, "max_vt_sys_clk_freq_mhz" },
+ { CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ, 4, 0, "min_vt_pix_clk_freq_mhz" },
+ { CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ, 4, 0, "max_vt_pix_clk_freq_mhz" },
+ { CCS_R_MIN_VT_PIX_CLK_DIV, 2, 0, "min_vt_pix_clk_div" },
+ { CCS_R_MAX_VT_PIX_CLK_DIV, 2, 0, "max_vt_pix_clk_div" },
+ { CCS_R_CLOCK_CALCULATION, 1, 0, "clock_calculation" },
+ { CCS_R_NUM_OF_VT_LANES, 1, 0, "num_of_vt_lanes" },
+ { CCS_R_NUM_OF_OP_LANES, 1, 0, "num_of_op_lanes" },
+ { CCS_R_OP_BITS_PER_LANE, 1, 0, "op_bits_per_lane" },
+ { CCS_R_MIN_FRAME_LENGTH_LINES, 2, 0, "min_frame_length_lines" },
+ { CCS_R_MAX_FRAME_LENGTH_LINES, 2, 0, "max_frame_length_lines" },
+ { CCS_R_MIN_LINE_LENGTH_PCK, 2, 0, "min_line_length_pck" },
+ { CCS_R_MAX_LINE_LENGTH_PCK, 2, 0, "max_line_length_pck" },
+ { CCS_R_MIN_LINE_BLANKING_PCK, 2, 0, "min_line_blanking_pck" },
+ { CCS_R_MIN_FRAME_BLANKING_LINES, 2, 0, "min_frame_blanking_lines" },
+ { CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE, 1, 0, "min_line_length_pck_step_size" },
+ { CCS_R_TIMING_MODE_CAPABILITY, 1, 0, "timing_mode_capability" },
+ { CCS_R_FRAME_MARGIN_MAX_VALUE, 2, 0, "frame_margin_max_value" },
+ { CCS_R_FRAME_MARGIN_MIN_VALUE, 1, 0, "frame_margin_min_value" },
+ { CCS_R_GAIN_DELAY_TYPE, 1, 0, "gain_delay_type" },
+ { CCS_R_MIN_OP_SYS_CLK_DIV, 2, 0, "min_op_sys_clk_div" },
+ { CCS_R_MAX_OP_SYS_CLK_DIV, 2, 0, "max_op_sys_clk_div" },
+ { CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ, 4, 0, "min_op_sys_clk_freq_mhz" },
+ { CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ, 4, 0, "max_op_sys_clk_freq_mhz" },
+ { CCS_R_MIN_OP_PIX_CLK_DIV, 2, 0, "min_op_pix_clk_div" },
+ { CCS_R_MAX_OP_PIX_CLK_DIV, 2, 0, "max_op_pix_clk_div" },
+ { CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ, 4, 0, "min_op_pix_clk_freq_mhz" },
+ { CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ, 4, 0, "max_op_pix_clk_freq_mhz" },
+ { CCS_R_X_ADDR_MIN, 2, 0, "x_addr_min" },
+ { CCS_R_Y_ADDR_MIN, 2, 0, "y_addr_min" },
+ { CCS_R_X_ADDR_MAX, 2, 0, "x_addr_max" },
+ { CCS_R_Y_ADDR_MAX, 2, 0, "y_addr_max" },
+ { CCS_R_MIN_X_OUTPUT_SIZE, 2, 0, "min_x_output_size" },
+ { CCS_R_MIN_Y_OUTPUT_SIZE, 2, 0, "min_y_output_size" },
+ { CCS_R_MAX_X_OUTPUT_SIZE, 2, 0, "max_x_output_size" },
+ { CCS_R_MAX_Y_OUTPUT_SIZE, 2, 0, "max_y_output_size" },
+ { CCS_R_X_ADDR_START_DIV_CONSTANT, 1, 0, "x_addr_start_div_constant" },
+ { CCS_R_Y_ADDR_START_DIV_CONSTANT, 1, 0, "y_addr_start_div_constant" },
+ { CCS_R_X_ADDR_END_DIV_CONSTANT, 1, 0, "x_addr_end_div_constant" },
+ { CCS_R_Y_ADDR_END_DIV_CONSTANT, 1, 0, "y_addr_end_div_constant" },
+ { CCS_R_X_SIZE_DIV, 1, 0, "x_size_div" },
+ { CCS_R_Y_SIZE_DIV, 1, 0, "y_size_div" },
+ { CCS_R_X_OUTPUT_DIV, 1, 0, "x_output_div" },
+ { CCS_R_Y_OUTPUT_DIV, 1, 0, "y_output_div" },
+ { CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT, 1, 0, "non_flexible_resolution_support" },
+ { CCS_R_MIN_OP_PRE_PLL_CLK_DIV, 2, 0, "min_op_pre_pll_clk_div" },
+ { CCS_R_MAX_OP_PRE_PLL_CLK_DIV, 2, 0, "max_op_pre_pll_clk_div" },
+ { CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_ip_clk_freq_mhz" },
+ { CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_ip_clk_freq_mhz" },
+ { CCS_R_MIN_OP_PLL_MULTIPLIER, 2, 0, "min_op_pll_multiplier" },
+ { CCS_R_MAX_OP_PLL_MULTIPLIER, 2, 0, "max_op_pll_multiplier" },
+ { CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_op_clk_freq_mhz" },
+ { CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_op_clk_freq_mhz" },
+ { CCS_R_CLOCK_TREE_PLL_CAPABILITY, 1, 0, "clock_tree_pll_capability" },
+ { CCS_R_CLOCK_CAPA_TYPE_CAPABILITY, 1, 0, "clock_capa_type_capability" },
+ { CCS_R_MIN_EVEN_INC, 2, 0, "min_even_inc" },
+ { CCS_R_MIN_ODD_INC, 2, 0, "min_odd_inc" },
+ { CCS_R_MAX_EVEN_INC, 2, 0, "max_even_inc" },
+ { CCS_R_MAX_ODD_INC, 2, 0, "max_odd_inc" },
+ { CCS_R_AUX_SUBSAMP_CAPABILITY, 1, 0, "aux_subsamp_capability" },
+ { CCS_R_AUX_SUBSAMP_MONO_CAPABILITY, 1, 0, "aux_subsamp_mono_capability" },
+ { CCS_R_MONOCHROME_CAPABILITY, 1, 0, "monochrome_capability" },
+ { CCS_R_PIXEL_READOUT_CAPABILITY, 1, 0, "pixel_readout_capability" },
+ { CCS_R_MIN_EVEN_INC_MONO, 2, 0, "min_even_inc_mono" },
+ { CCS_R_MAX_EVEN_INC_MONO, 2, 0, "max_even_inc_mono" },
+ { CCS_R_MIN_ODD_INC_MONO, 2, 0, "min_odd_inc_mono" },
+ { CCS_R_MAX_ODD_INC_MONO, 2, 0, "max_odd_inc_mono" },
+ { CCS_R_MIN_EVEN_INC_BC2, 2, 0, "min_even_inc_bc2" },
+ { CCS_R_MAX_EVEN_INC_BC2, 2, 0, "max_even_inc_bc2" },
+ { CCS_R_MIN_ODD_INC_BC2, 2, 0, "min_odd_inc_bc2" },
+ { CCS_R_MAX_ODD_INC_BC2, 2, 0, "max_odd_inc_bc2" },
+ { CCS_R_MIN_EVEN_INC_MONO_BC2, 2, 0, "min_even_inc_mono_bc2" },
+ { CCS_R_MAX_EVEN_INC_MONO_BC2, 2, 0, "max_even_inc_mono_bc2" },
+ { CCS_R_MIN_ODD_INC_MONO_BC2, 2, 0, "min_odd_inc_mono_bc2" },
+ { CCS_R_MAX_ODD_INC_MONO_BC2, 2, 0, "max_odd_inc_mono_bc2" },
+ { CCS_R_SCALING_CAPABILITY, 2, 0, "scaling_capability" },
+ { CCS_R_SCALER_M_MIN, 2, 0, "scaler_m_min" },
+ { CCS_R_SCALER_M_MAX, 2, 0, "scaler_m_max" },
+ { CCS_R_SCALER_N_MIN, 2, 0, "scaler_n_min" },
+ { CCS_R_SCALER_N_MAX, 2, 0, "scaler_n_max" },
+ { CCS_R_DIGITAL_CROP_CAPABILITY, 1, 0, "digital_crop_capability" },
+ { CCS_R_HDR_CAPABILITY_1, 1, 0, "hdr_capability_1" },
+ { CCS_R_MIN_HDR_BIT_DEPTH, 1, 0, "min_hdr_bit_depth" },
+ { CCS_R_HDR_RESOLUTION_SUB_TYPES, 1, 0, "hdr_resolution_sub_types" },
+ { CCS_R_HDR_RESOLUTION_SUB_TYPE(0), 2, 0, "hdr_resolution_sub_type" },
+ { CCS_R_HDR_CAPABILITY_2, 1, 0, "hdr_capability_2" },
+ { CCS_R_MAX_HDR_BIT_DEPTH, 1, 0, "max_hdr_bit_depth" },
+ { CCS_R_USL_SUPPORT_CAPABILITY, 1, 0, "usl_support_capability" },
+ { CCS_R_USL_CLOCK_MODE_D_CAPABILITY, 1, 0, "usl_clock_mode_d_capability" },
+ { CCS_R_MIN_OP_SYS_CLK_DIV_REV, 1, 0, "min_op_sys_clk_div_rev" },
+ { CCS_R_MAX_OP_SYS_CLK_DIV_REV, 1, 0, "max_op_sys_clk_div_rev" },
+ { CCS_R_MIN_OP_PIX_CLK_DIV_REV, 1, 0, "min_op_pix_clk_div_rev" },
+ { CCS_R_MAX_OP_PIX_CLK_DIV_REV, 1, 0, "max_op_pix_clk_div_rev" },
+ { CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "min_op_sys_clk_freq_rev_mhz" },
+ { CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "max_op_sys_clk_freq_rev_mhz" },
+ { CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "min_op_pix_clk_freq_rev_mhz" },
+ { CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "max_op_pix_clk_freq_rev_mhz" },
+ { CCS_R_MAX_BITRATE_REV_D_MODE_MBPS, 4, 0, "max_bitrate_rev_d_mode_mbps" },
+ { CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS, 4, 0, "max_symrate_rev_c_mode_msps" },
+ { CCS_R_COMPRESSION_CAPABILITY, 1, 0, "compression_capability" },
+ { CCS_R_TEST_MODE_CAPABILITY, 2, 0, "test_mode_capability" },
+ { CCS_R_PN9_DATA_FORMAT1, 1, 0, "pn9_data_format1" },
+ { CCS_R_PN9_DATA_FORMAT2, 1, 0, "pn9_data_format2" },
+ { CCS_R_PN9_DATA_FORMAT3, 1, 0, "pn9_data_format3" },
+ { CCS_R_PN9_DATA_FORMAT4, 1, 0, "pn9_data_format4" },
+ { CCS_R_PN9_MISC_CAPABILITY, 1, 0, "pn9_misc_capability" },
+ { CCS_R_TEST_PATTERN_CAPABILITY, 1, 0, "test_pattern_capability" },
+ { CCS_R_PATTERN_SIZE_DIV_M1, 1, 0, "pattern_size_div_m1" },
+ { CCS_R_FIFO_SUPPORT_CAPABILITY, 1, 0, "fifo_support_capability" },
+ { CCS_R_PHY_CTRL_CAPABILITY, 1, 0, "phy_ctrl_capability" },
+ { CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_dphy_lane_mode_capability" },
+ { CCS_R_CSI_SIGNALING_MODE_CAPABILITY, 1, 0, "csi_signaling_mode_capability" },
+ { CCS_R_FAST_STANDBY_CAPABILITY, 1, 0, "fast_standby_capability" },
+ { CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY, 1, 0, "csi_address_control_capability" },
+ { CCS_R_DATA_TYPE_CAPABILITY, 1, 0, "data_type_capability" },
+ { CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_cphy_lane_mode_capability" },
+ { CCS_R_EMB_DATA_CAPABILITY, 1, 0, "emb_data_capability" },
+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_d_mode_mbps 0" },
+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_d_mode_mbps 4" },
+ { CCS_R_TEMP_SENSOR_CAPABILITY, 1, 0, "temp_sensor_capability" },
+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_c_mode_mbps 0" },
+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_c_mode_mbps 4" },
+ { CCS_R_DPHY_EQUALIZATION_CAPABILITY, 1, 0, "dphy_equalization_capability" },
+ { CCS_R_CPHY_EQUALIZATION_CAPABILITY, 1, 0, "cphy_equalization_capability" },
+ { CCS_R_DPHY_PREAMBLE_CAPABILITY, 1, 0, "dphy_preamble_capability" },
+ { CCS_R_DPHY_SSC_CAPABILITY, 1, 0, "dphy_ssc_capability" },
+ { CCS_R_CPHY_CALIBRATION_CAPABILITY, 1, 0, "cphy_calibration_capability" },
+ { CCS_R_DPHY_CALIBRATION_CAPABILITY, 1, 0, "dphy_calibration_capability" },
+ { CCS_R_PHY_CTRL_CAPABILITY_2, 1, 0, "phy_ctrl_capability_2" },
+ { CCS_R_LRTE_CPHY_CAPABILITY, 1, 0, "lrte_cphy_capability" },
+ { CCS_R_LRTE_DPHY_CAPABILITY, 1, 0, "lrte_dphy_capability" },
+ { CCS_R_ALPS_CAPABILITY_DPHY, 1, 0, "alps_capability_dphy" },
+ { CCS_R_ALPS_CAPABILITY_CPHY, 1, 0, "alps_capability_cphy" },
+ { CCS_R_SCRAMBLING_CAPABILITY, 1, 0, "scrambling_capability" },
+ { CCS_R_DPHY_MANUAL_CONSTANT, 1, 0, "dphy_manual_constant" },
+ { CCS_R_CPHY_MANUAL_CONSTANT, 1, 0, "cphy_manual_constant" },
+ { CCS_R_CSI2_INTERFACE_CAPABILITY_MISC, 1, 0, "CSI2_interface_capability_misc" },
+ { CCS_R_PHY_CTRL_CAPABILITY_3, 1, 0, "PHY_ctrl_capability_3" },
+ { CCS_R_DPHY_SF, 1, 0, "dphy_sf" },
+ { CCS_R_CPHY_SF, 1, 0, "cphy_sf" },
+ { CCS_R_DPHY_LIMITS_1, 1, 0, "dphy_limits_1" },
+ { CCS_R_DPHY_LIMITS_2, 1, 0, "dphy_limits_2" },
+ { CCS_R_DPHY_LIMITS_3, 1, 0, "dphy_limits_3" },
+ { CCS_R_DPHY_LIMITS_4, 1, 0, "dphy_limits_4" },
+ { CCS_R_DPHY_LIMITS_5, 1, 0, "dphy_limits_5" },
+ { CCS_R_DPHY_LIMITS_6, 1, 0, "dphy_limits_6" },
+ { CCS_R_CPHY_LIMITS_1, 1, 0, "cphy_limits_1" },
+ { CCS_R_CPHY_LIMITS_2, 1, 0, "cphy_limits_2" },
+ { CCS_R_CPHY_LIMITS_3, 1, 0, "cphy_limits_3" },
+ { CCS_R_MIN_FRAME_LENGTH_LINES_BIN, 2, 0, "min_frame_length_lines_bin" },
+ { CCS_R_MAX_FRAME_LENGTH_LINES_BIN, 2, 0, "max_frame_length_lines_bin" },
+ { CCS_R_MIN_LINE_LENGTH_PCK_BIN, 2, 0, "min_line_length_pck_bin" },
+ { CCS_R_MAX_LINE_LENGTH_PCK_BIN, 2, 0, "max_line_length_pck_bin" },
+ { CCS_R_MIN_LINE_BLANKING_PCK_BIN, 2, 0, "min_line_blanking_pck_bin" },
+ { CCS_R_FINE_INTEGRATION_TIME_MIN_BIN, 2, 0, "fine_integration_time_min_bin" },
+ { CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN, 2, 0, "fine_integration_time_max_margin_bin" },
+ { CCS_R_BINNING_CAPABILITY, 1, 0, "binning_capability" },
+ { CCS_R_BINNING_WEIGHTING_CAPABILITY, 1, 0, "binning_weighting_capability" },
+ { CCS_R_BINNING_SUB_TYPES, 1, 0, "binning_sub_types" },
+ { CCS_R_BINNING_SUB_TYPE(0), 64, 0, "binning_sub_type" },
+ { CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY, 1, 0, "binning_weighting_mono_capability" },
+ { CCS_R_BINNING_SUB_TYPES_MONO, 1, 0, "binning_sub_types_mono" },
+ { CCS_R_BINNING_SUB_TYPE_MONO(0), 64, 0, "binning_sub_type_mono" },
+ { CCS_R_DATA_TRANSFER_IF_CAPABILITY, 1, 0, "data_transfer_if_capability" },
+ { CCS_R_SHADING_CORRECTION_CAPABILITY, 1, 0, "shading_correction_capability" },
+ { CCS_R_GREEN_IMBALANCE_CAPABILITY, 1, 0, "green_imbalance_capability" },
+ { CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY, 1, 0, "module_specific_correction_capability" },
+ { CCS_R_DEFECT_CORRECTION_CAPABILITY, 2, 0, "defect_correction_capability" },
+ { CCS_R_DEFECT_CORRECTION_CAPABILITY_2, 2, 0, "defect_correction_capability_2" },
+ { CCS_R_NF_CAPABILITY, 1, 0, "nf_capability" },
+ { CCS_R_OB_READOUT_CAPABILITY, 1, 0, "ob_readout_capability" },
+ { CCS_R_COLOR_FEEDBACK_CAPABILITY, 1, 0, "color_feedback_capability" },
+ { CCS_R_CFA_PATTERN_CAPABILITY, 1, 0, "CFA_pattern_capability" },
+ { CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY, 1, 0, "CFA_pattern_conversion_capability" },
+ { CCS_R_FLASH_MODE_CAPABILITY, 1, 0, "flash_mode_capability" },
+ { CCS_R_SA_STROBE_MODE_CAPABILITY, 1, 0, "sa_strobe_mode_capability" },
+ { CCS_R_RESET_MAX_DELAY, 1, 0, "reset_max_delay" },
+ { CCS_R_RESET_MIN_TIME, 1, 0, "reset_min_time" },
+ { CCS_R_PDAF_CAPABILITY_1, 1, 0, "pdaf_capability_1" },
+ { CCS_R_PDAF_CAPABILITY_2, 1, 0, "pdaf_capability_2" },
+ { CCS_R_BRACKETING_LUT_CAPABILITY_1, 1, 0, "bracketing_lut_capability_1" },
+ { CCS_R_BRACKETING_LUT_CAPABILITY_2, 1, 0, "bracketing_lut_capability_2" },
+ { CCS_R_BRACKETING_LUT_SIZE, 1, 0, "bracketing_lut_size" },
+ { 0 } /* Guardian */
+};
diff --git a/drivers/media/i2c/smiapp/ccs-limits.h b/drivers/media/i2c/smiapp/ccs-limits.h
new file mode 100644
index 000000000000..1efa43c23a2e
--- /dev/null
+++ b/drivers/media/i2c/smiapp/ccs-limits.h
@@ -0,0 +1,259 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/* Copyright (C) 2019--2020 Intel Corporation */
+
+#ifndef __CCS_LIMITS_H__
+#define __CCS_LIMITS_H__
+
+#include <linux/bits.h>
+#include <linux/types.h>
+
+struct ccs_limit {
+ u32 reg;
+ u16 size;
+ u16 flags;
+ const char *name;
+};
+
+#define CCS_L_FL_SAME_REG BIT(0)
+
+extern const struct ccs_limit ccs_limits[];
+
+#define CCS_L_FRAME_FORMAT_MODEL_TYPE 0
+#define CCS_L_FRAME_FORMAT_MODEL_SUBTYPE 1
+#define CCS_L_FRAME_FORMAT_DESCRIPTOR 2
+#define CCS_L_FRAME_FORMAT_DESCRIPTOR_OFFSET(n) ((n) * 2)
+#define CCS_L_FRAME_FORMAT_DESCRIPTOR_4 3
+#define CCS_L_FRAME_FORMAT_DESCRIPTOR_4_OFFSET(n) ((n) * 4)
+#define CCS_L_ANALOG_GAIN_CAPABILITY 4
+#define CCS_L_ANALOG_GAIN_CODE_MIN 5
+#define CCS_L_ANALOG_GAIN_CODE_MAX 6
+#define CCS_L_ANALOG_GAIN_CODE_STEP 7
+#define CCS_L_ANALOG_GAIN_TYPE 8
+#define CCS_L_ANALOG_GAIN_M0 9
+#define CCS_L_ANALOG_GAIN_C0 10
+#define CCS_L_ANALOG_GAIN_M1 11
+#define CCS_L_ANALOG_GAIN_C1 12
+#define CCS_L_ANALOG_LINEAR_GAIN_MIN 13
+#define CCS_L_ANALOG_LINEAR_GAIN_MAX 14
+#define CCS_L_ANALOG_LINEAR_GAIN_STEP_SIZE 15
+#define CCS_L_ANALOG_EXPONENTIAL_GAIN_MIN 16
+#define CCS_L_ANALOG_EXPONENTIAL_GAIN_MAX 17
+#define CCS_L_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE 18
+#define CCS_L_DATA_FORMAT_MODEL_TYPE 19
+#define CCS_L_DATA_FORMAT_MODEL_SUBTYPE 20
+#define CCS_L_DATA_FORMAT_DESCRIPTOR 21
+#define CCS_L_DATA_FORMAT_DESCRIPTOR_OFFSET(n) ((n) * 2)
+#define CCS_L_INTEGRATION_TIME_CAPABILITY 22
+#define CCS_L_COARSE_INTEGRATION_TIME_MIN 23
+#define CCS_L_COARSE_INTEGRATION_TIME_MAX_MARGIN 24
+#define CCS_L_FINE_INTEGRATION_TIME_MIN 25
+#define CCS_L_FINE_INTEGRATION_TIME_MAX_MARGIN 26
+#define CCS_L_DIGITAL_GAIN_CAPABILITY 27
+#define CCS_L_DIGITAL_GAIN_MIN 28
+#define CCS_L_DIGITAL_GAIN_MAX 29
+#define CCS_L_DIGITAL_GAIN_STEP_SIZE 30
+#define CCS_L_PEDESTAL_CAPABILITY 31
+#define CCS_L_ADC_CAPABILITY 32
+#define CCS_L_ADC_BIT_DEPTH_CAPABILITY 33
+#define CCS_L_MIN_EXT_CLK_FREQ_MHZ 34
+#define CCS_L_MAX_EXT_CLK_FREQ_MHZ 35
+#define CCS_L_MIN_PRE_PLL_CLK_DIV 36
+#define CCS_L_MAX_PRE_PLL_CLK_DIV 37
+#define CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ 38
+#define CCS_L_MAX_PLL_IP_CLK_FREQ_MHZ 39
+#define CCS_L_MIN_PLL_MULTIPLIER 40
+#define CCS_L_MAX_PLL_MULTIPLIER 41
+#define CCS_L_MIN_PLL_OP_CLK_FREQ_MHZ 42
+#define CCS_L_MAX_PLL_OP_CLK_FREQ_MHZ 43
+#define CCS_L_MIN_VT_SYS_CLK_DIV 44
+#define CCS_L_MAX_VT_SYS_CLK_DIV 45
+#define CCS_L_MIN_VT_SYS_CLK_FREQ_MHZ 46
+#define CCS_L_MAX_VT_SYS_CLK_FREQ_MHZ 47
+#define CCS_L_MIN_VT_PIX_CLK_FREQ_MHZ 48
+#define CCS_L_MAX_VT_PIX_CLK_FREQ_MHZ 49
+#define CCS_L_MIN_VT_PIX_CLK_DIV 50
+#define CCS_L_MAX_VT_PIX_CLK_DIV 51
+#define CCS_L_CLOCK_CALCULATION 52
+#define CCS_L_NUM_OF_VT_LANES 53
+#define CCS_L_NUM_OF_OP_LANES 54
+#define CCS_L_OP_BITS_PER_LANE 55
+#define CCS_L_MIN_FRAME_LENGTH_LINES 56
+#define CCS_L_MAX_FRAME_LENGTH_LINES 57
+#define CCS_L_MIN_LINE_LENGTH_PCK 58
+#define CCS_L_MAX_LINE_LENGTH_PCK 59
+#define CCS_L_MIN_LINE_BLANKING_PCK 60
+#define CCS_L_MIN_FRAME_BLANKING_LINES 61
+#define CCS_L_MIN_LINE_LENGTH_PCK_STEP_SIZE 62
+#define CCS_L_TIMING_MODE_CAPABILITY 63
+#define CCS_L_FRAME_MARGIN_MAX_VALUE 64
+#define CCS_L_FRAME_MARGIN_MIN_VALUE 65
+#define CCS_L_GAIN_DELAY_TYPE 66
+#define CCS_L_MIN_OP_SYS_CLK_DIV 67
+#define CCS_L_MAX_OP_SYS_CLK_DIV 68
+#define CCS_L_MIN_OP_SYS_CLK_FREQ_MHZ 69
+#define CCS_L_MAX_OP_SYS_CLK_FREQ_MHZ 70
+#define CCS_L_MIN_OP_PIX_CLK_DIV 71
+#define CCS_L_MAX_OP_PIX_CLK_DIV 72
+#define CCS_L_MIN_OP_PIX_CLK_FREQ_MHZ 73
+#define CCS_L_MAX_OP_PIX_CLK_FREQ_MHZ 74
+#define CCS_L_X_ADDR_MIN 75
+#define CCS_L_Y_ADDR_MIN 76
+#define CCS_L_X_ADDR_MAX 77
+#define CCS_L_Y_ADDR_MAX 78
+#define CCS_L_MIN_X_OUTPUT_SIZE 79
+#define CCS_L_MIN_Y_OUTPUT_SIZE 80
+#define CCS_L_MAX_X_OUTPUT_SIZE 81
+#define CCS_L_MAX_Y_OUTPUT_SIZE 82
+#define CCS_L_X_ADDR_START_DIV_CONSTANT 83
+#define CCS_L_Y_ADDR_START_DIV_CONSTANT 84
+#define CCS_L_X_ADDR_END_DIV_CONSTANT 85
+#define CCS_L_Y_ADDR_END_DIV_CONSTANT 86
+#define CCS_L_X_SIZE_DIV 87
+#define CCS_L_Y_SIZE_DIV 88
+#define CCS_L_X_OUTPUT_DIV 89
+#define CCS_L_Y_OUTPUT_DIV 90
+#define CCS_L_NON_FLEXIBLE_RESOLUTION_SUPPORT 91
+#define CCS_L_MIN_OP_PRE_PLL_CLK_DIV 92
+#define CCS_L_MAX_OP_PRE_PLL_CLK_DIV 93
+#define CCS_L_MIN_OP_PLL_IP_CLK_FREQ_MHZ 94
+#define CCS_L_MAX_OP_PLL_IP_CLK_FREQ_MHZ 95
+#define CCS_L_MIN_OP_PLL_MULTIPLIER 96
+#define CCS_L_MAX_OP_PLL_MULTIPLIER 97
+#define CCS_L_MIN_OP_PLL_OP_CLK_FREQ_MHZ 98
+#define CCS_L_MAX_OP_PLL_OP_CLK_FREQ_MHZ 99
+#define CCS_L_CLOCK_TREE_PLL_CAPABILITY 100
+#define CCS_L_CLOCK_CAPA_TYPE_CAPABILITY 101
+#define CCS_L_MIN_EVEN_INC 102
+#define CCS_L_MIN_ODD_INC 103
+#define CCS_L_MAX_EVEN_INC 104
+#define CCS_L_MAX_ODD_INC 105
+#define CCS_L_AUX_SUBSAMP_CAPABILITY 106
+#define CCS_L_AUX_SUBSAMP_MONO_CAPABILITY 107
+#define CCS_L_MONOCHROME_CAPABILITY 108
+#define CCS_L_PIXEL_READOUT_CAPABILITY 109
+#define CCS_L_MIN_EVEN_INC_MONO 110
+#define CCS_L_MAX_EVEN_INC_MONO 111
+#define CCS_L_MIN_ODD_INC_MONO 112
+#define CCS_L_MAX_ODD_INC_MONO 113
+#define CCS_L_MIN_EVEN_INC_BC2 114
+#define CCS_L_MAX_EVEN_INC_BC2 115
+#define CCS_L_MIN_ODD_INC_BC2 116
+#define CCS_L_MAX_ODD_INC_BC2 117
+#define CCS_L_MIN_EVEN_INC_MONO_BC2 118
+#define CCS_L_MAX_EVEN_INC_MONO_BC2 119
+#define CCS_L_MIN_ODD_INC_MONO_BC2 120
+#define CCS_L_MAX_ODD_INC_MONO_BC2 121
+#define CCS_L_SCALING_CAPABILITY 122
+#define CCS_L_SCALER_M_MIN 123
+#define CCS_L_SCALER_M_MAX 124
+#define CCS_L_SCALER_N_MIN 125
+#define CCS_L_SCALER_N_MAX 126
+#define CCS_L_DIGITAL_CROP_CAPABILITY 127
+#define CCS_L_HDR_CAPABILITY_1 128
+#define CCS_L_MIN_HDR_BIT_DEPTH 129
+#define CCS_L_HDR_RESOLUTION_SUB_TYPES 130
+#define CCS_L_HDR_RESOLUTION_SUB_TYPE 131
+#define CCS_L_HDR_RESOLUTION_SUB_TYPE_OFFSET(n) (n)
+#define CCS_L_HDR_CAPABILITY_2 132
+#define CCS_L_MAX_HDR_BIT_DEPTH 133
+#define CCS_L_USL_SUPPORT_CAPABILITY 134
+#define CCS_L_USL_CLOCK_MODE_D_CAPABILITY 135
+#define CCS_L_MIN_OP_SYS_CLK_DIV_REV 136
+#define CCS_L_MAX_OP_SYS_CLK_DIV_REV 137
+#define CCS_L_MIN_OP_PIX_CLK_DIV_REV 138
+#define CCS_L_MAX_OP_PIX_CLK_DIV_REV 139
+#define CCS_L_MIN_OP_SYS_CLK_FREQ_REV_MHZ 140
+#define CCS_L_MAX_OP_SYS_CLK_FREQ_REV_MHZ 141
+#define CCS_L_MIN_OP_PIX_CLK_FREQ_REV_MHZ 142
+#define CCS_L_MAX_OP_PIX_CLK_FREQ_REV_MHZ 143
+#define CCS_L_MAX_BITRATE_REV_D_MODE_MBPS 144
+#define CCS_L_MAX_SYMRATE_REV_C_MODE_MSPS 145
+#define CCS_L_COMPRESSION_CAPABILITY 146
+#define CCS_L_TEST_MODE_CAPABILITY 147
+#define CCS_L_PN9_DATA_FORMAT1 148
+#define CCS_L_PN9_DATA_FORMAT2 149
+#define CCS_L_PN9_DATA_FORMAT3 150
+#define CCS_L_PN9_DATA_FORMAT4 151
+#define CCS_L_PN9_MISC_CAPABILITY 152
+#define CCS_L_TEST_PATTERN_CAPABILITY 153
+#define CCS_L_PATTERN_SIZE_DIV_M1 154
+#define CCS_L_FIFO_SUPPORT_CAPABILITY 155
+#define CCS_L_PHY_CTRL_CAPABILITY 156
+#define CCS_L_CSI_DPHY_LANE_MODE_CAPABILITY 157
+#define CCS_L_CSI_SIGNALING_MODE_CAPABILITY 158
+#define CCS_L_FAST_STANDBY_CAPABILITY 159
+#define CCS_L_CSI_ADDRESS_CONTROL_CAPABILITY 160
+#define CCS_L_DATA_TYPE_CAPABILITY 161
+#define CCS_L_CSI_CPHY_LANE_MODE_CAPABILITY 162
+#define CCS_L_EMB_DATA_CAPABILITY 163
+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS 164
+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_OFFSET(n) ((n) * 4)
+#define CCS_L_TEMP_SENSOR_CAPABILITY 165
+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS 166
+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_OFFSET(n) ((n) * 4)
+#define CCS_L_DPHY_EQUALIZATION_CAPABILITY 167
+#define CCS_L_CPHY_EQUALIZATION_CAPABILITY 168
+#define CCS_L_DPHY_PREAMBLE_CAPABILITY 169
+#define CCS_L_DPHY_SSC_CAPABILITY 170
+#define CCS_L_CPHY_CALIBRATION_CAPABILITY 171
+#define CCS_L_DPHY_CALIBRATION_CAPABILITY 172
+#define CCS_L_PHY_CTRL_CAPABILITY_2 173
+#define CCS_L_LRTE_CPHY_CAPABILITY 174
+#define CCS_L_LRTE_DPHY_CAPABILITY 175
+#define CCS_L_ALPS_CAPABILITY_DPHY 176
+#define CCS_L_ALPS_CAPABILITY_CPHY 177
+#define CCS_L_SCRAMBLING_CAPABILITY 178
+#define CCS_L_DPHY_MANUAL_CONSTANT 179
+#define CCS_L_CPHY_MANUAL_CONSTANT 180
+#define CCS_L_CSI2_INTERFACE_CAPABILITY_MISC 181
+#define CCS_L_PHY_CTRL_CAPABILITY_3 182
+#define CCS_L_DPHY_SF 183
+#define CCS_L_CPHY_SF 184
+#define CCS_L_DPHY_LIMITS_1 185
+#define CCS_L_DPHY_LIMITS_2 186
+#define CCS_L_DPHY_LIMITS_3 187
+#define CCS_L_DPHY_LIMITS_4 188
+#define CCS_L_DPHY_LIMITS_5 189
+#define CCS_L_DPHY_LIMITS_6 190
+#define CCS_L_CPHY_LIMITS_1 191
+#define CCS_L_CPHY_LIMITS_2 192
+#define CCS_L_CPHY_LIMITS_3 193
+#define CCS_L_MIN_FRAME_LENGTH_LINES_BIN 194
+#define CCS_L_MAX_FRAME_LENGTH_LINES_BIN 195
+#define CCS_L_MIN_LINE_LENGTH_PCK_BIN 196
+#define CCS_L_MAX_LINE_LENGTH_PCK_BIN 197
+#define CCS_L_MIN_LINE_BLANKING_PCK_BIN 198
+#define CCS_L_FINE_INTEGRATION_TIME_MIN_BIN 199
+#define CCS_L_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN 200
+#define CCS_L_BINNING_CAPABILITY 201
+#define CCS_L_BINNING_WEIGHTING_CAPABILITY 202
+#define CCS_L_BINNING_SUB_TYPES 203
+#define CCS_L_BINNING_SUB_TYPE 204
+#define CCS_L_BINNING_SUB_TYPE_OFFSET(n) (n)
+#define CCS_L_BINNING_WEIGHTING_MONO_CAPABILITY 205
+#define CCS_L_BINNING_SUB_TYPES_MONO 206
+#define CCS_L_BINNING_SUB_TYPE_MONO 207
+#define CCS_L_BINNING_SUB_TYPE_MONO_OFFSET(n) (n)
+#define CCS_L_DATA_TRANSFER_IF_CAPABILITY 208
+#define CCS_L_SHADING_CORRECTION_CAPABILITY 209
+#define CCS_L_GREEN_IMBALANCE_CAPABILITY 210
+#define CCS_L_MODULE_SPECIFIC_CORRECTION_CAPABILITY 211
+#define CCS_L_DEFECT_CORRECTION_CAPABILITY 212
+#define CCS_L_DEFECT_CORRECTION_CAPABILITY_2 213
+#define CCS_L_NF_CAPABILITY 214
+#define CCS_L_OB_READOUT_CAPABILITY 215
+#define CCS_L_COLOR_FEEDBACK_CAPABILITY 216
+#define CCS_L_CFA_PATTERN_CAPABILITY 217
+#define CCS_L_CFA_PATTERN_CONVERSION_CAPABILITY 218
+#define CCS_L_FLASH_MODE_CAPABILITY 219
+#define CCS_L_SA_STROBE_MODE_CAPABILITY 220
+#define CCS_L_RESET_MAX_DELAY 221
+#define CCS_L_RESET_MIN_TIME 222
+#define CCS_L_PDAF_CAPABILITY_1 223
+#define CCS_L_PDAF_CAPABILITY_2 224
+#define CCS_L_BRACKETING_LUT_CAPABILITY_1 225
+#define CCS_L_BRACKETING_LUT_CAPABILITY_2 226
+#define CCS_L_BRACKETING_LUT_SIZE 227
+#define CCS_L_LAST 228
+
+#endif /* __CCS_LIMITS_H__ */
diff --git a/drivers/media/i2c/smiapp/ccs-regs.h b/drivers/media/i2c/smiapp/ccs-regs.h
new file mode 100644
index 000000000000..4b3e5df2121f
--- /dev/null
+++ b/drivers/media/i2c/smiapp/ccs-regs.h
@@ -0,0 +1,954 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/* Copyright (C) 2019--2020 Intel Corporation */
+
+#ifndef __CCS_REGS_H__
+#define __CCS_REGS_H__
+
+#include <linux/bits.h>
+
+#define CCS_FL_BASE 16
+#define CCS_FL_16BIT BIT(CCS_FL_BASE)
+#define CCS_FL_32BIT BIT(CCS_FL_BASE + 1)
+#define CCS_FL_FLOAT_IREAL BIT(CCS_FL_BASE + 2)
+#define CCS_FL_IREAL BIT(CCS_FL_BASE + 3)
+#define CCS_R_ADDR(r) ((r) & 0xffff)
+
+#define CCS_R_MODULE_MODEL_ID (0x0000 | CCS_FL_16BIT)
+#define CCS_R_MODULE_REVISION_NUMBER_MAJOR 0x0002
+#define CCS_R_FRAME_COUNT 0x0005
+#define CCS_R_PIXEL_ORDER 0x0006
+#define CCS_PIXEL_ORDER_GRBG 0U
+#define CCS_PIXEL_ORDER_RGGB 1U
+#define CCS_PIXEL_ORDER_BGGR 2U
+#define CCS_PIXEL_ORDER_GBRG 3U
+#define CCS_R_MIPI_CCS_VERSION 0x0007
+#define CCS_MIPI_CCS_VERSION_V1_0 0x10
+#define CCS_MIPI_CCS_VERSION_V1_1 0x11
+#define CCS_MIPI_CCS_VERSION_MAJOR_SHIFT 4U
+#define CCS_MIPI_CCS_VERSION_MAJOR_MASK 0xf0
+#define CCS_MIPI_CCS_VERSION_MINOR_SHIFT 0U
+#define CCS_MIPI_CCS_VERSION_MINOR_MASK 0xf
+#define CCS_R_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT)
+#define CCS_R_MODULE_MANUFACTURER_ID (0x000e | CCS_FL_16BIT)
+#define CCS_R_MODULE_REVISION_NUMBER_MINOR 0x0010
+#define CCS_R_MODULE_DATE_YEAR 0x0012
+#define CCS_R_MODULE_DATE_MONTH 0x0013
+#define CCS_R_MODULE_DATE_DAY 0x0014
+#define CCS_R_MODULE_DATE_PHASE 0x0015
+#define CCS_MODULE_DATE_PHASE_SHIFT 0U
+#define CCS_MODULE_DATE_PHASE_MASK 0x7
+#define CCS_MODULE_DATE_PHASE_TS 0U
+#define CCS_MODULE_DATE_PHASE_ES 1U
+#define CCS_MODULE_DATE_PHASE_CS 2U
+#define CCS_MODULE_DATE_PHASE_MP 3U
+#define CCS_R_SENSOR_MODEL_ID (0x0016 | CCS_FL_16BIT)
+#define CCS_R_SENSOR_REVISION_NUMBER 0x0018
+#define CCS_R_SENSOR_FIRMWARE_VERSION 0x001a
+#define CCS_R_SERIAL_NUMBER (0x001c | CCS_FL_32BIT)
+#define CCS_R_SENSOR_MANUFACTURER_ID (0x0020 | CCS_FL_16BIT)
+#define CCS_R_SENSOR_REVISION_NUMBER_16 (0x0022 | CCS_FL_16BIT)
+#define CCS_R_FRAME_FORMAT_MODEL_TYPE 0x0040
+#define CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE 1U
+#define CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE 2U
+#define CCS_R_FRAME_FORMAT_MODEL_SUBTYPE 0x0041
+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U
+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf
+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U
+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0
+#define CCS_R_FRAME_FORMAT_DESCRIPTOR(n) ((0x0042 | CCS_FL_16BIT) + (n) * 2)
+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MIN_N 0U
+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MAX_N 14U
+#define CCS_R_FRAME_FORMAT_DESCRIPTOR_4(n) ((0x0060 | CCS_FL_32BIT) + (n) * 4)
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_SHIFT 0U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK 0xfff
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT 12U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK 0xf000
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED 1U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL 2U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_BLACK_PIXEL 3U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DARK_PIXEL 4U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL 5U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_0 8U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_1 9U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_2 10U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_3 11U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_4 12U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_5 13U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_6 14U
+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MIN_N 0U
+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MAX_N 7U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_SHIFT 0U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK 0xffff
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_SHIFT 28U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK 0xf0000000
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_EMBEDDED 1U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DUMMY_PIXEL 2U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_BLACK_PIXEL 3U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DARK_PIXEL 4U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_VISIBLE_PIXEL 5U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_0 8U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_1 9U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_2 10U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_3 11U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_4 12U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_5 13U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_6 14U
+#define CCS_R_ANALOG_GAIN_CAPABILITY (0x0080 | CCS_FL_16BIT)
+#define CCS_ANALOG_GAIN_CAPABILITY_GLOBAL 0U
+#define CCS_ANALOG_GAIN_CAPABILITY_ALTERNATE_GLOBAL 2U
+#define CCS_R_ANALOG_GAIN_CODE_MIN (0x0084 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_CODE_MAX (0x0086 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_CODE_STEP (0x0088 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_TYPE (0x008a | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_M0 (0x008c | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_C0 (0x008e | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_M1 (0x0090 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_C1 (0x0092 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_LINEAR_GAIN_MIN (0x0094 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_LINEAR_GAIN_MAX (0x0096 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE (0x0098 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN (0x009a | CCS_FL_16BIT)
+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX (0x009c | CCS_FL_16BIT)
+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE (0x009e | CCS_FL_16BIT)
+#define CCS_R_DATA_FORMAT_MODEL_TYPE 0x00c0
+#define CCS_DATA_FORMAT_MODEL_TYPE_NORMAL 1U
+#define CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED 2U
+#define CCS_R_DATA_FORMAT_MODEL_SUBTYPE 0x00c1
+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U
+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf
+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U
+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0
+#define CCS_R_DATA_FORMAT_DESCRIPTOR(n) ((0x00c2 | CCS_FL_16BIT) + (n) * 2)
+#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MIN_N 0U
+#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N 15U
+#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_SHIFT 0U
+#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK 0xff
+#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT 8U
+#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_MASK 0xff00
+#define CCS_R_MODE_SELECT 0x0100
+#define CCS_MODE_SELECT_SOFTWARE_STANDBY 0U
+#define CCS_MODE_SELECT_STREAMING 1U
+#define CCS_R_IMAGE_ORIENTATION 0x0101
+#define CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR BIT(0)
+#define CCS_IMAGE_ORIENTATION_VERTICAL_FLIP BIT(1)
+#define CCS_R_SOFTWARE_RESET 0x0103
+#define CCS_SOFTWARE_RESET_OFF 0U
+#define CCS_SOFTWARE_RESET_ON 1U
+#define CCS_R_GROUPED_PARAMETER_HOLD 0x0104
+#define CCS_R_MASK_CORRUPTED_FRAMES 0x0105
+#define CCS_MASK_CORRUPTED_FRAMES_ALLOW 0U
+#define CCS_MASK_CORRUPTED_FRAMES_MASK 1U
+#define CCS_R_FAST_STANDBY_CTRL 0x0106
+#define CCS_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0U
+#define CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION 1U
+#define CCS_R_CCI_ADDRESS_CTRL 0x0107
+#define CCS_R_2ND_CCI_IF_CTRL 0x0108
+#define CCS_2ND_CCI_IF_CTRL_ENABLE BIT(0)
+#define CCS_2ND_CCI_IF_CTRL_ACK BIT(1)
+#define CCS_R_2ND_CCI_ADDRESS_CTRL 0x0109
+#define CCS_R_CSI_CHANNEL_IDENTIFIER 0x0110
+#define CCS_R_CSI_SIGNALING_MODE 0x0111
+#define CCS_CSI_SIGNALING_MODE_CSI_2_DPHY 2U
+#define CCS_CSI_SIGNALING_MODE_CSI_2_CPHY 3U
+#define CCS_R_CSI_DATA_FORMAT (0x0112 | CCS_FL_16BIT)
+#define CCS_R_CSI_LANE_MODE 0x0114
+#define CCS_R_DPCM_FRAME_DT 0x011d
+#define CCS_R_BOTTOM_EMBEDDED_DATA_DT 0x011e
+#define CCS_R_BOTTOM_EMBEDDED_DATA_VC 0x011f
+#define CCS_R_GAIN_MODE 0x0120
+#define CCS_GAIN_MODE_GLOBAL 0U
+#define CCS_GAIN_MODE_ALTERNATE 1U
+#define CCS_R_ADC_BIT_DEPTH 0x0121
+#define CCS_R_EMB_DATA_CTRL 0x0122
+#define CCS_EMB_DATA_CTRL_RAW8_PACKING_FOR_RAW16 BIT(0)
+#define CCS_EMB_DATA_CTRL_RAW10_PACKING_FOR_RAW20 BIT(1)
+#define CCS_EMB_DATA_CTRL_RAW12_PACKING_FOR_RAW24 BIT(2)
+#define CCS_R_GPIO_TRIG_MODE 0x0130
+#define CCS_R_EXTCLK_FREQUENCY_MHZ (0x0136 | (CCS_FL_16BIT | CCS_FL_IREAL))
+#define CCS_R_TEMP_SENSOR_CTRL 0x0138
+#define CCS_TEMP_SENSOR_CTRL_ENABLE BIT(0)
+#define CCS_R_TEMP_SENSOR_MODE 0x0139
+#define CCS_R_TEMP_SENSOR_OUTPUT 0x013a
+#define CCS_R_FINE_INTEGRATION_TIME (0x0200 | CCS_FL_16BIT)
+#define CCS_R_COARSE_INTEGRATION_TIME (0x0202 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_CODE_GLOBAL (0x0204 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_LINEAR_GAIN_GLOBAL (0x0206 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_GLOBAL (0x0208 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_GAIN_GLOBAL (0x020e | CCS_FL_16BIT)
+#define CCS_R_SHORT_ANALOG_GAIN_GLOBAL (0x0216 | CCS_FL_16BIT)
+#define CCS_R_SHORT_DIGITAL_GAIN_GLOBAL (0x0218 | CCS_FL_16BIT)
+#define CCS_R_HDR_MODE 0x0220
+#define CCS_HDR_MODE_ENABLED BIT(0)
+#define CCS_HDR_MODE_SEPARATE_ANALOG_GAIN BIT(1)
+#define CCS_HDR_MODE_UPSCALING BIT(2)
+#define CCS_HDR_MODE_RESET_SYNC BIT(3)
+#define CCS_HDR_MODE_TIMING_MODE BIT(4)
+#define CCS_HDR_MODE_EXPOSURE_CTRL_DIRECT BIT(5)
+#define CCS_HDR_MODE_SEPARATE_DIGITAL_GAIN BIT(6)
+#define CCS_R_HDR_RESOLUTION_REDUCTION 0x0221
+#define CCS_HDR_RESOLUTION_REDUCTION_ROW_SHIFT 0U
+#define CCS_HDR_RESOLUTION_REDUCTION_ROW_MASK 0xf
+#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_SHIFT 4U
+#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_MASK 0xf0
+#define CCS_R_EXPOSURE_RATIO 0x0222
+#define CCS_R_HDR_INTERNAL_BIT_DEPTH 0x0223
+#define CCS_R_DIRECT_SHORT_INTEGRATION_TIME (0x0224 | CCS_FL_16BIT)
+#define CCS_R_SHORT_ANALOG_LINEAR_GAIN_GLOBAL (0x0226 | CCS_FL_16BIT)
+#define CCS_R_SHORT_ANALOG_EXPONENTIAL_GAIN_GLOBAL (0x0228 | CCS_FL_16BIT)
+#define CCS_R_VT_PIX_CLK_DIV (0x0300 | CCS_FL_16BIT)
+#define CCS_R_VT_SYS_CLK_DIV (0x0302 | CCS_FL_16BIT)
+#define CCS_R_PRE_PLL_CLK_DIV (0x0304 | CCS_FL_16BIT)
+#define CCS_R_PLL_MULTIPLIER (0x0306 | CCS_FL_16BIT)
+#define CCS_R_OP_PIX_CLK_DIV (0x0308 | CCS_FL_16BIT)
+#define CCS_R_OP_SYS_CLK_DIV (0x030a | CCS_FL_16BIT)
+#define CCS_R_OP_PRE_PLL_CLK_DIV (0x030c | CCS_FL_16BIT)
+#define CCS_R_OP_PLL_MULTIPLIER (0x031e | CCS_FL_16BIT)
+#define CCS_R_PLL_MODE 0x0310
+#define CCS_PLL_MODE_SHIFT 0U
+#define CCS_PLL_MODE_MASK 0x1
+#define CCS_PLL_MODE_SINGLE 0U
+#define CCS_PLL_MODE_DUAL 1U
+#define CCS_R_OP_PIX_CLK_DIV_REV (0x0312 | CCS_FL_16BIT)
+#define CCS_R_OP_SYS_CLK_DIV_REV (0x0314 | CCS_FL_16BIT)
+#define CCS_R_FRAME_LENGTH_LINES (0x0340 | CCS_FL_16BIT)
+#define CCS_R_LINE_LENGTH_PCK (0x0342 | CCS_FL_16BIT)
+#define CCS_R_X_ADDR_START (0x0344 | CCS_FL_16BIT)
+#define CCS_R_Y_ADDR_START (0x0346 | CCS_FL_16BIT)
+#define CCS_R_X_ADDR_END (0x0348 | CCS_FL_16BIT)
+#define CCS_R_Y_ADDR_END (0x034a | CCS_FL_16BIT)
+#define CCS_R_X_OUTPUT_SIZE (0x034c | CCS_FL_16BIT)
+#define CCS_R_Y_OUTPUT_SIZE (0x034e | CCS_FL_16BIT)
+#define CCS_R_FRAME_LENGTH_CTRL 0x0350
+#define CCS_FRAME_LENGTH_CTRL_AUTOMATIC BIT(0)
+#define CCS_R_TIMING_MODE_CTRL 0x0352
+#define CCS_TIMING_MODE_CTRL_MANUAL_READOUT BIT(0)
+#define CCS_TIMING_MODE_CTRL_DELAYED_EXPOSURE BIT(1)
+#define CCS_R_START_READOUT_RS 0x0353
+#define CCS_START_READOUT_RS_MANUAL_READOUT_START BIT(0)
+#define CCS_R_FRAME_MARGIN (0x0354 | CCS_FL_16BIT)
+#define CCS_R_X_EVEN_INC (0x0380 | CCS_FL_16BIT)
+#define CCS_R_X_ODD_INC (0x0382 | CCS_FL_16BIT)
+#define CCS_R_Y_EVEN_INC (0x0384 | CCS_FL_16BIT)
+#define CCS_R_Y_ODD_INC (0x0386 | CCS_FL_16BIT)
+#define CCS_R_MONOCHROME_EN 0x0390
+#define CCS_MONOCHROME_EN_ENABLED 0U
+#define CCS_R_SCALING_MODE (0x0400 | CCS_FL_16BIT)
+#define CCS_SCALING_MODE_NO_SCALING 0U
+#define CCS_SCALING_MODE_HORIZONTAL 1U
+#define CCS_R_SCALE_M (0x0404 | CCS_FL_16BIT)
+#define CCS_R_SCALE_N (0x0406 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_X_OFFSET (0x0408 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_Y_OFFSET (0x040a | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_IMAGE_WIDTH (0x040c | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_IMAGE_HEIGHT (0x040e | CCS_FL_16BIT)
+#define CCS_R_COMPRESSION_MODE (0x0500 | CCS_FL_16BIT)
+#define CCS_COMPRESSION_MODE_NONE 0U
+#define CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE 1U
+#define CCS_R_TEST_PATTERN_MODE (0x0600 | CCS_FL_16BIT)
+#define CCS_TEST_PATTERN_MODE_NONE 0U
+#define CCS_TEST_PATTERN_MODE_SOLID_COLOR 1U
+#define CCS_TEST_PATTERN_MODE_COLOR_BARS 2U
+#define CCS_TEST_PATTERN_MODE_FADE_TO_GREY 3U
+#define CCS_TEST_PATTERN_MODE_PN9 4U
+#define CCS_TEST_PATTERN_MODE_COLOR_TILE 5U
+#define CCS_R_TEST_DATA_RED (0x0602 | CCS_FL_16BIT)
+#define CCS_R_TEST_DATA_GREENR (0x0604 | CCS_FL_16BIT)
+#define CCS_R_TEST_DATA_BLUE (0x0606 | CCS_FL_16BIT)
+#define CCS_R_TEST_DATA_GREENB (0x0608 | CCS_FL_16BIT)
+#define CCS_R_VALUE_STEP_SIZE_SMOOTH 0x060a
+#define CCS_R_VALUE_STEP_SIZE_QUANTISED 0x060b
+#define CCS_R_TCLK_POST 0x0800
+#define CCS_R_THS_PREPARE 0x0801
+#define CCS_R_THS_ZERO_MIN 0x0802
+#define CCS_R_THS_TRAIL 0x0803
+#define CCS_R_TCLK_TRAIL_MIN 0x0804
+#define CCS_R_TCLK_PREPARE 0x0805
+#define CCS_R_TCLK_ZERO 0x0806
+#define CCS_R_TLPX 0x0807
+#define CCS_R_PHY_CTRL 0x0808
+#define CCS_PHY_CTRL_AUTO 0U
+#define CCS_PHY_CTRL_UI 1U
+#define CCS_PHY_CTRL_MANUAL 2U
+#define CCS_R_TCLK_POST_EX (0x080a | CCS_FL_16BIT)
+#define CCS_R_THS_PREPARE_EX (0x080c | CCS_FL_16BIT)
+#define CCS_R_THS_ZERO_MIN_EX (0x080e | CCS_FL_16BIT)
+#define CCS_R_THS_TRAIL_EX (0x0810 | CCS_FL_16BIT)
+#define CCS_R_TCLK_TRAIL_MIN_EX (0x0812 | CCS_FL_16BIT)
+#define CCS_R_TCLK_PREPARE_EX (0x0814 | CCS_FL_16BIT)
+#define CCS_R_TCLK_ZERO_EX (0x0816 | CCS_FL_16BIT)
+#define CCS_R_TLPX_EX (0x0818 | CCS_FL_16BIT)
+#define CCS_R_REQUESTED_LINK_RATE (0x0820 | CCS_FL_32BIT)
+#define CCS_R_DPHY_EQUALIZATION_MODE 0x0824
+#define CCS_DPHY_EQUALIZATION_MODE_EQ2 BIT(0)
+#define CCS_R_PHY_EQUALIZATION_CTRL 0x0825
+#define CCS_PHY_EQUALIZATION_CTRL_ENABLE BIT(0)
+#define CCS_R_DPHY_PREAMBLE_CTRL 0x0826
+#define CCS_DPHY_PREAMBLE_CTRL_ENABLE BIT(0)
+#define CCS_R_DPHY_PREAMBLE_LENGTH 0x0826
+#define CCS_R_PHY_SSC_CTRL 0x0828
+#define CCS_PHY_SSC_CTRL_ENABLE BIT(0)
+#define CCS_R_MANUAL_LP_CTRL 0x0829
+#define CCS_MANUAL_LP_CTRL_ENABLE BIT(0)
+#define CCS_R_TWAKEUP 0x082a
+#define CCS_R_TINIT 0x082b
+#define CCS_R_THS_EXIT 0x082c
+#define CCS_R_THS_EXIT_EX (0x082e | CCS_FL_16BIT)
+#define CCS_R_PHY_PERIODIC_CALIBRATION_CTRL 0x0830
+#define CCS_PHY_PERIODIC_CALIBRATION_CTRL_FRAME_BLANKING BIT(0)
+#define CCS_R_PHY_PERIODIC_CALIBRATION_INTERVAL 0x0831
+#define CCS_R_PHY_INIT_CALIBRATION_CTRL 0x0832
+#define CCS_PHY_INIT_CALIBRATION_CTRL_STREAM_START BIT(0)
+#define CCS_R_DPHY_CALIBRATION_MODE 0x0833
+#define CCS_DPHY_CALIBRATION_MODE_ALSO_ALTERNATE BIT(0)
+#define CCS_R_CPHY_CALIBRATION_MODE 0x0834
+#define CCS_CPHY_CALIBRATION_MODE_FORMAT_1 0U
+#define CCS_CPHY_CALIBRATION_MODE_FORMAT_2 1U
+#define CCS_CPHY_CALIBRATION_MODE_FORMAT_3 2U
+#define CCS_R_T3_CALPREAMBLE_LENGTH 0x0835
+#define CCS_R_T3_CALPREAMBLE_LENGTH_PER 0x0836
+#define CCS_R_T3_CALALTSEQ_LENGTH 0x0837
+#define CCS_R_T3_CALALTSEQ_LENGTH_PER 0x0838
+#define CCS_R_FM2_INIT_SEED (0x083a | CCS_FL_16BIT)
+#define CCS_R_T3_CALUDEFSEQ_LENGTH (0x083c | CCS_FL_16BIT)
+#define CCS_R_T3_CALUDEFSEQ_LENGTH_PER (0x083e | CCS_FL_16BIT)
+#define CCS_R_TGR_PREAMBLE_LENGTH 0x0841
+#define CCS_TGR_PREAMBLE_LENGTH_PREAMABLE_PROG_SEQ BIT(7)
+#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_SHIFT 0U
+#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_MASK 0x3f
+#define CCS_R_TGR_POST_LENGTH 0x0842
+#define CCS_TGR_POST_LENGTH_POST_LENGTH_SHIFT 0U
+#define CCS_TGR_POST_LENGTH_POST_LENGTH_MASK 0x1f
+#define CCS_R_TGR_PREAMBLE_PROG_SEQUENCE(n2) (0x0843 + (n2))
+#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MIN_N2 0U
+#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MAX_N2 6U
+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_SHIFT 3U
+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_MASK 0x38
+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_SHIFT 0U
+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_MASK 0x7
+#define CCS_R_T3_PREPARE (0x084e | CCS_FL_16BIT)
+#define CCS_R_T3_LPX (0x0850 | CCS_FL_16BIT)
+#define CCS_R_ALPS_CTRL 0x085a
+#define CCS_ALPS_CTRL_LVLP_DPHY BIT(0)
+#define CCS_ALPS_CTRL_LVLP_CPHY BIT(1)
+#define CCS_ALPS_CTRL_ALP_CPHY BIT(2)
+#define CCS_R_TX_REG_CSI_EPD_EN_SSP_CPHY (0x0860 | CCS_FL_16BIT)
+#define CCS_R_TX_REG_CSI_EPD_OP_SLP_CPHY (0x0862 | CCS_FL_16BIT)
+#define CCS_R_TX_REG_CSI_EPD_EN_SSP_DPHY (0x0864 | CCS_FL_16BIT)
+#define CCS_R_TX_REG_CSI_EPD_OP_SLP_DPHY (0x0866 | CCS_FL_16BIT)
+#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_CPHY 0x0868
+#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_DPHY 0x0869
+#define CCS_R_SCRAMBLING_CTRL 0x0870
+#define CCS_SCRAMBLING_CTRL_ENABLED BIT(0)
+#define CCS_SCRAMBLING_CTRL_SHIFT 2U
+#define CCS_SCRAMBLING_CTRL_MASK 0xc
+#define CCS_SCRAMBLING_CTRL_1_SEED_CPHY 0U
+#define CCS_SCRAMBLING_CTRL_4_SEED_CPHY 3U
+#define CCS_R_LANE_SEED_VALUE(seed, lane) ((0x0872 | CCS_FL_16BIT) + (seed) * 16 + (lane) * 2)
+#define CCS_LIM_LANE_SEED_VALUE_MIN_SEED 0U
+#define CCS_LIM_LANE_SEED_VALUE_MAX_SEED 3U
+#define CCS_LIM_LANE_SEED_VALUE_MIN_LANE 0U
+#define CCS_LIM_LANE_SEED_VALUE_MAX_LANE 7U
+#define CCS_R_TX_USL_REV_ENTRY (0x08c0 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_REV_CLOCK_COUNTER (0x08c2 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_REV_LP_COUNTER (0x08c4 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_REV_FRAME_COUNTER (0x08c6 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_REV_CHRONOLOGICAL_TIMER (0x08c8 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_FWD_ENTRY (0x08ca | CCS_FL_16BIT)
+#define CCS_R_TX_USL_GPIO (0x08cc | CCS_FL_16BIT)
+#define CCS_R_TX_USL_OPERATION (0x08ce | CCS_FL_16BIT)
+#define CCS_TX_USL_OPERATION_RESET BIT(0)
+#define CCS_R_TX_USL_ALP_CTRL (0x08d0 | CCS_FL_16BIT)
+#define CCS_TX_USL_ALP_CTRL_CLOCK_PAUSE BIT(0)
+#define CCS_R_TX_USL_APP_BTA_ACK_TIMEOUT (0x08d2 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_SNS_BTA_ACK_TIMEOUT (0x08d2 | CCS_FL_16BIT)
+#define CCS_R_USL_CLOCK_MODE_D_CTRL 0x08d2
+#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_STANDBY BIT(0)
+#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_VBLANK BIT(1)
+#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_HBLANK BIT(2)
+#define CCS_R_BINNING_MODE 0x0900
+#define CCS_R_BINNING_TYPE 0x0901
+#define CCS_R_BINNING_WEIGHTING 0x0902
+#define CCS_R_DATA_TRANSFER_IF_1_CTRL 0x0a00
+#define CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE BIT(0)
+#define CCS_DATA_TRANSFER_IF_1_CTRL_WRITE BIT(1)
+#define CCS_DATA_TRANSFER_IF_1_CTRL_CLEAR_ERROR BIT(2)
+#define CCS_R_DATA_TRANSFER_IF_1_STATUS 0x0a01
+#define CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY BIT(0)
+#define CCS_DATA_TRANSFER_IF_1_STATUS_WRITE_IF_READY BIT(1)
+#define CCS_DATA_TRANSFER_IF_1_STATUS_DATA_CORRUPTED BIT(2)
+#define CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE BIT(3)
+#define CCS_R_DATA_TRANSFER_IF_1_PAGE_SELECT 0x0a02
+#define CCS_R_DATA_TRANSFER_IF_1_DATA(p) (0x0a04 + (p))
+#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MIN_P 0U
+#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P 63U
+#define CCS_R_SHADING_CORRECTION_EN 0x0b00
+#define CCS_SHADING_CORRECTION_EN_ENABLE BIT(0)
+#define CCS_R_LUMINANCE_CORRECTION_LEVEL 0x0b01
+#define CCS_R_GREEN_IMBALANCE_FILTER_EN 0x0b02
+#define CCS_GREEN_IMBALANCE_FILTER_EN_ENABLE BIT(0)
+#define CCS_R_MAPPED_DEFECT_CORRECT_EN 0x0b05
+#define CCS_MAPPED_DEFECT_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_SINGLE_DEFECT_CORRECT_EN 0x0b06
+#define CCS_SINGLE_DEFECT_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_DYNAMIC_COUPLET_CORRECT_EN 0x0b08
+#define CCS_DYNAMIC_COUPLET_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_COMBINED_DEFECT_CORRECT_EN 0x0b0a
+#define CCS_COMBINED_DEFECT_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_MODULE_SPECIFIC_CORRECTION_EN 0x0b0c
+#define CCS_MODULE_SPECIFIC_CORRECTION_EN_ENABLE BIT(0)
+#define CCS_R_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN 0x0b13
+#define CCS_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_NF_CTRL 0x0b15
+#define CCS_NF_CTRL_LUMA BIT(0)
+#define CCS_NF_CTRL_CHROMA BIT(1)
+#define CCS_NF_CTRL_COMBINED BIT(2)
+#define CCS_R_OB_READOUT_CONTROL 0x0b30
+#define CCS_OB_READOUT_CONTROL_ENABLE BIT(0)
+#define CCS_OB_READOUT_CONTROL_INTERLEAVING BIT(1)
+#define CCS_R_OB_VIRTUAL_CHANNEL 0x0b31
+#define CCS_R_OB_DT 0x0b32
+#define CCS_R_OB_DATA_FORMAT 0x0b33
+#define CCS_R_COLOR_TEMPERATURE (0x0b8c | CCS_FL_16BIT)
+#define CCS_R_ABSOLUTE_GAIN_GREENR (0x0b8e | CCS_FL_16BIT)
+#define CCS_R_ABSOLUTE_GAIN_RED (0x0b90 | CCS_FL_16BIT)
+#define CCS_R_ABSOLUTE_GAIN_BLUE (0x0b92 | CCS_FL_16BIT)
+#define CCS_R_ABSOLUTE_GAIN_GREENB (0x0b94 | CCS_FL_16BIT)
+#define CCS_R_CFA_CONVERSION_CTRL 0x0ba0
+#define CCS_CFA_CONVERSION_CTRL_BAYER_CONVERSION_ENABLE BIT(0)
+#define CCS_R_FLASH_STROBE_ADJUSTMENT 0x0c12
+#define CCS_R_FLASH_STROBE_START_POINT (0x0c14 | CCS_FL_16BIT)
+#define CCS_R_TFLASH_STROBE_DELAY_RS_CTRL (0x0c16 | CCS_FL_16BIT)
+#define CCS_R_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL (0x0c18 | CCS_FL_16BIT)
+#define CCS_R_FLASH_MODE_RS 0x0c1a
+#define CCS_FLASH_MODE_RS_CONTINUOUS BIT(0)
+#define CCS_FLASH_MODE_RS_TRUNCATE BIT(1)
+#define CCS_FLASH_MODE_RS_ASYNC BIT(3)
+#define CCS_R_FLASH_TRIGGER_RS 0x0c1b
+#define CCS_R_FLASH_STATUS 0x0c1c
+#define CCS_FLASH_STATUS_RETIMED BIT(0)
+#define CCS_R_SA_STROBE_MODE 0x0c1d
+#define CCS_SA_STROBE_MODE_CONTINUOUS BIT(0)
+#define CCS_SA_STROBE_MODE_TRUNCATE BIT(1)
+#define CCS_SA_STROBE_MODE_ASYNC BIT(3)
+#define CCS_SA_STROBE_MODE_ADJUST_EDGE BIT(4)
+#define CCS_R_SA_STROBE_START_POINT (0x0c1e | CCS_FL_16BIT)
+#define CCS_R_TSA_STROBE_DELAY_CTRL (0x0c20 | CCS_FL_16BIT)
+#define CCS_R_TSA_STROBE_WIDTH_CTRL (0x0c22 | CCS_FL_16BIT)
+#define CCS_R_SA_STROBE_TRIGGER 0x0c24
+#define CCS_R_SA_STROBE_STATUS 0x0c25
+#define CCS_SA_STROBE_STATUS_RETIMED BIT(0)
+#define CCS_R_TSA_STROBE_RE_DELAY_CTRL (0x0c30 | CCS_FL_16BIT)
+#define CCS_R_TSA_STROBE_FE_DELAY_CTRL (0x0c32 | CCS_FL_16BIT)
+#define CCS_R_PDAF_CTRL (0x0d00 | CCS_FL_16BIT)
+#define CCS_PDAF_CTRL_ENABLE BIT(0)
+#define CCS_PDAF_CTRL_PROCESSED BIT(1)
+#define CCS_PDAF_CTRL_INTERLEAVED BIT(2)
+#define CCS_PDAF_CTRL_VISIBLE_PDAF_CORRECTION BIT(3)
+#define CCS_R_PDAF_VC 0x0d02
+#define CCS_R_PDAF_DT 0x0d03
+#define CCS_R_PD_X_ADDR_START (0x0d04 | CCS_FL_16BIT)
+#define CCS_R_PD_Y_ADDR_START (0x0d06 | CCS_FL_16BIT)
+#define CCS_R_PD_X_ADDR_END (0x0d08 | CCS_FL_16BIT)
+#define CCS_R_PD_Y_ADDR_END (0x0d0a | CCS_FL_16BIT)
+#define CCS_R_BRACKETING_LUT_CTRL 0x0e00
+#define CCS_R_BRACKETING_LUT_MODE 0x0e01
+#define CCS_BRACKETING_LUT_MODE_CONTINUE_STREAMING BIT(0)
+#define CCS_BRACKETING_LUT_MODE_LOOP_MODE BIT(1)
+#define CCS_R_BRACKETING_LUT_ENTRY_CTRL 0x0e02
+#define CCS_R_BRACKETING_LUT_FRAME(n) (0x0e10 + (n))
+#define CCS_LIM_BRACKETING_LUT_FRAME_MIN_N 0U
+#define CCS_LIM_BRACKETING_LUT_FRAME_MAX_N 239U
+#define CCS_R_INTEGRATION_TIME_CAPABILITY (0x1000 | CCS_FL_16BIT)
+#define CCS_INTEGRATION_TIME_CAPABILITY_FINE BIT(0)
+#define CCS_R_COARSE_INTEGRATION_TIME_MIN (0x1004 | CCS_FL_16BIT)
+#define CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN (0x1006 | CCS_FL_16BIT)
+#define CCS_R_FINE_INTEGRATION_TIME_MIN (0x1008 | CCS_FL_16BIT)
+#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN (0x100a | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_GAIN_CAPABILITY 0x1081
+#define CCS_DIGITAL_GAIN_CAPABILITY_NONE 0U
+#define CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL 2U
+#define CCS_R_DIGITAL_GAIN_MIN (0x1084 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_GAIN_MAX (0x1086 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_GAIN_STEP_SIZE (0x1088 | CCS_FL_16BIT)
+#define CCS_R_PEDESTAL_CAPABILITY 0x10e0
+#define CCS_R_ADC_CAPABILITY 0x10f0
+#define CCS_ADC_CAPABILITY_BIT_DEPTH_CTRL BIT(0)
+#define CCS_R_ADC_BIT_DEPTH_CAPABILITY (0x10f4 | CCS_FL_32BIT)
+#define CCS_R_MIN_EXT_CLK_FREQ_MHZ (0x1100 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_EXT_CLK_FREQ_MHZ (0x1104 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_PRE_PLL_CLK_DIV (0x1108 | CCS_FL_16BIT)
+#define CCS_R_MAX_PRE_PLL_CLK_DIV (0x110a | CCS_FL_16BIT)
+#define CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ (0x110c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ (0x1110 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_PLL_MULTIPLIER (0x1114 | CCS_FL_16BIT)
+#define CCS_R_MAX_PLL_MULTIPLIER (0x1116 | CCS_FL_16BIT)
+#define CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ (0x1118 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ (0x111c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_VT_SYS_CLK_DIV (0x1120 | CCS_FL_16BIT)
+#define CCS_R_MAX_VT_SYS_CLK_DIV (0x1122 | CCS_FL_16BIT)
+#define CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ (0x1124 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ (0x1128 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ (0x112c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ (0x1130 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_VT_PIX_CLK_DIV (0x1134 | CCS_FL_16BIT)
+#define CCS_R_MAX_VT_PIX_CLK_DIV (0x1136 | CCS_FL_16BIT)
+#define CCS_R_CLOCK_CALCULATION 0x1138
+#define CCS_CLOCK_CALCULATION_LANE_SPEED BIT(0)
+#define CCS_CLOCK_CALCULATION_LINK_DECOUPLED BIT(1)
+#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR BIT(2)
+#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR BIT(3)
+#define CCS_R_NUM_OF_VT_LANES 0x1139
+#define CCS_R_NUM_OF_OP_LANES 0x113a
+#define CCS_R_OP_BITS_PER_LANE 0x113b
+#define CCS_R_MIN_FRAME_LENGTH_LINES (0x1140 | CCS_FL_16BIT)
+#define CCS_R_MAX_FRAME_LENGTH_LINES (0x1142 | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_LENGTH_PCK (0x1144 | CCS_FL_16BIT)
+#define CCS_R_MAX_LINE_LENGTH_PCK (0x1146 | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_BLANKING_PCK (0x1148 | CCS_FL_16BIT)
+#define CCS_R_MIN_FRAME_BLANKING_LINES (0x114a | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE 0x114c
+#define CCS_R_TIMING_MODE_CAPABILITY 0x114d
+#define CCS_TIMING_MODE_CAPABILITY_AUTO_FRAME_LENGTH BIT(0)
+#define CCS_TIMING_MODE_CAPABILITY_ROLLING_SHUTTER_MANUAL_READOUT BIT(2)
+#define CCS_TIMING_MODE_CAPABILITY_DELAYED_EXPOSURE_START BIT(3)
+#define CCS_TIMING_MODE_CAPABILITY_MANUAL_EXPOSURE_EMBEDDED_DATA BIT(4)
+#define CCS_R_FRAME_MARGIN_MAX_VALUE (0x114e | CCS_FL_16BIT)
+#define CCS_R_FRAME_MARGIN_MIN_VALUE 0x1150
+#define CCS_R_GAIN_DELAY_TYPE 0x1151
+#define CCS_GAIN_DELAY_TYPE_FIXED 0U
+#define CCS_GAIN_DELAY_TYPE_VARIABLE 1U
+#define CCS_R_MIN_OP_SYS_CLK_DIV (0x1160 | CCS_FL_16BIT)
+#define CCS_R_MAX_OP_SYS_CLK_DIV (0x1162 | CCS_FL_16BIT)
+#define CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ (0x1164 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ (0x1168 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_OP_PIX_CLK_DIV (0x116c | CCS_FL_16BIT)
+#define CCS_R_MAX_OP_PIX_CLK_DIV (0x116e | CCS_FL_16BIT)
+#define CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ (0x1170 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ (0x1174 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_X_ADDR_MIN (0x1180 | CCS_FL_16BIT)
+#define CCS_R_Y_ADDR_MIN (0x1182 | CCS_FL_16BIT)
+#define CCS_R_X_ADDR_MAX (0x1184 | CCS_FL_16BIT)
+#define CCS_R_Y_ADDR_MAX (0x1186 | CCS_FL_16BIT)
+#define CCS_R_MIN_X_OUTPUT_SIZE (0x1188 | CCS_FL_16BIT)
+#define CCS_R_MIN_Y_OUTPUT_SIZE (0x118a | CCS_FL_16BIT)
+#define CCS_R_MAX_X_OUTPUT_SIZE (0x118c | CCS_FL_16BIT)
+#define CCS_R_MAX_Y_OUTPUT_SIZE (0x118e | CCS_FL_16BIT)
+#define CCS_R_X_ADDR_START_DIV_CONSTANT 0x1190
+#define CCS_R_Y_ADDR_START_DIV_CONSTANT 0x1191
+#define CCS_R_X_ADDR_END_DIV_CONSTANT 0x1192
+#define CCS_R_Y_ADDR_END_DIV_CONSTANT 0x1193
+#define CCS_R_X_SIZE_DIV 0x1194
+#define CCS_R_Y_SIZE_DIV 0x1195
+#define CCS_R_X_OUTPUT_DIV 0x1196
+#define CCS_R_Y_OUTPUT_DIV 0x1197
+#define CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT 0x1198
+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_PIX_ADDR BIT(0)
+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_OUTPUT_RES BIT(1)
+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_CROP_NO_PAD BIT(2)
+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_SIZE_LANE_DEP BIT(3)
+#define CCS_R_MIN_OP_PRE_PLL_CLK_DIV (0x11a0 | CCS_FL_16BIT)
+#define CCS_R_MAX_OP_PRE_PLL_CLK_DIV (0x11a2 | CCS_FL_16BIT)
+#define CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ (0x11a4 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ (0x11a8 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_OP_PLL_MULTIPLIER (0x11ac | CCS_FL_16BIT)
+#define CCS_R_MAX_OP_PLL_MULTIPLIER (0x11ae | CCS_FL_16BIT)
+#define CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ (0x11b0 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ (0x11b4 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_CLOCK_TREE_PLL_CAPABILITY 0x11b8
+#define CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL BIT(0)
+#define CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL BIT(1)
+#define CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER BIT(2)
+#define CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV BIT(3)
+#define CCS_R_CLOCK_CAPA_TYPE_CAPABILITY 0x11b9
+#define CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL BIT(0)
+#define CCS_R_MIN_EVEN_INC (0x11c0 | CCS_FL_16BIT)
+#define CCS_R_MIN_ODD_INC (0x11c2 | CCS_FL_16BIT)
+#define CCS_R_MAX_EVEN_INC (0x11c4 | CCS_FL_16BIT)
+#define CCS_R_MAX_ODD_INC (0x11c6 | CCS_FL_16BIT)
+#define CCS_R_AUX_SUBSAMP_CAPABILITY 0x11c8
+#define CCS_AUX_SUBSAMP_CAPABILITY_FACTOR_POWER_OF_2 BIT(1)
+#define CCS_R_AUX_SUBSAMP_MONO_CAPABILITY 0x11c9
+#define CCS_AUX_SUBSAMP_MONO_CAPABILITY_FACTOR_POWER_OF_2 BIT(1)
+#define CCS_R_MONOCHROME_CAPABILITY 0x11ca
+#define CCS_MONOCHROME_CAPABILITY_INC_ODD 0U
+#define CCS_MONOCHROME_CAPABILITY_INC_EVEN 1U
+#define CCS_R_PIXEL_READOUT_CAPABILITY 0x11cb
+#define CCS_PIXEL_READOUT_CAPABILITY_BAYER 0U
+#define CCS_PIXEL_READOUT_CAPABILITY_MONOCHROME 1U
+#define CCS_PIXEL_READOUT_CAPABILITY_BAYER_AND_MONO 2U
+#define CCS_R_MIN_EVEN_INC_MONO (0x11cc | CCS_FL_16BIT)
+#define CCS_R_MAX_EVEN_INC_MONO (0x11ce | CCS_FL_16BIT)
+#define CCS_R_MIN_ODD_INC_MONO (0x11d0 | CCS_FL_16BIT)
+#define CCS_R_MAX_ODD_INC_MONO (0x11d2 | CCS_FL_16BIT)
+#define CCS_R_MIN_EVEN_INC_BC2 (0x11d4 | CCS_FL_16BIT)
+#define CCS_R_MAX_EVEN_INC_BC2 (0x11d6 | CCS_FL_16BIT)
+#define CCS_R_MIN_ODD_INC_BC2 (0x11d8 | CCS_FL_16BIT)
+#define CCS_R_MAX_ODD_INC_BC2 (0x11da | CCS_FL_16BIT)
+#define CCS_R_MIN_EVEN_INC_MONO_BC2 (0x11dc | CCS_FL_16BIT)
+#define CCS_R_MAX_EVEN_INC_MONO_BC2 (0x11de | CCS_FL_16BIT)
+#define CCS_R_MIN_ODD_INC_MONO_BC2 (0x11f0 | CCS_FL_16BIT)
+#define CCS_R_MAX_ODD_INC_MONO_BC2 (0x11f2 | CCS_FL_16BIT)
+#define CCS_R_SCALING_CAPABILITY (0x1200 | CCS_FL_16BIT)
+#define CCS_SCALING_CAPABILITY_NONE 0U
+#define CCS_SCALING_CAPABILITY_HORIZONTAL 1U
+#define CCS_SCALING_CAPABILITY_RESERVED 2U
+#define CCS_R_SCALER_M_MIN (0x1204 | CCS_FL_16BIT)
+#define CCS_R_SCALER_M_MAX (0x1206 | CCS_FL_16BIT)
+#define CCS_R_SCALER_N_MIN (0x1208 | CCS_FL_16BIT)
+#define CCS_R_SCALER_N_MAX (0x120a | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_CAPABILITY 0x120e
+#define CCS_DIGITAL_CROP_CAPABILITY_NONE 0U
+#define CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1U
+#define CCS_R_HDR_CAPABILITY_1 0x1210
+#define CCS_HDR_CAPABILITY_1_2X2_BINNING BIT(0)
+#define CCS_HDR_CAPABILITY_1_COMBINED_ANALOG_GAIN BIT(1)
+#define CCS_HDR_CAPABILITY_1_SEPARATE_ANALOG_GAIN BIT(2)
+#define CCS_HDR_CAPABILITY_1_UPSCALING BIT(3)
+#define CCS_HDR_CAPABILITY_1_RESET_SYNC BIT(4)
+#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_TIMING BIT(5)
+#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_SYNTHESIS BIT(6)
+#define CCS_R_MIN_HDR_BIT_DEPTH 0x1211
+#define CCS_R_HDR_RESOLUTION_SUB_TYPES 0x1212
+#define CCS_R_HDR_RESOLUTION_SUB_TYPE(n) (0x1213 + (n))
+#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MIN_N 0U
+#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MAX_N 1U
+#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_SHIFT 0U
+#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_MASK 0xf
+#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_SHIFT 4U
+#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_MASK 0xf0
+#define CCS_R_HDR_CAPABILITY_2 0x121b
+#define CCS_HDR_CAPABILITY_2_COMBINED_DIGITAL_GAIN BIT(0)
+#define CCS_HDR_CAPABILITY_2_SEPARATE_DIGITAL_GAIN BIT(1)
+#define CCS_HDR_CAPABILITY_2_TIMING_MODE BIT(3)
+#define CCS_HDR_CAPABILITY_2_SYNTHESIS_MODE BIT(4)
+#define CCS_R_MAX_HDR_BIT_DEPTH 0x121c
+#define CCS_R_USL_SUPPORT_CAPABILITY 0x1230
+#define CCS_USL_SUPPORT_CAPABILITY_CLOCK_TREE BIT(0)
+#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_TREE BIT(1)
+#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_CALC BIT(2)
+#define CCS_R_USL_CLOCK_MODE_D_CAPABILITY 0x1231
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_STANDBY BIT(0)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_VBLANK BIT(1)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_HBLANK BIT(2)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_STANDBY BIT(3)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_VBLANK BIT(4)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_HBLANK BIT(5)
+#define CCS_R_MIN_OP_SYS_CLK_DIV_REV 0x1234
+#define CCS_R_MAX_OP_SYS_CLK_DIV_REV 0x1236
+#define CCS_R_MIN_OP_PIX_CLK_DIV_REV 0x1238
+#define CCS_R_MAX_OP_PIX_CLK_DIV_REV 0x123a
+#define CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ (0x123c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ (0x1240 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ (0x1244 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ (0x1248 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_BITRATE_REV_D_MODE_MBPS (0x124c | (CCS_FL_32BIT | CCS_FL_IREAL))
+#define CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS (0x1250 | (CCS_FL_32BIT | CCS_FL_IREAL))
+#define CCS_R_COMPRESSION_CAPABILITY 0x1300
+#define CCS_COMPRESSION_CAPABILITY_DPCM_PCM_SIMPLE BIT(0)
+#define CCS_R_TEST_MODE_CAPABILITY (0x1310 | CCS_FL_16BIT)
+#define CCS_TEST_MODE_CAPABILITY_SOLID_COLOR BIT(0)
+#define CCS_TEST_MODE_CAPABILITY_COLOR_BARS BIT(1)
+#define CCS_TEST_MODE_CAPABILITY_FADE_TO_GREY BIT(2)
+#define CCS_TEST_MODE_CAPABILITY_PN9 BIT(3)
+#define CCS_TEST_MODE_CAPABILITY_COLOR_TILE BIT(5)
+#define CCS_R_PN9_DATA_FORMAT1 0x1312
+#define CCS_R_PN9_DATA_FORMAT2 0x1313
+#define CCS_R_PN9_DATA_FORMAT3 0x1314
+#define CCS_R_PN9_DATA_FORMAT4 0x1315
+#define CCS_R_PN9_MISC_CAPABILITY 0x1316
+#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_SHIFT 0U
+#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_MASK 0x7
+#define CCS_PN9_MISC_CAPABILITY_COMPRESSION BIT(3)
+#define CCS_R_TEST_PATTERN_CAPABILITY 0x1317
+#define CCS_TEST_PATTERN_CAPABILITY_NO_REPEAT BIT(1)
+#define CCS_R_PATTERN_SIZE_DIV_M1 0x1318
+#define CCS_R_FIFO_SUPPORT_CAPABILITY 0x1502
+#define CCS_FIFO_SUPPORT_CAPABILITY_NONE 0U
+#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING 1U
+#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING 2U
+#define CCS_R_PHY_CTRL_CAPABILITY 0x1600
+#define CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL BIT(0)
+#define CCS_PHY_CTRL_CAPABILITY_UI_PHY_CTL BIT(1)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_1_CTL BIT(2)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_2_CTL BIT(3)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_CTL BIT(4)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_1_CTL BIT(5)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_2_CTL BIT(6)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_CTL BIT(7)
+#define CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY 0x1601
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7)
+#define CCS_R_CSI_SIGNALING_MODE_CAPABILITY 0x1602
+#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_DPHY BIT(2)
+#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_CPHY BIT(3)
+#define CCS_R_FAST_STANDBY_CAPABILITY 0x1603
+#define CCS_FAST_STANDBY_CAPABILITY_NO_FRAME_TRUNCATION 0U
+#define CCS_FAST_STANDBY_CAPABILITY_FRAME_TRUNCATION 1U
+#define CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY 0x1604
+#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_CCI_ADDR_CHANGE BIT(0)
+#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_2ND_CCI_ADDR BIT(1)
+#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_SW_CHANGEABLE_2ND_CCI_ADDR BIT(2)
+#define CCS_R_DATA_TYPE_CAPABILITY 0x1605
+#define CCS_DATA_TYPE_CAPABILITY_DPCM_PROGRAMMABLE BIT(0)
+#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_DT_PROGRAMMABLE BIT(1)
+#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_VC_PROGRAMMABLE BIT(2)
+#define CCS_DATA_TYPE_CAPABILITY_EXT_VC_RANGE BIT(3)
+#define CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY 0x1606
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7)
+#define CCS_R_EMB_DATA_CAPABILITY 0x1607
+#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW16 BIT(0)
+#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW20 BIT(1)
+#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW24 BIT(2)
+#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW16 BIT(3)
+#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW20 BIT(4)
+#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW24 BIT(5)
+#define CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(n) ((0x1608 | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) < 4 ? (n) * 4 : 0x32 + ((n) - 4) * 4))
+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MIN_N 0U
+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MAX_N 7U
+#define CCS_R_TEMP_SENSOR_CAPABILITY 0x1618
+#define CCS_TEMP_SENSOR_CAPABILITY_SUPPORTED BIT(0)
+#define CCS_TEMP_SENSOR_CAPABILITY_CCS_FORMAT BIT(1)
+#define CCS_TEMP_SENSOR_CAPABILITY_RESET_0X80 BIT(2)
+#define CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(n) ((0x161a | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) < 4 ? (n) * 4 : 0x30 + ((n) - 4) * 4))
+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MIN_N 0U
+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MAX_N 7U
+#define CCS_R_DPHY_EQUALIZATION_CAPABILITY 0x162b
+#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
+#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ1 BIT(1)
+#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ2 BIT(2)
+#define CCS_R_CPHY_EQUALIZATION_CAPABILITY 0x162c
+#define CCS_CPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
+#define CCS_R_DPHY_PREAMBLE_CAPABILITY 0x162d
+#define CCS_DPHY_PREAMBLE_CAPABILITY_PREAMBLE_SEQ_CTRL BIT(0)
+#define CCS_R_DPHY_SSC_CAPABILITY 0x162e
+#define CCS_DPHY_SSC_CAPABILITY_SUPPORTED BIT(0)
+#define CCS_R_CPHY_CALIBRATION_CAPABILITY 0x162f
+#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
+#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1)
+#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_1_CTRL BIT(2)
+#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_2_CTRL BIT(3)
+#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_3_CTRL BIT(4)
+#define CCS_R_DPHY_CALIBRATION_CAPABILITY 0x1630
+#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
+#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1)
+#define CCS_DPHY_CALIBRATION_CAPABILITY_ALTERNATE_SEQ BIT(2)
+#define CCS_R_PHY_CTRL_CAPABILITY_2 0x1631
+#define CCS_PHY_CTRL_CAPABILITY_2_TGR_LENGTH BIT(0)
+#define CCS_PHY_CTRL_CAPABILITY_2_TGR_PREAMBLE_PROG_SEQ BIT(1)
+#define CCS_PHY_CTRL_CAPABILITY_2_EXTRA_CPHY_MANUAL_TIMING BIT(2)
+#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CDPHY BIT(3)
+#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_DPHY BIT(4)
+#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CPHY BIT(5)
+#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_DPHY BIT(6)
+#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_CPHY BIT(7)
+#define CCS_R_LRTE_CPHY_CAPABILITY 0x1632
+#define CCS_LRTE_CPHY_CAPABILITY_PDQ_SHORT BIT(0)
+#define CCS_LRTE_CPHY_CAPABILITY_SPACER_SHORT BIT(1)
+#define CCS_LRTE_CPHY_CAPABILITY_PDQ_LONG BIT(2)
+#define CCS_LRTE_CPHY_CAPABILITY_SPACER_LONG BIT(3)
+#define CCS_LRTE_CPHY_CAPABILITY_SPACER_NO_PDQ BIT(4)
+#define CCS_R_LRTE_DPHY_CAPABILITY 0x1633
+#define CCS_LRTE_DPHY_CAPABILITY_PDQ_SHORT_OPT1 BIT(0)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT1 BIT(1)
+#define CCS_LRTE_DPHY_CAPABILITY_PDQ_LONG_OPT1 BIT(2)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT1 BIT(3)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT2 BIT(4)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT2 BIT(5)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_NO_PDQ_OPT1 BIT(6)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_VARIABLE_OPT2 BIT(7)
+#define CCS_R_ALPS_CAPABILITY_DPHY 0x1634
+#define CCS_ALPS_CAPABILITY_DPHY_LVLP_NOT_SUPPORTED 0U
+#define CCS_ALPS_CAPABILITY_DPHY_LVLP_SUPPORTED 1U
+#define CCS_ALPS_CAPABILITY_DPHY_CONTROLLABLE_LVLP 2U
+#define CCS_R_ALPS_CAPABILITY_CPHY 0x1635
+#define CCS_ALPS_CAPABILITY_CPHY_LVLP_NOT_SUPPORTED 0U
+#define CCS_ALPS_CAPABILITY_CPHY_LVLP_SUPPORTED 1U
+#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_LVLP 2U
+#define CCS_ALPS_CAPABILITY_CPHY_ALP_NOT_SUPPORTED 0xc
+#define CCS_ALPS_CAPABILITY_CPHY_ALP_SUPPORTED 0xd
+#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_ALP 0xe
+#define CCS_R_SCRAMBLING_CAPABILITY 0x1636
+#define CCS_SCRAMBLING_CAPABILITY_SCRAMBLING_SUPPORTED BIT(0)
+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_SHIFT 1U
+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_MASK 0x6
+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_1 0U
+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_4 3U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_SHIFT 3U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_MASK 0x38
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_0 0U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_1 1U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_4 4U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_PER_LANE BIT(6)
+#define CCS_R_DPHY_MANUAL_CONSTANT 0x1637
+#define CCS_R_CPHY_MANUAL_CONSTANT 0x1638
+#define CCS_R_CSI2_INTERFACE_CAPABILITY_MISC 0x1639
+#define CCS_CSI2_INTERFACE_CAPABILITY_MISC_EOTP_SHORT_PKT_OPT2 BIT(0)
+#define CCS_R_PHY_CTRL_CAPABILITY_3 0x165c
+#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_TIMING_NOT_MULTIPLE BIT(0)
+#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_MIN_TIMING_VALUE_1 BIT(1)
+#define CCS_PHY_CTRL_CAPABILITY_3_TWAKEUP_SUPPORTED BIT(2)
+#define CCS_PHY_CTRL_CAPABILITY_3_TINIT_SUPPORTED BIT(3)
+#define CCS_PHY_CTRL_CAPABILITY_3_THS_EXIT_SUPPORTED BIT(4)
+#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_TIMING_NOT_MULTIPLE BIT(5)
+#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_MIN_TIMING_VALUE_1 BIT(6)
+#define CCS_R_DPHY_SF 0x165d
+#define CCS_R_CPHY_SF 0x165e
+#define CCS_CPHY_SF_TWAKEUP_SHIFT 0U
+#define CCS_CPHY_SF_TWAKEUP_MASK 0xf
+#define CCS_CPHY_SF_TINIT_SHIFT 4U
+#define CCS_CPHY_SF_TINIT_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_1 0x165f
+#define CCS_DPHY_LIMITS_1_THS_PREPARE_SHIFT 0U
+#define CCS_DPHY_LIMITS_1_THS_PREPARE_MASK 0xf
+#define CCS_DPHY_LIMITS_1_THS_ZERO_SHIFT 4U
+#define CCS_DPHY_LIMITS_1_THS_ZERO_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_2 0x1660
+#define CCS_DPHY_LIMITS_2_THS_TRAIL_SHIFT 0U
+#define CCS_DPHY_LIMITS_2_THS_TRAIL_MASK 0xf
+#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_SHIFT 4U
+#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_3 0x1661
+#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_SHIFT 0U
+#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_MASK 0xf
+#define CCS_DPHY_LIMITS_3_TCLK_ZERO_SHIFT 4U
+#define CCS_DPHY_LIMITS_3_TCLK_ZERO_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_4 0x1662
+#define CCS_DPHY_LIMITS_4_TCLK_POST_SHIFT 0U
+#define CCS_DPHY_LIMITS_4_TCLK_POST_MASK 0xf
+#define CCS_DPHY_LIMITS_4_TLPX_SHIFT 4U
+#define CCS_DPHY_LIMITS_4_TLPX_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_5 0x1663
+#define CCS_DPHY_LIMITS_5_THS_EXIT_SHIFT 0U
+#define CCS_DPHY_LIMITS_5_THS_EXIT_MASK 0xf
+#define CCS_DPHY_LIMITS_5_TWAKEUP_SHIFT 4U
+#define CCS_DPHY_LIMITS_5_TWAKEUP_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_6 0x1664
+#define CCS_DPHY_LIMITS_6_TINIT_SHIFT 0U
+#define CCS_DPHY_LIMITS_6_TINIT_MASK 0xf
+#define CCS_R_CPHY_LIMITS_1 0x1665
+#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_SHIFT 0U
+#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_MASK 0xf
+#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_SHIFT 4U
+#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_MASK 0xf0
+#define CCS_R_CPHY_LIMITS_2 0x1666
+#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_SHIFT 0U
+#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_MASK 0xf
+#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_SHIFT 4U
+#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_MASK 0xf0
+#define CCS_R_CPHY_LIMITS_3 0x1667
+#define CCS_CPHY_LIMITS_3_TINIT_MAX_SHIFT 0U
+#define CCS_CPHY_LIMITS_3_TINIT_MAX_MASK 0xf
+#define CCS_R_MIN_FRAME_LENGTH_LINES_BIN (0x1700 | CCS_FL_16BIT)
+#define CCS_R_MAX_FRAME_LENGTH_LINES_BIN (0x1702 | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_LENGTH_PCK_BIN (0x1704 | CCS_FL_16BIT)
+#define CCS_R_MAX_LINE_LENGTH_PCK_BIN (0x1706 | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_BLANKING_PCK_BIN (0x1708 | CCS_FL_16BIT)
+#define CCS_R_FINE_INTEGRATION_TIME_MIN_BIN (0x170a | CCS_FL_16BIT)
+#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN (0x170c | CCS_FL_16BIT)
+#define CCS_R_BINNING_CAPABILITY 0x1710
+#define CCS_BINNING_CAPABILITY_UNSUPPORTED 0U
+#define CCS_BINNING_CAPABILITY_BINNING_THEN_SUBSAMPLING 1U
+#define CCS_BINNING_CAPABILITY_SUBSAMPLING_THEN_BINNING 2U
+#define CCS_R_BINNING_WEIGHTING_CAPABILITY 0x1711
+#define CCS_BINNING_WEIGHTING_CAPABILITY_AVERAGED BIT(0)
+#define CCS_BINNING_WEIGHTING_CAPABILITY_SUMMED BIT(1)
+#define CCS_BINNING_WEIGHTING_CAPABILITY_BAYER_CORRECTED BIT(2)
+#define CCS_BINNING_WEIGHTING_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3)
+#define CCS_R_BINNING_SUB_TYPES 0x1712
+#define CCS_R_BINNING_SUB_TYPE(n) (0x1713 + (n))
+#define CCS_LIM_BINNING_SUB_TYPE_MIN_N 0U
+#define CCS_LIM_BINNING_SUB_TYPE_MAX_N 63U
+#define CCS_BINNING_SUB_TYPE_ROW_SHIFT 0U
+#define CCS_BINNING_SUB_TYPE_ROW_MASK 0xf
+#define CCS_BINNING_SUB_TYPE_COLUMN_SHIFT 4U
+#define CCS_BINNING_SUB_TYPE_COLUMN_MASK 0xf0
+#define CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY 0x1771
+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_AVERAGED BIT(0)
+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_SUMMED BIT(1)
+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_BAYER_CORRECTED BIT(2)
+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3)
+#define CCS_R_BINNING_SUB_TYPES_MONO 0x1772
+#define CCS_R_BINNING_SUB_TYPE_MONO(n) (0x1773 + (n))
+#define CCS_LIM_BINNING_SUB_TYPE_MONO_MIN_N 0U
+#define CCS_LIM_BINNING_SUB_TYPE_MONO_MAX_N 63U
+#define CCS_R_DATA_TRANSFER_IF_CAPABILITY 0x1800
+#define CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
+#define CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING BIT(2)
+#define CCS_R_SHADING_CORRECTION_CAPABILITY 0x1900
+#define CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING BIT(0)
+#define CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION BIT(1)
+#define CCS_R_GREEN_IMBALANCE_CAPABILITY 0x1901
+#define CCS_GREEN_IMBALANCE_CAPABILITY_SUPPORTED BIT(0)
+#define CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY 0x1903
+#define CCS_R_DEFECT_CORRECTION_CAPABILITY (0x1904 | CCS_FL_16BIT)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_MAPPED_DEFECT BIT(0)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_COUPLET BIT(2)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_SINGLE BIT(5)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_COMBINED_DYNAMIC BIT(8)
+#define CCS_R_DEFECT_CORRECTION_CAPABILITY_2 (0x1906 | CCS_FL_16BIT)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_2_DYNAMIC_TRIPLET BIT(3)
+#define CCS_R_NF_CAPABILITY 0x1908
+#define CCS_NF_CAPABILITY_LUMA BIT(0)
+#define CCS_NF_CAPABILITY_CHROMA BIT(1)
+#define CCS_NF_CAPABILITY_COMBINED BIT(2)
+#define CCS_R_OB_READOUT_CAPABILITY 0x1980
+#define CCS_OB_READOUT_CAPABILITY_CONTROLLABLE_READOUT BIT(0)
+#define CCS_OB_READOUT_CAPABILITY_VISIBLE_PIXEL_READOUT BIT(1)
+#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_VC_READOUT BIT(2)
+#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_DT_READOUT BIT(3)
+#define CCS_OB_READOUT_CAPABILITY_PROG_DATA_FORMAT BIT(4)
+#define CCS_R_COLOR_FEEDBACK_CAPABILITY 0x1987
+#define CCS_COLOR_FEEDBACK_CAPABILITY_KELVIN BIT(0)
+#define CCS_COLOR_FEEDBACK_CAPABILITY_AWB_GAIN BIT(1)
+#define CCS_R_CFA_PATTERN_CAPABILITY 0x1990
+#define CCS_CFA_PATTERN_CAPABILITY_BAYER 0U
+#define CCS_CFA_PATTERN_CAPABILITY_MONOCHROME 1U
+#define CCS_CFA_PATTERN_CAPABILITY_4X4_QUAD_BAYER 2U
+#define CCS_CFA_PATTERN_CAPABILITY_VENDOR_SPECIFIC 3U
+#define CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY 0x1991
+#define CCS_CFA_PATTERN_CONVERSION_CAPABILITY_BAYER BIT(0)
+#define CCS_R_FLASH_MODE_CAPABILITY 0x1a02
+#define CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
+#define CCS_R_SA_STROBE_MODE_CAPABILITY 0x1a03
+#define CCS_SA_STROBE_MODE_CAPABILITY_FIXED_WIDTH BIT(0)
+#define CCS_SA_STROBE_MODE_CAPABILITY_EDGE_CTRL BIT(1)
+#define CCS_R_RESET_MAX_DELAY 0x1a10
+#define CCS_R_RESET_MIN_TIME 0x1a11
+#define CCS_R_PDAF_CAPABILITY_1 0x1b80
+#define CCS_PDAF_CAPABILITY_1_SUPPORTED BIT(0)
+#define CCS_PDAF_CAPABILITY_1_PROCESSED_BOTTOM_EMBEDDED BIT(1)
+#define CCS_PDAF_CAPABILITY_1_PROCESSED_INTERLEAVED BIT(2)
+#define CCS_PDAF_CAPABILITY_1_RAW_BOTTOM_EMBEDDED BIT(3)
+#define CCS_PDAF_CAPABILITY_1_RAW_INTERLEAVED BIT(4)
+#define CCS_PDAF_CAPABILITY_1_VISIBLE_PDAF_CORRECTION BIT(5)
+#define CCS_PDAF_CAPABILITY_1_VC_INTERLEAVING BIT(6)
+#define CCS_PDAF_CAPABILITY_1_DT_INTERLEAVING BIT(7)
+#define CCS_R_PDAF_CAPABILITY_2 0x1b81
+#define CCS_PDAF_CAPABILITY_2_ROI BIT(0)
+#define CCS_PDAF_CAPABILITY_2_AFTER_DIGITAL_CROP BIT(1)
+#define CCS_PDAF_CAPABILITY_2_CTRL_RETIMED BIT(2)
+#define CCS_R_BRACKETING_LUT_CAPABILITY_1 0x1c00
+#define CCS_BRACKETING_LUT_CAPABILITY_1_COARSE_INTEGRATION BIT(0)
+#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_ANALOG_GAIN BIT(1)
+#define CCS_BRACKETING_LUT_CAPABILITY_1_FLASH BIT(4)
+#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_DIGITAL_GAIN BIT(5)
+#define CCS_BRACKETING_LUT_CAPABILITY_1_ALTERNATE_GLOBAL_ANALOG_GAIN BIT(6)
+#define CCS_R_BRACKETING_LUT_CAPABILITY_2 0x1c01
+#define CCS_BRACKETING_LUT_CAPABILITY_2_SINGLE_BRACKETING_MODE BIT(0)
+#define CCS_BRACKETING_LUT_CAPABILITY_2_LOOPED_BRACKETING_MODE BIT(1)
+#define CCS_R_BRACKETING_LUT_SIZE 0x1c02
+
+#endif /* __CCS_REGS_H__ */
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 04/29] smiapp: Use CCS register flags
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (2 preceding siblings ...)
2020-11-27 10:32 ` [PATCH v2 03/29] smiapp: Import CCS definitions Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 05/29] smiapp: Calculate CCS limit offsets and limit buffer size Sakari Ailus
` (24 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Use the CCS register flags instead of the old smia flags. The
new flags include the register width information that was separate from
the register flags previously.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-reg-defs.h | 8 ++++----
drivers/media/i2c/smiapp/smiapp-regs.c | 20 +++++++++++++-------
drivers/media/i2c/smiapp/smiapp-regs.h | 13 ++++---------
3 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-reg-defs.h b/drivers/media/i2c/smiapp/smiapp-reg-defs.h
index 865488befc09..ec574007908b 100644
--- a/drivers/media/i2c/smiapp/smiapp-reg-defs.h
+++ b/drivers/media/i2c/smiapp/smiapp-reg-defs.h
@@ -7,11 +7,11 @@
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
-#define SMIAPP_REG_MK_U8(r) ((SMIAPP_REG_8BIT << 16) | (r))
-#define SMIAPP_REG_MK_U16(r) ((SMIAPP_REG_16BIT << 16) | (r))
-#define SMIAPP_REG_MK_U32(r) ((SMIAPP_REG_32BIT << 16) | (r))
+#define SMIAPP_REG_MK_U8(r) (r)
+#define SMIAPP_REG_MK_U16(r) (CCS_FL_16BIT | (r))
+#define SMIAPP_REG_MK_U32(r) (CCS_FL_32BIT | (r))
-#define SMIAPP_REG_MK_F32(r) (SMIAPP_REG_FLAG_FLOAT | (SMIAPP_REG_32BIT << 16) | (r))
+#define SMIAPP_REG_MK_F32(r) (CCS_FL_FLOAT_IREAL | CCS_FL_32BIT | (r))
#define SMIAPP_REG_U16_MODEL_ID SMIAPP_REG_MK_U16(0x0000)
#define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR SMIAPP_REG_MK_U8(0x0002)
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.c b/drivers/media/i2c/smiapp/smiapp-regs.c
index 1b58b7c6c839..904054d303ba 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.c
+++ b/drivers/media/i2c/smiapp/smiapp-regs.c
@@ -133,6 +133,16 @@ static int ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg,
return 0;
}
+unsigned int ccs_reg_width(u32 reg)
+{
+ if (reg & CCS_FL_16BIT)
+ return sizeof(uint16_t);
+ if (reg & CCS_FL_32BIT)
+ return sizeof(uint32_t);
+
+ return sizeof(uint8_t);
+}
+
/*
* Read a 8/16/32-bit i2c register. The value is returned in 'val'.
* Returns zero if successful, or non-zero otherwise.
@@ -141,13 +151,9 @@ static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val,
bool only8)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- u8 len = SMIAPP_REG_WIDTH(reg);
+ unsigned int len = ccs_reg_width(reg);
int rval;
- if (len != SMIAPP_REG_8BIT && len != SMIAPP_REG_16BIT
- && len != SMIAPP_REG_32BIT)
- return -EINVAL;
-
if (!only8)
rval = ____smiapp_read(sensor, SMIAPP_REG_ADDR(reg), len, val);
else
@@ -156,7 +162,7 @@ static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val,
if (rval < 0)
return rval;
- if (reg & SMIAPP_REG_FLAG_FLOAT)
+ if (reg & CCS_FL_FLOAT_IREAL)
*val = float_to_u32_mul_1000000(client, *val);
return 0;
@@ -204,7 +210,7 @@ int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
struct i2c_msg msg;
unsigned char data[6];
unsigned int retries;
- u8 len = SMIAPP_REG_WIDTH(reg);
+ unsigned int len = ccs_reg_width(reg);
int r;
if (len > sizeof(data) - 2)
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/smiapp-regs.h
index 8fda6ed5668c..7223f5f89109 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.h
+++ b/drivers/media/i2c/smiapp/smiapp-regs.h
@@ -14,16 +14,9 @@
#include <linux/i2c.h>
#include <linux/types.h>
-#define SMIAPP_REG_ADDR(reg) ((u16)reg)
-#define SMIAPP_REG_WIDTH(reg) ((u8)(reg >> 16))
-#define SMIAPP_REG_FLAGS(reg) ((u8)(reg >> 24))
-
-/* Use upper 8 bits of the type field for flags */
-#define SMIAPP_REG_FLAG_FLOAT (1 << 24)
+#include "ccs-regs.h"
-#define SMIAPP_REG_8BIT 1
-#define SMIAPP_REG_16BIT 2
-#define SMIAPP_REG_32BIT 4
+#define SMIAPP_REG_ADDR(reg) ((u16)reg)
struct smiapp_sensor;
@@ -33,4 +26,6 @@ int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val);
int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val);
int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val);
+unsigned int ccs_reg_width(u32 reg);
+
#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 05/29] smiapp: Calculate CCS limit offsets and limit buffer size
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (3 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 04/29] smiapp: Use CCS register flags Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 06/29] smiapp: Remove macros for defining registers, merge definitions Sakari Ailus
` (23 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Calculate the limit offsets and the size of the limit buffer. CCS limits
are read into this buffer, and the offsets are helpful in accessing the
information in it.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/Makefile | 2 +-
drivers/media/i2c/smiapp/smiapp-core.c | 40 +++++++++++++++++++++++++-
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/smiapp/Makefile
index 86f57a43f8e8..efb643d2acac 100644
--- a/drivers/media/i2c/smiapp/Makefile
+++ b/drivers/media/i2c/smiapp/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
smiapp-objs += smiapp-core.o smiapp-regs.o \
- smiapp-quirk.o smiapp-limits.o
+ smiapp-quirk.o smiapp-limits.o ccs-limits.o
obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o
ccflags-y += -I $(srctree)/drivers/media/i2c
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index 105ef29152e8..75862e7647f8 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -27,6 +27,7 @@
#include <media/v4l2-fwnode.h>
#include <media/v4l2-device.h>
+#include "ccs-limits.h"
#include "smiapp.h"
#define SMIAPP_ALIGN_DIM(dim, flags) \
@@ -34,6 +35,11 @@
? ALIGN((dim), 2) \
: (dim) & ~1)
+static struct ccs_limit_offset {
+ u16 lim;
+ u16 info;
+} ccs_limit_offsets[CCS_L_LAST + 1];
+
/*
* smiapp_module_idents - supported camera modules
*/
@@ -3166,7 +3172,39 @@ static struct i2c_driver smiapp_i2c_driver = {
.id_table = smiapp_id_table,
};
-module_i2c_driver(smiapp_i2c_driver);
+static int smiapp_module_init(void)
+{
+ unsigned int i, l;
+
+ for (i = 0, l = 0; ccs_limits[i].size && l < CCS_L_LAST; i++) {
+ if (!(ccs_limits[i].flags & CCS_L_FL_SAME_REG)) {
+ ccs_limit_offsets[l + 1].lim =
+ ALIGN(ccs_limit_offsets[l].lim +
+ ccs_limits[i].size,
+ ccs_reg_width(ccs_limits[i + 1].reg));
+ ccs_limit_offsets[l].info = i;
+ l++;
+ } else {
+ ccs_limit_offsets[l].lim += ccs_limits[i].size;
+ }
+ }
+
+ if (WARN_ON(ccs_limits[i].size))
+ return -EINVAL;
+
+ if (WARN_ON(l != CCS_L_LAST))
+ return -EINVAL;
+
+ return i2c_register_driver(THIS_MODULE, &smiapp_i2c_driver);
+}
+
+static void smiapp_module_cleanup(void)
+{
+ i2c_del_driver(&smiapp_i2c_driver);
+}
+
+module_init(smiapp_module_init);
+module_exit(smiapp_module_cleanup);
MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
MODULE_DESCRIPTION("Generic SMIA/SMIA++ camera module driver");
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 06/29] smiapp: Remove macros for defining registers, merge definitions
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (4 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 05/29] smiapp: Calculate CCS limit offsets and limit buffer size Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 07/29] smiapp: Add macros for accessing CCS registers Sakari Ailus
` (22 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Remove macros for defining new SMIA registers, instead put the register
flags to the register definition itself. Also move the register flags to
the same file.
This is not expected to be updated but rather left there as a reference.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-quirk.c | 2 +-
drivers/media/i2c/smiapp/smiapp-reg-defs.h | 1046 +++++++++++---------
drivers/media/i2c/smiapp/smiapp-reg.h | 116 ---
drivers/media/i2c/smiapp/smiapp.h | 2 +-
4 files changed, 570 insertions(+), 596 deletions(-)
delete mode 100644 drivers/media/i2c/smiapp/smiapp-reg.h
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/smiapp-quirk.c
index ab96d6067fc3..308ca0b03f5a 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.c
+++ b/drivers/media/i2c/smiapp/smiapp-quirk.c
@@ -14,7 +14,7 @@
static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val)
{
- return smiapp_write(sensor, SMIAPP_REG_MK_U8(reg), val);
+ return smiapp_write(sensor, reg, val);
}
static int smiapp_write_8s(struct smiapp_sensor *sensor,
diff --git a/drivers/media/i2c/smiapp/smiapp-reg-defs.h b/drivers/media/i2c/smiapp/smiapp-reg-defs.h
index ec574007908b..06b69b1ab55f 100644
--- a/drivers/media/i2c/smiapp/smiapp-reg-defs.h
+++ b/drivers/media/i2c/smiapp/smiapp-reg-defs.h
@@ -7,483 +7,573 @@
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
-#define SMIAPP_REG_MK_U8(r) (r)
-#define SMIAPP_REG_MK_U16(r) (CCS_FL_16BIT | (r))
-#define SMIAPP_REG_MK_U32(r) (CCS_FL_32BIT | (r))
-#define SMIAPP_REG_MK_F32(r) (CCS_FL_FLOAT_IREAL | CCS_FL_32BIT | (r))
+#ifndef __SMIAPP_REG_DEFS_H__
+#define __SMIAPP_REG_DEFS_H__
-#define SMIAPP_REG_U16_MODEL_ID SMIAPP_REG_MK_U16(0x0000)
-#define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR SMIAPP_REG_MK_U8(0x0002)
-#define SMIAPP_REG_U8_MANUFACTURER_ID SMIAPP_REG_MK_U8(0x0003)
-#define SMIAPP_REG_U8_SMIA_VERSION SMIAPP_REG_MK_U8(0x0004)
-#define SMIAPP_REG_U8_FRAME_COUNT SMIAPP_REG_MK_U8(0x0005)
-#define SMIAPP_REG_U8_PIXEL_ORDER SMIAPP_REG_MK_U8(0x0006)
-#define SMIAPP_REG_U16_DATA_PEDESTAL SMIAPP_REG_MK_U16(0x0008)
-#define SMIAPP_REG_U8_PIXEL_DEPTH SMIAPP_REG_MK_U8(0x000c)
-#define SMIAPP_REG_U8_REVISION_NUMBER_MINOR SMIAPP_REG_MK_U8(0x0010)
-#define SMIAPP_REG_U8_SMIAPP_VERSION SMIAPP_REG_MK_U8(0x0011)
-#define SMIAPP_REG_U8_MODULE_DATE_YEAR SMIAPP_REG_MK_U8(0x0012)
-#define SMIAPP_REG_U8_MODULE_DATE_MONTH SMIAPP_REG_MK_U8(0x0013)
-#define SMIAPP_REG_U8_MODULE_DATE_DAY SMIAPP_REG_MK_U8(0x0014)
-#define SMIAPP_REG_U8_MODULE_DATE_PHASE SMIAPP_REG_MK_U8(0x0015)
-#define SMIAPP_REG_U16_SENSOR_MODEL_ID SMIAPP_REG_MK_U16(0x0016)
-#define SMIAPP_REG_U8_SENSOR_REVISION_NUMBER SMIAPP_REG_MK_U8(0x0018)
-#define SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID SMIAPP_REG_MK_U8(0x0019)
-#define SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION SMIAPP_REG_MK_U8(0x001a)
-#define SMIAPP_REG_U32_SERIAL_NUMBER SMIAPP_REG_MK_U32(0x001c)
-#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE SMIAPP_REG_MK_U8(0x0040)
-#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE SMIAPP_REG_MK_U8(0x0041)
-#define SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(n) SMIAPP_REG_MK_U16(0x0042 + ((n) << 1)) /* 0 <= n <= 14 */
-#define SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(n) SMIAPP_REG_MK_U32(0x0060 + ((n) << 2)) /* 0 <= n <= 7 */
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY SMIAPP_REG_MK_U16(0x0080)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN SMIAPP_REG_MK_U16(0x0084)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX SMIAPP_REG_MK_U16(0x0086)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP SMIAPP_REG_MK_U16(0x0088)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_TYPE SMIAPP_REG_MK_U16(0x008a)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_M0 SMIAPP_REG_MK_U16(0x008c)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_C0 SMIAPP_REG_MK_U16(0x008e)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_M1 SMIAPP_REG_MK_U16(0x0090)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_C1 SMIAPP_REG_MK_U16(0x0092)
-#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE SMIAPP_REG_MK_U8(0x00c0)
-#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_SUBTYPE SMIAPP_REG_MK_U8(0x00c1)
-#define SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(n) SMIAPP_REG_MK_U16(0x00c2 + ((n) << 1))
-#define SMIAPP_REG_U8_MODE_SELECT SMIAPP_REG_MK_U8(0x0100)
-#define SMIAPP_REG_U8_IMAGE_ORIENTATION SMIAPP_REG_MK_U8(0x0101)
-#define SMIAPP_REG_U8_SOFTWARE_RESET SMIAPP_REG_MK_U8(0x0103)
-#define SMIAPP_REG_U8_GROUPED_PARAMETER_HOLD SMIAPP_REG_MK_U8(0x0104)
-#define SMIAPP_REG_U8_MASK_CORRUPTED_FRAMES SMIAPP_REG_MK_U8(0x0105)
-#define SMIAPP_REG_U8_FAST_STANDBY_CTRL SMIAPP_REG_MK_U8(0x0106)
-#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL SMIAPP_REG_MK_U8(0x0107)
-#define SMIAPP_REG_U8_2ND_CCI_IF_CONTROL SMIAPP_REG_MK_U8(0x0108)
-#define SMIAPP_REG_U8_2ND_CCI_ADDRESS_CONTROL SMIAPP_REG_MK_U8(0x0109)
-#define SMIAPP_REG_U8_CSI_CHANNEL_IDENTIFIER SMIAPP_REG_MK_U8(0x0110)
-#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE SMIAPP_REG_MK_U8(0x0111)
-#define SMIAPP_REG_U16_CSI_DATA_FORMAT SMIAPP_REG_MK_U16(0x0112)
-#define SMIAPP_REG_U8_CSI_LANE_MODE SMIAPP_REG_MK_U8(0x0114)
-#define SMIAPP_REG_U8_CSI2_10_TO_8_DT SMIAPP_REG_MK_U8(0x0115)
-#define SMIAPP_REG_U8_CSI2_10_TO_7_DT SMIAPP_REG_MK_U8(0x0116)
-#define SMIAPP_REG_U8_CSI2_10_TO_6_DT SMIAPP_REG_MK_U8(0x0117)
-#define SMIAPP_REG_U8_CSI2_12_TO_8_DT SMIAPP_REG_MK_U8(0x0118)
-#define SMIAPP_REG_U8_CSI2_12_TO_7_DT SMIAPP_REG_MK_U8(0x0119)
-#define SMIAPP_REG_U8_CSI2_12_TO_6_DT SMIAPP_REG_MK_U8(0x011a)
-#define SMIAPP_REG_U8_CSI2_14_TO_10_DT SMIAPP_REG_MK_U8(0x011b)
-#define SMIAPP_REG_U8_CSI2_14_TO_8_DT SMIAPP_REG_MK_U8(0x011c)
-#define SMIAPP_REG_U8_CSI2_16_TO_10_DT SMIAPP_REG_MK_U8(0x011d)
-#define SMIAPP_REG_U8_CSI2_16_TO_8_DT SMIAPP_REG_MK_U8(0x011e)
-#define SMIAPP_REG_U8_GAIN_MODE SMIAPP_REG_MK_U8(0x0120)
-#define SMIAPP_REG_U16_VANA_VOLTAGE SMIAPP_REG_MK_U16(0x0130)
-#define SMIAPP_REG_U16_VDIG_VOLTAGE SMIAPP_REG_MK_U16(0x0132)
-#define SMIAPP_REG_U16_VIO_VOLTAGE SMIAPP_REG_MK_U16(0x0134)
-#define SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ SMIAPP_REG_MK_U16(0x0136)
-#define SMIAPP_REG_U8_TEMP_SENSOR_CONTROL SMIAPP_REG_MK_U8(0x0138)
-#define SMIAPP_REG_U8_TEMP_SENSOR_MODE SMIAPP_REG_MK_U8(0x0139)
-#define SMIAPP_REG_U8_TEMP_SENSOR_OUTPUT SMIAPP_REG_MK_U8(0x013a)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME SMIAPP_REG_MK_U16(0x0200)
-#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME SMIAPP_REG_MK_U16(0x0202)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL SMIAPP_REG_MK_U16(0x0204)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENR SMIAPP_REG_MK_U16(0x0206)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_RED SMIAPP_REG_MK_U16(0x0208)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_BLUE SMIAPP_REG_MK_U16(0x020a)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENB SMIAPP_REG_MK_U16(0x020c)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENR SMIAPP_REG_MK_U16(0x020e)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_RED SMIAPP_REG_MK_U16(0x0210)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_BLUE SMIAPP_REG_MK_U16(0x0212)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENB SMIAPP_REG_MK_U16(0x0214)
-#define SMIAPP_REG_U16_VT_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x0300)
-#define SMIAPP_REG_U16_VT_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x0302)
-#define SMIAPP_REG_U16_PRE_PLL_CLK_DIV SMIAPP_REG_MK_U16(0x0304)
-#define SMIAPP_REG_U16_PLL_MULTIPLIER SMIAPP_REG_MK_U16(0x0306)
-#define SMIAPP_REG_U16_OP_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x0308)
-#define SMIAPP_REG_U16_OP_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x030a)
-#define SMIAPP_REG_U16_FRAME_LENGTH_LINES SMIAPP_REG_MK_U16(0x0340)
-#define SMIAPP_REG_U16_LINE_LENGTH_PCK SMIAPP_REG_MK_U16(0x0342)
-#define SMIAPP_REG_U16_X_ADDR_START SMIAPP_REG_MK_U16(0x0344)
-#define SMIAPP_REG_U16_Y_ADDR_START SMIAPP_REG_MK_U16(0x0346)
-#define SMIAPP_REG_U16_X_ADDR_END SMIAPP_REG_MK_U16(0x0348)
-#define SMIAPP_REG_U16_Y_ADDR_END SMIAPP_REG_MK_U16(0x034a)
-#define SMIAPP_REG_U16_X_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x034c)
-#define SMIAPP_REG_U16_Y_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x034e)
-#define SMIAPP_REG_U16_X_EVEN_INC SMIAPP_REG_MK_U16(0x0380)
-#define SMIAPP_REG_U16_X_ODD_INC SMIAPP_REG_MK_U16(0x0382)
-#define SMIAPP_REG_U16_Y_EVEN_INC SMIAPP_REG_MK_U16(0x0384)
-#define SMIAPP_REG_U16_Y_ODD_INC SMIAPP_REG_MK_U16(0x0386)
-#define SMIAPP_REG_U16_SCALING_MODE SMIAPP_REG_MK_U16(0x0400)
-#define SMIAPP_REG_U16_SPATIAL_SAMPLING SMIAPP_REG_MK_U16(0x0402)
-#define SMIAPP_REG_U16_SCALE_M SMIAPP_REG_MK_U16(0x0404)
-#define SMIAPP_REG_U16_SCALE_N SMIAPP_REG_MK_U16(0x0406)
-#define SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET SMIAPP_REG_MK_U16(0x0408)
-#define SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET SMIAPP_REG_MK_U16(0x040a)
-#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH SMIAPP_REG_MK_U16(0x040c)
-#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT SMIAPP_REG_MK_U16(0x040e)
-#define SMIAPP_REG_U16_COMPRESSION_MODE SMIAPP_REG_MK_U16(0x0500)
-#define SMIAPP_REG_U16_TEST_PATTERN_MODE SMIAPP_REG_MK_U16(0x0600)
-#define SMIAPP_REG_U16_TEST_DATA_RED SMIAPP_REG_MK_U16(0x0602)
-#define SMIAPP_REG_U16_TEST_DATA_GREENR SMIAPP_REG_MK_U16(0x0604)
-#define SMIAPP_REG_U16_TEST_DATA_BLUE SMIAPP_REG_MK_U16(0x0606)
-#define SMIAPP_REG_U16_TEST_DATA_GREENB SMIAPP_REG_MK_U16(0x0608)
-#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_WIDTH SMIAPP_REG_MK_U16(0x060a)
-#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_POSITION SMIAPP_REG_MK_U16(0x060c)
-#define SMIAPP_REG_U16_VERTICAL_CURSOR_WIDTH SMIAPP_REG_MK_U16(0x060e)
-#define SMIAPP_REG_U16_VERTICAL_CURSOR_POSITION SMIAPP_REG_MK_U16(0x0610)
-#define SMIAPP_REG_U16_FIFO_WATER_MARK_PIXELS SMIAPP_REG_MK_U16(0x0700)
-#define SMIAPP_REG_U8_TCLK_POST SMIAPP_REG_MK_U8(0x0800)
-#define SMIAPP_REG_U8_THS_PREPARE SMIAPP_REG_MK_U8(0x0801)
-#define SMIAPP_REG_U8_THS_ZERO_MIN SMIAPP_REG_MK_U8(0x0802)
-#define SMIAPP_REG_U8_THS_TRAIL SMIAPP_REG_MK_U8(0x0803)
-#define SMIAPP_REG_U8_TCLK_TRAIL_MIN SMIAPP_REG_MK_U8(0x0804)
-#define SMIAPP_REG_U8_TCLK_PREPARE SMIAPP_REG_MK_U8(0x0805)
-#define SMIAPP_REG_U8_TCLK_ZERO SMIAPP_REG_MK_U8(0x0806)
-#define SMIAPP_REG_U8_TLPX SMIAPP_REG_MK_U8(0x0807)
-#define SMIAPP_REG_U8_DPHY_CTRL SMIAPP_REG_MK_U8(0x0808)
-#define SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS SMIAPP_REG_MK_U32(0x0820)
-#define SMIAPP_REG_U8_BINNING_MODE SMIAPP_REG_MK_U8(0x0900)
-#define SMIAPP_REG_U8_BINNING_TYPE SMIAPP_REG_MK_U8(0x0901)
-#define SMIAPP_REG_U8_BINNING_WEIGHTING SMIAPP_REG_MK_U8(0x0902)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL SMIAPP_REG_MK_U8(0x0a00)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS SMIAPP_REG_MK_U8(0x0a01)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT SMIAPP_REG_MK_U8(0x0a02)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 SMIAPP_REG_MK_U8(0x0a04)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_1 SMIAPP_REG_MK_U8(0x0a05)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_2 SMIAPP_REG_MK_U8(0x0a06)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_3 SMIAPP_REG_MK_U8(0x0a07)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_4 SMIAPP_REG_MK_U8(0x0a08)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_5 SMIAPP_REG_MK_U8(0x0a09)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_12 SMIAPP_REG_MK_U8(0x0a10)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_13 SMIAPP_REG_MK_U8(0x0a11)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_14 SMIAPP_REG_MK_U8(0x0a12)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_15 SMIAPP_REG_MK_U8(0x0a13)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_16 SMIAPP_REG_MK_U8(0x0a14)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_17 SMIAPP_REG_MK_U8(0x0a15)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_18 SMIAPP_REG_MK_U8(0x0a16)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_19 SMIAPP_REG_MK_U8(0x0a17)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_20 SMIAPP_REG_MK_U8(0x0a18)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_21 SMIAPP_REG_MK_U8(0x0a19)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_22 SMIAPP_REG_MK_U8(0x0a1a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_23 SMIAPP_REG_MK_U8(0x0a1b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_24 SMIAPP_REG_MK_U8(0x0a1c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_25 SMIAPP_REG_MK_U8(0x0a1d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_26 SMIAPP_REG_MK_U8(0x0a1e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_27 SMIAPP_REG_MK_U8(0x0a1f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_28 SMIAPP_REG_MK_U8(0x0a20)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_29 SMIAPP_REG_MK_U8(0x0a21)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_30 SMIAPP_REG_MK_U8(0x0a22)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_31 SMIAPP_REG_MK_U8(0x0a23)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_32 SMIAPP_REG_MK_U8(0x0a24)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_33 SMIAPP_REG_MK_U8(0x0a25)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_34 SMIAPP_REG_MK_U8(0x0a26)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_35 SMIAPP_REG_MK_U8(0x0a27)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_36 SMIAPP_REG_MK_U8(0x0a28)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_37 SMIAPP_REG_MK_U8(0x0a29)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_38 SMIAPP_REG_MK_U8(0x0a2a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_39 SMIAPP_REG_MK_U8(0x0a2b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_40 SMIAPP_REG_MK_U8(0x0a2c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_41 SMIAPP_REG_MK_U8(0x0a2d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_42 SMIAPP_REG_MK_U8(0x0a2e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_43 SMIAPP_REG_MK_U8(0x0a2f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_44 SMIAPP_REG_MK_U8(0x0a30)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_45 SMIAPP_REG_MK_U8(0x0a31)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_46 SMIAPP_REG_MK_U8(0x0a32)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_47 SMIAPP_REG_MK_U8(0x0a33)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_48 SMIAPP_REG_MK_U8(0x0a34)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_49 SMIAPP_REG_MK_U8(0x0a35)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_50 SMIAPP_REG_MK_U8(0x0a36)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_51 SMIAPP_REG_MK_U8(0x0a37)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_52 SMIAPP_REG_MK_U8(0x0a38)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_53 SMIAPP_REG_MK_U8(0x0a39)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_54 SMIAPP_REG_MK_U8(0x0a3a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_55 SMIAPP_REG_MK_U8(0x0a3b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_56 SMIAPP_REG_MK_U8(0x0a3c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_57 SMIAPP_REG_MK_U8(0x0a3d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_58 SMIAPP_REG_MK_U8(0x0a3e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_59 SMIAPP_REG_MK_U8(0x0a3f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_60 SMIAPP_REG_MK_U8(0x0a40)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_61 SMIAPP_REG_MK_U8(0x0a41)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_62 SMIAPP_REG_MK_U8(0x0a42)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_63 SMIAPP_REG_MK_U8(0x0a43)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_CTRL SMIAPP_REG_MK_U8(0x0a44)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_STATUS SMIAPP_REG_MK_U8(0x0a45)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_PAGE_SELECT SMIAPP_REG_MK_U8(0x0a46)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_0 SMIAPP_REG_MK_U8(0x0a48)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_1 SMIAPP_REG_MK_U8(0x0a49)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_2 SMIAPP_REG_MK_U8(0x0a4a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_3 SMIAPP_REG_MK_U8(0x0a4b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_4 SMIAPP_REG_MK_U8(0x0a4c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_5 SMIAPP_REG_MK_U8(0x0a4d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_6 SMIAPP_REG_MK_U8(0x0a4e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_7 SMIAPP_REG_MK_U8(0x0a4f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_8 SMIAPP_REG_MK_U8(0x0a50)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_9 SMIAPP_REG_MK_U8(0x0a51)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_10 SMIAPP_REG_MK_U8(0x0a52)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_11 SMIAPP_REG_MK_U8(0x0a53)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_12 SMIAPP_REG_MK_U8(0x0a54)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_13 SMIAPP_REG_MK_U8(0x0a55)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_14 SMIAPP_REG_MK_U8(0x0a56)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_15 SMIAPP_REG_MK_U8(0x0a57)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_16 SMIAPP_REG_MK_U8(0x0a58)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_17 SMIAPP_REG_MK_U8(0x0a59)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_18 SMIAPP_REG_MK_U8(0x0a5a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_19 SMIAPP_REG_MK_U8(0x0a5b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_20 SMIAPP_REG_MK_U8(0x0a5c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_21 SMIAPP_REG_MK_U8(0x0a5d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_22 SMIAPP_REG_MK_U8(0x0a5e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_23 SMIAPP_REG_MK_U8(0x0a5f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_24 SMIAPP_REG_MK_U8(0x0a60)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_25 SMIAPP_REG_MK_U8(0x0a61)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_26 SMIAPP_REG_MK_U8(0x0a62)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_27 SMIAPP_REG_MK_U8(0x0a63)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_28 SMIAPP_REG_MK_U8(0x0a64)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_29 SMIAPP_REG_MK_U8(0x0a65)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_30 SMIAPP_REG_MK_U8(0x0a66)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_31 SMIAPP_REG_MK_U8(0x0a67)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_32 SMIAPP_REG_MK_U8(0x0a68)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_33 SMIAPP_REG_MK_U8(0x0a69)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_34 SMIAPP_REG_MK_U8(0x0a6a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_35 SMIAPP_REG_MK_U8(0x0a6b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_36 SMIAPP_REG_MK_U8(0x0a6c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_37 SMIAPP_REG_MK_U8(0x0a6d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_38 SMIAPP_REG_MK_U8(0x0a6e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_39 SMIAPP_REG_MK_U8(0x0a6f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_40 SMIAPP_REG_MK_U8(0x0a70)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_41 SMIAPP_REG_MK_U8(0x0a71)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_42 SMIAPP_REG_MK_U8(0x0a72)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_43 SMIAPP_REG_MK_U8(0x0a73)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_44 SMIAPP_REG_MK_U8(0x0a74)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_45 SMIAPP_REG_MK_U8(0x0a75)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_46 SMIAPP_REG_MK_U8(0x0a76)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_47 SMIAPP_REG_MK_U8(0x0a77)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_48 SMIAPP_REG_MK_U8(0x0a78)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_49 SMIAPP_REG_MK_U8(0x0a79)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_50 SMIAPP_REG_MK_U8(0x0a7a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_51 SMIAPP_REG_MK_U8(0x0a7b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_52 SMIAPP_REG_MK_U8(0x0a7c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_53 SMIAPP_REG_MK_U8(0x0a7d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_54 SMIAPP_REG_MK_U8(0x0a7e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_55 SMIAPP_REG_MK_U8(0x0a7f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_56 SMIAPP_REG_MK_U8(0x0a80)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_57 SMIAPP_REG_MK_U8(0x0a81)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_58 SMIAPP_REG_MK_U8(0x0a82)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_59 SMIAPP_REG_MK_U8(0x0a83)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_60 SMIAPP_REG_MK_U8(0x0a84)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_61 SMIAPP_REG_MK_U8(0x0a85)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_62 SMIAPP_REG_MK_U8(0x0a86)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_63 SMIAPP_REG_MK_U8(0x0a87)
-#define SMIAPP_REG_U8_SHADING_CORRECTION_ENABLE SMIAPP_REG_MK_U8(0x0b00)
-#define SMIAPP_REG_U8_LUMINANCE_CORRECTION_LEVEL SMIAPP_REG_MK_U8(0x0b01)
-#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_ENABLE SMIAPP_REG_MK_U8(0x0b02)
-#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_WEIGHT SMIAPP_REG_MK_U8(0x0b03)
-#define SMIAPP_REG_U8_BLACK_LEVEL_CORRECTION_ENABLE SMIAPP_REG_MK_U8(0x0b04)
-#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b05)
-#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b06)
-#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_WEIGHT SMIAPP_REG_MK_U8(0x0b07)
-#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b08)
-#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_WEIGHT SMIAPP_REG_MK_U8(0x0b09)
-#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b0a)
-#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_WEIGHT SMIAPP_REG_MK_U8(0x0b0b)
-#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_ENABLE SMIAPP_REG_MK_U8(0x0b0c)
-#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_WEIGHT SMIAPP_REG_MK_U8(0x0b0d)
-#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b0e)
-#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b0f)
-#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b10)
-#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b11)
-#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b12)
-#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b13)
-#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b14)
-#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b15)
-#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b16)
-#define SMIAPP_REG_U8_EDOF_MODE SMIAPP_REG_MK_U8(0x0b80)
-#define SMIAPP_REG_U8_SHARPNESS SMIAPP_REG_MK_U8(0x0b83)
-#define SMIAPP_REG_U8_DENOISING SMIAPP_REG_MK_U8(0x0b84)
-#define SMIAPP_REG_U8_MODULE_SPECIFIC SMIAPP_REG_MK_U8(0x0b85)
-#define SMIAPP_REG_U16_DEPTH_OF_FIELD SMIAPP_REG_MK_U16(0x0b86)
-#define SMIAPP_REG_U16_FOCUS_DISTANCE SMIAPP_REG_MK_U16(0x0b88)
-#define SMIAPP_REG_U8_ESTIMATION_MODE_CTRL SMIAPP_REG_MK_U8(0x0b8a)
-#define SMIAPP_REG_U16_COLOUR_TEMPERATURE SMIAPP_REG_MK_U16(0x0b8c)
-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENR SMIAPP_REG_MK_U16(0x0b8e)
-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_RED SMIAPP_REG_MK_U16(0x0b90)
-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_BLUE SMIAPP_REG_MK_U16(0x0b92)
-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENB SMIAPP_REG_MK_U16(0x0b94)
-#define SMIAPP_REG_U8_ESTIMATION_ZONE_MODE SMIAPP_REG_MK_U8(0x0bc0)
-#define SMIAPP_REG_U16_FIXED_ZONE_WEIGHTING SMIAPP_REG_MK_U16(0x0bc2)
-#define SMIAPP_REG_U16_CUSTOM_ZONE_X_START SMIAPP_REG_MK_U16(0x0bc4)
-#define SMIAPP_REG_U16_CUSTOM_ZONE_Y_START SMIAPP_REG_MK_U16(0x0bc6)
-#define SMIAPP_REG_U16_CUSTOM_ZONE_WIDTH SMIAPP_REG_MK_U16(0x0bc8)
-#define SMIAPP_REG_U16_CUSTOM_ZONE_HEIGHT SMIAPP_REG_MK_U16(0x0bca)
-#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL1 SMIAPP_REG_MK_U8(0x0c00)
-#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL2 SMIAPP_REG_MK_U8(0x0c01)
-#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_1 SMIAPP_REG_MK_U8(0x0c02)
-#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_2 SMIAPP_REG_MK_U8(0x0c03)
-#define SMIAPP_REG_U16_TRDY_CTRL SMIAPP_REG_MK_U16(0x0c04)
-#define SMIAPP_REG_U16_TRDOUT_CTRL SMIAPP_REG_MK_U16(0x0c06)
-#define SMIAPP_REG_U16_TSHUTTER_STROBE_DELAY_CTRL SMIAPP_REG_MK_U16(0x0c08)
-#define SMIAPP_REG_U16_TSHUTTER_STROBE_WIDTH_CTRL SMIAPP_REG_MK_U16(0x0c0a)
-#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_CTRL SMIAPP_REG_MK_U16(0x0c0c)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_CTRL SMIAPP_REG_MK_U16(0x0c0e)
-#define SMIAPP_REG_U16_TGRST_INTERVAL_CTRL SMIAPP_REG_MK_U16(0x0c10)
-#define SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT SMIAPP_REG_MK_U8(0x0c12)
-#define SMIAPP_REG_U16_FLASH_STROBE_START_POINT SMIAPP_REG_MK_U16(0x0c14)
-#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL SMIAPP_REG_MK_U16(0x0c16)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL SMIAPP_REG_MK_U16(0x0c18)
-#define SMIAPP_REG_U8_FLASH_MODE_RS SMIAPP_REG_MK_U8(0x0c1a)
-#define SMIAPP_REG_U8_FLASH_TRIGGER_RS SMIAPP_REG_MK_U8(0x0c1b)
-#define SMIAPP_REG_U8_FLASH_STATUS SMIAPP_REG_MK_U8(0x0c1c)
-#define SMIAPP_REG_U8_SA_STROBE_MODE SMIAPP_REG_MK_U8(0x0c1d)
-#define SMIAPP_REG_U16_SA_STROBE_START_POINT SMIAPP_REG_MK_U16(0x0c1e)
-#define SMIAPP_REG_U16_TSA_STROBE_DELAY_CTRL SMIAPP_REG_MK_U16(0x0c20)
-#define SMIAPP_REG_U16_TSA_STROBE_WIDTH_CTRL SMIAPP_REG_MK_U16(0x0c22)
-#define SMIAPP_REG_U8_SA_STROBE_TRIGGER SMIAPP_REG_MK_U8(0x0c24)
-#define SMIAPP_REG_U8_SPECIAL_ACTUATOR_STATUS SMIAPP_REG_MK_U8(0x0c25)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_RS_CTRL SMIAPP_REG_MK_U16(0x0c26)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_RS_CTRL SMIAPP_REG_MK_U16(0x0c28)
-#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_RS_CTRL SMIAPP_REG_MK_U8(0x0c2a)
-#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_CTRL SMIAPP_REG_MK_U8(0x0c2b)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_CTRL SMIAPP_REG_MK_U16(0x0c2c)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_CTRL SMIAPP_REG_MK_U16(0x0c2e)
-#define SMIAPP_REG_U8_LOW_LEVEL_CTRL SMIAPP_REG_MK_U8(0x0c80)
-#define SMIAPP_REG_U16_MAIN_TRIGGER_REF_POINT SMIAPP_REG_MK_U16(0x0c82)
-#define SMIAPP_REG_U16_MAIN_TRIGGER_T3 SMIAPP_REG_MK_U16(0x0c84)
-#define SMIAPP_REG_U8_MAIN_TRIGGER_COUNT SMIAPP_REG_MK_U8(0x0c86)
-#define SMIAPP_REG_U16_PHASE1_TRIGGER_T3 SMIAPP_REG_MK_U16(0x0c88)
-#define SMIAPP_REG_U8_PHASE1_TRIGGER_COUNT SMIAPP_REG_MK_U8(0x0c8a)
-#define SMIAPP_REG_U16_PHASE2_TRIGGER_T3 SMIAPP_REG_MK_U16(0x0c8c)
-#define SMIAPP_REG_U8_PHASE2_TRIGGER_COUNT SMIAPP_REG_MK_U8(0x0c8e)
-#define SMIAPP_REG_U8_MECH_SHUTTER_CTRL SMIAPP_REG_MK_U8(0x0d00)
-#define SMIAPP_REG_U8_OPERATION_MODE SMIAPP_REG_MK_U8(0x0d01)
-#define SMIAPP_REG_U8_ACT_STATE1 SMIAPP_REG_MK_U8(0x0d02)
-#define SMIAPP_REG_U8_ACT_STATE2 SMIAPP_REG_MK_U8(0x0d03)
-#define SMIAPP_REG_U16_FOCUS_CHANGE SMIAPP_REG_MK_U16(0x0d80)
-#define SMIAPP_REG_U16_FOCUS_CHANGE_CONTROL SMIAPP_REG_MK_U16(0x0d82)
-#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE1 SMIAPP_REG_MK_U16(0x0d84)
-#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE2 SMIAPP_REG_MK_U16(0x0d86)
-#define SMIAPP_REG_U8_STROBE_COUNT_PHASE1 SMIAPP_REG_MK_U8(0x0d88)
-#define SMIAPP_REG_U8_STROBE_COUNT_PHASE2 SMIAPP_REG_MK_U8(0x0d89)
-#define SMIAPP_REG_U8_POSITION SMIAPP_REG_MK_U8(0x0d8a)
-#define SMIAPP_REG_U8_BRACKETING_LUT_CONTROL SMIAPP_REG_MK_U8(0x0e00)
-#define SMIAPP_REG_U8_BRACKETING_LUT_MODE SMIAPP_REG_MK_U8(0x0e01)
-#define SMIAPP_REG_U8_BRACKETING_LUT_ENTRY_CONTROL SMIAPP_REG_MK_U8(0x0e02)
-#define SMIAPP_REG_U8_LUT_PARAMETERS_START SMIAPP_REG_MK_U8(0x0e10)
-#define SMIAPP_REG_U8_LUT_PARAMETERS_END SMIAPP_REG_MK_U8(0x0eff)
-#define SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY SMIAPP_REG_MK_U16(0x1000)
-#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN SMIAPP_REG_MK_U16(0x1004)
-#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN SMIAPP_REG_MK_U16(0x1006)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN SMIAPP_REG_MK_U16(0x1008)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN SMIAPP_REG_MK_U16(0x100a)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY SMIAPP_REG_MK_U16(0x1080)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_MIN SMIAPP_REG_MK_U16(0x1084)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_MAX SMIAPP_REG_MK_U16(0x1086)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_STEP_SIZE SMIAPP_REG_MK_U16(0x1088)
-#define SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1100)
-#define SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1104)
-#define SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV SMIAPP_REG_MK_U16(0x1108)
-#define SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV SMIAPP_REG_MK_U16(0x110a)
-#define SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ SMIAPP_REG_MK_F32(0x110c)
-#define SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ SMIAPP_REG_MK_F32(0x1110)
-#define SMIAPP_REG_U16_MIN_PLL_MULTIPLIER SMIAPP_REG_MK_U16(0x1114)
-#define SMIAPP_REG_U16_MAX_PLL_MULTIPLIER SMIAPP_REG_MK_U16(0x1116)
-#define SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ SMIAPP_REG_MK_F32(0x1118)
-#define SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ SMIAPP_REG_MK_F32(0x111c)
-#define SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1120)
-#define SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1122)
-#define SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1124)
-#define SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1128)
-#define SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x112c)
-#define SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1130)
-#define SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x1134)
-#define SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x1136)
-#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES SMIAPP_REG_MK_U16(0x1140)
-#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES SMIAPP_REG_MK_U16(0x1142)
-#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK SMIAPP_REG_MK_U16(0x1144)
-#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK SMIAPP_REG_MK_U16(0x1146)
-#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK SMIAPP_REG_MK_U16(0x1148)
-#define SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES SMIAPP_REG_MK_U16(0x114a)
-#define SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE SMIAPP_REG_MK_U8(0x114c)
-#define SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1160)
-#define SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1162)
-#define SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1164)
-#define SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1168)
-#define SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x116c)
-#define SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x116e)
-#define SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1170)
-#define SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1174)
-#define SMIAPP_REG_U16_X_ADDR_MIN SMIAPP_REG_MK_U16(0x1180)
-#define SMIAPP_REG_U16_Y_ADDR_MIN SMIAPP_REG_MK_U16(0x1182)
-#define SMIAPP_REG_U16_X_ADDR_MAX SMIAPP_REG_MK_U16(0x1184)
-#define SMIAPP_REG_U16_Y_ADDR_MAX SMIAPP_REG_MK_U16(0x1186)
-#define SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x1188)
-#define SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x118a)
-#define SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x118c)
-#define SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x118e)
-#define SMIAPP_REG_U16_MIN_EVEN_INC SMIAPP_REG_MK_U16(0x11c0)
-#define SMIAPP_REG_U16_MAX_EVEN_INC SMIAPP_REG_MK_U16(0x11c2)
-#define SMIAPP_REG_U16_MIN_ODD_INC SMIAPP_REG_MK_U16(0x11c4)
-#define SMIAPP_REG_U16_MAX_ODD_INC SMIAPP_REG_MK_U16(0x11c6)
-#define SMIAPP_REG_U16_SCALING_CAPABILITY SMIAPP_REG_MK_U16(0x1200)
-#define SMIAPP_REG_U16_SCALER_M_MIN SMIAPP_REG_MK_U16(0x1204)
-#define SMIAPP_REG_U16_SCALER_M_MAX SMIAPP_REG_MK_U16(0x1206)
-#define SMIAPP_REG_U16_SCALER_N_MIN SMIAPP_REG_MK_U16(0x1208)
-#define SMIAPP_REG_U16_SCALER_N_MAX SMIAPP_REG_MK_U16(0x120a)
-#define SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY SMIAPP_REG_MK_U16(0x120c)
-#define SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY SMIAPP_REG_MK_U8(0x120e)
-#define SMIAPP_REG_U16_COMPRESSION_CAPABILITY SMIAPP_REG_MK_U16(0x1300)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINRED SMIAPP_REG_MK_U16(0x1400)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINRED SMIAPP_REG_MK_U16(0x1402)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINRED SMIAPP_REG_MK_U16(0x1404)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINGREEN SMIAPP_REG_MK_U16(0x1406)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINGREEN SMIAPP_REG_MK_U16(0x1408)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINGREEN SMIAPP_REG_MK_U16(0x140a)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINBLUE SMIAPP_REG_MK_U16(0x140c)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINBLUE SMIAPP_REG_MK_U16(0x140e)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINBLUE SMIAPP_REG_MK_U16(0x1410)
-#define SMIAPP_REG_U16_FIFO_SIZE_PIXELS SMIAPP_REG_MK_U16(0x1500)
-#define SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY SMIAPP_REG_MK_U8(0x1502)
-#define SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY SMIAPP_REG_MK_U8(0x1600)
-#define SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x1601)
-#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x1602)
-#define SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY SMIAPP_REG_MK_U8(0x1603)
-#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY SMIAPP_REG_MK_U8(0x1604)
-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x1608)
-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x160c)
-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x1610)
-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x1614)
-#define SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY SMIAPP_REG_MK_U8(0x1618)
-#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN SMIAPP_REG_MK_U16(0x1700)
-#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN SMIAPP_REG_MK_U16(0x1702)
-#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN SMIAPP_REG_MK_U16(0x1704)
-#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN SMIAPP_REG_MK_U16(0x1706)
-#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN SMIAPP_REG_MK_U16(0x1708)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN SMIAPP_REG_MK_U16(0x170a)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN SMIAPP_REG_MK_U16(0x170c)
-#define SMIAPP_REG_U8_BINNING_CAPABILITY SMIAPP_REG_MK_U8(0x1710)
-#define SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY SMIAPP_REG_MK_U8(0x1711)
-#define SMIAPP_REG_U8_BINNING_SUBTYPES SMIAPP_REG_MK_U8(0x1712)
-#define SMIAPP_REG_U8_BINNING_TYPE_n(n) SMIAPP_REG_MK_U8(0x1713 + (n)) /* 1 <= n <= 237 */
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY SMIAPP_REG_MK_U8(0x1800)
-#define SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY SMIAPP_REG_MK_U8(0x1900)
-#define SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY SMIAPP_REG_MK_U8(0x1901)
-#define SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY SMIAPP_REG_MK_U8(0x1902)
-#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY SMIAPP_REG_MK_U8(0x1903)
-#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY SMIAPP_REG_MK_U16(0x1904)
-#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2 SMIAPP_REG_MK_U16(0x1906)
-#define SMIAPP_REG_U8_EDOF_CAPABILITY SMIAPP_REG_MK_U8(0x1980)
-#define SMIAPP_REG_U8_ESTIMATION_FRAMES SMIAPP_REG_MK_U8(0x1981)
-#define SMIAPP_REG_U8_SUPPORTS_SHARPNESS_ADJ SMIAPP_REG_MK_U8(0x1982)
-#define SMIAPP_REG_U8_SUPPORTS_DENOISING_ADJ SMIAPP_REG_MK_U8(0x1983)
-#define SMIAPP_REG_U8_SUPPORTS_MODULE_SPECIFIC_ADJ SMIAPP_REG_MK_U8(0x1984)
-#define SMIAPP_REG_U8_SUPPORTS_DEPTH_OF_FIELD_ADJ SMIAPP_REG_MK_U8(0x1985)
-#define SMIAPP_REG_U8_SUPPORTS_FOCUS_DISTANCE_ADJ SMIAPP_REG_MK_U8(0x1986)
-#define SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY SMIAPP_REG_MK_U8(0x1987)
-#define SMIAPP_REG_U8_EDOF_SUPPORT_AB_NXM SMIAPP_REG_MK_U8(0x1988)
-#define SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x19c0)
-#define SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY SMIAPP_REG_MK_U8(0x19c1)
-#define SMIAPP_REG_U16_EST_DEPTH_OF_FIELD SMIAPP_REG_MK_U16(0x19c2)
-#define SMIAPP_REG_U16_EST_FOCUS_DISTANCE SMIAPP_REG_MK_U16(0x19c4)
-#define SMIAPP_REG_U16_CAPABILITY_TRDY_MIN SMIAPP_REG_MK_U16(0x1a00)
-#define SMIAPP_REG_U8_FLASH_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x1a02)
-#define SMIAPP_REG_U16_MECH_SHUT_AND_ACT_START_ADDR SMIAPP_REG_MK_U16(0x1b02)
-#define SMIAPP_REG_U8_ACTUATOR_CAPABILITY SMIAPP_REG_MK_U8(0x1b04)
-#define SMIAPP_REG_U16_ACTUATOR_TYPE SMIAPP_REG_MK_U16(0x1b40)
-#define SMIAPP_REG_U8_AF_DEVICE_ADDRESS SMIAPP_REG_MK_U8(0x1b42)
-#define SMIAPP_REG_U16_FOCUS_CHANGE_ADDRESS SMIAPP_REG_MK_U16(0x1b44)
-#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1 SMIAPP_REG_MK_U8(0x1c00)
-#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2 SMIAPP_REG_MK_U8(0x1c01)
-#define SMIAPP_REG_U8_BRACKETING_LUT_SIZE SMIAPP_REG_MK_U8(0x1c02)
+/* Register addresses */
+#define SMIAPP_REG_U16_MODEL_ID (0x0000 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR 0x0002
+#define SMIAPP_REG_U8_MANUFACTURER_ID 0x0003
+#define SMIAPP_REG_U8_SMIA_VERSION 0x0004
+#define SMIAPP_REG_U8_FRAME_COUNT 0x0005
+#define SMIAPP_REG_U8_PIXEL_ORDER 0x0006
+#define SMIAPP_REG_U16_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_PIXEL_DEPTH 0x000c
+#define SMIAPP_REG_U8_REVISION_NUMBER_MINOR 0x0010
+#define SMIAPP_REG_U8_SMIAPP_VERSION 0x0011
+#define SMIAPP_REG_U8_MODULE_DATE_YEAR 0x0012
+#define SMIAPP_REG_U8_MODULE_DATE_MONTH 0x0013
+#define SMIAPP_REG_U8_MODULE_DATE_DAY 0x0014
+#define SMIAPP_REG_U8_MODULE_DATE_PHASE 0x0015
+#define SMIAPP_REG_U16_SENSOR_MODEL_ID (0x0016 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_SENSOR_REVISION_NUMBER 0x0018
+#define SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID 0x0019
+#define SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION 0x001a
+#define SMIAPP_REG_U32_SERIAL_NUMBER (0x001c | CCS_FL_32BIT)
+#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE 0x0040
+#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE 0x0041
+#define SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(n) ((0x0042 + ((n) << 1)) | CCS_FL_16BIT) /* 0 <= n <= 14 */
+#define SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(n) ((0x0060 + ((n) << 2)) | CCS_FL_32BIT) /* 0 <= n <= 7 */
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY (0x0080 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN (0x0084 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX (0x0086 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP (0x0088 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_TYPE (0x008a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_M0 (0x008c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_C0 (0x008e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_M1 (0x0090 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_C1 (0x0092 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE 0x00c0
+#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_SUBTYPE 0x00c1
+#define SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(n) ((0x00c2 + ((n) << 1)) | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_MODE_SELECT 0x0100
+#define SMIAPP_REG_U8_IMAGE_ORIENTATION 0x0101
+#define SMIAPP_REG_U8_SOFTWARE_RESET 0x0103
+#define SMIAPP_REG_U8_GROUPED_PARAMETER_HOLD 0x0104
+#define SMIAPP_REG_U8_MASK_CORRUPTED_FRAMES 0x0105
+#define SMIAPP_REG_U8_FAST_STANDBY_CTRL 0x0106
+#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL 0x0107
+#define SMIAPP_REG_U8_2ND_CCI_IF_CONTROL 0x0108
+#define SMIAPP_REG_U8_2ND_CCI_ADDRESS_CONTROL 0x0109
+#define SMIAPP_REG_U8_CSI_CHANNEL_IDENTIFIER 0x0110
+#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE 0x0111
+#define SMIAPP_REG_U16_CSI_DATA_FORMAT (0x0112 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_CSI_LANE_MODE 0x0114
+#define SMIAPP_REG_U8_CSI2_10_TO_8_DT 0x0115
+#define SMIAPP_REG_U8_CSI2_10_TO_7_DT 0x0116
+#define SMIAPP_REG_U8_CSI2_10_TO_6_DT 0x0117
+#define SMIAPP_REG_U8_CSI2_12_TO_8_DT 0x0118
+#define SMIAPP_REG_U8_CSI2_12_TO_7_DT 0x0119
+#define SMIAPP_REG_U8_CSI2_12_TO_6_DT 0x011a
+#define SMIAPP_REG_U8_CSI2_14_TO_10_DT 0x011b
+#define SMIAPP_REG_U8_CSI2_14_TO_8_DT 0x011c
+#define SMIAPP_REG_U8_CSI2_16_TO_10_DT 0x011d
+#define SMIAPP_REG_U8_CSI2_16_TO_8_DT 0x011e
+#define SMIAPP_REG_U8_GAIN_MODE 0x0120
+#define SMIAPP_REG_U16_VANA_VOLTAGE (0x0130 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VDIG_VOLTAGE (0x0132 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VIO_VOLTAGE (0x0134 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ (0x0136 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_TEMP_SENSOR_CONTROL 0x0138
+#define SMIAPP_REG_U8_TEMP_SENSOR_MODE 0x0139
+#define SMIAPP_REG_U8_TEMP_SENSOR_OUTPUT 0x013a
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME (0x0200 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME (0x0202 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL (0x0204 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENR (0x0206 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_RED (0x0208 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_BLUE (0x020a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENB (0x020c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENR (0x020e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_RED (0x0210 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_BLUE (0x0212 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENB (0x0214 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VT_PIX_CLK_DIV (0x0300 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VT_SYS_CLK_DIV (0x0302 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_PRE_PLL_CLK_DIV (0x0304 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_PLL_MULTIPLIER (0x0306 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_OP_PIX_CLK_DIV (0x0308 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_OP_SYS_CLK_DIV (0x030a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FRAME_LENGTH_LINES (0x0340 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_LINE_LENGTH_PCK (0x0342 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ADDR_START (0x0344 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_START (0x0346 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ADDR_END (0x0348 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_END (0x034a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_OUTPUT_SIZE (0x034c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_OUTPUT_SIZE (0x034e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_EVEN_INC (0x0380 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ODD_INC (0x0382 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_EVEN_INC (0x0384 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ODD_INC (0x0386 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALING_MODE (0x0400 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SPATIAL_SAMPLING (0x0402 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALE_M (0x0404 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALE_N (0x0406 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET (0x0408 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET (0x040a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH (0x040c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT (0x040e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COMPRESSION_MODE (0x0500 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_PATTERN_MODE (0x0600 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_RED (0x0602 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_GREENR (0x0604 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_BLUE (0x0606 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_GREENB (0x0608 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_WIDTH (0x060a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_POSITION (0x060c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VERTICAL_CURSOR_WIDTH (0x060e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VERTICAL_CURSOR_POSITION (0x0610 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FIFO_WATER_MARK_PIXELS (0x0700 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_TCLK_POST 0x0800
+#define SMIAPP_REG_U8_THS_PREPARE 0x0801
+#define SMIAPP_REG_U8_THS_ZERO_MIN 0x0802
+#define SMIAPP_REG_U8_THS_TRAIL 0x0803
+#define SMIAPP_REG_U8_TCLK_TRAIL_MIN 0x0804
+#define SMIAPP_REG_U8_TCLK_PREPARE 0x0805
+#define SMIAPP_REG_U8_TCLK_ZERO 0x0806
+#define SMIAPP_REG_U8_TLPX 0x0807
+#define SMIAPP_REG_U8_DPHY_CTRL 0x0808
+#define SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS (0x0820 | CCS_FL_32BIT)
+#define SMIAPP_REG_U8_BINNING_MODE 0x0900
+#define SMIAPP_REG_U8_BINNING_TYPE 0x0901
+#define SMIAPP_REG_U8_BINNING_WEIGHTING 0x0902
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL 0x0a00
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS 0x0a01
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT 0x0a02
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 0x0a04
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_1 0x0a05
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_2 0x0a06
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_3 0x0a07
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_4 0x0a08
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_5 0x0a09
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_12 0x0a10
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_13 0x0a11
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_14 0x0a12
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_15 0x0a13
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_16 0x0a14
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_17 0x0a15
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_18 0x0a16
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_19 0x0a17
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_20 0x0a18
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_21 0x0a19
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_22 0x0a1a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_23 0x0a1b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_24 0x0a1c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_25 0x0a1d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_26 0x0a1e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_27 0x0a1f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_28 0x0a20
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_29 0x0a21
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_30 0x0a22
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_31 0x0a23
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_32 0x0a24
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_33 0x0a25
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_34 0x0a26
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_35 0x0a27
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_36 0x0a28
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_37 0x0a29
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_38 0x0a2a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_39 0x0a2b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_40 0x0a2c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_41 0x0a2d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_42 0x0a2e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_43 0x0a2f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_44 0x0a30
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_45 0x0a31
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_46 0x0a32
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_47 0x0a33
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_48 0x0a34
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_49 0x0a35
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_50 0x0a36
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_51 0x0a37
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_52 0x0a38
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_53 0x0a39
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_54 0x0a3a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_55 0x0a3b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_56 0x0a3c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_57 0x0a3d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_58 0x0a3e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_59 0x0a3f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_60 0x0a40
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_61 0x0a41
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_62 0x0a42
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_63 0x0a43
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_CTRL 0x0a44
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_STATUS 0x0a45
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_PAGE_SELECT 0x0a46
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_0 0x0a48
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_1 0x0a49
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_2 0x0a4a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_3 0x0a4b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_4 0x0a4c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_5 0x0a4d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_6 0x0a4e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_7 0x0a4f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_8 0x0a50
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_9 0x0a51
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_10 0x0a52
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_11 0x0a53
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_12 0x0a54
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_13 0x0a55
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_14 0x0a56
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_15 0x0a57
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_16 0x0a58
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_17 0x0a59
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_18 0x0a5a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_19 0x0a5b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_20 0x0a5c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_21 0x0a5d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_22 0x0a5e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_23 0x0a5f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_24 0x0a60
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_25 0x0a61
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_26 0x0a62
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_27 0x0a63
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_28 0x0a64
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_29 0x0a65
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_30 0x0a66
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_31 0x0a67
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_32 0x0a68
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_33 0x0a69
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_34 0x0a6a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_35 0x0a6b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_36 0x0a6c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_37 0x0a6d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_38 0x0a6e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_39 0x0a6f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_40 0x0a70
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_41 0x0a71
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_42 0x0a72
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_43 0x0a73
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_44 0x0a74
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_45 0x0a75
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_46 0x0a76
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_47 0x0a77
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_48 0x0a78
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_49 0x0a79
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_50 0x0a7a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_51 0x0a7b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_52 0x0a7c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_53 0x0a7d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_54 0x0a7e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_55 0x0a7f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_56 0x0a80
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_57 0x0a81
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_58 0x0a82
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_59 0x0a83
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_60 0x0a84
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_61 0x0a85
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_62 0x0a86
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_63 0x0a87
+#define SMIAPP_REG_U8_SHADING_CORRECTION_ENABLE 0x0b00
+#define SMIAPP_REG_U8_LUMINANCE_CORRECTION_LEVEL 0x0b01
+#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_ENABLE 0x0b02
+#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_WEIGHT 0x0b03
+#define SMIAPP_REG_U8_BLACK_LEVEL_CORRECTION_ENABLE 0x0b04
+#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ENABLE 0x0b05
+#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_ENABLE 0x0b06
+#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_WEIGHT 0x0b07
+#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_ENABLE 0x0b08
+#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_WEIGHT 0x0b09
+#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_ENABLE 0x0b0a
+#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_WEIGHT 0x0b0b
+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_ENABLE 0x0b0c
+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_WEIGHT 0x0b0d
+#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ENABLE 0x0b0e
+#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ADJUST 0x0b0f
+#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ADJUST 0x0b10
+#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ENABLE 0x0b11
+#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ADJUST 0x0b12
+#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ENABLE 0x0b13
+#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ADJUST 0x0b14
+#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ENABLE 0x0b15
+#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ADJUST 0x0b16
+#define SMIAPP_REG_U8_EDOF_MODE 0x0b80
+#define SMIAPP_REG_U8_SHARPNESS 0x0b83
+#define SMIAPP_REG_U8_DENOISING 0x0b84
+#define SMIAPP_REG_U8_MODULE_SPECIFIC 0x0b85
+#define SMIAPP_REG_U16_DEPTH_OF_FIELD (0x0b86 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_DISTANCE (0x0b88 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_ESTIMATION_MODE_CTRL 0x0b8a
+#define SMIAPP_REG_U16_COLOUR_TEMPERATURE (0x0b8c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENR (0x0b8e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_RED (0x0b90 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_BLUE (0x0b92 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENB (0x0b94 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_ESTIMATION_ZONE_MODE 0x0bc0
+#define SMIAPP_REG_U16_FIXED_ZONE_WEIGHTING (0x0bc2 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_X_START (0x0bc4 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_Y_START (0x0bc6 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_WIDTH (0x0bc8 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_HEIGHT (0x0bca | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL1 0x0c00
+#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL2 0x0c01
+#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_1 0x0c02
+#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_2 0x0c03
+#define SMIAPP_REG_U16_TRDY_CTRL (0x0c04 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TRDOUT_CTRL (0x0c06 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSHUTTER_STROBE_DELAY_CTRL (0x0c08 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSHUTTER_STROBE_WIDTH_CTRL (0x0c0a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_CTRL (0x0c0c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_CTRL (0x0c0e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TGRST_INTERVAL_CTRL (0x0c10 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT 0x0c12
+#define SMIAPP_REG_U16_FLASH_STROBE_START_POINT (0x0c14 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL (0x0c16 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL (0x0c18 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FLASH_MODE_RS 0x0c1a
+#define SMIAPP_REG_U8_FLASH_TRIGGER_RS 0x0c1b
+#define SMIAPP_REG_U8_FLASH_STATUS 0x0c1c
+#define SMIAPP_REG_U8_SA_STROBE_MODE 0x0c1d
+#define SMIAPP_REG_U16_SA_STROBE_START_POINT (0x0c1e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSA_STROBE_DELAY_CTRL (0x0c20 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSA_STROBE_WIDTH_CTRL (0x0c22 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_SA_STROBE_TRIGGER 0x0c24
+#define SMIAPP_REG_U8_SPECIAL_ACTUATOR_STATUS 0x0c25
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_RS_CTRL (0x0c26 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_RS_CTRL (0x0c28 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_RS_CTRL 0x0c2a
+#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_CTRL 0x0c2b
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_CTRL (0x0c2c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_CTRL (0x0c2e | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_LOW_LEVEL_CTRL 0x0c80
+#define SMIAPP_REG_U16_MAIN_TRIGGER_REF_POINT (0x0c82 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAIN_TRIGGER_T3 (0x0c84 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_MAIN_TRIGGER_COUNT 0x0c86
+#define SMIAPP_REG_U16_PHASE1_TRIGGER_T3 (0x0c88 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_PHASE1_TRIGGER_COUNT 0x0c8a
+#define SMIAPP_REG_U16_PHASE2_TRIGGER_T3 (0x0c8c | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_PHASE2_TRIGGER_COUNT 0x0c8e
+#define SMIAPP_REG_U8_MECH_SHUTTER_CTRL 0x0d00
+#define SMIAPP_REG_U8_OPERATION_MODE 0x0d01
+#define SMIAPP_REG_U8_ACT_STATE1 0x0d02
+#define SMIAPP_REG_U8_ACT_STATE2 0x0d03
+#define SMIAPP_REG_U16_FOCUS_CHANGE (0x0d80 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_CHANGE_CONTROL (0x0d82 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE1 (0x0d84 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE2 (0x0d86 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_STROBE_COUNT_PHASE1 0x0d88
+#define SMIAPP_REG_U8_STROBE_COUNT_PHASE2 0x0d89
+#define SMIAPP_REG_U8_POSITION 0x0d8a
+#define SMIAPP_REG_U8_BRACKETING_LUT_CONTROL 0x0e00
+#define SMIAPP_REG_U8_BRACKETING_LUT_MODE 0x0e01
+#define SMIAPP_REG_U8_BRACKETING_LUT_ENTRY_CONTROL 0x0e02
+#define SMIAPP_REG_U8_LUT_PARAMETERS_START 0x0e10
+#define SMIAPP_REG_U8_LUT_PARAMETERS_END 0x0eff
+#define SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY (0x1000 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN (0x1004 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN (0x1006 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN (0x1008 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN (0x100a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY (0x1080 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_MIN (0x1084 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_MAX (0x1086 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_STEP_SIZE (0x1088 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ (0x1100 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ (0x1104 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV (0x1108 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV (0x110a | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ (0x110c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ (0x1110 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_PLL_MULTIPLIER (0x1114 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_PLL_MULTIPLIER (0x1116 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ (0x1118 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ (0x111c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV (0x1120 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV (0x1122 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ (0x1124 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ (0x1128 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ (0x112c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ (0x1130 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV (0x1134 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV (0x1136 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES (0x1140 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES (0x1142 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK (0x1144 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK (0x1146 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK (0x1148 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES (0x114a | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE 0x114c
+#define SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV (0x1160 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV (0x1162 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ (0x1164 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ (0x1168 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV (0x116c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV (0x116e | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ (0x1170 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ (0x1174 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_X_ADDR_MIN (0x1180 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_MIN (0x1182 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ADDR_MAX (0x1184 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_MAX (0x1186 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE (0x1188 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE (0x118a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE (0x118c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE (0x118e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_EVEN_INC (0x11c0 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_EVEN_INC (0x11c2 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_ODD_INC (0x11c4 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_ODD_INC (0x11c6 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALING_CAPABILITY (0x1200 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_M_MIN (0x1204 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_M_MAX (0x1206 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_N_MIN (0x1208 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_N_MAX (0x120a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY (0x120c | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY 0x120e
+#define SMIAPP_REG_U16_COMPRESSION_CAPABILITY (0x1300 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINRED (0x1400 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINRED (0x1402 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINRED (0x1404 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINGREEN (0x1406 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINGREEN (0x1408 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINGREEN (0x140a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINBLUE (0x140c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINBLUE (0x140e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINBLUE (0x1410 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FIFO_SIZE_PIXELS (0x1500 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY 0x1502
+#define SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY 0x1600
+#define SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY 0x1601
+#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY 0x1602
+#define SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY 0x1603
+#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY 0x1604
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS (0x1608 | CCS_FL_32BIT)
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS (0x160c | CCS_FL_32BIT)
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS (0x1610 | CCS_FL_32BIT)
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS (0x1614 | CCS_FL_32BIT)
+#define SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY 0x1618
+#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN (0x1700 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN (0x1702 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN (0x1704 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN (0x1706 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN (0x1708 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN (0x170a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN (0x170c | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_BINNING_CAPABILITY 0x1710
+#define SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY 0x1711
+#define SMIAPP_REG_U8_BINNING_SUBTYPES 0x1712
+#define SMIAPP_REG_U8_BINNING_TYPE_n(n) (0x1713 + (n)) /* 1 <= n <= 237 */
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY 0x1800
+#define SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY 0x1900
+#define SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY 0x1901
+#define SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY 0x1902
+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY 0x1903
+#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY (0x1904 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2 (0x1906 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_EDOF_CAPABILITY 0x1980
+#define SMIAPP_REG_U8_ESTIMATION_FRAMES 0x1981
+#define SMIAPP_REG_U8_SUPPORTS_SHARPNESS_ADJ 0x1982
+#define SMIAPP_REG_U8_SUPPORTS_DENOISING_ADJ 0x1983
+#define SMIAPP_REG_U8_SUPPORTS_MODULE_SPECIFIC_ADJ 0x1984
+#define SMIAPP_REG_U8_SUPPORTS_DEPTH_OF_FIELD_ADJ 0x1985
+#define SMIAPP_REG_U8_SUPPORTS_FOCUS_DISTANCE_ADJ 0x1986
+#define SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY 0x1987
+#define SMIAPP_REG_U8_EDOF_SUPPORT_AB_NXM 0x1988
+#define SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY 0x19c0
+#define SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY 0x19c1
+#define SMIAPP_REG_U16_EST_DEPTH_OF_FIELD (0x19c2 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_EST_FOCUS_DISTANCE (0x19c4 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CAPABILITY_TRDY_MIN (0x1a00 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FLASH_MODE_CAPABILITY 0x1a02
+#define SMIAPP_REG_U16_MECH_SHUT_AND_ACT_START_ADDR (0x1b02 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_ACTUATOR_CAPABILITY 0x1b04
+#define SMIAPP_REG_U16_ACTUATOR_TYPE (0x1b40 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_AF_DEVICE_ADDRESS 0x1b42
+#define SMIAPP_REG_U16_FOCUS_CHANGE_ADDRESS (0x1b44 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1 0x1c00
+#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2 0x1c01
+#define SMIAPP_REG_U8_BRACKETING_LUT_SIZE 0x1c02
+
+/* Register bit definitions */
+#define SMIAPP_IMAGE_ORIENTATION_HFLIP BIT(0)
+#define SMIAPP_IMAGE_ORIENTATION_VFLIP BIT(1)
+
+#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN BIT(0)
+#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_WR_EN BIT(1)
+#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_ERR_CLEAR BIT(2)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY BIT(0)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_WR_READY BIT(1)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EDATA BIT(2)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE BIT(3)
+
+#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
+#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL BIT(2)
+
+#define SMIAPP_SOFTWARE_RESET BIT(0)
+
+#define SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
+#define SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE BIT(1)
+
+#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK 0
+#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE 1
+#define SMIAPP_CSI_SIGNALLING_MODE_CSI2 2
+
+#define SMIAPP_DPHY_CTRL_AUTOMATIC 0
+/* DPHY control based on REQUESTED_LINK_BIT_RATE_MBPS */
+#define SMIAPP_DPHY_CTRL_UI 1
+#define SMIAPP_DPHY_CTRL_REGISTER 2
+
+#define SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR 1
+#define SMIAPP_COMPRESSION_MODE_ADVANCED_PREDICTOR 2
+
+#define SMIAPP_MODE_SELECT_SOFTWARE_STANDBY 0
+#define SMIAPP_MODE_SELECT_STREAMING 1
+
+#define SMIAPP_SCALING_MODE_NONE 0
+#define SMIAPP_SCALING_MODE_HORIZONTAL 1
+#define SMIAPP_SCALING_MODE_BOTH 2
+
+#define SMIAPP_SCALING_CAPABILITY_NONE 0
+#define SMIAPP_SCALING_CAPABILITY_HORIZONTAL 1
+#define SMIAPP_SCALING_CAPABILITY_BOTH 2 /* horizontal/both */
+
+/* digital crop right before scaler */
+#define SMIAPP_DIGITAL_CROP_CAPABILITY_NONE 0
+#define SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1
+
+#define SMIAPP_BINNING_CAPABILITY_NO 0
+#define SMIAPP_BINNING_CAPABILITY_YES 1
+
+/* Maximum number of binning subtypes */
+#define SMIAPP_BINNING_SUBTYPES 253
+
+#define SMIAPP_PIXEL_ORDER_GRBG 0
+#define SMIAPP_PIXEL_ORDER_RGGB 1
+#define SMIAPP_PIXEL_ORDER_BGGR 2
+#define SMIAPP_PIXEL_ORDER_GBRG 3
+
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL 1
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED 2
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N 8
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N 16
+
+#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE 0x01
+#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE 0x02
+#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK 0x0f
+#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK 0xf0
+#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT 4
+
+#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK 0xf000
+#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT 12
+#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK 0x0fff
+
+#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK 0xf0000000
+#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT 28
+#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK 0x0000ffff
+
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED 1
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY 2
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK 3
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK 4
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE 5
+
+#define SMIAPP_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0
+#define SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE 1
+
+/* Scaling N factor */
+#define SMIAPP_SCALE_N 16
+
+#endif /* __SMIAPP_REG_DEFS_H__ */
diff --git a/drivers/media/i2c/smiapp/smiapp-reg.h b/drivers/media/i2c/smiapp/smiapp-reg.h
deleted file mode 100644
index e6f96309786f..000000000000
--- a/drivers/media/i2c/smiapp/smiapp-reg.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * drivers/media/i2c/smiapp/smiapp-reg.h
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-
-#ifndef __SMIAPP_REG_H_
-#define __SMIAPP_REG_H_
-
-#include <linux/bits.h>
-
-#include "smiapp-reg-defs.h"
-
-/* Bits for above register */
-#define SMIAPP_IMAGE_ORIENTATION_HFLIP BIT(0)
-#define SMIAPP_IMAGE_ORIENTATION_VFLIP BIT(1)
-
-#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN BIT(0)
-#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_WR_EN BIT(1)
-#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_ERR_CLEAR BIT(2)
-#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY BIT(0)
-#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_WR_READY BIT(1)
-#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EDATA BIT(2)
-#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE BIT(3)
-
-#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
-#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL BIT(2)
-
-#define SMIAPP_SOFTWARE_RESET BIT(0)
-
-#define SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
-#define SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE BIT(1)
-
-#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK 0
-#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE 1
-#define SMIAPP_CSI_SIGNALLING_MODE_CSI2 2
-
-#define SMIAPP_DPHY_CTRL_AUTOMATIC 0
-/* DPHY control based on REQUESTED_LINK_BIT_RATE_MBPS */
-#define SMIAPP_DPHY_CTRL_UI 1
-#define SMIAPP_DPHY_CTRL_REGISTER 2
-
-#define SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR 1
-#define SMIAPP_COMPRESSION_MODE_ADVANCED_PREDICTOR 2
-
-#define SMIAPP_MODE_SELECT_SOFTWARE_STANDBY 0
-#define SMIAPP_MODE_SELECT_STREAMING 1
-
-#define SMIAPP_SCALING_MODE_NONE 0
-#define SMIAPP_SCALING_MODE_HORIZONTAL 1
-#define SMIAPP_SCALING_MODE_BOTH 2
-
-#define SMIAPP_SCALING_CAPABILITY_NONE 0
-#define SMIAPP_SCALING_CAPABILITY_HORIZONTAL 1
-#define SMIAPP_SCALING_CAPABILITY_BOTH 2 /* horizontal/both */
-
-/* digital crop right before scaler */
-#define SMIAPP_DIGITAL_CROP_CAPABILITY_NONE 0
-#define SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1
-
-#define SMIAPP_BINNING_CAPABILITY_NO 0
-#define SMIAPP_BINNING_CAPABILITY_YES 1
-
-/* Maximum number of binning subtypes */
-#define SMIAPP_BINNING_SUBTYPES 253
-
-#define SMIAPP_PIXEL_ORDER_GRBG 0
-#define SMIAPP_PIXEL_ORDER_RGGB 1
-#define SMIAPP_PIXEL_ORDER_BGGR 2
-#define SMIAPP_PIXEL_ORDER_GBRG 3
-
-#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL 1
-#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED 2
-#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N 8
-#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N 16
-
-#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE 0x01
-#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE 0x02
-#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK 0x0f
-#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK 0xf0
-#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT 4
-
-#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK 0xf000
-#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT 12
-#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK 0x0fff
-
-#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK 0xf0000000
-#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT 28
-#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK 0x0000ffff
-
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED 1
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY 2
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK 3
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK 4
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE 5
-
-#define SMIAPP_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0
-#define SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE 1
-
-/* Scaling N factor */
-#define SMIAPP_SCALE_N 16
-
-/* Image statistics registers */
-/* Registers 0x2000 to 0x2fff are reserved for future
- * use for statistics features.
- */
-
-/* Manufacturer Specific Registers: 0x3000 to 0x3fff
- * The manufacturer specifies these as a black box.
- */
-
-#endif /* __SMIAPP_REG_H_ */
diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
index 6f469934f9e3..7cef97db7f47 100644
--- a/drivers/media/i2c/smiapp/smiapp.h
+++ b/drivers/media/i2c/smiapp/smiapp.h
@@ -16,7 +16,7 @@
#include <media/v4l2-subdev.h>
#include "smiapp-pll.h"
-#include "smiapp-reg.h"
+#include "smiapp-reg-defs.h"
#include "smiapp-regs.h"
#include "smiapp-quirk.h"
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 07/29] smiapp: Add macros for accessing CCS registers
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (5 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 06/29] smiapp: Remove macros for defining registers, merge definitions Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 08/29] smiapp: Use MIPI CCS version and manufacturer ID information Sakari Ailus
` (21 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Add two helper macros for reading and writing the CCS registers as defined
in ccs-regs.h.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-regs.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/smiapp-regs.h
index 7223f5f89109..dc946096f368 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.h
+++ b/drivers/media/i2c/smiapp/smiapp-regs.h
@@ -28,4 +28,10 @@ int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val);
unsigned int ccs_reg_width(u32 reg);
+#define ccs_read(sensor, reg_name, val) \
+ smiapp_read(sensor, CCS_R_##reg_name, val)
+
+#define ccs_write(sensor, reg_name, val) \
+ smiapp_write(sensor, CCS_R_##reg_name, val)
+
#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 08/29] smiapp: Use MIPI CCS version and manufacturer ID information
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (6 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 07/29] smiapp: Add macros for accessing CCS registers Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 09/29] smiapp: Read CCS limit values Sakari Ailus
` (20 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Read MIPI CCS manufacturer and version information, and use the CCS IDs
over SMIA whenever they are set.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 76 +++++++++++++++++++-------
drivers/media/i2c/smiapp/smiapp.h | 20 ++++---
2 files changed, 68 insertions(+), 28 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index 75862e7647f8..bc9c80221d2f 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -2356,9 +2356,14 @@ smiapp_sysfs_ident_read(struct device *dev, struct device_attribute *attr,
struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
struct smiapp_module_info *minfo = &sensor->minfo;
- return snprintf(buf, PAGE_SIZE, "%2.2x%4.4x%2.2x\n",
- minfo->manufacturer_id, minfo->model_id,
- minfo->revision_number_major) + 1;
+ if (minfo->mipi_manufacturer_id)
+ return snprintf(buf, PAGE_SIZE, "%4.4x%4.4x%2.2x\n",
+ minfo->mipi_manufacturer_id, minfo->model_id,
+ minfo->revision_number_major) + 1;
+ else
+ return snprintf(buf, PAGE_SIZE, "%2.2x%4.4x%2.2x\n",
+ minfo->smia_manufacturer_id, minfo->model_id,
+ minfo->revision_number_major) + 1;
}
static DEVICE_ATTR(ident, S_IRUGO, smiapp_sysfs_ident_read, NULL);
@@ -2377,8 +2382,11 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
minfo->name = SMIAPP_NAME;
/* Module info */
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID,
- &minfo->manufacturer_id);
+ rval = ccs_read(sensor, MODULE_MANUFACTURER_ID,
+ &minfo->mipi_manufacturer_id);
+ if (!rval && !minfo->mipi_manufacturer_id)
+ rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID,
+ &minfo->smia_manufacturer_id);
if (!rval)
rval = smiapp_read_8only(sensor, SMIAPP_REG_U16_MODEL_ID,
&minfo->model_id);
@@ -2404,9 +2412,12 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
/* Sensor info */
if (!rval)
+ rval = ccs_read(sensor, SENSOR_MANUFACTURER_ID,
+ &minfo->sensor_mipi_manufacturer_id);
+ if (!rval && !minfo->sensor_mipi_manufacturer_id)
rval = smiapp_read_8only(sensor,
SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID,
- &minfo->sensor_manufacturer_id);
+ &minfo->sensor_smia_manufacturer_id);
if (!rval)
rval = smiapp_read_8only(sensor,
SMIAPP_REG_U16_SENSOR_MODEL_ID,
@@ -2422,9 +2433,11 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
/* SMIA */
if (!rval)
+ rval = ccs_read(sensor, MIPI_CCS_VERSION, &minfo->ccs_version);
+ if (!rval && !minfo->ccs_version)
rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION,
&minfo->smia_version);
- if (!rval)
+ if (!rval && !minfo->ccs_version)
rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION,
&minfo->smiapp_version);
@@ -2433,38 +2446,62 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
return -ENODEV;
}
- dev_dbg(&client->dev, "module 0x%2.2x-0x%4.4x\n",
- minfo->manufacturer_id, minfo->model_id);
+ if (minfo->mipi_manufacturer_id)
+ dev_dbg(&client->dev, "MIPI CCS module 0x%4.4x-0x%4.4x\n",
+ minfo->mipi_manufacturer_id, minfo->model_id);
+ else
+ dev_dbg(&client->dev, "SMIA module 0x%2.2x-0x%4.4x\n",
+ minfo->smia_manufacturer_id, minfo->model_id);
dev_dbg(&client->dev,
"module revision 0x%2.2x-0x%2.2x date %2.2d-%2.2d-%2.2d\n",
minfo->revision_number_major, minfo->revision_number_minor,
minfo->module_year, minfo->module_month, minfo->module_day);
- dev_dbg(&client->dev, "sensor 0x%2.2x-0x%4.4x\n",
- minfo->sensor_manufacturer_id, minfo->sensor_model_id);
+ if (minfo->sensor_mipi_manufacturer_id)
+ dev_dbg(&client->dev, "MIPI CCS sensor 0x%4.4x-0x%4.4x\n",
+ minfo->sensor_mipi_manufacturer_id,
+ minfo->sensor_model_id);
+ else
+ dev_dbg(&client->dev, "SMIA sensor 0x%2.2x-0x%4.4x\n",
+ minfo->sensor_smia_manufacturer_id,
+ minfo->sensor_model_id);
dev_dbg(&client->dev,
"sensor revision 0x%2.2x firmware version 0x%2.2x\n",
minfo->sensor_revision_number, minfo->sensor_firmware_version);
- dev_dbg(&client->dev, "smia version %2.2d smiapp version %2.2d\n",
- minfo->smia_version, minfo->smiapp_version);
+ if (minfo->ccs_version)
+ dev_dbg(&client->dev, "MIPI CCS version %u.%u",
+ (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MAJOR_MASK)
+ >> CCS_MIPI_CCS_VERSION_MAJOR_SHIFT,
+ (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MINOR_MASK));
+ else
+ dev_dbg(&client->dev,
+ "smia version %2.2d smiapp version %2.2d\n",
+ minfo->smia_version, minfo->smiapp_version);
/*
* Some modules have bad data in the lvalues below. Hope the
* rvalues have better stuff. The lvalues are module
* parameters whereas the rvalues are sensor parameters.
*/
- if (!minfo->manufacturer_id && !minfo->model_id) {
- minfo->manufacturer_id = minfo->sensor_manufacturer_id;
+ if (minfo->sensor_smia_manufacturer_id &&
+ !minfo->smia_manufacturer_id && !minfo->model_id) {
+ minfo->smia_manufacturer_id =
+ minfo->sensor_smia_manufacturer_id;
minfo->model_id = minfo->sensor_model_id;
minfo->revision_number_major = minfo->sensor_revision_number;
}
for (i = 0; i < ARRAY_SIZE(smiapp_module_idents); i++) {
- if (smiapp_module_idents[i].manufacturer_id
- != minfo->manufacturer_id)
+ if (smiapp_module_idents[i].mipi_manufacturer_id &&
+ smiapp_module_idents[i].mipi_manufacturer_id
+ != minfo->mipi_manufacturer_id)
+ continue;
+ if (smiapp_module_idents[i].smia_manufacturer_id &&
+ smiapp_module_idents[i].smia_manufacturer_id
+ != minfo->smia_manufacturer_id)
continue;
if (smiapp_module_idents[i].model_id != minfo->model_id)
continue;
@@ -2488,9 +2525,8 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
dev_warn(&client->dev,
"no quirks for this module; let's hope it's fully compliant\n");
- dev_dbg(&client->dev, "the sensor is called %s, ident %2.2x%4.4x%2.2x\n",
- minfo->name, minfo->manufacturer_id, minfo->model_id,
- minfo->revision_number_major);
+ dev_dbg(&client->dev, "the sensor is called %s\n",
+ minfo->name);
return 0;
}
diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
index 7cef97db7f47..b1d0e3d71630 100644
--- a/drivers/media/i2c/smiapp/smiapp.h
+++ b/drivers/media/i2c/smiapp/smiapp.h
@@ -91,8 +91,9 @@ struct smiapp_quirk;
#define SMIAPP_MODULE_IDENT_FLAG_REV_LE (1 << 0)
struct smiapp_module_ident {
- u8 manufacturer_id;
+ u16 mipi_manufacturer_id;
u16 model_id;
+ u8 smia_manufacturer_id;
u8 revision_number_major;
u8 flags;
@@ -102,7 +103,8 @@ struct smiapp_module_ident {
};
struct smiapp_module_info {
- u32 manufacturer_id;
+ u32 smia_manufacturer_id;
+ u32 mipi_manufacturer_id;
u32 model_id;
u32 revision_number_major;
u32 revision_number_minor;
@@ -111,13 +113,15 @@ struct smiapp_module_info {
u32 module_month;
u32 module_day;
- u32 sensor_manufacturer_id;
+ u32 sensor_smia_manufacturer_id;
+ u32 sensor_mipi_manufacturer_id;
u32 sensor_model_id;
u32 sensor_revision_number;
u32 sensor_firmware_version;
u32 smia_version;
u32 smiapp_version;
+ u32 ccs_version;
u32 smiapp_profile;
@@ -126,7 +130,7 @@ struct smiapp_module_info {
};
#define SMIAPP_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \
- { .manufacturer_id = manufacturer, \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = fl, \
@@ -134,7 +138,7 @@ struct smiapp_module_info {
.quirk = _quirk, }
#define SMIAPP_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \
- { .manufacturer_id = manufacturer, \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \
@@ -142,14 +146,14 @@ struct smiapp_module_info {
.quirk = _quirk, }
#define SMIAPP_IDENT_L(manufacturer, model, rev, _name) \
- { .manufacturer_id = manufacturer, \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \
.name = _name, }
#define SMIAPP_IDENT_Q(manufacturer, model, rev, _name, _quirk) \
- { .manufacturer_id = manufacturer, \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = 0, \
@@ -157,7 +161,7 @@ struct smiapp_module_info {
.quirk = _quirk, }
#define SMIAPP_IDENT(manufacturer, model, rev, _name) \
- { .manufacturer_id = manufacturer, \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = 0, \
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 09/29] smiapp: Read CCS limit values
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (7 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 08/29] smiapp: Use MIPI CCS version and manufacturer ID information Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 10/29] smiapp: Switch to CCS limits Sakari Ailus
` (19 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Read limit and capability values into a driver allocated buffer. This will
later replace (most of) the existing SMIA limits.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 177 ++++++++++++++++++++++++-
drivers/media/i2c/smiapp/smiapp.h | 4 +
2 files changed, 176 insertions(+), 5 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index bc9c80221d2f..4b33b9a1d52c 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -28,6 +28,7 @@
#include <media/v4l2-device.h>
#include "ccs-limits.h"
+#include "ccs-regs.h"
#include "smiapp.h"
#define SMIAPP_ALIGN_DIM(dim, flags) \
@@ -102,6 +103,164 @@ static int smiapp_read_all_smia_limits(struct smiapp_sensor *sensor)
return 0;
}
+static void ccs_assign_limit(void *ptr, unsigned int width, u32 val)
+{
+ switch (width) {
+ case sizeof(u8):
+ *(u8 *)ptr = val;
+ break;
+ case sizeof(u16):
+ *(u16 *)ptr = val;
+ break;
+ case sizeof(u32):
+ *(u32 *)ptr = val;
+ break;
+ }
+}
+
+static int ccs_limit_ptr(struct smiapp_sensor *sensor, unsigned int limit,
+ unsigned int offset, void **__ptr)
+{
+ const struct ccs_limit *linfo;
+
+ if (WARN_ON(limit >= CCS_L_LAST))
+ return -EINVAL;
+
+ linfo = &ccs_limits[ccs_limit_offsets[limit].info];
+
+ if (WARN_ON(!sensor->ccs_limits) ||
+ WARN_ON(offset + ccs_reg_width(linfo->reg) >
+ ccs_limit_offsets[limit + 1].lim))
+ return -EINVAL;
+
+ *__ptr = sensor->ccs_limits + ccs_limit_offsets[limit].lim + offset;
+
+ return 0;
+}
+
+void ccs_replace_limit(struct smiapp_sensor *sensor,
+ unsigned int limit, unsigned int offset, u32 val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ const struct ccs_limit *linfo;
+ void *ptr;
+ int ret;
+
+ ret = ccs_limit_ptr(sensor, limit, offset, &ptr);
+ if (ret)
+ return;
+
+ linfo = &ccs_limits[ccs_limit_offsets[limit].info];
+
+ dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" %u = %d, 0x%x\n",
+ linfo->reg, linfo->name, offset, val, val);
+
+ ccs_assign_limit(ptr, ccs_reg_width(linfo->reg), val);
+}
+
+static u32 ccs_get_limit(struct smiapp_sensor *sensor,
+ unsigned int limit, unsigned int offset)
+{
+ void *ptr;
+ int ret;
+
+ ret = ccs_limit_ptr(sensor, limit, offset, &ptr);
+ if (ret)
+ return 0;
+
+ switch (ccs_reg_width(ccs_limits[ccs_limit_offsets[limit].info].reg)) {
+ case sizeof(u8):
+ return *(u8 *)ptr;
+ case sizeof(u16):
+ return *(u16 *)ptr;
+ case sizeof(u32):
+ return *(u32 *)ptr;
+ }
+
+ WARN_ON(1);
+
+ return 0;
+}
+
+#define CCS_LIM(sensor, limit) \
+ ccs_get_limit(sensor, CCS_L_##limit, 0)
+
+#define CCS_LIM_AT(sensor, limit, offset) \
+ ccs_get_limit(sensor, CCS_L_##limit, CCS_L_##limit##_OFFSET(offset))
+
+static int ccs_read_all_limits(struct smiapp_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ void *ptr, *alloc, *end;
+ unsigned int i, l;
+ int ret;
+
+ kfree(sensor->ccs_limits);
+ sensor->ccs_limits = NULL;
+
+ alloc = kzalloc(ccs_limit_offsets[CCS_L_LAST].lim, GFP_KERNEL);
+ if (!alloc)
+ return -ENOMEM;
+
+ end = alloc + ccs_limit_offsets[CCS_L_LAST].lim;
+
+ for (i = 0, l = 0, ptr = alloc; ccs_limits[i].size; i++) {
+ u32 reg = ccs_limits[i].reg;
+ unsigned int width = ccs_reg_width(reg);
+ unsigned int j;
+
+ if (l == CCS_L_LAST) {
+ dev_err(&client->dev,
+ "internal error --- end of limit array\n");
+ ret = -EINVAL;
+ goto out_err;
+ }
+
+ for (j = 0; j < ccs_limits[i].size / width;
+ j++, reg += width, ptr += width) {
+ u32 val;
+
+ ret = smiapp_read(sensor, reg, &val);
+ if (ret)
+ goto out_err;
+
+ if (ptr + width > end) {
+ dev_err(&client->dev,
+ "internal error --- no room for regs\n");
+ ret = -EINVAL;
+ goto out_err;
+ }
+
+ ccs_assign_limit(ptr, width, val);
+
+ dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n",
+ reg, ccs_limits[i].name, val, val);
+ }
+
+ if (ccs_limits[i].flags & CCS_L_FL_SAME_REG)
+ continue;
+
+ l++;
+ ptr = alloc + ccs_limit_offsets[l].lim;
+ }
+
+ if (l != CCS_L_LAST) {
+ dev_err(&client->dev,
+ "internal error --- insufficient limits\n");
+ ret = -EINVAL;
+ goto out_err;
+ }
+
+ sensor->ccs_limits = alloc;
+
+ return 0;
+
+out_err:
+ kfree(alloc);
+
+ return ret;
+}
+
static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
@@ -2970,10 +3129,14 @@ static int smiapp_probe(struct i2c_client *client)
goto out_power_off;
}
+ rval = ccs_read_all_limits(sensor);
+ if (rval)
+ goto out_power_off;
+
rval = smiapp_read_frame_fmt(sensor);
if (rval) {
rval = -ENODEV;
- goto out_power_off;
+ goto out_free_ccs_limits;
}
/*
@@ -2997,7 +3160,7 @@ static int smiapp_probe(struct i2c_client *client)
rval = smiapp_call_quirk(sensor, limits);
if (rval) {
dev_err(&client->dev, "limits quirks failed\n");
- goto out_power_off;
+ goto out_free_ccs_limits;
}
if (SMIA_LIM(sensor, BINNING_CAPABILITY)) {
@@ -3007,7 +3170,7 @@ static int smiapp_probe(struct i2c_client *client)
SMIAPP_REG_U8_BINNING_SUBTYPES, &val);
if (rval < 0) {
rval = -ENODEV;
- goto out_power_off;
+ goto out_free_ccs_limits;
}
sensor->nbinning_subtypes = min_t(u8, val,
SMIAPP_BINNING_SUBTYPES);
@@ -3017,7 +3180,7 @@ static int smiapp_probe(struct i2c_client *client)
sensor, SMIAPP_REG_U8_BINNING_TYPE_n(i), &val);
if (rval < 0) {
rval = -ENODEV;
- goto out_power_off;
+ goto out_free_ccs_limits;
}
sensor->binning_subtypes[i] =
*(struct smiapp_binning_subtype *)&val;
@@ -3033,7 +3196,7 @@ static int smiapp_probe(struct i2c_client *client)
if (device_create_file(&client->dev, &dev_attr_ident) != 0) {
dev_err(&client->dev, "sysfs ident entry creation failed\n");
rval = -ENOENT;
- goto out_power_off;
+ goto out_free_ccs_limits;
}
if (sensor->minfo.smiapp_version &&
@@ -3150,6 +3313,9 @@ static int smiapp_probe(struct i2c_client *client)
out_cleanup:
smiapp_cleanup(sensor);
+out_free_ccs_limits:
+ kfree(sensor->ccs_limits);
+
out_power_off:
smiapp_power_off(&client->dev);
mutex_destroy(&sensor->mutex);
@@ -3176,6 +3342,7 @@ static int smiapp_remove(struct i2c_client *client)
}
smiapp_cleanup(sensor);
mutex_destroy(&sensor->mutex);
+ kfree(sensor->ccs_limits);
return 0;
}
diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
index b1d0e3d71630..08ca1b3d1b2f 100644
--- a/drivers/media/i2c/smiapp/smiapp.h
+++ b/drivers/media/i2c/smiapp/smiapp.h
@@ -228,6 +228,7 @@ struct smiapp_sensor {
struct clk *ext_clk;
struct gpio_desc *xshutdown;
u32 limits[SMIAPP_LIMIT_LAST];
+ void *ccs_limits;
u8 nbinning_subtypes;
struct smiapp_binning_subtype binning_subtypes[SMIAPP_BINNING_SUBTYPES];
u32 mbus_frame_fmts;
@@ -281,4 +282,7 @@ struct smiapp_sensor {
#define to_smiapp_sensor(_sd) \
(to_smiapp_subdev(_sd)->sensor)
+void ccs_replace_limit(struct smiapp_sensor *sensor,
+ unsigned int limit, unsigned int offset, u32 val);
+
#endif /* __SMIAPP_PRIV_H_ */
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 10/29] smiapp: Switch to CCS limits
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (8 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 09/29] smiapp: Read CCS limit values Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 11/29] smiapp: Obtain frame descriptor from " Sakari Ailus
` (18 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Use the CCS limit definitions instead of the SMIA ones. This allows
accessing CCS capabilities where needed as well as dropping the old SMIA
limits.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/Makefile | 2 +-
drivers/media/i2c/smiapp/smiapp-core.c | 255 ++++++++++-------------
drivers/media/i2c/smiapp/smiapp-limits.c | 118 -----------
drivers/media/i2c/smiapp/smiapp-limits.h | 114 ----------
drivers/media/i2c/smiapp/smiapp-quirk.c | 25 +--
drivers/media/i2c/smiapp/smiapp-quirk.h | 3 -
drivers/media/i2c/smiapp/smiapp.h | 10 -
7 files changed, 113 insertions(+), 414 deletions(-)
delete mode 100644 drivers/media/i2c/smiapp/smiapp-limits.c
delete mode 100644 drivers/media/i2c/smiapp/smiapp-limits.h
diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/smiapp/Makefile
index efb643d2acac..a7bf53dd4a63 100644
--- a/drivers/media/i2c/smiapp/Makefile
+++ b/drivers/media/i2c/smiapp/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
smiapp-objs += smiapp-core.o smiapp-regs.o \
- smiapp-quirk.o smiapp-limits.o ccs-limits.o
+ smiapp-quirk.o ccs-limits.o
obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o
ccflags-y += -I $(srctree)/drivers/media/i2c
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index 4b33b9a1d52c..2c1a13507965 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -64,45 +64,6 @@ static const struct smiapp_module_ident smiapp_module_idents[] = {
*
*/
-static u32 smiapp_get_limit(struct smiapp_sensor *sensor,
- unsigned int limit)
-{
- if (WARN_ON(limit >= SMIAPP_LIMIT_LAST))
- return 1;
-
- return sensor->limits[limit];
-}
-
-#define SMIA_LIM(sensor, limit) \
- smiapp_get_limit(sensor, SMIAPP_LIMIT_##limit)
-
-static int smiapp_read_all_smia_limits(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- unsigned int i;
- int rval;
-
- for (i = 0; i < SMIAPP_LIMIT_LAST; i++) {
- u32 val;
-
- rval = smiapp_read(
- sensor, smiapp_reg_limits[i].addr, &val);
- if (rval)
- return rval;
-
- sensor->limits[i] = val;
-
- dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n",
- smiapp_reg_limits[i].addr,
- smiapp_reg_limits[i].what, val, val);
- }
-
- if (SMIA_LIM(sensor, SCALER_N_MIN) == 0)
- smiapp_replace_limit(sensor, SMIAPP_LIMIT_SCALER_N_MIN, 16);
-
- return 0;
-}
-
static void ccs_assign_limit(void *ptr, unsigned int width, u32 val)
{
switch (width) {
@@ -253,6 +214,9 @@ static int ccs_read_all_limits(struct smiapp_sensor *sensor)
sensor->ccs_limits = alloc;
+ if (CCS_LIM(sensor, SCALER_N_MIN) < 16)
+ ccs_replace_limit(sensor, CCS_L_SCALER_N_MIN, 0, 16);
+
return 0;
out_err:
@@ -444,35 +408,35 @@ static int smiapp_pll_try(struct smiapp_sensor *sensor,
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct smiapp_pll_limits lim = {
- .min_pre_pll_clk_div = SMIA_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
- .max_pre_pll_clk_div = SMIA_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
- .min_pll_ip_freq_hz = SMIA_LIM(sensor, MIN_PLL_IP_FREQ_HZ),
- .max_pll_ip_freq_hz = SMIA_LIM(sensor, MAX_PLL_IP_FREQ_HZ),
- .min_pll_multiplier = SMIA_LIM(sensor, MIN_PLL_MULTIPLIER),
- .max_pll_multiplier = SMIA_LIM(sensor, MAX_PLL_MULTIPLIER),
- .min_pll_op_freq_hz = SMIA_LIM(sensor, MIN_PLL_OP_FREQ_HZ),
- .max_pll_op_freq_hz = SMIA_LIM(sensor, MAX_PLL_OP_FREQ_HZ),
-
- .op.min_sys_clk_div = SMIA_LIM(sensor, MIN_OP_SYS_CLK_DIV),
- .op.max_sys_clk_div = SMIA_LIM(sensor, MAX_OP_SYS_CLK_DIV),
- .op.min_pix_clk_div = SMIA_LIM(sensor, MIN_OP_PIX_CLK_DIV),
- .op.max_pix_clk_div = SMIA_LIM(sensor, MAX_OP_PIX_CLK_DIV),
- .op.min_sys_clk_freq_hz = SMIA_LIM(sensor, MIN_OP_SYS_CLK_FREQ_HZ),
- .op.max_sys_clk_freq_hz = SMIA_LIM(sensor, MAX_OP_SYS_CLK_FREQ_HZ),
- .op.min_pix_clk_freq_hz = SMIA_LIM(sensor, MIN_OP_PIX_CLK_FREQ_HZ),
- .op.max_pix_clk_freq_hz = SMIA_LIM(sensor, MAX_OP_PIX_CLK_FREQ_HZ),
-
- .vt.min_sys_clk_div = SMIA_LIM(sensor, MIN_VT_SYS_CLK_DIV),
- .vt.max_sys_clk_div = SMIA_LIM(sensor, MAX_VT_SYS_CLK_DIV),
- .vt.min_pix_clk_div = SMIA_LIM(sensor, MIN_VT_PIX_CLK_DIV),
- .vt.max_pix_clk_div = SMIA_LIM(sensor, MAX_VT_PIX_CLK_DIV),
- .vt.min_sys_clk_freq_hz = SMIA_LIM(sensor, MIN_VT_SYS_CLK_FREQ_HZ),
- .vt.max_sys_clk_freq_hz = SMIA_LIM(sensor, MAX_VT_SYS_CLK_FREQ_HZ),
- .vt.min_pix_clk_freq_hz = SMIA_LIM(sensor, MIN_VT_PIX_CLK_FREQ_HZ),
- .vt.max_pix_clk_freq_hz = SMIA_LIM(sensor, MAX_VT_PIX_CLK_FREQ_HZ),
-
- .min_line_length_pck_bin = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN),
- .min_line_length_pck = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK),
+ .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
+ .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
+ .min_pll_ip_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ),
+ .max_pll_ip_freq_hz = CCS_LIM(sensor, MAX_PLL_IP_CLK_FREQ_MHZ),
+ .min_pll_multiplier = CCS_LIM(sensor, MIN_PLL_MULTIPLIER),
+ .max_pll_multiplier = CCS_LIM(sensor, MAX_PLL_MULTIPLIER),
+ .min_pll_op_freq_hz = CCS_LIM(sensor, MIN_PLL_OP_CLK_FREQ_MHZ),
+ .max_pll_op_freq_hz = CCS_LIM(sensor, MAX_PLL_OP_CLK_FREQ_MHZ),
+
+ .op.min_sys_clk_div = CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV),
+ .op.max_sys_clk_div = CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV),
+ .op.min_pix_clk_div = CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV),
+ .op.max_pix_clk_div = CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV),
+ .op.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_OP_SYS_CLK_FREQ_MHZ),
+ .op.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_OP_SYS_CLK_FREQ_MHZ),
+ .op.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PIX_CLK_FREQ_MHZ),
+ .op.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PIX_CLK_FREQ_MHZ),
+
+ .vt.min_sys_clk_div = CCS_LIM(sensor, MIN_VT_SYS_CLK_DIV),
+ .vt.max_sys_clk_div = CCS_LIM(sensor, MAX_VT_SYS_CLK_DIV),
+ .vt.min_pix_clk_div = CCS_LIM(sensor, MIN_VT_PIX_CLK_DIV),
+ .vt.max_pix_clk_div = CCS_LIM(sensor, MAX_VT_PIX_CLK_DIV),
+ .vt.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_VT_SYS_CLK_FREQ_MHZ),
+ .vt.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_VT_SYS_CLK_FREQ_MHZ),
+ .vt.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_VT_PIX_CLK_FREQ_MHZ),
+ .vt.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_VT_PIX_CLK_FREQ_MHZ),
+
+ .min_line_length_pck_bin = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN),
+ .min_line_length_pck = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK),
};
return smiapp_pll_calculate(&client->dev, &lim, pll);
@@ -515,7 +479,7 @@ static void __smiapp_update_exposure_limits(struct smiapp_sensor *sensor)
max = sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height
+ sensor->vblank->val
- - SMIA_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN);
+ - CCS_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN);
__v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max, ctrl->step, max);
}
@@ -770,10 +734,10 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor)
sensor->analog_gain = v4l2_ctrl_new_std(
&sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
V4L2_CID_ANALOGUE_GAIN,
- SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MIN),
- SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MAX),
- max(SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_STEP), 1U),
- SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MIN));
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX),
+ max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U),
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
/* Exposure limits will be updated soon, use just something here. */
sensor->exposure = v4l2_ctrl_new_std(
@@ -1032,21 +996,21 @@ static void smiapp_update_blanking(struct smiapp_sensor *sensor)
int min, max;
if (sensor->binning_vertical > 1 || sensor->binning_horizontal > 1) {
- min_fll = SMIA_LIM(sensor, MIN_FRAME_LENGTH_LINES_BIN);
- max_fll = SMIA_LIM(sensor, MAX_FRAME_LENGTH_LINES_BIN);
- min_llp = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN);
- max_llp = SMIA_LIM(sensor, MAX_LINE_LENGTH_PCK_BIN);
- min_lbp = SMIA_LIM(sensor, MIN_LINE_BLANKING_PCK_BIN);
+ min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES_BIN);
+ max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES_BIN);
+ min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN);
+ max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK_BIN);
+ min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK_BIN);
} else {
- min_fll = SMIA_LIM(sensor, MIN_FRAME_LENGTH_LINES);
- max_fll = SMIA_LIM(sensor, MAX_FRAME_LENGTH_LINES);
- min_llp = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK);
- max_llp = SMIA_LIM(sensor, MAX_LINE_LENGTH_PCK);
- min_lbp = SMIA_LIM(sensor, MIN_LINE_BLANKING_PCK);
+ min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES);
+ max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES);
+ min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK);
+ max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK);
+ min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK);
}
min = max_t(int,
- SMIA_LIM(sensor, MIN_FRAME_BLANKING_LINES),
+ CCS_LIM(sensor, MIN_FRAME_BLANKING_LINES),
min_fll -
sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height);
max = max_fll - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height;
@@ -1124,8 +1088,8 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
return -ENODATA;
}
- if (SMIA_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
- SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL) {
+ if (CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
+ CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING) {
for (i = 1000; i > 0; i--) {
if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY)
break;
@@ -1577,8 +1541,8 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
*/
/* Digital crop */
- if (SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY)
- == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
+ if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
rval = smiapp_write(
sensor, SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET,
sensor->scaler->crop[SMIAPP_PAD_SINK].left);
@@ -1605,8 +1569,8 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
}
/* Scaling */
- if (SMIA_LIM(sensor, SCALING_CAPABILITY)
- != SMIAPP_SCALING_CAPABILITY_NONE) {
+ if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE) {
rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALING_MODE,
sensor->scaling_mode);
if (rval < 0)
@@ -1628,9 +1592,9 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
if (rval < 0)
goto out;
- if ((SMIA_LIM(sensor, FLASH_MODE_CAPABILITY) &
- (SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE |
- SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE)) &&
+ if (CCS_LIM(sensor, FLASH_MODE_CAPABILITY) &
+ (CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE |
+ SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE) &&
sensor->hwcfg->strobe_setup != NULL &&
sensor->hwcfg->strobe_setup->trigger != 0) {
rval = smiapp_setup_flash_strobe(sensor);
@@ -1876,7 +1840,7 @@ static void smiapp_propagate(struct v4l2_subdev *subdev,
if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
if (ssd == sensor->scaler) {
sensor->scale_m =
- SMIA_LIM(sensor, SCALER_N_MIN);
+ CCS_LIM(sensor, SCALER_N_MIN);
sensor->scaling_mode =
SMIAPP_SCALING_MODE_NONE;
} else if (ssd == sensor->binner) {
@@ -1988,12 +1952,12 @@ static int smiapp_set_format(struct v4l2_subdev *subdev,
fmt->format.width =
clamp(fmt->format.width,
- SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE),
- SMIA_LIM(sensor, MAX_X_OUTPUT_SIZE));
+ CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
+ CCS_LIM(sensor, MAX_X_OUTPUT_SIZE));
fmt->format.height =
clamp(fmt->format.height,
- SMIA_LIM(sensor, MIN_Y_OUTPUT_SIZE),
- SMIA_LIM(sensor, MAX_Y_OUTPUT_SIZE));
+ CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
+ CCS_LIM(sensor, MAX_Y_OUTPUT_SIZE));
smiapp_get_crop_compose(subdev, cfg, crops, NULL, fmt->which);
@@ -2046,7 +2010,7 @@ static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w,
val -= abs(w - ask_w);
val -= abs(h - ask_h);
- if (w < SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE))
+ if (w < CCS_LIM(sensor, MIN_X_OUTPUT_SIZE))
val -= SCALING_GOODNESS_EXTREME;
dev_dbg(&client->dev, "w %d ask_w %d h %d ask_h %d goodness %d\n",
@@ -2112,7 +2076,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
struct i2c_client *client = v4l2_get_subdevdata(subdev);
struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
u32 min, max, a, b, max_m;
- u32 scale_m = SMIA_LIM(sensor, SCALER_N_MIN);
+ u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN);
int mode = SMIAPP_SCALING_MODE_HORIZONTAL;
u32 try[4];
u32 ntry = 0;
@@ -2125,19 +2089,19 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
crops[SMIAPP_PAD_SINK]->height);
a = crops[SMIAPP_PAD_SINK]->width
- * SMIA_LIM(sensor, SCALER_N_MIN) / sel->r.width;
+ * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.width;
b = crops[SMIAPP_PAD_SINK]->height
- * SMIA_LIM(sensor, SCALER_N_MIN) / sel->r.height;
+ * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.height;
max_m = crops[SMIAPP_PAD_SINK]->width
- * SMIA_LIM(sensor, SCALER_N_MIN)
- / SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE);
+ * CCS_LIM(sensor, SCALER_N_MIN)
+ / CCS_LIM(sensor, MIN_X_OUTPUT_SIZE);
- a = clamp(a, SMIA_LIM(sensor, SCALER_M_MIN),
- SMIA_LIM(sensor, SCALER_M_MAX));
- b = clamp(b, SMIA_LIM(sensor, SCALER_M_MIN),
- SMIA_LIM(sensor, SCALER_M_MAX));
- max_m = clamp(max_m, SMIA_LIM(sensor, SCALER_M_MIN),
- SMIA_LIM(sensor, SCALER_M_MAX));
+ a = clamp(a, CCS_LIM(sensor, SCALER_M_MIN),
+ CCS_LIM(sensor, SCALER_M_MAX));
+ b = clamp(b, CCS_LIM(sensor, SCALER_M_MIN),
+ CCS_LIM(sensor, SCALER_M_MAX));
+ max_m = clamp(max_m, CCS_LIM(sensor, SCALER_M_MIN),
+ CCS_LIM(sensor, SCALER_M_MAX));
dev_dbg(&client->dev, "scaling: a %d b %d max_m %d\n", a, b, max_m);
@@ -2163,8 +2127,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
int this = scaling_goodness(
subdev,
crops[SMIAPP_PAD_SINK]->width
- / try[i]
- * SMIA_LIM(sensor, SCALER_N_MIN),
+ / try[i] * CCS_LIM(sensor, SCALER_N_MIN),
sel->r.width,
crops[SMIAPP_PAD_SINK]->height,
sel->r.height,
@@ -2178,18 +2141,18 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
best = this;
}
- if (SMIA_LIM(sensor, SCALING_CAPABILITY)
- == SMIAPP_SCALING_CAPABILITY_HORIZONTAL)
+ if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ == CCS_SCALING_CAPABILITY_HORIZONTAL)
continue;
this = scaling_goodness(
subdev, crops[SMIAPP_PAD_SINK]->width
/ try[i]
- * SMIA_LIM(sensor, SCALER_N_MIN),
+ * CCS_LIM(sensor, SCALER_N_MIN),
sel->r.width,
crops[SMIAPP_PAD_SINK]->height
/ try[i]
- * SMIA_LIM(sensor, SCALER_N_MIN),
+ * CCS_LIM(sensor, SCALER_N_MIN),
sel->r.height,
sel->flags);
@@ -2203,12 +2166,12 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
sel->r.width =
(crops[SMIAPP_PAD_SINK]->width
/ scale_m
- * SMIA_LIM(sensor, SCALER_N_MIN)) & ~1;
+ * CCS_LIM(sensor, SCALER_N_MIN)) & ~1;
if (mode == SMIAPP_SCALING_MODE_BOTH)
sel->r.height =
(crops[SMIAPP_PAD_SINK]->height
/ scale_m
- * SMIA_LIM(sensor, SCALER_N_MIN))
+ * CCS_LIM(sensor, SCALER_N_MIN))
& ~1;
else
sel->r.height = crops[SMIAPP_PAD_SINK]->height;
@@ -2262,10 +2225,9 @@ static int __smiapp_sel_supported(struct v4l2_subdev *subdev,
if (ssd == sensor->src
&& sel->pad == SMIAPP_PAD_SRC)
return 0;
- if (ssd == sensor->scaler
- && sel->pad == SMIAPP_PAD_SINK
- && SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY)
- == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP)
+ if (ssd == sensor->scaler && sel->pad == SMIAPP_PAD_SINK &&
+ CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP)
return 0;
return -EINVAL;
case V4L2_SEL_TGT_NATIVE_SIZE:
@@ -2279,9 +2241,8 @@ static int __smiapp_sel_supported(struct v4l2_subdev *subdev,
return -EINVAL;
if (ssd == sensor->binner)
return 0;
- if (ssd == sensor->scaler
- && SMIA_LIM(sensor, SCALING_CAPABILITY)
- != SMIAPP_SCALING_CAPABILITY_NONE)
+ if (ssd == sensor->scaler && CCS_LIM(sensor, SCALING_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE)
return 0;
fallthrough;
default:
@@ -2345,8 +2306,8 @@ static void smiapp_get_native_size(struct smiapp_subdev *ssd,
{
r->top = 0;
r->left = 0;
- r->width = SMIA_LIM(ssd->sensor, X_ADDR_MAX) + 1;
- r->height = SMIA_LIM(ssd->sensor, Y_ADDR_MAX) + 1;
+ r->width = CCS_LIM(ssd->sensor, X_ADDR_MAX) + 1;
+ r->height = CCS_LIM(ssd->sensor, Y_ADDR_MAX) + 1;
}
static int __smiapp_get_selection(struct v4l2_subdev *subdev,
@@ -2431,10 +2392,10 @@ static int smiapp_set_selection(struct v4l2_subdev *subdev,
sel->r.height = SMIAPP_ALIGN_DIM(sel->r.height, sel->flags);
sel->r.width = max_t(unsigned int,
- SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE),
+ CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
sel->r.width);
sel->r.height = max_t(unsigned int,
- SMIA_LIM(sensor, MIN_Y_OUTPUT_SIZE),
+ CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
sel->r.height);
switch (sel->target) {
@@ -3123,12 +3084,6 @@ static int smiapp_probe(struct i2c_client *client)
goto out_power_off;
}
- rval = smiapp_read_all_smia_limits(sensor);
- if (rval) {
- rval = -ENODEV;
- goto out_power_off;
- }
-
rval = ccs_read_all_limits(sensor);
if (rval)
goto out_power_off;
@@ -3163,7 +3118,7 @@ static int smiapp_probe(struct i2c_client *client)
goto out_free_ccs_limits;
}
- if (SMIA_LIM(sensor, BINNING_CAPABILITY)) {
+ if (CCS_LIM(sensor, BINNING_CAPABILITY)) {
u32 val;
rval = smiapp_read(sensor,
@@ -3200,8 +3155,8 @@ static int smiapp_probe(struct i2c_client *client)
}
if (sensor->minfo.smiapp_version &&
- SMIA_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
- SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED) {
+ CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
+ CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED) {
if (device_create_file(&client->dev, &dev_attr_nvm) != 0) {
dev_err(&client->dev, "sysfs nvm entry failed\n");
rval = -EBUSY;
@@ -3210,22 +3165,22 @@ static int smiapp_probe(struct i2c_client *client)
}
/* We consider this as profile 0 sensor if any of these are zero. */
- if (!SMIA_LIM(sensor, MIN_OP_SYS_CLK_DIV) ||
- !SMIA_LIM(sensor, MAX_OP_SYS_CLK_DIV) ||
- !SMIA_LIM(sensor, MIN_OP_PIX_CLK_DIV) ||
- !SMIA_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
+ if (!CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV) ||
+ !CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV) ||
+ !CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV) ||
+ !CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
sensor->minfo.smiapp_profile = SMIAPP_PROFILE_0;
- } else if (SMIA_LIM(sensor, SCALING_CAPABILITY)
- != SMIAPP_SCALING_CAPABILITY_NONE) {
- if (SMIA_LIM(sensor, SCALING_CAPABILITY)
- == SMIAPP_SCALING_CAPABILITY_HORIZONTAL)
+ } else if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE) {
+ if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ == CCS_SCALING_CAPABILITY_HORIZONTAL)
sensor->minfo.smiapp_profile = SMIAPP_PROFILE_1;
else
sensor->minfo.smiapp_profile = SMIAPP_PROFILE_2;
sensor->scaler = &sensor->ssds[sensor->ssds_used];
sensor->ssds_used++;
- } else if (SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY)
- == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
+ } else if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
sensor->scaler = &sensor->ssds[sensor->ssds_used];
sensor->ssds_used++;
}
@@ -3234,13 +3189,13 @@ static int smiapp_probe(struct i2c_client *client)
sensor->pixel_array = &sensor->ssds[sensor->ssds_used];
sensor->ssds_used++;
- sensor->scale_m = SMIA_LIM(sensor, SCALER_N_MIN);
+ sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
/* prepare PLL configuration input values */
sensor->pll.bus_type = SMIAPP_PLL_BUS_TYPE_CSI2;
sensor->pll.csi2.lanes = sensor->hwcfg->lanes;
sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk;
- sensor->pll.scale_n = SMIA_LIM(sensor, SCALER_N_MIN);
+ sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
/* Profile 0 sensors have no separate OP clock branch. */
if (sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS;
diff --git a/drivers/media/i2c/smiapp/smiapp-limits.c b/drivers/media/i2c/smiapp/smiapp-limits.c
deleted file mode 100644
index de5ee5296713..000000000000
--- a/drivers/media/i2c/smiapp/smiapp-limits.c
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * drivers/media/i2c/smiapp/smiapp-limits.c
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-
-#include "smiapp.h"
-
-struct smiapp_reg_limits smiapp_reg_limits[] = {
- { SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY, "analogue_gain_capability" }, /* 0 */
- { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN, "analogue_gain_code_min" },
- { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX, "analogue_gain_code_max" },
- { SMIAPP_REG_U8_THS_ZERO_MIN, "ths_zero_min" },
- { SMIAPP_REG_U8_TCLK_TRAIL_MIN, "tclk_trail_min" },
- { SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY, "integration_time_capability" }, /* 5 */
- { SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN, "coarse_integration_time_min" },
- { SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN, "coarse_integration_time_max_margin" },
- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN, "fine_integration_time_min" },
- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN, "fine_integration_time_max_margin" },
- { SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY, "digital_gain_capability" }, /* 10 */
- { SMIAPP_REG_U16_DIGITAL_GAIN_MIN, "digital_gain_min" },
- { SMIAPP_REG_U16_DIGITAL_GAIN_MAX, "digital_gain_max" },
- { SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ, "min_ext_clk_freq_hz" },
- { SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ, "max_ext_clk_freq_hz" },
- { SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV, "min_pre_pll_clk_div" }, /* 15 */
- { SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV, "max_pre_pll_clk_div" },
- { SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ, "min_pll_ip_freq_hz" },
- { SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ, "max_pll_ip_freq_hz" },
- { SMIAPP_REG_U16_MIN_PLL_MULTIPLIER, "min_pll_multiplier" },
- { SMIAPP_REG_U16_MAX_PLL_MULTIPLIER, "max_pll_multiplier" }, /* 20 */
- { SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ, "min_pll_op_freq_hz" },
- { SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ, "max_pll_op_freq_hz" },
- { SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV, "min_vt_sys_clk_div" },
- { SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV, "max_vt_sys_clk_div" },
- { SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ, "min_vt_sys_clk_freq_hz" }, /* 25 */
- { SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ, "max_vt_sys_clk_freq_hz" },
- { SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ, "min_vt_pix_clk_freq_hz" },
- { SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ, "max_vt_pix_clk_freq_hz" },
- { SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV, "min_vt_pix_clk_div" },
- { SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV, "max_vt_pix_clk_div" }, /* 30 */
- { SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES, "min_frame_length_lines" },
- { SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES, "max_frame_length_lines" },
- { SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK, "min_line_length_pck" },
- { SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK, "max_line_length_pck" },
- { SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK, "min_line_blanking_pck" }, /* 35 */
- { SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES, "min_frame_blanking_lines" },
- { SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE, "min_line_length_pck_step_size" },
- { SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV, "min_op_sys_clk_div" },
- { SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV, "max_op_sys_clk_div" },
- { SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ, "min_op_sys_clk_freq_hz" }, /* 40 */
- { SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ, "max_op_sys_clk_freq_hz" },
- { SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV, "min_op_pix_clk_div" },
- { SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV, "max_op_pix_clk_div" },
- { SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ, "min_op_pix_clk_freq_hz" },
- { SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ, "max_op_pix_clk_freq_hz" }, /* 45 */
- { SMIAPP_REG_U16_X_ADDR_MIN, "x_addr_min" },
- { SMIAPP_REG_U16_Y_ADDR_MIN, "y_addr_min" },
- { SMIAPP_REG_U16_X_ADDR_MAX, "x_addr_max" },
- { SMIAPP_REG_U16_Y_ADDR_MAX, "y_addr_max" },
- { SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE, "min_x_output_size" }, /* 50 */
- { SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE, "min_y_output_size" },
- { SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE, "max_x_output_size" },
- { SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE, "max_y_output_size" },
- { SMIAPP_REG_U16_MIN_EVEN_INC, "min_even_inc" },
- { SMIAPP_REG_U16_MAX_EVEN_INC, "max_even_inc" }, /* 55 */
- { SMIAPP_REG_U16_MIN_ODD_INC, "min_odd_inc" },
- { SMIAPP_REG_U16_MAX_ODD_INC, "max_odd_inc" },
- { SMIAPP_REG_U16_SCALING_CAPABILITY, "scaling_capability" },
- { SMIAPP_REG_U16_SCALER_M_MIN, "scaler_m_min" },
- { SMIAPP_REG_U16_SCALER_M_MAX, "scaler_m_max" }, /* 60 */
- { SMIAPP_REG_U16_SCALER_N_MIN, "scaler_n_min" },
- { SMIAPP_REG_U16_SCALER_N_MAX, "scaler_n_max" },
- { SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY, "spatial_sampling_capability" },
- { SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY, "digital_crop_capability" },
- { SMIAPP_REG_U16_COMPRESSION_CAPABILITY, "compression_capability" }, /* 65 */
- { SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY, "fifo_support_capability" },
- { SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY, "dphy_ctrl_capability" },
- { SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY, "csi_lane_mode_capability" },
- { SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY, "csi_signalling_mode_capability" },
- { SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY, "fast_standby_capability" }, /* 70 */
- { SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY, "cci_address_control_capability" },
- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS, "max_per_lane_bitrate_1_lane_mode_mbps" },
- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS, "max_per_lane_bitrate_2_lane_mode_mbps" },
- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS, "max_per_lane_bitrate_3_lane_mode_mbps" },
- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS, "max_per_lane_bitrate_4_lane_mode_mbps" }, /* 75 */
- { SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY, "temp_sensor_capability" },
- { SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN, "min_frame_length_lines_bin" },
- { SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN, "max_frame_length_lines_bin" },
- { SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN, "min_line_length_pck_bin" },
- { SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN, "max_line_length_pck_bin" }, /* 80 */
- { SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN, "min_line_blanking_pck_bin" },
- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN, "fine_integration_time_min_bin" },
- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN, "fine_integration_time_max_margin_bin" },
- { SMIAPP_REG_U8_BINNING_CAPABILITY, "binning_capability" },
- { SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY, "binning_weighting_capability" }, /* 85 */
- { SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY, "data_transfer_if_capability" },
- { SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY, "shading_correction_capability" },
- { SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY, "green_imbalance_capability" },
- { SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY, "black_level_capability" },
- { SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY, "module_specific_correction_capability" }, /* 90 */
- { SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY, "defect_correction_capability" },
- { SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2, "defect_correction_capability_2" },
- { SMIAPP_REG_U8_EDOF_CAPABILITY, "edof_capability" },
- { SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY, "colour_feedback_capability" },
- { SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY, "estimation_mode_capability" }, /* 95 */
- { SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY, "estimation_zone_capability" },
- { SMIAPP_REG_U16_CAPABILITY_TRDY_MIN, "capability_trdy_min" },
- { SMIAPP_REG_U8_FLASH_MODE_CAPABILITY, "flash_mode_capability" },
- { SMIAPP_REG_U8_ACTUATOR_CAPABILITY, "actuator_capability" },
- { SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1, "bracketing_lut_capability_1" }, /* 100 */
- { SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2, "bracketing_lut_capability_2" },
- { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP, "analogue_gain_code_step" },
- { 0, NULL },
-};
diff --git a/drivers/media/i2c/smiapp/smiapp-limits.h b/drivers/media/i2c/smiapp/smiapp-limits.h
deleted file mode 100644
index dbac0b4975f9..000000000000
--- a/drivers/media/i2c/smiapp/smiapp-limits.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * drivers/media/i2c/smiapp/smiapp-limits.h
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-
-#define SMIAPP_LIMIT_ANALOGUE_GAIN_CAPABILITY 0
-#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MIN 1
-#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MAX 2
-#define SMIAPP_LIMIT_THS_ZERO_MIN 3
-#define SMIAPP_LIMIT_TCLK_TRAIL_MIN 4
-#define SMIAPP_LIMIT_INTEGRATION_TIME_CAPABILITY 5
-#define SMIAPP_LIMIT_COARSE_INTEGRATION_TIME_MIN 6
-#define SMIAPP_LIMIT_COARSE_INTEGRATION_TIME_MAX_MARGIN 7
-#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MIN 8
-#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MAX_MARGIN 9
-#define SMIAPP_LIMIT_DIGITAL_GAIN_CAPABILITY 10
-#define SMIAPP_LIMIT_DIGITAL_GAIN_MIN 11
-#define SMIAPP_LIMIT_DIGITAL_GAIN_MAX 12
-#define SMIAPP_LIMIT_MIN_EXT_CLK_FREQ_HZ 13
-#define SMIAPP_LIMIT_MAX_EXT_CLK_FREQ_HZ 14
-#define SMIAPP_LIMIT_MIN_PRE_PLL_CLK_DIV 15
-#define SMIAPP_LIMIT_MAX_PRE_PLL_CLK_DIV 16
-#define SMIAPP_LIMIT_MIN_PLL_IP_FREQ_HZ 17
-#define SMIAPP_LIMIT_MAX_PLL_IP_FREQ_HZ 18
-#define SMIAPP_LIMIT_MIN_PLL_MULTIPLIER 19
-#define SMIAPP_LIMIT_MAX_PLL_MULTIPLIER 20
-#define SMIAPP_LIMIT_MIN_PLL_OP_FREQ_HZ 21
-#define SMIAPP_LIMIT_MAX_PLL_OP_FREQ_HZ 22
-#define SMIAPP_LIMIT_MIN_VT_SYS_CLK_DIV 23
-#define SMIAPP_LIMIT_MAX_VT_SYS_CLK_DIV 24
-#define SMIAPP_LIMIT_MIN_VT_SYS_CLK_FREQ_HZ 25
-#define SMIAPP_LIMIT_MAX_VT_SYS_CLK_FREQ_HZ 26
-#define SMIAPP_LIMIT_MIN_VT_PIX_CLK_FREQ_HZ 27
-#define SMIAPP_LIMIT_MAX_VT_PIX_CLK_FREQ_HZ 28
-#define SMIAPP_LIMIT_MIN_VT_PIX_CLK_DIV 29
-#define SMIAPP_LIMIT_MAX_VT_PIX_CLK_DIV 30
-#define SMIAPP_LIMIT_MIN_FRAME_LENGTH_LINES 31
-#define SMIAPP_LIMIT_MAX_FRAME_LENGTH_LINES 32
-#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK 33
-#define SMIAPP_LIMIT_MAX_LINE_LENGTH_PCK 34
-#define SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK 35
-#define SMIAPP_LIMIT_MIN_FRAME_BLANKING_LINES 36
-#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK_STEP_SIZE 37
-#define SMIAPP_LIMIT_MIN_OP_SYS_CLK_DIV 38
-#define SMIAPP_LIMIT_MAX_OP_SYS_CLK_DIV 39
-#define SMIAPP_LIMIT_MIN_OP_SYS_CLK_FREQ_HZ 40
-#define SMIAPP_LIMIT_MAX_OP_SYS_CLK_FREQ_HZ 41
-#define SMIAPP_LIMIT_MIN_OP_PIX_CLK_DIV 42
-#define SMIAPP_LIMIT_MAX_OP_PIX_CLK_DIV 43
-#define SMIAPP_LIMIT_MIN_OP_PIX_CLK_FREQ_HZ 44
-#define SMIAPP_LIMIT_MAX_OP_PIX_CLK_FREQ_HZ 45
-#define SMIAPP_LIMIT_X_ADDR_MIN 46
-#define SMIAPP_LIMIT_Y_ADDR_MIN 47
-#define SMIAPP_LIMIT_X_ADDR_MAX 48
-#define SMIAPP_LIMIT_Y_ADDR_MAX 49
-#define SMIAPP_LIMIT_MIN_X_OUTPUT_SIZE 50
-#define SMIAPP_LIMIT_MIN_Y_OUTPUT_SIZE 51
-#define SMIAPP_LIMIT_MAX_X_OUTPUT_SIZE 52
-#define SMIAPP_LIMIT_MAX_Y_OUTPUT_SIZE 53
-#define SMIAPP_LIMIT_MIN_EVEN_INC 54
-#define SMIAPP_LIMIT_MAX_EVEN_INC 55
-#define SMIAPP_LIMIT_MIN_ODD_INC 56
-#define SMIAPP_LIMIT_MAX_ODD_INC 57
-#define SMIAPP_LIMIT_SCALING_CAPABILITY 58
-#define SMIAPP_LIMIT_SCALER_M_MIN 59
-#define SMIAPP_LIMIT_SCALER_M_MAX 60
-#define SMIAPP_LIMIT_SCALER_N_MIN 61
-#define SMIAPP_LIMIT_SCALER_N_MAX 62
-#define SMIAPP_LIMIT_SPATIAL_SAMPLING_CAPABILITY 63
-#define SMIAPP_LIMIT_DIGITAL_CROP_CAPABILITY 64
-#define SMIAPP_LIMIT_COMPRESSION_CAPABILITY 65
-#define SMIAPP_LIMIT_FIFO_SUPPORT_CAPABILITY 66
-#define SMIAPP_LIMIT_DPHY_CTRL_CAPABILITY 67
-#define SMIAPP_LIMIT_CSI_LANE_MODE_CAPABILITY 68
-#define SMIAPP_LIMIT_CSI_SIGNALLING_MODE_CAPABILITY 69
-#define SMIAPP_LIMIT_FAST_STANDBY_CAPABILITY 70
-#define SMIAPP_LIMIT_CCI_ADDRESS_CONTROL_CAPABILITY 71
-#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS 72
-#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS 73
-#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS 74
-#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS 75
-#define SMIAPP_LIMIT_TEMP_SENSOR_CAPABILITY 76
-#define SMIAPP_LIMIT_MIN_FRAME_LENGTH_LINES_BIN 77
-#define SMIAPP_LIMIT_MAX_FRAME_LENGTH_LINES_BIN 78
-#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK_BIN 79
-#define SMIAPP_LIMIT_MAX_LINE_LENGTH_PCK_BIN 80
-#define SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK_BIN 81
-#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MIN_BIN 82
-#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN 83
-#define SMIAPP_LIMIT_BINNING_CAPABILITY 84
-#define SMIAPP_LIMIT_BINNING_WEIGHTING_CAPABILITY 85
-#define SMIAPP_LIMIT_DATA_TRANSFER_IF_CAPABILITY 86
-#define SMIAPP_LIMIT_SHADING_CORRECTION_CAPABILITY 87
-#define SMIAPP_LIMIT_GREEN_IMBALANCE_CAPABILITY 88
-#define SMIAPP_LIMIT_BLACK_LEVEL_CAPABILITY 89
-#define SMIAPP_LIMIT_MODULE_SPECIFIC_CORRECTION_CAPABILITY 90
-#define SMIAPP_LIMIT_DEFECT_CORRECTION_CAPABILITY 91
-#define SMIAPP_LIMIT_DEFECT_CORRECTION_CAPABILITY_2 92
-#define SMIAPP_LIMIT_EDOF_CAPABILITY 93
-#define SMIAPP_LIMIT_COLOUR_FEEDBACK_CAPABILITY 94
-#define SMIAPP_LIMIT_ESTIMATION_MODE_CAPABILITY 95
-#define SMIAPP_LIMIT_ESTIMATION_ZONE_CAPABILITY 96
-#define SMIAPP_LIMIT_CAPABILITY_TRDY_MIN 97
-#define SMIAPP_LIMIT_FLASH_MODE_CAPABILITY 98
-#define SMIAPP_LIMIT_ACTUATOR_CAPABILITY 99
-#define SMIAPP_LIMIT_BRACKETING_LUT_CAPABILITY_1 100
-#define SMIAPP_LIMIT_BRACKETING_LUT_CAPABILITY_2 101
-#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_STEP 102
-#define SMIAPP_LIMIT_LAST 103
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/smiapp-quirk.c
index 308ca0b03f5a..24630c7650d2 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.c
+++ b/drivers/media/i2c/smiapp/smiapp-quirk.c
@@ -10,6 +10,8 @@
#include <linux/delay.h>
+#include "ccs-limits.h"
+
#include "smiapp.h"
static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val)
@@ -36,17 +38,6 @@ static int smiapp_write_8s(struct smiapp_sensor *sensor,
return 0;
}
-void smiapp_replace_limit(struct smiapp_sensor *sensor,
- u32 limit, u32 val)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
-
- dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" = %d, 0x%x\n",
- smiapp_reg_limits[limit].addr,
- smiapp_reg_limits[limit].what, val, val);
- sensor->limits[limit] = val;
-}
-
static int jt8ew9_limits(struct smiapp_sensor *sensor)
{
if (sensor->minfo.revision_number_major < 0x03)
@@ -54,9 +45,8 @@ static int jt8ew9_limits(struct smiapp_sensor *sensor)
/* Below 24 gain doesn't have effect at all, */
/* but ~59 is needed for full dynamic range */
- smiapp_replace_limit(sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MIN, 59);
- smiapp_replace_limit(
- sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MAX, 6000);
+ ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MIN, 0, 59);
+ ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MAX, 0, 6000);
return 0;
}
@@ -126,9 +116,8 @@ const struct smiapp_quirk smiapp_imx125es_quirk = {
static int jt8ev1_limits(struct smiapp_sensor *sensor)
{
- smiapp_replace_limit(sensor, SMIAPP_LIMIT_X_ADDR_MAX, 4271);
- smiapp_replace_limit(sensor,
- SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK_BIN, 184);
+ ccs_replace_limit(sensor, CCS_L_X_ADDR_MAX, 0, 4271);
+ ccs_replace_limit(sensor, CCS_L_MIN_LINE_BLANKING_PCK_BIN, 0, 184);
return 0;
}
@@ -221,7 +210,7 @@ const struct smiapp_quirk smiapp_jt8ev1_quirk = {
static int tcm8500md_limits(struct smiapp_sensor *sensor)
{
- smiapp_replace_limit(sensor, SMIAPP_LIMIT_MIN_PLL_IP_FREQ_HZ, 2700000);
+ ccs_replace_limit(sensor, CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0, 2700000);
return 0;
}
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.h b/drivers/media/i2c/smiapp/smiapp-quirk.h
index 17505be60c1d..8a479f17cd19 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.h
+++ b/drivers/media/i2c/smiapp/smiapp-quirk.h
@@ -55,9 +55,6 @@ struct smiapp_reg_8 {
u8 val;
};
-void smiapp_replace_limit(struct smiapp_sensor *sensor,
- u32 limit, u32 val);
-
#define SMIAPP_MK_QUIRK_REG_8(_reg, _val) \
{ \
.reg = (u16)_reg, \
diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
index 08ca1b3d1b2f..1a67cf485dcc 100644
--- a/drivers/media/i2c/smiapp/smiapp.h
+++ b/drivers/media/i2c/smiapp/smiapp.h
@@ -84,8 +84,6 @@ struct smiapp_hwconfig {
struct smiapp_flash_strobe_parms *strobe_setup;
};
-#include "smiapp-limits.h"
-
struct smiapp_quirk;
#define SMIAPP_MODULE_IDENT_FLAG_REV_LE (1 << 0)
@@ -167,13 +165,6 @@ struct smiapp_module_info {
.flags = 0, \
.name = _name, }
-struct smiapp_reg_limits {
- u32 addr;
- char *what;
-};
-
-extern struct smiapp_reg_limits smiapp_reg_limits[];
-
struct smiapp_csi_data_format {
u32 code;
u8 width;
@@ -227,7 +218,6 @@ struct smiapp_sensor {
struct regulator *vana;
struct clk *ext_clk;
struct gpio_desc *xshutdown;
- u32 limits[SMIAPP_LIMIT_LAST];
void *ccs_limits;
u8 nbinning_subtypes;
struct smiapp_binning_subtype binning_subtypes[SMIAPP_BINNING_SUBTYPES];
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 11/29] smiapp: Obtain frame descriptor from CCS limits
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (9 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 10/29] smiapp: Switch to CCS limits Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 12/29] smiapp: Use CCS limits in reading data format descriptors Sakari Ailus
` (17 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Obtain the frame descriptor from the CCS limits, instead of reading them
directly from the frame descriptor registers.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 70 +++++++++++---------------
1 file changed, 30 insertions(+), 40 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index 2c1a13507965..daeff6186727 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -228,34 +228,29 @@ static int ccs_read_all_limits(struct smiapp_sensor *sensor)
static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- u32 fmt_model_type, fmt_model_subtype, ncol_desc, nrow_desc;
+ u8 fmt_model_type, fmt_model_subtype, ncol_desc, nrow_desc;
unsigned int i;
int pixel_count = 0;
int line_count = 0;
- int rval;
-
- rval = smiapp_read(sensor, SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE,
- &fmt_model_type);
- if (rval)
- return rval;
- rval = smiapp_read(sensor, SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE,
- &fmt_model_subtype);
- if (rval)
- return rval;
+ fmt_model_type = CCS_LIM(sensor, FRAME_FORMAT_MODEL_TYPE);
+ fmt_model_subtype = CCS_LIM(sensor, FRAME_FORMAT_MODEL_SUBTYPE);
ncol_desc = (fmt_model_subtype
- & SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK)
- >> SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT;
+ & CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK)
+ >> CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT;
nrow_desc = fmt_model_subtype
- & SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK;
+ & CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK;
dev_dbg(&client->dev, "format_model_type %s\n",
- fmt_model_type == SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE
+ fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE
? "2 byte" :
- fmt_model_type == SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE
+ fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE
? "4 byte" : "is simply bad");
+ dev_dbg(&client->dev, "%u column and %u row descriptors\n",
+ ncol_desc, nrow_desc);
+
for (i = 0; i < ncol_desc + nrow_desc; i++) {
u32 desc;
u32 pixelcode;
@@ -264,29 +259,24 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
char *what;
u32 reg;
- if (fmt_model_type == SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE) {
- reg = SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(i);
- rval = smiapp_read(sensor, reg, &desc);
- if (rval)
- return rval;
+ if (fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE) {
+ desc = CCS_LIM_AT(sensor, FRAME_FORMAT_DESCRIPTOR, i);
pixelcode =
(desc
- & SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK)
- >> SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT;
- pixels = desc & SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK;
+ & CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK)
+ >> CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT;
+ pixels = desc & CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK;
} else if (fmt_model_type
- == SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE) {
- reg = SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(i);
- rval = smiapp_read(sensor, reg, &desc);
- if (rval)
- return rval;
+ == CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE) {
+ desc = CCS_LIM_AT(sensor, FRAME_FORMAT_DESCRIPTOR_4, i);
pixelcode =
(desc
- & SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK)
- >> SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT;
- pixels = desc & SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK;
+ & CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK)
+ >> CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_SHIFT;
+ pixels = desc &
+ CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK;
} else {
dev_dbg(&client->dev,
"invalid frame format model type %d\n",
@@ -300,19 +290,19 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
which = "rows";
switch (pixelcode) {
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED:
what = "embedded";
break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL:
what = "dummy";
break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_BLACK_PIXEL:
what = "black";
break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DARK_PIXEL:
what = "dark";
break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL:
what = "visible";
break;
default:
@@ -326,7 +316,7 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
if (i < ncol_desc) {
if (pixelcode ==
- SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE)
+ CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL)
sensor->visible_pixel_start = pixel_count;
pixel_count += pixels;
continue;
@@ -334,13 +324,13 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
/* Handle row descriptors */
switch (pixelcode) {
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED:
if (sensor->embedded_end)
break;
sensor->embedded_start = line_count;
sensor->embedded_end = line_count + pixels;
break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE:
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL:
sensor->image_start = line_count;
break;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 12/29] smiapp: Use CCS limits in reading data format descriptors
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (10 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 11/29] smiapp: Obtain frame descriptor from " Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 13/29] smiapp: Use CCS limits in reading binning capabilities Sakari Ailus
` (16 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
The CCS limits have the information so use it instead.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 22 +++++++++-------------
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index daeff6186727..c332b6ecf0bd 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -842,10 +842,7 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
unsigned int i, pixel_order;
int rval;
- rval = smiapp_read(
- sensor, SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE, &type);
- if (rval)
- return rval;
+ type = CCS_LIM(sensor, DATA_FORMAT_MODEL_TYPE);
dev_dbg(&client->dev, "data_format_model_type %d\n", type);
@@ -863,11 +860,11 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
pixel_order_str[pixel_order]);
switch (type) {
- case SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL:
+ case CCS_DATA_FORMAT_MODEL_TYPE_NORMAL:
n = SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N;
break;
- case SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED:
- n = SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N;
+ case CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED:
+ n = CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N + 1;
break;
default:
return -EINVAL;
@@ -879,11 +876,7 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
for (i = 0; i < n; i++) {
unsigned int fmt, j;
- rval = smiapp_read(
- sensor,
- SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(i), &fmt);
- if (rval)
- return rval;
+ fmt = CCS_LIM_AT(sensor, DATA_FORMAT_DESCRIPTOR, i);
dev_dbg(&client->dev, "%u: bpp %u, compressed %u\n",
i, fmt >> 8, (u8)fmt);
@@ -895,7 +888,10 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
if (f->pixel_order != SMIAPP_PIXEL_ORDER_GRBG)
continue;
- if (f->width != fmt >> 8 || f->compressed != (u8)fmt)
+ if (f->width != fmt >>
+ CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT ||
+ f->compressed !=
+ (fmt & CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK))
continue;
dev_dbg(&client->dev, "jolly good! %d\n", j);
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 13/29] smiapp: Use CCS limits in reading binning capabilities
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (11 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 12/29] smiapp: Use CCS limits in reading data format descriptors Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 14/29] smiapp: Use CCS registers Sakari Ailus
` (15 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Use CCS limits for obtaining binning capabilities and subtypes.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 27 +++++++++-----------------
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index c332b6ecf0bd..d786f91c1eae 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -3105,26 +3105,17 @@ static int smiapp_probe(struct i2c_client *client)
}
if (CCS_LIM(sensor, BINNING_CAPABILITY)) {
- u32 val;
-
- rval = smiapp_read(sensor,
- SMIAPP_REG_U8_BINNING_SUBTYPES, &val);
- if (rval < 0) {
- rval = -ENODEV;
- goto out_free_ccs_limits;
- }
- sensor->nbinning_subtypes = min_t(u8, val,
- SMIAPP_BINNING_SUBTYPES);
+ sensor->nbinning_subtypes =
+ min_t(u8, CCS_LIM(sensor, BINNING_SUB_TYPES),
+ CCS_LIM_BINNING_SUB_TYPE_MAX_N);
for (i = 0; i < sensor->nbinning_subtypes; i++) {
- rval = smiapp_read(
- sensor, SMIAPP_REG_U8_BINNING_TYPE_n(i), &val);
- if (rval < 0) {
- rval = -ENODEV;
- goto out_free_ccs_limits;
- }
- sensor->binning_subtypes[i] =
- *(struct smiapp_binning_subtype *)&val;
+ sensor->binning_subtypes[i].horizontal =
+ CCS_LIM_AT(sensor, BINNING_SUB_TYPE, i) >>
+ CCS_BINNING_SUB_TYPE_COLUMN_SHIFT;
+ sensor->binning_subtypes[i].vertical =
+ CCS_LIM_AT(sensor, BINNING_SUB_TYPE, i) &
+ CCS_BINNING_SUB_TYPE_ROW_MASK;
dev_dbg(&client->dev, "binning %xx%x\n",
sensor->binning_subtypes[i].horizontal,
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 14/29] smiapp: Use CCS registers
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (12 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 13/29] smiapp: Use CCS limits in reading binning capabilities Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 15/29] smiapp: Remove quirk function for writing a single 8-bit register Sakari Ailus
` (14 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Switch to CCS standard registers where they exist. The still relevant SMIA
registers are left as-is and the redundant ones are removed.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 272 +++++++++++--------------
drivers/media/i2c/smiapp/smiapp.h | 4 +-
2 files changed, 118 insertions(+), 158 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index d786f91c1eae..382a2d14f0f4 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -28,7 +28,6 @@
#include <media/v4l2-device.h>
#include "ccs-limits.h"
-#include "ccs-regs.h"
#include "smiapp.h"
#define SMIAPP_ALIGN_DIM(dim, flags) \
@@ -357,40 +356,34 @@ static int smiapp_pll_configure(struct smiapp_sensor *sensor)
struct smiapp_pll *pll = &sensor->pll;
int rval;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_VT_PIX_CLK_DIV, pll->vt.pix_clk_div);
+ rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt.pix_clk_div);
if (rval < 0)
return rval;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_VT_SYS_CLK_DIV, pll->vt.sys_clk_div);
+ rval = ccs_write(sensor, VT_SYS_CLK_DIV, pll->vt.sys_clk_div);
if (rval < 0)
return rval;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_PRE_PLL_CLK_DIV, pll->pre_pll_clk_div);
+ rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->pre_pll_clk_div);
if (rval < 0)
return rval;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_PLL_MULTIPLIER, pll->pll_multiplier);
+ rval = ccs_write(sensor, PLL_MULTIPLIER, pll->pll_multiplier);
if (rval < 0)
return rval;
/* Lane op clock ratio does not apply here. */
- rval = smiapp_write(
- sensor, SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS,
- DIV_ROUND_UP(pll->op.sys_clk_freq_hz, 1000000 / 256 / 256));
+ rval = ccs_write(sensor, REQUESTED_LINK_RATE,
+ DIV_ROUND_UP(pll->op.sys_clk_freq_hz,
+ 1000000 / 256 / 256));
if (rval < 0 || sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
return rval;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_OP_PIX_CLK_DIV, pll->op.pix_clk_div);
+ rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op.pix_clk_div);
if (rval < 0)
return rval;
- return smiapp_write(
- sensor, SMIAPP_REG_U16_OP_SYS_CLK_DIV, pll->op.sys_clk_div);
+ return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op.sys_clk_div);
}
static int smiapp_pll_try(struct smiapp_sensor *sensor,
@@ -522,10 +515,10 @@ static u32 smiapp_pixel_order(struct smiapp_sensor *sensor)
if (sensor->hflip) {
if (sensor->hflip->val)
- flip |= SMIAPP_IMAGE_ORIENTATION_HFLIP;
+ flip |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR;
if (sensor->vflip->val)
- flip |= SMIAPP_IMAGE_ORIENTATION_VFLIP;
+ flip |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
}
flip ^= sensor->hvflip_inv_mask;
@@ -585,10 +578,10 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
return -EBUSY;
if (sensor->hflip->val)
- orient |= SMIAPP_IMAGE_ORIENTATION_HFLIP;
+ orient |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR;
if (sensor->vflip->val)
- orient |= SMIAPP_IMAGE_ORIENTATION_VFLIP;
+ orient |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
orient ^= sensor->hvflip_inv_mask;
@@ -633,60 +626,50 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
switch (ctrl->id) {
case V4L2_CID_ANALOGUE_GAIN:
- rval = smiapp_write(
- sensor,
- SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL, ctrl->val);
+ rval = ccs_write(sensor, ANALOG_GAIN_CODE_GLOBAL, ctrl->val);
break;
case V4L2_CID_EXPOSURE:
- rval = smiapp_write(
- sensor,
- SMIAPP_REG_U16_COARSE_INTEGRATION_TIME, ctrl->val);
+ rval = ccs_write(sensor, COARSE_INTEGRATION_TIME, ctrl->val);
break;
case V4L2_CID_HFLIP:
case V4L2_CID_VFLIP:
- rval = smiapp_write(sensor, SMIAPP_REG_U8_IMAGE_ORIENTATION,
- orient);
+ rval = ccs_write(sensor, IMAGE_ORIENTATION, orient);
break;
case V4L2_CID_VBLANK:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_FRAME_LENGTH_LINES,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height
- + ctrl->val);
+ rval = ccs_write(sensor, FRAME_LENGTH_LINES,
+ sensor->pixel_array->crop[
+ SMIAPP_PA_PAD_SRC].height
+ + ctrl->val);
break;
case V4L2_CID_HBLANK:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_LINE_LENGTH_PCK,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width
- + ctrl->val);
+ rval = ccs_write(sensor, LINE_LENGTH_PCK,
+ sensor->pixel_array->crop[
+ SMIAPP_PA_PAD_SRC].width
+ + ctrl->val);
break;
case V4L2_CID_TEST_PATTERN:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_PATTERN_MODE, ctrl->val);
+ rval = ccs_write(sensor, TEST_PATTERN_MODE, ctrl->val);
break;
case V4L2_CID_TEST_PATTERN_RED:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_DATA_RED, ctrl->val);
+ rval = ccs_write(sensor, TEST_DATA_RED, ctrl->val);
break;
case V4L2_CID_TEST_PATTERN_GREENR:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_DATA_GREENR, ctrl->val);
+ rval = ccs_write(sensor, TEST_DATA_GREENR, ctrl->val);
break;
case V4L2_CID_TEST_PATTERN_BLUE:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_DATA_BLUE, ctrl->val);
+ rval = ccs_write(sensor, TEST_DATA_BLUE, ctrl->val);
break;
case V4L2_CID_TEST_PATTERN_GREENB:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_DATA_GREENB, ctrl->val);
+ rval = ccs_write(sensor, TEST_DATA_GREENB, ctrl->val);
break;
case V4L2_CID_PIXEL_RATE:
@@ -846,8 +829,7 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
dev_dbg(&client->dev, "data_format_model_type %d\n", type);
- rval = smiapp_read(sensor, SMIAPP_REG_U8_PIXEL_ORDER,
- &pixel_order);
+ rval = ccs_read(sensor, PIXEL_ORDER, &pixel_order);
if (rval)
return rval;
@@ -1054,22 +1036,20 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
*status = 0;
- rval = smiapp_write(sensor,
- SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT, p);
+ rval = ccs_write(sensor, DATA_TRANSFER_IF_1_PAGE_SELECT, p);
if (rval)
return rval;
- rval = smiapp_write(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL,
- SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN);
+ rval = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL,
+ CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE);
if (rval)
return rval;
- rval = smiapp_read(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS,
- &s);
+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s);
if (rval)
return rval;
- if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE) {
+ if (s & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE) {
*status = s;
return -ENODATA;
}
@@ -1077,14 +1057,10 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
if (CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING) {
for (i = 1000; i > 0; i--) {
- if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY)
+ if (s & CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY)
break;
- rval = smiapp_read(
- sensor,
- SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS,
- &s);
-
+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s);
if (rval)
return rval;
}
@@ -1093,12 +1069,10 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
return -ETIMEDOUT;
}
- for (i = 0; i < SMIAPP_NVM_PAGE_SIZE; i++) {
+ for (i = 0; i <= CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P; i++) {
u32 v;
- rval = smiapp_read(sensor,
- SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 + i,
- &v);
+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_DATA(i), &v);
if (rval)
return rval;
@@ -1115,20 +1089,21 @@ static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm,
u32 p;
int rval = 0, rval2;
- for (p = 0; p < nvm_size / SMIAPP_NVM_PAGE_SIZE && !rval; p++) {
+ for (p = 0; p < nvm_size / (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1)
+ && !rval; p++) {
rval = smiapp_read_nvm_page(sensor, p, nvm, &status);
- nvm += SMIAPP_NVM_PAGE_SIZE;
+ nvm += CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1;
}
if (rval == -ENODATA &&
- status & SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE)
+ status & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE)
rval = 0;
- rval2 = smiapp_write(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL, 0);
+ rval2 = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL, 0);
if (rval < 0)
return rval;
else
- return rval2 ?: p * SMIAPP_NVM_PAGE_SIZE;
+ return rval2 ?: p * (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1);
}
/*
@@ -1144,16 +1119,15 @@ static int smiapp_change_cci_addr(struct smiapp_sensor *sensor)
client->addr = sensor->hwcfg->i2c_addr_dfl;
- rval = smiapp_write(sensor,
- SMIAPP_REG_U8_CCI_ADDRESS_CONTROL,
- sensor->hwcfg->i2c_addr_alt << 1);
+ rval = ccs_write(sensor, CCI_ADDRESS_CTRL,
+ sensor->hwcfg->i2c_addr_alt << 1);
if (rval)
return rval;
client->addr = sensor->hwcfg->i2c_addr_alt;
/* verify addr change went ok */
- rval = smiapp_read(sensor, SMIAPP_REG_U8_CCI_ADDRESS_CONTROL, &val);
+ rval = ccs_read(sensor, CCI_ADDRESS_CTRL, &val);
if (rval)
return rval;
@@ -1259,34 +1233,30 @@ static int smiapp_setup_flash_strobe(struct smiapp_sensor *sensor)
strobe_width_high_rs = (tmp + strobe_adjustment - 1) /
strobe_adjustment;
- rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_MODE_RS,
- strobe_setup->mode);
+ rval = ccs_write(sensor, FLASH_MODE_RS, strobe_setup->mode);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT,
- strobe_adjustment);
+ rval = ccs_write(sensor, FLASH_STROBE_ADJUSTMENT, strobe_adjustment);
if (rval < 0)
goto out;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL,
- strobe_width_high_rs);
+ rval = ccs_write(sensor, TFLASH_STROBE_WIDTH_HIGH_RS_CTRL,
+ strobe_width_high_rs);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL,
- strobe_setup->strobe_delay);
+ rval = ccs_write(sensor, TFLASH_STROBE_DELAY_RS_CTRL,
+ strobe_setup->strobe_delay);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U16_FLASH_STROBE_START_POINT,
- strobe_setup->stobe_start_point);
+ rval = ccs_write(sensor, FLASH_STROBE_START_POINT,
+ strobe_setup->stobe_start_point);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_TRIGGER_RS,
- strobe_setup->trigger);
+ rval = ccs_write(sensor, FLASH_TRIGGER_RS, strobe_setup->trigger);
out:
sensor->hwcfg->strobe_setup->trigger = 0;
@@ -1349,8 +1319,7 @@ static int smiapp_power_on(struct device *dev)
}
}
- rval = smiapp_write(sensor, SMIAPP_REG_U8_SOFTWARE_RESET,
- SMIAPP_SOFTWARE_RESET);
+ rval = ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
if (rval < 0) {
dev_err(dev, "software reset failed\n");
goto out_cci_addr_fail;
@@ -1364,45 +1333,42 @@ static int smiapp_power_on(struct device *dev)
}
}
- rval = smiapp_write(sensor, SMIAPP_REG_U16_COMPRESSION_MODE,
- SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR);
+ rval = ccs_write(sensor, COMPRESSION_MODE,
+ CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE);
if (rval) {
dev_err(dev, "compression mode set failed\n");
goto out_cci_addr_fail;
}
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ,
- sensor->hwcfg->ext_clk / (1000000 / (1 << 8)));
+ rval = ccs_write(sensor, EXTCLK_FREQUENCY_MHZ,
+ sensor->hwcfg->ext_clk / (1000000 / (1 << 8)));
if (rval) {
dev_err(dev, "extclk frequency set failed\n");
goto out_cci_addr_fail;
}
- rval = smiapp_write(sensor, SMIAPP_REG_U8_CSI_LANE_MODE,
- sensor->hwcfg->lanes - 1);
+ rval = ccs_write(sensor, CSI_LANE_MODE, sensor->hwcfg->lanes - 1);
if (rval) {
dev_err(dev, "csi lane mode set failed\n");
goto out_cci_addr_fail;
}
- rval = smiapp_write(sensor, SMIAPP_REG_U8_FAST_STANDBY_CTRL,
- SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE);
+ rval = ccs_write(sensor, FAST_STANDBY_CTRL,
+ CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION);
if (rval) {
dev_err(dev, "fast standby set failed\n");
goto out_cci_addr_fail;
}
- rval = smiapp_write(sensor, SMIAPP_REG_U8_CSI_SIGNALLING_MODE,
- sensor->hwcfg->csi_signalling_mode);
+ rval = ccs_write(sensor, CSI_SIGNALING_MODE,
+ sensor->hwcfg->csi_signalling_mode);
if (rval) {
dev_err(dev, "csi signalling mode set failed\n");
goto out_cci_addr_fail;
}
/* DPHY control done by sensor based on requested link rate */
- rval = smiapp_write(sensor, SMIAPP_REG_U8_DPHY_CTRL,
- SMIAPP_DPHY_CTRL_UI);
+ rval = ccs_write(sensor, PHY_CTRL, CCS_PHY_CTRL_UI);
if (rval < 0)
goto out_cci_addr_fail;
@@ -1439,9 +1405,7 @@ static int smiapp_power_off(struct device *dev)
* will fail. So do a soft reset explicitly here.
*/
if (sensor->hwcfg->i2c_addr_alt)
- smiapp_write(sensor,
- SMIAPP_REG_U8_SOFTWARE_RESET,
- SMIAPP_SOFTWARE_RESET);
+ ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
gpiod_set_value(sensor->xshutdown, 0);
clk_disable_unprepare(sensor->ext_clk);
@@ -1464,9 +1428,9 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
mutex_lock(&sensor->mutex);
- rval = smiapp_write(sensor, SMIAPP_REG_U16_CSI_DATA_FORMAT,
- (sensor->csi_format->width << 8) |
- sensor->csi_format->compressed);
+ rval = ccs_write(sensor, CSI_DATA_FORMAT,
+ (sensor->csi_format->width << 8) |
+ sensor->csi_format->compressed);
if (rval)
goto out;
@@ -1479,14 +1443,13 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
(sensor->binning_horizontal << 4)
| sensor->binning_vertical;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U8_BINNING_TYPE, binning_type);
+ rval = ccs_write(sensor, BINNING_TYPE, binning_type);
if (rval < 0)
goto out;
binning_mode = 1;
}
- rval = smiapp_write(sensor, SMIAPP_REG_U8_BINNING_MODE, binning_mode);
+ rval = ccs_write(sensor, BINNING_MODE, binning_mode);
if (rval < 0)
goto out;
@@ -1496,26 +1459,26 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
goto out;
/* Analog crop start coordinates */
- rval = smiapp_write(sensor, SMIAPP_REG_U16_X_ADDR_START,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left);
+ rval = ccs_write(sensor, X_ADDR_START,
+ sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U16_Y_ADDR_START,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top);
+ rval = ccs_write(sensor, Y_ADDR_START,
+ sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top);
if (rval < 0)
goto out;
/* Analog crop end coordinates */
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_X_ADDR_END,
+ rval = ccs_write(
+ sensor, X_ADDR_END,
sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left
+ sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width - 1);
if (rval < 0)
goto out;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_Y_ADDR_END,
+ rval = ccs_write(
+ sensor, Y_ADDR_END,
sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top
+ sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height - 1);
if (rval < 0)
@@ -1529,26 +1492,26 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
/* Digital crop */
if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
== CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET,
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_X_OFFSET,
sensor->scaler->crop[SMIAPP_PAD_SINK].left);
if (rval < 0)
goto out;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET,
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_Y_OFFSET,
sensor->scaler->crop[SMIAPP_PAD_SINK].top);
if (rval < 0)
goto out;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH,
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_IMAGE_WIDTH,
sensor->scaler->crop[SMIAPP_PAD_SINK].width);
if (rval < 0)
goto out;
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT,
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_IMAGE_HEIGHT,
sensor->scaler->crop[SMIAPP_PAD_SINK].height);
if (rval < 0)
goto out;
@@ -1557,24 +1520,22 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
/* Scaling */
if (CCS_LIM(sensor, SCALING_CAPABILITY)
!= CCS_SCALING_CAPABILITY_NONE) {
- rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALING_MODE,
- sensor->scaling_mode);
+ rval = ccs_write(sensor, SCALING_MODE, sensor->scaling_mode);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALE_M,
- sensor->scale_m);
+ rval = ccs_write(sensor, SCALE_M, sensor->scale_m);
if (rval < 0)
goto out;
}
/* Output size from sensor */
- rval = smiapp_write(sensor, SMIAPP_REG_U16_X_OUTPUT_SIZE,
- sensor->src->crop[SMIAPP_PAD_SRC].width);
+ rval = ccs_write(sensor, X_OUTPUT_SIZE,
+ sensor->src->crop[SMIAPP_PAD_SRC].width);
if (rval < 0)
goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U16_Y_OUTPUT_SIZE,
- sensor->src->crop[SMIAPP_PAD_SRC].height);
+ rval = ccs_write(sensor, Y_OUTPUT_SIZE,
+ sensor->src->crop[SMIAPP_PAD_SRC].height);
if (rval < 0)
goto out;
@@ -1594,8 +1555,7 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
goto out;
}
- rval = smiapp_write(sensor, SMIAPP_REG_U8_MODE_SELECT,
- SMIAPP_MODE_SELECT_STREAMING);
+ rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_STREAMING);
out:
mutex_unlock(&sensor->mutex);
@@ -1609,8 +1569,7 @@ static int smiapp_stop_streaming(struct smiapp_sensor *sensor)
int rval;
mutex_lock(&sensor->mutex);
- rval = smiapp_write(sensor, SMIAPP_REG_U8_MODE_SELECT,
- SMIAPP_MODE_SELECT_SOFTWARE_STANDBY);
+ rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_SOFTWARE_STANDBY);
if (rval)
goto out;
@@ -1828,7 +1787,7 @@ static void smiapp_propagate(struct v4l2_subdev *subdev,
sensor->scale_m =
CCS_LIM(sensor, SCALER_N_MIN);
sensor->scaling_mode =
- SMIAPP_SCALING_MODE_NONE;
+ CCS_SCALING_MODE_NO_SCALING;
} else if (ssd == sensor->binner) {
sensor->binning_horizontal = 1;
sensor->binning_vertical = 1;
@@ -2063,7 +2022,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
u32 min, max, a, b, max_m;
u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN);
- int mode = SMIAPP_SCALING_MODE_HORIZONTAL;
+ int mode = CCS_SCALING_MODE_HORIZONTAL;
u32 try[4];
u32 ntry = 0;
unsigned int i;
@@ -2123,7 +2082,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
if (this > best) {
scale_m = try[i];
- mode = SMIAPP_SCALING_MODE_HORIZONTAL;
+ mode = CCS_SCALING_MODE_HORIZONTAL;
best = this;
}
@@ -2494,26 +2453,24 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID,
&minfo->smia_manufacturer_id);
if (!rval)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U16_MODEL_ID,
+ rval = smiapp_read_8only(sensor, CCS_R_MODULE_MODEL_ID,
&minfo->model_id);
if (!rval)
rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_REVISION_NUMBER_MAJOR,
+ CCS_R_MODULE_REVISION_NUMBER_MAJOR,
&minfo->revision_number_major);
if (!rval)
rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_REVISION_NUMBER_MINOR,
+ CCS_R_MODULE_REVISION_NUMBER_MINOR,
&minfo->revision_number_minor);
if (!rval)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_MODULE_DATE_YEAR,
+ rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_YEAR,
&minfo->module_year);
if (!rval)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_MODULE_DATE_MONTH,
+ rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_MONTH,
&minfo->module_month);
if (!rval)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MODULE_DATE_DAY,
+ rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_DAY,
&minfo->module_day);
/* Sensor info */
@@ -2522,19 +2479,19 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
&minfo->sensor_mipi_manufacturer_id);
if (!rval && !minfo->sensor_mipi_manufacturer_id)
rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID,
+ CCS_R_SENSOR_MANUFACTURER_ID,
&minfo->sensor_smia_manufacturer_id);
if (!rval)
rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U16_SENSOR_MODEL_ID,
+ CCS_R_SENSOR_MODEL_ID,
&minfo->sensor_model_id);
if (!rval)
rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_SENSOR_REVISION_NUMBER,
+ CCS_R_SENSOR_REVISION_NUMBER,
&minfo->sensor_revision_number);
if (!rval)
rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION,
+ CCS_R_SENSOR_FIRMWARE_VERSION,
&minfo->sensor_firmware_version);
/* SMIA */
@@ -2919,7 +2876,7 @@ static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev)
switch (bus_cfg.bus_type) {
case V4L2_MBUS_CSI2_DPHY:
- hwcfg->csi_signalling_mode = SMIAPP_CSI_SIGNALLING_MODE_CSI2;
+ hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_DPHY;
hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
break;
case V4L2_MBUS_CCP2:
@@ -3095,8 +3052,9 @@ static int smiapp_probe(struct i2c_client *client)
*/
if (sensor->hwcfg->module_board_orient ==
SMIAPP_MODULE_BOARD_ORIENT_180)
- sensor->hvflip_inv_mask = SMIAPP_IMAGE_ORIENTATION_HFLIP |
- SMIAPP_IMAGE_ORIENTATION_VFLIP;
+ sensor->hvflip_inv_mask =
+ CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR |
+ CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
rval = smiapp_call_quirk(sensor, limits);
if (rval) {
diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
index 1a67cf485dcc..c6e4e05a7522 100644
--- a/drivers/media/i2c/smiapp/smiapp.h
+++ b/drivers/media/i2c/smiapp/smiapp.h
@@ -15,6 +15,8 @@
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
+#include "ccs-regs.h"
+
#include "smiapp-pll.h"
#include "smiapp-reg-defs.h"
#include "smiapp-regs.h"
@@ -220,7 +222,7 @@ struct smiapp_sensor {
struct gpio_desc *xshutdown;
void *ccs_limits;
u8 nbinning_subtypes;
- struct smiapp_binning_subtype binning_subtypes[SMIAPP_BINNING_SUBTYPES];
+ struct smiapp_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1];
u32 mbus_frame_fmts;
const struct smiapp_csi_data_format *csi_format;
const struct smiapp_csi_data_format *internal_csi_format;
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 15/29] smiapp: Remove quirk function for writing a single 8-bit register
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (13 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 14/29] smiapp: Use CCS registers Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 16/29] smiapp: Rename register access functions Sakari Ailus
` (13 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
This function is no longer needed as the smiapp_write() function can be
used to write 8-bit registers with plain register addresses.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-quirk.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/smiapp-quirk.c
index 24630c7650d2..9422eb61b424 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.c
+++ b/drivers/media/i2c/smiapp/smiapp-quirk.c
@@ -14,11 +14,6 @@
#include "smiapp.h"
-static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val)
-{
- return smiapp_write(sensor, reg, val);
-}
-
static int smiapp_write_8s(struct smiapp_sensor *sensor,
const struct smiapp_reg_8 *regs, int len)
{
@@ -26,7 +21,7 @@ static int smiapp_write_8s(struct smiapp_sensor *sensor,
int rval;
for (; len > 0; len--, regs++) {
- rval = smiapp_write_8(sensor, regs->reg, regs->val);
+ rval = smiapp_write(sensor, regs->reg, regs->val);
if (rval < 0) {
dev_err(&client->dev,
"error %d writing reg 0x%4.4x, val 0x%2.2x",
@@ -170,7 +165,7 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
static int jt8ev1_pre_streamon(struct smiapp_sensor *sensor)
{
- return smiapp_write_8(sensor, 0x3328, 0x00);
+ return smiapp_write(sensor, 0x3328, 0x00);
}
static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
@@ -178,7 +173,7 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
int rval;
/* Workaround: allows fast standby to work properly */
- rval = smiapp_write_8(sensor, 0x3205, 0x04);
+ rval = smiapp_write(sensor, 0x3205, 0x04);
if (rval < 0)
return rval;
@@ -186,11 +181,11 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
usleep_range(2000, 2050);
/* Restore it */
- rval = smiapp_write_8(sensor, 0x3205, 0x00);
+ rval = smiapp_write(sensor, 0x3205, 0x00);
if (rval < 0)
return rval;
- return smiapp_write_8(sensor, 0x3328, 0x80);
+ return smiapp_write(sensor, 0x3328, 0x80);
}
static int jt8ev1_init(struct smiapp_sensor *sensor)
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 16/29] smiapp: Rename register access functions
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (14 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 15/29] smiapp: Remove quirk function for writing a single 8-bit register Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 17/29] smiapp: Internal rename to CCS Sakari Ailus
` (12 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Rename register access functions by changing smiapp to ccs.
The functions operating on register addresses have "addr" appended to the
name.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/smiapp-core.c | 67 +++++++++++++------------
drivers/media/i2c/smiapp/smiapp-quirk.c | 22 ++++----
drivers/media/i2c/smiapp/smiapp-regs.c | 47 ++++++++---------
drivers/media/i2c/smiapp/smiapp-regs.h | 14 +++---
4 files changed, 76 insertions(+), 74 deletions(-)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index 382a2d14f0f4..b12e41a6a410 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -180,7 +180,7 @@ static int ccs_read_all_limits(struct smiapp_sensor *sensor)
j++, reg += width, ptr += width) {
u32 val;
- ret = smiapp_read(sensor, reg, &val);
+ ret = ccs_read_addr(sensor, reg, &val);
if (ret)
goto out_err;
@@ -2450,59 +2450,60 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
rval = ccs_read(sensor, MODULE_MANUFACTURER_ID,
&minfo->mipi_manufacturer_id);
if (!rval && !minfo->mipi_manufacturer_id)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID,
- &minfo->smia_manufacturer_id);
+ rval = ccs_read_addr_8only(sensor,
+ SMIAPP_REG_U8_MANUFACTURER_ID,
+ &minfo->smia_manufacturer_id);
if (!rval)
- rval = smiapp_read_8only(sensor, CCS_R_MODULE_MODEL_ID,
- &minfo->model_id);
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_MODEL_ID,
+ &minfo->model_id);
if (!rval)
- rval = smiapp_read_8only(sensor,
- CCS_R_MODULE_REVISION_NUMBER_MAJOR,
- &minfo->revision_number_major);
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_MODULE_REVISION_NUMBER_MAJOR,
+ &minfo->revision_number_major);
if (!rval)
- rval = smiapp_read_8only(sensor,
- CCS_R_MODULE_REVISION_NUMBER_MINOR,
- &minfo->revision_number_minor);
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_MODULE_REVISION_NUMBER_MINOR,
+ &minfo->revision_number_minor);
if (!rval)
- rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_YEAR,
- &minfo->module_year);
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_YEAR,
+ &minfo->module_year);
if (!rval)
- rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_MONTH,
- &minfo->module_month);
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_MONTH,
+ &minfo->module_month);
if (!rval)
- rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_DAY,
- &minfo->module_day);
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_DAY,
+ &minfo->module_day);
/* Sensor info */
if (!rval)
rval = ccs_read(sensor, SENSOR_MANUFACTURER_ID,
&minfo->sensor_mipi_manufacturer_id);
if (!rval && !minfo->sensor_mipi_manufacturer_id)
- rval = smiapp_read_8only(sensor,
- CCS_R_SENSOR_MANUFACTURER_ID,
- &minfo->sensor_smia_manufacturer_id);
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_MANUFACTURER_ID,
+ &minfo->sensor_smia_manufacturer_id);
if (!rval)
- rval = smiapp_read_8only(sensor,
- CCS_R_SENSOR_MODEL_ID,
- &minfo->sensor_model_id);
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_MODEL_ID,
+ &minfo->sensor_model_id);
if (!rval)
- rval = smiapp_read_8only(sensor,
- CCS_R_SENSOR_REVISION_NUMBER,
- &minfo->sensor_revision_number);
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_REVISION_NUMBER,
+ &minfo->sensor_revision_number);
if (!rval)
- rval = smiapp_read_8only(sensor,
- CCS_R_SENSOR_FIRMWARE_VERSION,
- &minfo->sensor_firmware_version);
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_FIRMWARE_VERSION,
+ &minfo->sensor_firmware_version);
/* SMIA */
if (!rval)
rval = ccs_read(sensor, MIPI_CCS_VERSION, &minfo->ccs_version);
if (!rval && !minfo->ccs_version)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION,
- &minfo->smia_version);
+ rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION,
+ &minfo->smia_version);
if (!rval && !minfo->ccs_version)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION,
- &minfo->smiapp_version);
+ rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION,
+ &minfo->smiapp_version);
if (rval) {
dev_err(&client->dev, "sensor detection failed\n");
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/smiapp-quirk.c
index 9422eb61b424..5db97a16eccf 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.c
+++ b/drivers/media/i2c/smiapp/smiapp-quirk.c
@@ -14,14 +14,14 @@
#include "smiapp.h"
-static int smiapp_write_8s(struct smiapp_sensor *sensor,
- const struct smiapp_reg_8 *regs, int len)
+static int ccs_write_addr_8s(struct smiapp_sensor *sensor,
+ const struct smiapp_reg_8 *regs, int len)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
for (; len > 0; len--, regs++) {
- rval = smiapp_write(sensor, regs->reg, regs->val);
+ rval = ccs_write_addr(sensor, regs->reg, regs->val);
if (rval < 0) {
dev_err(&client->dev,
"error %d writing reg 0x%4.4x, val 0x%2.2x",
@@ -81,7 +81,7 @@ static int jt8ew9_post_poweron(struct smiapp_sensor *sensor)
};
- return smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
+ return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
}
const struct smiapp_quirk smiapp_jt8ew9_quirk = {
@@ -102,7 +102,7 @@ static int imx125es_post_poweron(struct smiapp_sensor *sensor)
{ 0x3b08, 0x8c },
};
- return smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
+ return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
}
const struct smiapp_quirk smiapp_imx125es_quirk = {
@@ -148,13 +148,13 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
{ 0x30b0, 0x01 },
};
- rval = smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
+ rval = ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
if (rval < 0)
return rval;
switch (sensor->hwcfg->ext_clk) {
case 9600000:
- return smiapp_write_8s(sensor, regs_96,
+ return ccs_write_addr_8s(sensor, regs_96,
ARRAY_SIZE(regs_96));
default:
dev_warn(&client->dev, "no MSRs for %d Hz ext_clk\n",
@@ -165,7 +165,7 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
static int jt8ev1_pre_streamon(struct smiapp_sensor *sensor)
{
- return smiapp_write(sensor, 0x3328, 0x00);
+ return ccs_write_addr(sensor, 0x3328, 0x00);
}
static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
@@ -173,7 +173,7 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
int rval;
/* Workaround: allows fast standby to work properly */
- rval = smiapp_write(sensor, 0x3205, 0x04);
+ rval = ccs_write_addr(sensor, 0x3205, 0x04);
if (rval < 0)
return rval;
@@ -181,11 +181,11 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
usleep_range(2000, 2050);
/* Restore it */
- rval = smiapp_write(sensor, 0x3205, 0x00);
+ rval = ccs_write_addr(sensor, 0x3205, 0x00);
if (rval < 0)
return rval;
- return smiapp_write(sensor, 0x3328, 0x80);
+ return ccs_write_addr(sensor, 0x3328, 0x80);
}
static int jt8ev1_init(struct smiapp_sensor *sensor)
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.c b/drivers/media/i2c/smiapp/smiapp-regs.c
index 904054d303ba..173d9f8fe56c 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.c
+++ b/drivers/media/i2c/smiapp/smiapp-regs.c
@@ -66,8 +66,8 @@ static uint32_t float_to_u32_mul_1000000(struct i2c_client *client,
* Read a 8/16/32-bit i2c register. The value is returned in 'val'.
* Returns zero if successful, or non-zero otherwise.
*/
-static int ____smiapp_read(struct smiapp_sensor *sensor, u16 reg,
- u16 len, u32 *val)
+static int ____ccs_read_addr(struct smiapp_sensor *sensor, u16 reg, u16 len,
+ u32 *val)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct i2c_msg msg;
@@ -113,8 +113,8 @@ static int ____smiapp_read(struct smiapp_sensor *sensor, u16 reg,
}
/* Read a register using 8-bit access only. */
-static int ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg,
- u16 len, u32 *val)
+static int ____ccs_read_addr_8only(struct smiapp_sensor *sensor, u16 reg,
+ u16 len, u32 *val)
{
unsigned int i;
int rval;
@@ -124,7 +124,7 @@ static int ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg,
for (i = 0; i < len; i++) {
u32 val8;
- rval = ____smiapp_read(sensor, reg + i, 1, &val8);
+ rval = ____ccs_read_addr(sensor, reg + i, 1, &val8);
if (rval < 0)
return rval;
*val |= val8 << ((len - i - 1) << 3);
@@ -147,18 +147,19 @@ unsigned int ccs_reg_width(u32 reg)
* Read a 8/16/32-bit i2c register. The value is returned in 'val'.
* Returns zero if successful, or non-zero otherwise.
*/
-static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val,
- bool only8)
+static int __ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val,
+ bool only8)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
unsigned int len = ccs_reg_width(reg);
int rval;
if (!only8)
- rval = ____smiapp_read(sensor, SMIAPP_REG_ADDR(reg), len, val);
+ rval = ____ccs_read_addr(sensor, SMIAPP_REG_ADDR(reg), len,
+ val);
else
- rval = ____smiapp_read_8only(sensor, SMIAPP_REG_ADDR(reg), len,
- val);
+ rval = ____ccs_read_addr_8only(sensor, SMIAPP_REG_ADDR(reg),
+ len, val);
if (rval < 0)
return rval;
@@ -168,16 +169,16 @@ static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val,
return 0;
}
-int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val)
+int ccs_read_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val)
{
- return __smiapp_read(
+ return __ccs_read_addr(
sensor, reg, val,
smiapp_needs_quirk(sensor,
SMIAPP_QUIRK_FLAG_8BIT_READ_ONLY));
}
-static int smiapp_read_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val,
- bool force8)
+static int ccs_read_addr_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val,
+ bool force8)
{
int rval;
@@ -189,22 +190,22 @@ static int smiapp_read_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val,
return rval;
if (force8)
- return __smiapp_read(sensor, reg, val, true);
+ return __ccs_read_addr(sensor, reg, val, true);
- return smiapp_read_no_quirk(sensor, reg, val);
+ return ccs_read_addr_no_quirk(sensor, reg, val);
}
-int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val)
+int ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val)
{
- return smiapp_read_quirk(sensor, reg, val, false);
+ return ccs_read_addr_quirk(sensor, reg, val, false);
}
-int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val)
+int ccs_read_addr_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val)
{
- return smiapp_read_quirk(sensor, reg, val, true);
+ return ccs_read_addr_quirk(sensor, reg, val, true);
}
-int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
+int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct i2c_msg msg;
@@ -253,7 +254,7 @@ int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
* Write to a 8/16-bit register.
* Returns zero if successful, or non-zero otherwise.
*/
-int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val)
+int ccs_write_addr(struct smiapp_sensor *sensor, u32 reg, u32 val)
{
int rval;
@@ -263,5 +264,5 @@ int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val)
if (rval < 0)
return rval;
- return smiapp_write_no_quirk(sensor, reg, val);
+ return ccs_write_addr_no_quirk(sensor, reg, val);
}
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/smiapp-regs.h
index dc946096f368..5df794f65dfc 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.h
+++ b/drivers/media/i2c/smiapp/smiapp-regs.h
@@ -20,18 +20,18 @@
struct smiapp_sensor;
-int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val);
-int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val);
+int ccs_read_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val);
+int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val);
+int ccs_write_addr(struct smiapp_sensor *sensor, u32 reg, u32 val);
unsigned int ccs_reg_width(u32 reg);
#define ccs_read(sensor, reg_name, val) \
- smiapp_read(sensor, CCS_R_##reg_name, val)
+ ccs_read_addr(sensor, CCS_R_##reg_name, val)
#define ccs_write(sensor, reg_name, val) \
- smiapp_write(sensor, CCS_R_##reg_name, val)
+ ccs_write_addr(sensor, CCS_R_##reg_name, val)
#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 17/29] smiapp: Internal rename to CCS
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (15 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 16/29] smiapp: Rename register access functions Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 18/29] smiapp: Differentiate CCS sensors from SMIA in subdev naming Sakari Ailus
` (11 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Rename internal names to reflect the driver's new reference. The module
name remains the same.
Also fix trivial coding style issues on the way related to e.g. alignment
changes due to the rename.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/Makefile | 4 +-
.../i2c/smiapp/{smiapp-core.c => ccs-core.c} | 888 +++++++++---------
.../smiapp/{smiapp-quirk.c => ccs-quirk.c} | 43 +-
.../smiapp/{smiapp-quirk.h => ccs-quirk.h} | 46 +-
.../{smiapp-regs.c => ccs-reg-access.c} | 41 +-
.../{smiapp-regs.h => ccs-reg-access.h} | 16 +-
drivers/media/i2c/smiapp/{smiapp.h => ccs.h} | 124 +--
7 files changed, 576 insertions(+), 586 deletions(-)
rename drivers/media/i2c/smiapp/{smiapp-core.c => ccs-core.c} (75%)
rename drivers/media/i2c/smiapp/{smiapp-quirk.c => ccs-quirk.c} (83%)
rename drivers/media/i2c/smiapp/{smiapp-quirk.h => ccs-quirk.h} (59%)
rename drivers/media/i2c/smiapp/{smiapp-regs.c => ccs-reg-access.c} (79%)
rename drivers/media/i2c/smiapp/{smiapp-regs.h => ccs-reg-access.h} (55%)
rename drivers/media/i2c/smiapp/{smiapp.h => ccs.h} (65%)
diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/smiapp/Makefile
index a7bf53dd4a63..c9d300b5d2bc 100644
--- a/drivers/media/i2c/smiapp/Makefile
+++ b/drivers/media/i2c/smiapp/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-smiapp-objs += smiapp-core.o smiapp-regs.o \
- smiapp-quirk.o ccs-limits.o
+smiapp-objs += ccs-core.o ccs-reg-access.o \
+ ccs-quirk.o ccs-limits.o
obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o
ccflags-y += -I $(srctree)/drivers/media/i2c
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/ccs-core.c
similarity index 75%
rename from drivers/media/i2c/smiapp/smiapp-core.c
rename to drivers/media/i2c/smiapp/ccs-core.c
index b12e41a6a410..f9dbf1407a33 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/ccs-core.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp/smiapp-core.c
+ * drivers/media/i2c/smiapp/ccs-core.c
*
* Generic driver for SMIA/SMIA++ compliant camera modules
*
@@ -27,10 +27,10 @@
#include <media/v4l2-fwnode.h>
#include <media/v4l2-device.h>
+#include "ccs.h"
#include "ccs-limits.h"
-#include "smiapp.h"
-#define SMIAPP_ALIGN_DIM(dim, flags) \
+#define CCS_ALIGN_DIM(dim, flags) \
((flags) & V4L2_SEL_FLAG_GE \
? ALIGN((dim), 2) \
: (dim) & ~1)
@@ -41,20 +41,20 @@ static struct ccs_limit_offset {
} ccs_limit_offsets[CCS_L_LAST + 1];
/*
- * smiapp_module_idents - supported camera modules
+ * ccs_module_idents - supported camera modules
*/
-static const struct smiapp_module_ident smiapp_module_idents[] = {
- SMIAPP_IDENT_L(0x01, 0x022b, -1, "vs6555"),
- SMIAPP_IDENT_L(0x01, 0x022e, -1, "vw6558"),
- SMIAPP_IDENT_L(0x07, 0x7698, -1, "ovm7698"),
- SMIAPP_IDENT_L(0x0b, 0x4242, -1, "smiapp-003"),
- SMIAPP_IDENT_L(0x0c, 0x208a, -1, "tcm8330md"),
- SMIAPP_IDENT_LQ(0x0c, 0x2134, -1, "tcm8500md", &smiapp_tcm8500md_quirk),
- SMIAPP_IDENT_L(0x0c, 0x213e, -1, "et8en2"),
- SMIAPP_IDENT_L(0x0c, 0x2184, -1, "tcm8580md"),
- SMIAPP_IDENT_LQ(0x0c, 0x560f, -1, "jt8ew9", &smiapp_jt8ew9_quirk),
- SMIAPP_IDENT_LQ(0x10, 0x4141, -1, "jt8ev1", &smiapp_jt8ev1_quirk),
- SMIAPP_IDENT_LQ(0x10, 0x4241, -1, "imx125es", &smiapp_imx125es_quirk),
+static const struct ccs_module_ident ccs_module_idents[] = {
+ CCS_IDENT_L(0x01, 0x022b, -1, "vs6555"),
+ CCS_IDENT_L(0x01, 0x022e, -1, "vw6558"),
+ CCS_IDENT_L(0x07, 0x7698, -1, "ovm7698"),
+ CCS_IDENT_L(0x0b, 0x4242, -1, "smiapp-003"),
+ CCS_IDENT_L(0x0c, 0x208a, -1, "tcm8330md"),
+ CCS_IDENT_LQ(0x0c, 0x2134, -1, "tcm8500md", &smiapp_tcm8500md_quirk),
+ CCS_IDENT_L(0x0c, 0x213e, -1, "et8en2"),
+ CCS_IDENT_L(0x0c, 0x2184, -1, "tcm8580md"),
+ CCS_IDENT_LQ(0x0c, 0x560f, -1, "jt8ew9", &smiapp_jt8ew9_quirk),
+ CCS_IDENT_LQ(0x10, 0x4141, -1, "jt8ev1", &smiapp_jt8ev1_quirk),
+ CCS_IDENT_LQ(0x10, 0x4241, -1, "imx125es", &smiapp_imx125es_quirk),
};
/*
@@ -78,7 +78,7 @@ static void ccs_assign_limit(void *ptr, unsigned int width, u32 val)
}
}
-static int ccs_limit_ptr(struct smiapp_sensor *sensor, unsigned int limit,
+static int ccs_limit_ptr(struct ccs_sensor *sensor, unsigned int limit,
unsigned int offset, void **__ptr)
{
const struct ccs_limit *linfo;
@@ -98,7 +98,7 @@ static int ccs_limit_ptr(struct smiapp_sensor *sensor, unsigned int limit,
return 0;
}
-void ccs_replace_limit(struct smiapp_sensor *sensor,
+void ccs_replace_limit(struct ccs_sensor *sensor,
unsigned int limit, unsigned int offset, u32 val)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
@@ -118,7 +118,7 @@ void ccs_replace_limit(struct smiapp_sensor *sensor,
ccs_assign_limit(ptr, ccs_reg_width(linfo->reg), val);
}
-static u32 ccs_get_limit(struct smiapp_sensor *sensor,
+static u32 ccs_get_limit(struct ccs_sensor *sensor,
unsigned int limit, unsigned int offset)
{
void *ptr;
@@ -148,7 +148,7 @@ static u32 ccs_get_limit(struct smiapp_sensor *sensor,
#define CCS_LIM_AT(sensor, limit, offset) \
ccs_get_limit(sensor, CCS_L_##limit, CCS_L_##limit##_OFFSET(offset))
-static int ccs_read_all_limits(struct smiapp_sensor *sensor)
+static int ccs_read_all_limits(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
void *ptr, *alloc, *end;
@@ -224,7 +224,7 @@ static int ccs_read_all_limits(struct smiapp_sensor *sensor)
return ret;
}
-static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
+static int ccs_read_frame_fmt(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
u8 fmt_model_type, fmt_model_subtype, ncol_desc, nrow_desc;
@@ -351,7 +351,7 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
return 0;
}
-static int smiapp_pll_configure(struct smiapp_sensor *sensor)
+static int ccs_pll_configure(struct ccs_sensor *sensor)
{
struct smiapp_pll *pll = &sensor->pll;
int rval;
@@ -386,8 +386,7 @@ static int smiapp_pll_configure(struct smiapp_sensor *sensor)
return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op.sys_clk_div);
}
-static int smiapp_pll_try(struct smiapp_sensor *sensor,
- struct smiapp_pll *pll)
+static int ccs_pll_try(struct ccs_sensor *sensor, struct smiapp_pll *pll)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct smiapp_pll_limits lim = {
@@ -425,7 +424,7 @@ static int smiapp_pll_try(struct smiapp_sensor *sensor,
return smiapp_pll_calculate(&client->dev, &lim, pll);
}
-static int smiapp_pll_update(struct smiapp_sensor *sensor)
+static int ccs_pll_update(struct ccs_sensor *sensor)
{
struct smiapp_pll *pll = &sensor->pll;
int rval;
@@ -437,7 +436,7 @@ static int smiapp_pll_update(struct smiapp_sensor *sensor)
pll->scale_m = sensor->scale_m;
pll->bits_per_pixel = sensor->csi_format->compressed;
- rval = smiapp_pll_try(sensor, pll);
+ rval = ccs_pll_try(sensor, pll);
if (rval < 0)
return rval;
@@ -455,12 +454,12 @@ static int smiapp_pll_update(struct smiapp_sensor *sensor)
*
*/
-static void __smiapp_update_exposure_limits(struct smiapp_sensor *sensor)
+static void __ccs_update_exposure_limits(struct ccs_sensor *sensor)
{
struct v4l2_ctrl *ctrl = sensor->exposure;
int max;
- max = sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height
+ max = sensor->pixel_array->crop[CCS_PA_PAD_SRC].height
+ sensor->vblank->val
- CCS_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN);
@@ -475,40 +474,40 @@ static void __smiapp_update_exposure_limits(struct smiapp_sensor *sensor)
* 3. Pixel order, same as in pixel_order_str. Formats for all four pixel
* orders must be defined.
*/
-static const struct smiapp_csi_data_format smiapp_csi_data_formats[] = {
- { MEDIA_BUS_FMT_SGRBG16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_GBRG, },
+static const struct ccs_csi_data_format ccs_csi_data_formats[] = {
+ { MEDIA_BUS_FMT_SGRBG16_1X16, 16, 16, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB16_1X16, 16, 16, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR16_1X16, 16, 16, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG16_1X16, 16, 16, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG14_1X14, 14, 14, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB14_1X14, 14, 14, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR14_1X14, 14, 14, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG14_1X14, 14, 14, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG12_1X12, 12, 12, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB12_1X12, 12, 12, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR12_1X12, 12, 12, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG12_1X12, 12, 12, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG10_1X10, 10, 10, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB10_1X10, 10, 10, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR10_1X10, 10, 10, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG10_1X10, 10, 10, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG8_1X8, 8, 8, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB8_1X8, 8, 8, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR8_1X8, 8, 8, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG8_1X8, 8, 8, CCS_PIXEL_ORDER_GBRG, },
};
static const char *pixel_order_str[] = { "GRBG", "RGGB", "BGGR", "GBRG" };
#define to_csi_format_idx(fmt) (((unsigned long)(fmt) \
- - (unsigned long)smiapp_csi_data_formats) \
- / sizeof(*smiapp_csi_data_formats))
+ - (unsigned long)ccs_csi_data_formats) \
+ / sizeof(*ccs_csi_data_formats))
-static u32 smiapp_pixel_order(struct smiapp_sensor *sensor)
+static u32 ccs_pixel_order(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int flip = 0;
@@ -527,31 +526,31 @@ static u32 smiapp_pixel_order(struct smiapp_sensor *sensor)
return sensor->default_pixel_order ^ flip;
}
-static void smiapp_update_mbus_formats(struct smiapp_sensor *sensor)
+static void ccs_update_mbus_formats(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
unsigned int csi_format_idx =
to_csi_format_idx(sensor->csi_format) & ~3;
unsigned int internal_csi_format_idx =
to_csi_format_idx(sensor->internal_csi_format) & ~3;
- unsigned int pixel_order = smiapp_pixel_order(sensor);
+ unsigned int pixel_order = ccs_pixel_order(sensor);
sensor->mbus_frame_fmts =
sensor->default_mbus_frame_fmts << pixel_order;
sensor->csi_format =
- &smiapp_csi_data_formats[csi_format_idx + pixel_order];
+ &ccs_csi_data_formats[csi_format_idx + pixel_order];
sensor->internal_csi_format =
- &smiapp_csi_data_formats[internal_csi_format_idx
+ &ccs_csi_data_formats[internal_csi_format_idx
+ pixel_order];
BUG_ON(max(internal_csi_format_idx, csi_format_idx) + pixel_order
- >= ARRAY_SIZE(smiapp_csi_data_formats));
+ >= ARRAY_SIZE(ccs_csi_data_formats));
dev_dbg(&client->dev, "new pixel order %s\n",
pixel_order_str[pixel_order]);
}
-static const char * const smiapp_test_patterns[] = {
+static const char * const ccs_test_patterns[] = {
"Disabled",
"Solid Colour",
"Eight Vertical Colour Bars",
@@ -559,10 +558,10 @@ static const char * const smiapp_test_patterns[] = {
"Pseudorandom Sequence (PN9)",
};
-static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
+static int ccs_set_ctrl(struct v4l2_ctrl *ctrl)
{
- struct smiapp_sensor *sensor =
- container_of(ctrl->handler, struct smiapp_subdev, ctrl_handler)
+ struct ccs_sensor *sensor =
+ container_of(ctrl->handler, struct ccs_subdev, ctrl_handler)
->sensor;
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int pm_status;
@@ -585,17 +584,17 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
orient ^= sensor->hvflip_inv_mask;
- smiapp_update_mbus_formats(sensor);
+ ccs_update_mbus_formats(sensor);
break;
case V4L2_CID_VBLANK:
exposure = sensor->exposure->val;
- __smiapp_update_exposure_limits(sensor);
+ __ccs_update_exposure_limits(sensor);
if (exposure > sensor->exposure->maximum) {
sensor->exposure->val = sensor->exposure->maximum;
- rval = smiapp_set_ctrl(sensor->exposure);
+ rval = ccs_set_ctrl(sensor->exposure);
if (rval < 0)
return rval;
}
@@ -605,7 +604,7 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
if (sensor->streaming)
return -EBUSY;
- rval = smiapp_pll_update(sensor);
+ rval = ccs_pll_update(sensor);
if (rval)
return rval;
@@ -641,14 +640,14 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
case V4L2_CID_VBLANK:
rval = ccs_write(sensor, FRAME_LENGTH_LINES,
sensor->pixel_array->crop[
- SMIAPP_PA_PAD_SRC].height
+ CCS_PA_PAD_SRC].height
+ ctrl->val);
break;
case V4L2_CID_HBLANK:
rval = ccs_write(sensor, LINE_LENGTH_PCK,
sensor->pixel_array->crop[
- SMIAPP_PA_PAD_SRC].width
+ CCS_PA_PAD_SRC].width
+ ctrl->val);
break;
@@ -689,11 +688,11 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
return rval;
}
-static const struct v4l2_ctrl_ops smiapp_ctrl_ops = {
- .s_ctrl = smiapp_set_ctrl,
+static const struct v4l2_ctrl_ops ccs_ctrl_ops = {
+ .s_ctrl = ccs_set_ctrl,
};
-static int smiapp_init_controls(struct smiapp_sensor *sensor)
+static int ccs_init_controls(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -705,7 +704,7 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor)
sensor->pixel_array->ctrl_handler.lock = &sensor->mutex;
sensor->analog_gain = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_ANALOGUE_GAIN,
CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX),
@@ -714,38 +713,38 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor)
/* Exposure limits will be updated soon, use just something here. */
sensor->exposure = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_EXPOSURE, 0, 0, 1, 0);
sensor->hflip = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_HFLIP, 0, 1, 1, 0);
sensor->vflip = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_VFLIP, 0, 1, 1, 0);
sensor->vblank = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_VBLANK, 0, 1, 1, 0);
if (sensor->vblank)
sensor->vblank->flags |= V4L2_CTRL_FLAG_UPDATE;
sensor->hblank = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_HBLANK, 0, 1, 1, 0);
if (sensor->hblank)
sensor->hblank->flags |= V4L2_CTRL_FLAG_UPDATE;
sensor->pixel_rate_parray = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
v4l2_ctrl_new_std_menu_items(&sensor->pixel_array->ctrl_handler,
- &smiapp_ctrl_ops, V4L2_CID_TEST_PATTERN,
- ARRAY_SIZE(smiapp_test_patterns) - 1,
- 0, 0, smiapp_test_patterns);
+ &ccs_ctrl_ops, V4L2_CID_TEST_PATTERN,
+ ARRAY_SIZE(ccs_test_patterns) - 1,
+ 0, 0, ccs_test_patterns);
if (sensor->pixel_array->ctrl_handler.error) {
dev_err(&client->dev,
@@ -766,7 +765,7 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor)
sensor->src->ctrl_handler.lock = &sensor->mutex;
sensor->pixel_rate_csi = v4l2_ctrl_new_std(
- &sensor->src->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->src->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
if (sensor->src->ctrl_handler.error) {
@@ -785,7 +784,7 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor)
* For controls that require information on available media bus codes
* and linke frequencies.
*/
-static int smiapp_init_late_controls(struct smiapp_sensor *sensor)
+static int ccs_init_late_controls(struct ccs_sensor *sensor)
{
unsigned long *valid_link_freqs = &sensor->valid_link_freqs[
sensor->csi_format->compressed - sensor->compressed_min_bpp];
@@ -796,19 +795,19 @@ static int smiapp_init_late_controls(struct smiapp_sensor *sensor)
sensor->test_data[i] = v4l2_ctrl_new_std(
&sensor->pixel_array->ctrl_handler,
- &smiapp_ctrl_ops, V4L2_CID_TEST_PATTERN_RED + i,
+ &ccs_ctrl_ops, V4L2_CID_TEST_PATTERN_RED + i,
0, max_value, 1, max_value);
}
sensor->link_freq = v4l2_ctrl_new_int_menu(
- &sensor->src->ctrl_handler, &smiapp_ctrl_ops,
+ &sensor->src->ctrl_handler, &ccs_ctrl_ops,
V4L2_CID_LINK_FREQ, __fls(*valid_link_freqs),
__ffs(*valid_link_freqs), sensor->hwcfg->op_sys_clock);
return sensor->src->ctrl_handler.error;
}
-static void smiapp_free_controls(struct smiapp_sensor *sensor)
+static void ccs_free_controls(struct ccs_sensor *sensor)
{
unsigned int i;
@@ -816,7 +815,7 @@ static void smiapp_free_controls(struct smiapp_sensor *sensor)
v4l2_ctrl_handler_free(&sensor->ssds[i].ctrl_handler);
}
-static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
+static int ccs_get_mbus_formats(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct smiapp_pll *pll = &sensor->pll;
@@ -863,11 +862,11 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
dev_dbg(&client->dev, "%u: bpp %u, compressed %u\n",
i, fmt >> 8, (u8)fmt);
- for (j = 0; j < ARRAY_SIZE(smiapp_csi_data_formats); j++) {
- const struct smiapp_csi_data_format *f =
- &smiapp_csi_data_formats[j];
+ for (j = 0; j < ARRAY_SIZE(ccs_csi_data_formats); j++) {
+ const struct ccs_csi_data_format *f =
+ &ccs_csi_data_formats[j];
- if (f->pixel_order != SMIAPP_PIXEL_ORDER_GRBG)
+ if (f->pixel_order != CCS_PIXEL_ORDER_GRBG)
continue;
if (f->width != fmt >>
@@ -887,12 +886,12 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
pll->binning_vertical = 1;
pll->scale_m = sensor->scale_m;
- for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) {
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
sensor->compressed_min_bpp =
- min(smiapp_csi_data_formats[i].compressed,
+ min(ccs_csi_data_formats[i].compressed,
sensor->compressed_min_bpp);
compressed_max_bpp =
- max(smiapp_csi_data_formats[i].compressed,
+ max(ccs_csi_data_formats[i].compressed,
compressed_max_bpp);
}
@@ -903,9 +902,9 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
if (!sensor->valid_link_freqs)
return -ENOMEM;
- for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) {
- const struct smiapp_csi_data_format *f =
- &smiapp_csi_data_formats[i];
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
+ const struct ccs_csi_data_format *f =
+ &ccs_csi_data_formats[i];
unsigned long *valid_link_freqs =
&sensor->valid_link_freqs[
f->compressed - sensor->compressed_min_bpp];
@@ -919,7 +918,7 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
for (j = 0; sensor->hwcfg->op_sys_clock[j]; j++) {
pll->link_freq = sensor->hwcfg->op_sys_clock[j];
- rval = smiapp_pll_try(sensor, pll);
+ rval = ccs_pll_try(sensor, pll);
dev_dbg(&client->dev, "link freq %u Hz, bpp %u %s\n",
pll->link_freq, pll->bits_per_pixel,
rval ? "not ok" : "ok");
@@ -951,12 +950,12 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
return -EINVAL;
}
- smiapp_update_mbus_formats(sensor);
+ ccs_update_mbus_formats(sensor);
return 0;
}
-static void smiapp_update_blanking(struct smiapp_sensor *sensor)
+static void ccs_update_blanking(struct ccs_sensor *sensor)
{
struct v4l2_ctrl *vblank = sensor->vblank;
struct v4l2_ctrl *hblank = sensor->hblank;
@@ -980,42 +979,42 @@ static void smiapp_update_blanking(struct smiapp_sensor *sensor)
min = max_t(int,
CCS_LIM(sensor, MIN_FRAME_BLANKING_LINES),
min_fll -
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height);
- max = max_fll - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height;
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].height);
+ max = max_fll - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height;
__v4l2_ctrl_modify_range(vblank, min, max, vblank->step, min);
min = max_t(int,
min_llp -
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width,
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].width,
min_lbp);
- max = max_llp - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width;
+ max = max_llp - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width;
__v4l2_ctrl_modify_range(hblank, min, max, hblank->step, min);
- __smiapp_update_exposure_limits(sensor);
+ __ccs_update_exposure_limits(sensor);
}
-static int smiapp_pll_blanking_update(struct smiapp_sensor *sensor)
+static int ccs_pll_blanking_update(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
- rval = smiapp_pll_update(sensor);
+ rval = ccs_pll_update(sensor);
if (rval < 0)
return rval;
/* Output from pixel array, including blanking */
- smiapp_update_blanking(sensor);
+ ccs_update_blanking(sensor);
dev_dbg(&client->dev, "vblank\t\t%d\n", sensor->vblank->val);
dev_dbg(&client->dev, "hblank\t\t%d\n", sensor->hblank->val);
dev_dbg(&client->dev, "real timeperframe\t100/%d\n",
sensor->pll.pixel_rate_pixel_array /
- ((sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width
+ ((sensor->pixel_array->crop[CCS_PA_PAD_SRC].width
+ sensor->hblank->val) *
- (sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height
+ (sensor->pixel_array->crop[CCS_PA_PAD_SRC].height
+ sensor->vblank->val) / 100));
return 0;
@@ -1027,8 +1026,8 @@ static int smiapp_pll_blanking_update(struct smiapp_sensor *sensor)
*
*/
-static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
- u8 *status)
+static int ccs_read_nvm_page(struct ccs_sensor *sensor, u32 p, u8 *nvm,
+ u8 *status)
{
unsigned int i;
int rval;
@@ -1082,8 +1081,8 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
return 0;
}
-static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm,
- size_t nvm_size)
+static int ccs_read_nvm(struct ccs_sensor *sensor, unsigned char *nvm,
+ size_t nvm_size)
{
u8 status = 0;
u32 p;
@@ -1091,7 +1090,7 @@ static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm,
for (p = 0; p < nvm_size / (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1)
&& !rval; p++) {
- rval = smiapp_read_nvm_page(sensor, p, nvm, &status);
+ rval = ccs_read_nvm_page(sensor, p, nvm, &status);
nvm += CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1;
}
@@ -1111,7 +1110,7 @@ static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm,
* SMIA++ CCI address control
*
*/
-static int smiapp_change_cci_addr(struct smiapp_sensor *sensor)
+static int ccs_change_cci_addr(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -1142,9 +1141,9 @@ static int smiapp_change_cci_addr(struct smiapp_sensor *sensor)
* SMIA++ Mode Control
*
*/
-static int smiapp_setup_flash_strobe(struct smiapp_sensor *sensor)
+static int ccs_setup_flash_strobe(struct ccs_sensor *sensor)
{
- struct smiapp_flash_strobe_parms *strobe_setup;
+ struct ccs_flash_strobe_parms *strobe_setup;
unsigned int ext_freq = sensor->hwcfg->ext_clk;
u32 tmp;
u32 strobe_adjustment;
@@ -1268,16 +1267,16 @@ static int smiapp_setup_flash_strobe(struct smiapp_sensor *sensor)
* Power management
*/
-static int smiapp_power_on(struct device *dev)
+static int ccs_power_on(struct device *dev)
{
struct v4l2_subdev *subdev = dev_get_drvdata(dev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
/*
* The sub-device related to the I2C device is always the
* source one, i.e. ssds[0].
*/
- struct smiapp_sensor *sensor =
- container_of(ssd, struct smiapp_sensor, ssds[0]);
+ struct ccs_sensor *sensor =
+ container_of(ssd, struct ccs_sensor, ssds[0]);
unsigned int sleep;
int rval;
@@ -1312,7 +1311,7 @@ static int smiapp_power_on(struct device *dev)
*/
if (sensor->hwcfg->i2c_addr_alt) {
- rval = smiapp_change_cci_addr(sensor);
+ rval = ccs_change_cci_addr(sensor);
if (rval) {
dev_err(dev, "cci address change error\n");
goto out_cci_addr_fail;
@@ -1326,7 +1325,7 @@ static int smiapp_power_on(struct device *dev)
}
if (sensor->hwcfg->i2c_addr_alt) {
- rval = smiapp_change_cci_addr(sensor);
+ rval = ccs_change_cci_addr(sensor);
if (rval) {
dev_err(dev, "cci address change error\n");
goto out_cci_addr_fail;
@@ -1372,7 +1371,7 @@ static int smiapp_power_on(struct device *dev)
if (rval < 0)
goto out_cci_addr_fail;
- rval = smiapp_call_quirk(sensor, post_poweron);
+ rval = ccs_call_quirk(sensor, post_poweron);
if (rval) {
dev_err(dev, "post_poweron quirks failed\n");
goto out_cci_addr_fail;
@@ -1390,12 +1389,12 @@ static int smiapp_power_on(struct device *dev)
return rval;
}
-static int smiapp_power_off(struct device *dev)
+static int ccs_power_off(struct device *dev)
{
struct v4l2_subdev *subdev = dev_get_drvdata(dev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct smiapp_sensor *sensor =
- container_of(ssd, struct smiapp_sensor, ssds[0]);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct ccs_sensor *sensor =
+ container_of(ssd, struct ccs_sensor, ssds[0]);
/*
* Currently power/clock to lens are enable/disabled separately
@@ -1420,7 +1419,7 @@ static int smiapp_power_off(struct device *dev)
* Video stream management
*/
-static int smiapp_start_streaming(struct smiapp_sensor *sensor)
+static int ccs_start_streaming(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
unsigned int binning_mode;
@@ -1454,33 +1453,33 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
goto out;
/* Set up PLL */
- rval = smiapp_pll_configure(sensor);
+ rval = ccs_pll_configure(sensor);
if (rval)
goto out;
/* Analog crop start coordinates */
rval = ccs_write(sensor, X_ADDR_START,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left);
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].left);
if (rval < 0)
goto out;
rval = ccs_write(sensor, Y_ADDR_START,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top);
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].top);
if (rval < 0)
goto out;
/* Analog crop end coordinates */
rval = ccs_write(
sensor, X_ADDR_END,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left
- + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width - 1);
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].left
+ + sensor->pixel_array->crop[CCS_PA_PAD_SRC].width - 1);
if (rval < 0)
goto out;
rval = ccs_write(
sensor, Y_ADDR_END,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top
- + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height - 1);
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].top
+ + sensor->pixel_array->crop[CCS_PA_PAD_SRC].height - 1);
if (rval < 0)
goto out;
@@ -1494,25 +1493,25 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
== CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
rval = ccs_write(
sensor, DIGITAL_CROP_X_OFFSET,
- sensor->scaler->crop[SMIAPP_PAD_SINK].left);
+ sensor->scaler->crop[CCS_PAD_SINK].left);
if (rval < 0)
goto out;
rval = ccs_write(
sensor, DIGITAL_CROP_Y_OFFSET,
- sensor->scaler->crop[SMIAPP_PAD_SINK].top);
+ sensor->scaler->crop[CCS_PAD_SINK].top);
if (rval < 0)
goto out;
rval = ccs_write(
sensor, DIGITAL_CROP_IMAGE_WIDTH,
- sensor->scaler->crop[SMIAPP_PAD_SINK].width);
+ sensor->scaler->crop[CCS_PAD_SINK].width);
if (rval < 0)
goto out;
rval = ccs_write(
sensor, DIGITAL_CROP_IMAGE_HEIGHT,
- sensor->scaler->crop[SMIAPP_PAD_SINK].height);
+ sensor->scaler->crop[CCS_PAD_SINK].height);
if (rval < 0)
goto out;
}
@@ -1531,11 +1530,11 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
/* Output size from sensor */
rval = ccs_write(sensor, X_OUTPUT_SIZE,
- sensor->src->crop[SMIAPP_PAD_SRC].width);
+ sensor->src->crop[CCS_PAD_SRC].width);
if (rval < 0)
goto out;
rval = ccs_write(sensor, Y_OUTPUT_SIZE,
- sensor->src->crop[SMIAPP_PAD_SRC].height);
+ sensor->src->crop[CCS_PAD_SRC].height);
if (rval < 0)
goto out;
@@ -1544,12 +1543,12 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE) &&
sensor->hwcfg->strobe_setup != NULL &&
sensor->hwcfg->strobe_setup->trigger != 0) {
- rval = smiapp_setup_flash_strobe(sensor);
+ rval = ccs_setup_flash_strobe(sensor);
if (rval)
goto out;
}
- rval = smiapp_call_quirk(sensor, pre_streamon);
+ rval = ccs_call_quirk(sensor, pre_streamon);
if (rval) {
dev_err(&client->dev, "pre_streamon quirks failed\n");
goto out;
@@ -1563,7 +1562,7 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
return rval;
}
-static int smiapp_stop_streaming(struct smiapp_sensor *sensor)
+static int ccs_stop_streaming(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -1573,7 +1572,7 @@ static int smiapp_stop_streaming(struct smiapp_sensor *sensor)
if (rval)
goto out;
- rval = smiapp_call_quirk(sensor, post_streamoff);
+ rval = ccs_call_quirk(sensor, post_streamoff);
if (rval)
dev_err(&client->dev, "post_streamoff quirks failed\n");
@@ -1586,7 +1585,7 @@ static int smiapp_stop_streaming(struct smiapp_sensor *sensor)
* V4L2 subdev video operations
*/
-static int smiapp_pm_get_init(struct smiapp_sensor *sensor)
+static int ccs_pm_get_init(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -1610,9 +1609,9 @@ static int smiapp_pm_get_init(struct smiapp_sensor *sensor)
return 0;
}
-static int smiapp_set_stream(struct v4l2_subdev *subdev, int enable)
+static int ccs_set_stream(struct v4l2_subdev *subdev, int enable)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -1620,7 +1619,7 @@ static int smiapp_set_stream(struct v4l2_subdev *subdev, int enable)
return 0;
if (!enable) {
- smiapp_stop_streaming(sensor);
+ ccs_stop_streaming(sensor);
sensor->streaming = false;
pm_runtime_mark_last_busy(&client->dev);
pm_runtime_put_autosuspend(&client->dev);
@@ -1628,13 +1627,13 @@ static int smiapp_set_stream(struct v4l2_subdev *subdev, int enable)
return 0;
}
- rval = smiapp_pm_get_init(sensor);
+ rval = ccs_pm_get_init(sensor);
if (rval)
return rval;
sensor->streaming = true;
- rval = smiapp_start_streaming(sensor);
+ rval = ccs_start_streaming(sensor);
if (rval < 0) {
sensor->streaming = false;
pm_runtime_mark_last_busy(&client->dev);
@@ -1644,12 +1643,12 @@ static int smiapp_set_stream(struct v4l2_subdev *subdev, int enable)
return rval;
}
-static int smiapp_enum_mbus_code(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_mbus_code_enum *code)
+static int ccs_enum_mbus_code(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
{
struct i2c_client *client = v4l2_get_subdevdata(subdev);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
unsigned int i;
int idx = -1;
int rval = -EINVAL;
@@ -1659,7 +1658,7 @@ static int smiapp_enum_mbus_code(struct v4l2_subdev *subdev,
dev_err(&client->dev, "subdev %s, pad %d, index %d\n",
subdev->name, code->pad, code->index);
- if (subdev != &sensor->src->sd || code->pad != SMIAPP_PAD_SRC) {
+ if (subdev != &sensor->src->sd || code->pad != CCS_PAD_SRC) {
if (code->index)
goto out;
@@ -1668,12 +1667,12 @@ static int smiapp_enum_mbus_code(struct v4l2_subdev *subdev,
goto out;
}
- for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) {
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
if (sensor->mbus_frame_fmts & (1 << i))
idx++;
if (idx == code->index) {
- code->code = smiapp_csi_data_formats[i].code;
+ code->code = ccs_csi_data_formats[i].code;
dev_err(&client->dev, "found index %d, i %d, code %x\n",
code->index, i, code->code);
rval = 0;
@@ -1687,22 +1686,21 @@ static int smiapp_enum_mbus_code(struct v4l2_subdev *subdev,
return rval;
}
-static u32 __smiapp_get_mbus_code(struct v4l2_subdev *subdev,
- unsigned int pad)
+static u32 __ccs_get_mbus_code(struct v4l2_subdev *subdev, unsigned int pad)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
- if (subdev == &sensor->src->sd && pad == SMIAPP_PAD_SRC)
+ if (subdev == &sensor->src->sd && pad == CCS_PAD_SRC)
return sensor->csi_format->code;
else
return sensor->internal_csi_format->code;
}
-static int __smiapp_get_format(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
+static int __ccs_get_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
{
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
fmt->format = *v4l2_subdev_get_try_format(subdev, cfg,
@@ -1715,7 +1713,7 @@ static int __smiapp_get_format(struct v4l2_subdev *subdev,
else
r = &ssd->sink_fmt;
- fmt->format.code = __smiapp_get_mbus_code(subdev, fmt->pad);
+ fmt->format.code = __ccs_get_mbus_code(subdev, fmt->pad);
fmt->format.width = r->width;
fmt->format.height = r->height;
fmt->format.field = V4L2_FIELD_NONE;
@@ -1724,26 +1722,26 @@ static int __smiapp_get_format(struct v4l2_subdev *subdev,
return 0;
}
-static int smiapp_get_format(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
+static int ccs_get_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
int rval;
mutex_lock(&sensor->mutex);
- rval = __smiapp_get_format(subdev, cfg, fmt);
+ rval = __ccs_get_format(subdev, cfg, fmt);
mutex_unlock(&sensor->mutex);
return rval;
}
-static void smiapp_get_crop_compose(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_rect **crops,
- struct v4l2_rect **comps, int which)
+static void ccs_get_crop_compose(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_rect **crops,
+ struct v4l2_rect **comps, int which)
{
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
unsigned int i;
if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
@@ -1761,27 +1759,27 @@ static void smiapp_get_crop_compose(struct v4l2_subdev *subdev,
}
if (comps) {
*comps = v4l2_subdev_get_try_compose(subdev, cfg,
- SMIAPP_PAD_SINK);
+ CCS_PAD_SINK);
BUG_ON(!*comps);
}
}
}
/* Changes require propagation only on sink pad. */
-static void smiapp_propagate(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg, int which,
- int target)
+static void ccs_propagate(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg, int which,
+ int target)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *comp, *crops[SMIAPP_PADS];
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *comp, *crops[CCS_PADS];
- smiapp_get_crop_compose(subdev, cfg, crops, &comp, which);
+ ccs_get_crop_compose(subdev, cfg, crops, &comp, which);
switch (target) {
case V4L2_SEL_TGT_CROP:
- comp->width = crops[SMIAPP_PAD_SINK]->width;
- comp->height = crops[SMIAPP_PAD_SINK]->height;
+ comp->width = crops[CCS_PAD_SINK]->width;
+ comp->height = crops[CCS_PAD_SINK]->height;
if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
if (ssd == sensor->scaler) {
sensor->scale_m =
@@ -1795,40 +1793,40 @@ static void smiapp_propagate(struct v4l2_subdev *subdev,
}
fallthrough;
case V4L2_SEL_TGT_COMPOSE:
- *crops[SMIAPP_PAD_SRC] = *comp;
+ *crops[CCS_PAD_SRC] = *comp;
break;
default:
BUG();
}
}
-static const struct smiapp_csi_data_format
-*smiapp_validate_csi_data_format(struct smiapp_sensor *sensor, u32 code)
+static const struct ccs_csi_data_format
+*ccs_validate_csi_data_format(struct ccs_sensor *sensor, u32 code)
{
unsigned int i;
- for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) {
- if (sensor->mbus_frame_fmts & (1 << i)
- && smiapp_csi_data_formats[i].code == code)
- return &smiapp_csi_data_formats[i];
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
+ if (sensor->mbus_frame_fmts & (1 << i) &&
+ ccs_csi_data_formats[i].code == code)
+ return &ccs_csi_data_formats[i];
}
return sensor->csi_format;
}
-static int smiapp_set_format_source(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
+static int ccs_set_format_source(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- const struct smiapp_csi_data_format *csi_format,
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ const struct ccs_csi_data_format *csi_format,
*old_csi_format = sensor->csi_format;
unsigned long *valid_link_freqs;
u32 code = fmt->format.code;
unsigned int i;
int rval;
- rval = __smiapp_get_format(subdev, cfg, fmt);
+ rval = __ccs_get_format(subdev, cfg, fmt);
if (rval)
return rval;
@@ -1839,7 +1837,7 @@ static int smiapp_set_format_source(struct v4l2_subdev *subdev,
if (subdev != &sensor->src->sd)
return 0;
- csi_format = smiapp_validate_csi_data_format(sensor, code);
+ csi_format = ccs_validate_csi_data_format(sensor, code);
fmt->format.code = csi_format->code;
@@ -1866,23 +1864,23 @@ static int smiapp_set_format_source(struct v4l2_subdev *subdev,
__fls(*valid_link_freqs), ~*valid_link_freqs,
__ffs(*valid_link_freqs));
- return smiapp_pll_update(sensor);
+ return ccs_pll_update(sensor);
}
-static int smiapp_set_format(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
+static int ccs_set_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *crops[SMIAPP_PADS];
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *crops[CCS_PADS];
mutex_lock(&sensor->mutex);
if (fmt->pad == ssd->source_pad) {
int rval;
- rval = smiapp_set_format_source(subdev, cfg, fmt);
+ rval = ccs_set_format_source(subdev, cfg, fmt);
mutex_unlock(&sensor->mutex);
@@ -1890,7 +1888,7 @@ static int smiapp_set_format(struct v4l2_subdev *subdev,
}
/* Sink pad. Width and height are changeable here. */
- fmt->format.code = __smiapp_get_mbus_code(subdev, fmt->pad);
+ fmt->format.code = __ccs_get_mbus_code(subdev, fmt->pad);
fmt->format.width &= ~1;
fmt->format.height &= ~1;
fmt->format.field = V4L2_FIELD_NONE;
@@ -1904,7 +1902,7 @@ static int smiapp_set_format(struct v4l2_subdev *subdev,
CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
CCS_LIM(sensor, MAX_Y_OUTPUT_SIZE));
- smiapp_get_crop_compose(subdev, cfg, crops, NULL, fmt->which);
+ ccs_get_crop_compose(subdev, cfg, crops, NULL, fmt->which);
crops[ssd->sink_pad]->left = 0;
crops[ssd->sink_pad]->top = 0;
@@ -1912,8 +1910,7 @@ static int smiapp_set_format(struct v4l2_subdev *subdev,
crops[ssd->sink_pad]->height = fmt->format.height;
if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
ssd->sink_fmt = *crops[ssd->sink_pad];
- smiapp_propagate(subdev, cfg, fmt->which,
- V4L2_SEL_TGT_CROP);
+ ccs_propagate(subdev, cfg, fmt->which, V4L2_SEL_TGT_CROP);
mutex_unlock(&sensor->mutex);
@@ -1929,7 +1926,7 @@ static int smiapp_set_format(struct v4l2_subdev *subdev,
static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w,
int h, int ask_h, u32 flags)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
struct i2c_client *client = v4l2_get_subdevdata(subdev);
int val = 0;
@@ -1964,27 +1961,27 @@ static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w,
return val;
}
-static void smiapp_set_compose_binner(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel,
- struct v4l2_rect **crops,
- struct v4l2_rect *comp)
+static void ccs_set_compose_binner(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel,
+ struct v4l2_rect **crops,
+ struct v4l2_rect *comp)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
unsigned int i;
unsigned int binh = 1, binv = 1;
int best = scaling_goodness(
subdev,
- crops[SMIAPP_PAD_SINK]->width, sel->r.width,
- crops[SMIAPP_PAD_SINK]->height, sel->r.height, sel->flags);
+ crops[CCS_PAD_SINK]->width, sel->r.width,
+ crops[CCS_PAD_SINK]->height, sel->r.height, sel->flags);
for (i = 0; i < sensor->nbinning_subtypes; i++) {
int this = scaling_goodness(
subdev,
- crops[SMIAPP_PAD_SINK]->width
+ crops[CCS_PAD_SINK]->width
/ sensor->binning_subtypes[i].horizontal,
sel->r.width,
- crops[SMIAPP_PAD_SINK]->height
+ crops[CCS_PAD_SINK]->height
/ sensor->binning_subtypes[i].vertical,
sel->r.height, sel->flags);
@@ -1999,8 +1996,8 @@ static void smiapp_set_compose_binner(struct v4l2_subdev *subdev,
sensor->binning_horizontal = binh;
}
- sel->r.width = (crops[SMIAPP_PAD_SINK]->width / binh) & ~1;
- sel->r.height = (crops[SMIAPP_PAD_SINK]->height / binv) & ~1;
+ sel->r.width = (crops[CCS_PAD_SINK]->width / binh) & ~1;
+ sel->r.height = (crops[CCS_PAD_SINK]->height / binv) & ~1;
}
/*
@@ -2012,14 +2009,14 @@ static void smiapp_set_compose_binner(struct v4l2_subdev *subdev,
* Also try whether horizontal scaler or full scaler gives a better
* result.
*/
-static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel,
- struct v4l2_rect **crops,
- struct v4l2_rect *comp)
+static void ccs_set_compose_scaler(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel,
+ struct v4l2_rect **crops,
+ struct v4l2_rect *comp)
{
struct i2c_client *client = v4l2_get_subdevdata(subdev);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
u32 min, max, a, b, max_m;
u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN);
int mode = CCS_SCALING_MODE_HORIZONTAL;
@@ -2029,15 +2026,15 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
int best = INT_MIN;
sel->r.width = min_t(unsigned int, sel->r.width,
- crops[SMIAPP_PAD_SINK]->width);
+ crops[CCS_PAD_SINK]->width);
sel->r.height = min_t(unsigned int, sel->r.height,
- crops[SMIAPP_PAD_SINK]->height);
+ crops[CCS_PAD_SINK]->height);
- a = crops[SMIAPP_PAD_SINK]->width
+ a = crops[CCS_PAD_SINK]->width
* CCS_LIM(sensor, SCALER_N_MIN) / sel->r.width;
- b = crops[SMIAPP_PAD_SINK]->height
+ b = crops[CCS_PAD_SINK]->height
* CCS_LIM(sensor, SCALER_N_MIN) / sel->r.height;
- max_m = crops[SMIAPP_PAD_SINK]->width
+ max_m = crops[CCS_PAD_SINK]->width
* CCS_LIM(sensor, SCALER_N_MIN)
/ CCS_LIM(sensor, MIN_X_OUTPUT_SIZE);
@@ -2071,10 +2068,10 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
for (i = 0; i < ntry; i++) {
int this = scaling_goodness(
subdev,
- crops[SMIAPP_PAD_SINK]->width
+ crops[CCS_PAD_SINK]->width
/ try[i] * CCS_LIM(sensor, SCALER_N_MIN),
sel->r.width,
- crops[SMIAPP_PAD_SINK]->height,
+ crops[CCS_PAD_SINK]->height,
sel->r.height,
sel->flags);
@@ -2091,11 +2088,11 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
continue;
this = scaling_goodness(
- subdev, crops[SMIAPP_PAD_SINK]->width
+ subdev, crops[CCS_PAD_SINK]->width
/ try[i]
* CCS_LIM(sensor, SCALER_N_MIN),
sel->r.width,
- crops[SMIAPP_PAD_SINK]->height
+ crops[CCS_PAD_SINK]->height
/ try[i]
* CCS_LIM(sensor, SCALER_N_MIN),
sel->r.height,
@@ -2109,17 +2106,17 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
}
sel->r.width =
- (crops[SMIAPP_PAD_SINK]->width
+ (crops[CCS_PAD_SINK]->width
/ scale_m
* CCS_LIM(sensor, SCALER_N_MIN)) & ~1;
if (mode == SMIAPP_SCALING_MODE_BOTH)
sel->r.height =
- (crops[SMIAPP_PAD_SINK]->height
+ (crops[CCS_PAD_SINK]->height
/ scale_m
* CCS_LIM(sensor, SCALER_N_MIN))
& ~1;
else
- sel->r.height = crops[SMIAPP_PAD_SINK]->height;
+ sel->r.height = crops[CCS_PAD_SINK]->height;
if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
sensor->scale_m = scale_m;
@@ -2127,57 +2124,54 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
}
}
/* We're only called on source pads. This function sets scaling. */
-static int smiapp_set_compose(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
+static int ccs_set_compose(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *comp, *crops[SMIAPP_PADS];
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *comp, *crops[CCS_PADS];
- smiapp_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
+ ccs_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
sel->r.top = 0;
sel->r.left = 0;
if (ssd == sensor->binner)
- smiapp_set_compose_binner(subdev, cfg, sel, crops, comp);
+ ccs_set_compose_binner(subdev, cfg, sel, crops, comp);
else
- smiapp_set_compose_scaler(subdev, cfg, sel, crops, comp);
+ ccs_set_compose_scaler(subdev, cfg, sel, crops, comp);
*comp = sel->r;
- smiapp_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_COMPOSE);
+ ccs_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_COMPOSE);
if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE)
- return smiapp_pll_blanking_update(sensor);
+ return ccs_pll_blanking_update(sensor);
return 0;
}
-static int __smiapp_sel_supported(struct v4l2_subdev *subdev,
- struct v4l2_subdev_selection *sel)
+static int __ccs_sel_supported(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_selection *sel)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
/* We only implement crop in three places. */
switch (sel->target) {
case V4L2_SEL_TGT_CROP:
case V4L2_SEL_TGT_CROP_BOUNDS:
- if (ssd == sensor->pixel_array
- && sel->pad == SMIAPP_PA_PAD_SRC)
+ if (ssd == sensor->pixel_array && sel->pad == CCS_PA_PAD_SRC)
return 0;
- if (ssd == sensor->src
- && sel->pad == SMIAPP_PAD_SRC)
+ if (ssd == sensor->src && sel->pad == CCS_PAD_SRC)
return 0;
- if (ssd == sensor->scaler && sel->pad == SMIAPP_PAD_SINK &&
+ if (ssd == sensor->scaler && sel->pad == CCS_PAD_SINK &&
CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
== CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP)
return 0;
return -EINVAL;
case V4L2_SEL_TGT_NATIVE_SIZE:
- if (ssd == sensor->pixel_array
- && sel->pad == SMIAPP_PA_PAD_SRC)
+ if (ssd == sensor->pixel_array && sel->pad == CCS_PA_PAD_SRC)
return 0;
return -EINVAL;
case V4L2_SEL_TGT_COMPOSE:
@@ -2195,16 +2189,16 @@ static int __smiapp_sel_supported(struct v4l2_subdev *subdev,
}
}
-static int smiapp_set_crop(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
+static int ccs_set_crop(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *src_size, *crops[SMIAPP_PADS];
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *src_size, *crops[CCS_PADS];
struct v4l2_rect _r;
- smiapp_get_crop_compose(subdev, cfg, crops, NULL, sel->which);
+ ccs_get_crop_compose(subdev, cfg, crops, NULL, sel->which);
if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
if (sel->pad == ssd->sink_pad)
@@ -2226,7 +2220,7 @@ static int smiapp_set_crop(struct v4l2_subdev *subdev,
}
}
- if (ssd == sensor->src && sel->pad == SMIAPP_PAD_SRC) {
+ if (ssd == sensor->src && sel->pad == CCS_PAD_SRC) {
sel->r.left = 0;
sel->r.top = 0;
}
@@ -2239,15 +2233,13 @@ static int smiapp_set_crop(struct v4l2_subdev *subdev,
*crops[sel->pad] = sel->r;
- if (ssd != sensor->pixel_array && sel->pad == SMIAPP_PAD_SINK)
- smiapp_propagate(subdev, cfg, sel->which,
- V4L2_SEL_TGT_CROP);
+ if (ssd != sensor->pixel_array && sel->pad == CCS_PAD_SINK)
+ ccs_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_CROP);
return 0;
}
-static void smiapp_get_native_size(struct smiapp_subdev *ssd,
- struct v4l2_rect *r)
+static void ccs_get_native_size(struct ccs_subdev *ssd, struct v4l2_rect *r)
{
r->top = 0;
r->left = 0;
@@ -2255,21 +2247,21 @@ static void smiapp_get_native_size(struct smiapp_subdev *ssd,
r->height = CCS_LIM(ssd->sensor, Y_ADDR_MAX) + 1;
}
-static int __smiapp_get_selection(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
+static int __ccs_get_selection(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *comp, *crops[SMIAPP_PADS];
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *comp, *crops[CCS_PADS];
struct v4l2_rect sink_fmt;
int ret;
- ret = __smiapp_sel_supported(subdev, sel);
+ ret = __ccs_sel_supported(subdev, sel);
if (ret)
return ret;
- smiapp_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
+ ccs_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
sink_fmt = ssd->sink_fmt;
@@ -2287,7 +2279,7 @@ static int __smiapp_get_selection(struct v4l2_subdev *subdev,
case V4L2_SEL_TGT_CROP_BOUNDS:
case V4L2_SEL_TGT_NATIVE_SIZE:
if (ssd == sensor->pixel_array)
- smiapp_get_native_size(ssd, &sel->r);
+ ccs_get_native_size(ssd, &sel->r);
else if (sel->pad == ssd->sink_pad)
sel->r = sink_fmt;
else
@@ -2305,27 +2297,28 @@ static int __smiapp_get_selection(struct v4l2_subdev *subdev,
return 0;
}
-static int smiapp_get_selection(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
+static int ccs_get_selection(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
int rval;
mutex_lock(&sensor->mutex);
- rval = __smiapp_get_selection(subdev, cfg, sel);
+ rval = __ccs_get_selection(subdev, cfg, sel);
mutex_unlock(&sensor->mutex);
return rval;
}
-static int smiapp_set_selection(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
+
+static int ccs_set_selection(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
int ret;
- ret = __smiapp_sel_supported(subdev, sel);
+ ret = __ccs_sel_supported(subdev, sel);
if (ret)
return ret;
@@ -2333,8 +2326,8 @@ static int smiapp_set_selection(struct v4l2_subdev *subdev,
sel->r.left = max(0, sel->r.left & ~1);
sel->r.top = max(0, sel->r.top & ~1);
- sel->r.width = SMIAPP_ALIGN_DIM(sel->r.width, sel->flags);
- sel->r.height = SMIAPP_ALIGN_DIM(sel->r.height, sel->flags);
+ sel->r.width = CCS_ALIGN_DIM(sel->r.width, sel->flags);
+ sel->r.height = CCS_ALIGN_DIM(sel->r.height, sel->flags);
sel->r.width = max_t(unsigned int,
CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
@@ -2345,10 +2338,10 @@ static int smiapp_set_selection(struct v4l2_subdev *subdev,
switch (sel->target) {
case V4L2_SEL_TGT_CROP:
- ret = smiapp_set_crop(subdev, cfg, sel);
+ ret = ccs_set_crop(subdev, cfg, sel);
break;
case V4L2_SEL_TGT_COMPOSE:
- ret = smiapp_set_compose(subdev, cfg, sel);
+ ret = ccs_set_compose(subdev, cfg, sel);
break;
default:
ret = -EINVAL;
@@ -2358,17 +2351,17 @@ static int smiapp_set_selection(struct v4l2_subdev *subdev,
return ret;
}
-static int smiapp_get_skip_frames(struct v4l2_subdev *subdev, u32 *frames)
+static int ccs_get_skip_frames(struct v4l2_subdev *subdev, u32 *frames)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
*frames = sensor->frame_skip;
return 0;
}
-static int smiapp_get_skip_top_lines(struct v4l2_subdev *subdev, u32 *lines)
+static int ccs_get_skip_top_lines(struct v4l2_subdev *subdev, u32 *lines)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
*lines = sensor->image_start;
@@ -2380,22 +2373,22 @@ static int smiapp_get_skip_top_lines(struct v4l2_subdev *subdev, u32 *lines)
*/
static ssize_t
-smiapp_sysfs_nvm_read(struct device *dev, struct device_attribute *attr,
- char *buf)
+ccs_sysfs_nvm_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev));
struct i2c_client *client = v4l2_get_subdevdata(subdev);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
int rval;
if (!sensor->dev_init_done)
return -EBUSY;
- rval = smiapp_pm_get_init(sensor);
+ rval = ccs_pm_get_init(sensor);
if (rval < 0)
return -ENODEV;
- rval = smiapp_read_nvm(sensor, buf, PAGE_SIZE);
+ rval = ccs_read_nvm(sensor, buf, PAGE_SIZE);
if (rval < 0) {
pm_runtime_put(&client->dev);
dev_err(&client->dev, "nvm read failed\n");
@@ -2411,15 +2404,15 @@ smiapp_sysfs_nvm_read(struct device *dev, struct device_attribute *attr,
*/
return rval;
}
-static DEVICE_ATTR(nvm, S_IRUGO, smiapp_sysfs_nvm_read, NULL);
+static DEVICE_ATTR(nvm, S_IRUGO, ccs_sysfs_nvm_read, NULL);
static ssize_t
-smiapp_sysfs_ident_read(struct device *dev, struct device_attribute *attr,
- char *buf)
+ccs_sysfs_ident_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev));
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_module_info *minfo = &sensor->minfo;
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_module_info *minfo = &sensor->minfo;
if (minfo->mipi_manufacturer_id)
return snprintf(buf, PAGE_SIZE, "%4.4x%4.4x%2.2x\n",
@@ -2431,16 +2424,16 @@ smiapp_sysfs_ident_read(struct device *dev, struct device_attribute *attr,
minfo->revision_number_major) + 1;
}
-static DEVICE_ATTR(ident, S_IRUGO, smiapp_sysfs_ident_read, NULL);
+static DEVICE_ATTR(ident, S_IRUGO, ccs_sysfs_ident_read, NULL);
/* -----------------------------------------------------------------------------
* V4L2 subdev core operations
*/
-static int smiapp_identify_module(struct smiapp_sensor *sensor)
+static int ccs_identify_module(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- struct smiapp_module_info *minfo = &sensor->minfo;
+ struct ccs_module_info *minfo = &sensor->minfo;
unsigned int i;
int rval = 0;
@@ -2558,34 +2551,34 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
minfo->revision_number_major = minfo->sensor_revision_number;
}
- for (i = 0; i < ARRAY_SIZE(smiapp_module_idents); i++) {
- if (smiapp_module_idents[i].mipi_manufacturer_id &&
- smiapp_module_idents[i].mipi_manufacturer_id
+ for (i = 0; i < ARRAY_SIZE(ccs_module_idents); i++) {
+ if (ccs_module_idents[i].mipi_manufacturer_id &&
+ ccs_module_idents[i].mipi_manufacturer_id
!= minfo->mipi_manufacturer_id)
continue;
- if (smiapp_module_idents[i].smia_manufacturer_id &&
- smiapp_module_idents[i].smia_manufacturer_id
+ if (ccs_module_idents[i].smia_manufacturer_id &&
+ ccs_module_idents[i].smia_manufacturer_id
!= minfo->smia_manufacturer_id)
continue;
- if (smiapp_module_idents[i].model_id != minfo->model_id)
+ if (ccs_module_idents[i].model_id != minfo->model_id)
continue;
- if (smiapp_module_idents[i].flags
- & SMIAPP_MODULE_IDENT_FLAG_REV_LE) {
- if (smiapp_module_idents[i].revision_number_major
+ if (ccs_module_idents[i].flags
+ & CCS_MODULE_IDENT_FLAG_REV_LE) {
+ if (ccs_module_idents[i].revision_number_major
< minfo->revision_number_major)
continue;
} else {
- if (smiapp_module_idents[i].revision_number_major
+ if (ccs_module_idents[i].revision_number_major
!= minfo->revision_number_major)
continue;
}
- minfo->name = smiapp_module_idents[i].name;
- minfo->quirk = smiapp_module_idents[i].quirk;
+ minfo->name = ccs_module_idents[i].name;
+ minfo->quirk = ccs_module_idents[i].quirk;
break;
}
- if (i >= ARRAY_SIZE(smiapp_module_idents))
+ if (i >= ARRAY_SIZE(ccs_module_idents))
dev_warn(&client->dev,
"no quirks for this module; let's hope it's fully compliant\n");
@@ -2595,14 +2588,14 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
return 0;
}
-static const struct v4l2_subdev_ops smiapp_ops;
-static const struct v4l2_subdev_internal_ops smiapp_internal_ops;
-static const struct media_entity_operations smiapp_entity_ops;
+static const struct v4l2_subdev_ops ccs_ops;
+static const struct v4l2_subdev_internal_ops ccs_internal_ops;
+static const struct media_entity_operations ccs_entity_ops;
-static int smiapp_register_subdev(struct smiapp_sensor *sensor,
- struct smiapp_subdev *ssd,
- struct smiapp_subdev *sink_ssd,
- u16 source_pad, u16 sink_pad, u32 link_flags)
+static int ccs_register_subdev(struct ccs_sensor *sensor,
+ struct ccs_subdev *ssd,
+ struct ccs_subdev *sink_ssd,
+ u16 source_pad, u16 sink_pad, u32 link_flags)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -2639,57 +2632,58 @@ static int smiapp_register_subdev(struct smiapp_sensor *sensor,
return 0;
}
-static void smiapp_unregistered(struct v4l2_subdev *subdev)
+static void ccs_unregistered(struct v4l2_subdev *subdev)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
unsigned int i;
for (i = 1; i < sensor->ssds_used; i++)
v4l2_device_unregister_subdev(&sensor->ssds[i].sd);
}
-static int smiapp_registered(struct v4l2_subdev *subdev)
+static int ccs_registered(struct v4l2_subdev *subdev)
{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
int rval;
if (sensor->scaler) {
- rval = smiapp_register_subdev(
- sensor, sensor->binner, sensor->scaler,
- SMIAPP_PAD_SRC, SMIAPP_PAD_SINK,
- MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
+ rval = ccs_register_subdev(sensor, sensor->binner,
+ sensor->scaler,
+ CCS_PAD_SRC, CCS_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED |
+ MEDIA_LNK_FL_IMMUTABLE);
if (rval < 0)
return rval;
}
- rval = smiapp_register_subdev(
- sensor, sensor->pixel_array, sensor->binner,
- SMIAPP_PA_PAD_SRC, SMIAPP_PAD_SINK,
- MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
+ rval = ccs_register_subdev(sensor, sensor->pixel_array, sensor->binner,
+ CCS_PA_PAD_SRC, CCS_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED |
+ MEDIA_LNK_FL_IMMUTABLE);
if (rval)
goto out_err;
return 0;
out_err:
- smiapp_unregistered(subdev);
+ ccs_unregistered(subdev);
return rval;
}
-static void smiapp_cleanup(struct smiapp_sensor *sensor)
+static void ccs_cleanup(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
device_remove_file(&client->dev, &dev_attr_nvm);
device_remove_file(&client->dev, &dev_attr_ident);
- smiapp_free_controls(sensor);
+ ccs_free_controls(sensor);
}
-static void smiapp_create_subdev(struct smiapp_sensor *sensor,
- struct smiapp_subdev *ssd, const char *name,
- unsigned short num_pads)
+static void ccs_create_subdev(struct ccs_sensor *sensor,
+ struct ccs_subdev *ssd, const char *name,
+ unsigned short num_pads)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
@@ -2697,7 +2691,7 @@ static void smiapp_create_subdev(struct smiapp_sensor *sensor,
return;
if (ssd != sensor->src)
- v4l2_subdev_init(&ssd->sd, &smiapp_ops);
+ v4l2_subdev_init(&ssd->sd, &ccs_ops);
ssd->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
ssd->sensor = sensor;
@@ -2707,7 +2701,7 @@ static void smiapp_create_subdev(struct smiapp_sensor *sensor,
v4l2_i2c_subdev_set_name(&ssd->sd, client, sensor->minfo.name, name);
- smiapp_get_native_size(ssd, &ssd->sink_fmt);
+ ccs_get_native_size(ssd, &ssd->sink_fmt);
ssd->compose.width = ssd->sink_fmt.width;
ssd->compose.height = ssd->sink_fmt.height;
@@ -2718,21 +2712,21 @@ static void smiapp_create_subdev(struct smiapp_sensor *sensor,
ssd->pads[ssd->sink_pad].flags = MEDIA_PAD_FL_SINK;
}
- ssd->sd.entity.ops = &smiapp_entity_ops;
+ ssd->sd.entity.ops = &ccs_entity_ops;
if (ssd == sensor->src)
return;
- ssd->sd.internal_ops = &smiapp_internal_ops;
+ ssd->sd.internal_ops = &ccs_internal_ops;
ssd->sd.owner = THIS_MODULE;
ssd->sd.dev = &client->dev;
v4l2_set_subdevdata(&ssd->sd, client);
}
-static int smiapp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+static int ccs_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
- struct smiapp_subdev *ssd = to_smiapp_subdev(sd);
- struct smiapp_sensor *sensor = ssd->sensor;
+ struct ccs_subdev *ssd = to_ccs_subdev(sd);
+ struct ccs_sensor *sensor = ssd->sensor;
unsigned int i;
mutex_lock(&sensor->mutex);
@@ -2744,7 +2738,7 @@ static int smiapp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
v4l2_subdev_get_try_crop(sd, fh->pad, i);
struct v4l2_rect *try_comp;
- smiapp_get_native_size(ssd, try_crop);
+ ccs_get_native_size(ssd, try_crop);
try_fmt->width = try_crop->width;
try_fmt->height = try_crop->height;
@@ -2763,52 +2757,52 @@ static int smiapp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
return 0;
}
-static const struct v4l2_subdev_video_ops smiapp_video_ops = {
- .s_stream = smiapp_set_stream,
+static const struct v4l2_subdev_video_ops ccs_video_ops = {
+ .s_stream = ccs_set_stream,
};
-static const struct v4l2_subdev_pad_ops smiapp_pad_ops = {
- .enum_mbus_code = smiapp_enum_mbus_code,
- .get_fmt = smiapp_get_format,
- .set_fmt = smiapp_set_format,
- .get_selection = smiapp_get_selection,
- .set_selection = smiapp_set_selection,
+static const struct v4l2_subdev_pad_ops ccs_pad_ops = {
+ .enum_mbus_code = ccs_enum_mbus_code,
+ .get_fmt = ccs_get_format,
+ .set_fmt = ccs_set_format,
+ .get_selection = ccs_get_selection,
+ .set_selection = ccs_set_selection,
};
-static const struct v4l2_subdev_sensor_ops smiapp_sensor_ops = {
- .g_skip_frames = smiapp_get_skip_frames,
- .g_skip_top_lines = smiapp_get_skip_top_lines,
+static const struct v4l2_subdev_sensor_ops ccs_sensor_ops = {
+ .g_skip_frames = ccs_get_skip_frames,
+ .g_skip_top_lines = ccs_get_skip_top_lines,
};
-static const struct v4l2_subdev_ops smiapp_ops = {
- .video = &smiapp_video_ops,
- .pad = &smiapp_pad_ops,
- .sensor = &smiapp_sensor_ops,
+static const struct v4l2_subdev_ops ccs_ops = {
+ .video = &ccs_video_ops,
+ .pad = &ccs_pad_ops,
+ .sensor = &ccs_sensor_ops,
};
-static const struct media_entity_operations smiapp_entity_ops = {
+static const struct media_entity_operations ccs_entity_ops = {
.link_validate = v4l2_subdev_link_validate,
};
-static const struct v4l2_subdev_internal_ops smiapp_internal_src_ops = {
- .registered = smiapp_registered,
- .unregistered = smiapp_unregistered,
- .open = smiapp_open,
+static const struct v4l2_subdev_internal_ops ccs_internal_src_ops = {
+ .registered = ccs_registered,
+ .unregistered = ccs_unregistered,
+ .open = ccs_open,
};
-static const struct v4l2_subdev_internal_ops smiapp_internal_ops = {
- .open = smiapp_open,
+static const struct v4l2_subdev_internal_ops ccs_internal_ops = {
+ .open = ccs_open,
};
/* -----------------------------------------------------------------------------
* I2C Driver
*/
-static int __maybe_unused smiapp_suspend(struct device *dev)
+static int __maybe_unused ccs_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct v4l2_subdev *subdev = i2c_get_clientdata(client);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
bool streaming = sensor->streaming;
int rval;
@@ -2821,7 +2815,7 @@ static int __maybe_unused smiapp_suspend(struct device *dev)
}
if (sensor->streaming)
- smiapp_stop_streaming(sensor);
+ ccs_stop_streaming(sensor);
/* save state for resume */
sensor->streaming = streaming;
@@ -2829,24 +2823,24 @@ static int __maybe_unused smiapp_suspend(struct device *dev)
return 0;
}
-static int __maybe_unused smiapp_resume(struct device *dev)
+static int __maybe_unused ccs_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct v4l2_subdev *subdev = i2c_get_clientdata(client);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
int rval = 0;
pm_runtime_put(dev);
if (sensor->streaming)
- rval = smiapp_start_streaming(sensor);
+ rval = ccs_start_streaming(sensor);
return rval;
}
-static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev)
+static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev)
{
- struct smiapp_hwconfig *hwcfg;
+ struct ccs_hwconfig *hwcfg;
struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
struct fwnode_handle *ep;
struct fwnode_handle *fwnode = dev_fwnode(dev);
@@ -2898,7 +2892,7 @@ static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev)
switch (rotation) {
case 180:
hwcfg->module_board_orient =
- SMIAPP_MODULE_BOARD_ORIENT_180;
+ CCS_MODULE_BOARD_ORIENT_180;
fallthrough;
case 0:
break;
@@ -2942,10 +2936,10 @@ static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev)
return NULL;
}
-static int smiapp_probe(struct i2c_client *client)
+static int ccs_probe(struct i2c_client *client)
{
- struct smiapp_sensor *sensor;
- struct smiapp_hwconfig *hwcfg = smiapp_get_hwconfig(&client->dev);
+ struct ccs_sensor *sensor;
+ struct ccs_hwconfig *hwcfg = ccs_get_hwconfig(&client->dev);
unsigned int i;
int rval;
@@ -2959,8 +2953,8 @@ static int smiapp_probe(struct i2c_client *client)
sensor->hwcfg = hwcfg;
sensor->src = &sensor->ssds[sensor->ssds_used];
- v4l2_i2c_subdev_init(&sensor->src->sd, client, &smiapp_ops);
- sensor->src->sd.internal_ops = &smiapp_internal_src_ops;
+ v4l2_i2c_subdev_init(&sensor->src->sd, client, &ccs_ops);
+ sensor->src->sd.internal_ops = &ccs_internal_src_ops;
sensor->vana = devm_regulator_get(&client->dev, "vana");
if (IS_ERR(sensor->vana)) {
@@ -3016,13 +3010,13 @@ static int smiapp_probe(struct i2c_client *client)
if (IS_ERR(sensor->xshutdown))
return PTR_ERR(sensor->xshutdown);
- rval = smiapp_power_on(&client->dev);
+ rval = ccs_power_on(&client->dev);
if (rval < 0)
return rval;
mutex_init(&sensor->mutex);
- rval = smiapp_identify_module(sensor);
+ rval = ccs_identify_module(sensor);
if (rval) {
rval = -ENODEV;
goto out_power_off;
@@ -3032,7 +3026,7 @@ static int smiapp_probe(struct i2c_client *client)
if (rval)
goto out_power_off;
- rval = smiapp_read_frame_fmt(sensor);
+ rval = ccs_read_frame_fmt(sensor);
if (rval) {
rval = -ENODEV;
goto out_free_ccs_limits;
@@ -3044,7 +3038,7 @@ static int smiapp_probe(struct i2c_client *client)
* The application of H-FLIP and V-FLIP on the sensor is modified by
* the sensor orientation on the board.
*
- * For SMIAPP_BOARD_SENSOR_ORIENT_180 the default behaviour is to set
+ * For CCS_BOARD_SENSOR_ORIENT_180 the default behaviour is to set
* both H-FLIP and V-FLIP for normal operation which also implies
* that a set/unset operation for user space HFLIP and VFLIP v4l2
* controls will need to be internally inverted.
@@ -3052,12 +3046,12 @@ static int smiapp_probe(struct i2c_client *client)
* Rotation also changes the bayer pattern.
*/
if (sensor->hwcfg->module_board_orient ==
- SMIAPP_MODULE_BOARD_ORIENT_180)
+ CCS_MODULE_BOARD_ORIENT_180)
sensor->hvflip_inv_mask =
CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR |
CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
- rval = smiapp_call_quirk(sensor, limits);
+ rval = ccs_call_quirk(sensor, limits);
if (rval) {
dev_err(&client->dev, "limits quirks failed\n");
goto out_free_ccs_limits;
@@ -3136,36 +3130,36 @@ static int smiapp_probe(struct i2c_client *client)
if (sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS;
- smiapp_create_subdev(sensor, sensor->scaler, " scaler", 2);
- smiapp_create_subdev(sensor, sensor->binner, " binner", 2);
- smiapp_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1);
+ ccs_create_subdev(sensor, sensor->scaler, " scaler", 2);
+ ccs_create_subdev(sensor, sensor->binner, " binner", 2);
+ ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1);
dev_dbg(&client->dev, "profile %d\n", sensor->minfo.smiapp_profile);
sensor->pixel_array->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
- rval = smiapp_init_controls(sensor);
+ rval = ccs_init_controls(sensor);
if (rval < 0)
goto out_cleanup;
- rval = smiapp_call_quirk(sensor, init);
+ rval = ccs_call_quirk(sensor, init);
if (rval)
goto out_cleanup;
- rval = smiapp_get_mbus_formats(sensor);
+ rval = ccs_get_mbus_formats(sensor);
if (rval) {
rval = -ENODEV;
goto out_cleanup;
}
- rval = smiapp_init_late_controls(sensor);
+ rval = ccs_init_late_controls(sensor);
if (rval) {
rval = -ENODEV;
goto out_cleanup;
}
mutex_lock(&sensor->mutex);
- rval = smiapp_pll_blanking_update(sensor);
+ rval = ccs_pll_blanking_update(sensor);
mutex_unlock(&sensor->mutex);
if (rval) {
dev_err(&client->dev, "update mode failed\n");
@@ -3202,71 +3196,71 @@ static int smiapp_probe(struct i2c_client *client)
media_entity_cleanup(&sensor->src->sd.entity);
out_cleanup:
- smiapp_cleanup(sensor);
+ ccs_cleanup(sensor);
out_free_ccs_limits:
kfree(sensor->ccs_limits);
out_power_off:
- smiapp_power_off(&client->dev);
+ ccs_power_off(&client->dev);
mutex_destroy(&sensor->mutex);
return rval;
}
-static int smiapp_remove(struct i2c_client *client)
+static int ccs_remove(struct i2c_client *client)
{
struct v4l2_subdev *subdev = i2c_get_clientdata(client);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
unsigned int i;
v4l2_async_unregister_subdev(subdev);
pm_runtime_disable(&client->dev);
if (!pm_runtime_status_suspended(&client->dev))
- smiapp_power_off(&client->dev);
+ ccs_power_off(&client->dev);
pm_runtime_set_suspended(&client->dev);
for (i = 0; i < sensor->ssds_used; i++) {
v4l2_device_unregister_subdev(&sensor->ssds[i].sd);
media_entity_cleanup(&sensor->ssds[i].sd.entity);
}
- smiapp_cleanup(sensor);
+ ccs_cleanup(sensor);
mutex_destroy(&sensor->mutex);
kfree(sensor->ccs_limits);
return 0;
}
-static const struct of_device_id smiapp_of_table[] = {
+static const struct of_device_id ccs_of_table[] = {
{ .compatible = "nokia,smia" },
{ },
};
-MODULE_DEVICE_TABLE(of, smiapp_of_table);
+MODULE_DEVICE_TABLE(of, ccs_of_table);
-static const struct i2c_device_id smiapp_id_table[] = {
+static const struct i2c_device_id ccs_id_table[] = {
{ SMIAPP_NAME, 0 },
{ },
};
-MODULE_DEVICE_TABLE(i2c, smiapp_id_table);
+MODULE_DEVICE_TABLE(i2c, ccs_id_table);
-static const struct dev_pm_ops smiapp_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(smiapp_suspend, smiapp_resume)
- SET_RUNTIME_PM_OPS(smiapp_power_off, smiapp_power_on, NULL)
+static const struct dev_pm_ops ccs_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(ccs_suspend, ccs_resume)
+ SET_RUNTIME_PM_OPS(ccs_power_off, ccs_power_on, NULL)
};
-static struct i2c_driver smiapp_i2c_driver = {
+static struct i2c_driver ccs_i2c_driver = {
.driver = {
- .of_match_table = smiapp_of_table,
- .name = SMIAPP_NAME,
- .pm = &smiapp_pm_ops,
+ .of_match_table = ccs_of_table,
+ .name = CCS_NAME,
+ .pm = &ccs_pm_ops,
},
- .probe_new = smiapp_probe,
- .remove = smiapp_remove,
- .id_table = smiapp_id_table,
+ .probe_new = ccs_probe,
+ .remove = ccs_remove,
+ .id_table = ccs_id_table,
};
-static int smiapp_module_init(void)
+static int ccs_module_init(void)
{
unsigned int i, l;
@@ -3289,17 +3283,17 @@ static int smiapp_module_init(void)
if (WARN_ON(l != CCS_L_LAST))
return -EINVAL;
- return i2c_register_driver(THIS_MODULE, &smiapp_i2c_driver);
+ return i2c_register_driver(THIS_MODULE, &ccs_i2c_driver);
}
-static void smiapp_module_cleanup(void)
+static void ccs_module_cleanup(void)
{
- i2c_del_driver(&smiapp_i2c_driver);
+ i2c_del_driver(&ccs_i2c_driver);
}
-module_init(smiapp_module_init);
-module_exit(smiapp_module_cleanup);
+module_init(ccs_module_init);
+module_exit(ccs_module_cleanup);
MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
-MODULE_DESCRIPTION("Generic SMIA/SMIA++ camera module driver");
+MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ camera sensor driver");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/ccs-quirk.c
similarity index 83%
rename from drivers/media/i2c/smiapp/smiapp-quirk.c
rename to drivers/media/i2c/smiapp/ccs-quirk.c
index 5db97a16eccf..6c48d0901952 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.c
+++ b/drivers/media/i2c/smiapp/ccs-quirk.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp/smiapp-quirk.c
+ * drivers/media/i2c/smiapp/ccs-quirk.c
*
* Generic driver for SMIA/SMIA++ compliant camera modules
*
@@ -10,12 +10,11 @@
#include <linux/delay.h>
+#include "ccs.h"
#include "ccs-limits.h"
-#include "smiapp.h"
-
-static int ccs_write_addr_8s(struct smiapp_sensor *sensor,
- const struct smiapp_reg_8 *regs, int len)
+static int ccs_write_addr_8s(struct ccs_sensor *sensor,
+ const struct ccs_reg_8 *regs, int len)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
@@ -33,7 +32,7 @@ static int ccs_write_addr_8s(struct smiapp_sensor *sensor,
return 0;
}
-static int jt8ew9_limits(struct smiapp_sensor *sensor)
+static int jt8ew9_limits(struct ccs_sensor *sensor)
{
if (sensor->minfo.revision_number_major < 0x03)
sensor->frame_skip = 1;
@@ -46,9 +45,9 @@ static int jt8ew9_limits(struct smiapp_sensor *sensor)
return 0;
}
-static int jt8ew9_post_poweron(struct smiapp_sensor *sensor)
+static int jt8ew9_post_poweron(struct ccs_sensor *sensor)
{
- static const struct smiapp_reg_8 regs[] = {
+ static const struct ccs_reg_8 regs[] = {
{ 0x30a3, 0xd8 }, /* Output port control : LVDS ports only */
{ 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
{ 0x30af, 0xd0 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
@@ -84,15 +83,15 @@ static int jt8ew9_post_poweron(struct smiapp_sensor *sensor)
return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
}
-const struct smiapp_quirk smiapp_jt8ew9_quirk = {
+const struct ccs_quirk smiapp_jt8ew9_quirk = {
.limits = jt8ew9_limits,
.post_poweron = jt8ew9_post_poweron,
};
-static int imx125es_post_poweron(struct smiapp_sensor *sensor)
+static int imx125es_post_poweron(struct ccs_sensor *sensor)
{
/* Taken from v02. No idea what the other two are. */
- static const struct smiapp_reg_8 regs[] = {
+ static const struct ccs_reg_8 regs[] = {
/*
* 0x3302: clk during frame blanking:
* 0x00 - HS mode, 0x01 - LP11
@@ -105,11 +104,11 @@ static int imx125es_post_poweron(struct smiapp_sensor *sensor)
return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
}
-const struct smiapp_quirk smiapp_imx125es_quirk = {
+const struct ccs_quirk smiapp_imx125es_quirk = {
.post_poweron = imx125es_post_poweron,
};
-static int jt8ev1_limits(struct smiapp_sensor *sensor)
+static int jt8ev1_limits(struct ccs_sensor *sensor)
{
ccs_replace_limit(sensor, CCS_L_X_ADDR_MAX, 0, 4271);
ccs_replace_limit(sensor, CCS_L_MIN_LINE_BLANKING_PCK_BIN, 0, 184);
@@ -117,11 +116,11 @@ static int jt8ev1_limits(struct smiapp_sensor *sensor)
return 0;
}
-static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
+static int jt8ev1_post_poweron(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
- static const struct smiapp_reg_8 regs[] = {
+ static const struct ccs_reg_8 regs[] = {
{ 0x3031, 0xcd }, /* For digital binning (EQ_MONI) */
{ 0x30a3, 0xd0 }, /* FLASH STROBE enable */
{ 0x3237, 0x00 }, /* For control of pulse timing for ADC */
@@ -142,7 +141,7 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
{ 0x33cf, 0xec }, /* For Black sun */
{ 0x3328, 0x80 }, /* Ugh. No idea what's this. */
};
- static const struct smiapp_reg_8 regs_96[] = {
+ static const struct ccs_reg_8 regs_96[] = {
{ 0x30ae, 0x00 }, /* For control of ADC clock */
{ 0x30af, 0xd0 },
{ 0x30b0, 0x01 },
@@ -163,12 +162,12 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
}
}
-static int jt8ev1_pre_streamon(struct smiapp_sensor *sensor)
+static int jt8ev1_pre_streamon(struct ccs_sensor *sensor)
{
return ccs_write_addr(sensor, 0x3328, 0x00);
}
-static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
+static int jt8ev1_post_streamoff(struct ccs_sensor *sensor)
{
int rval;
@@ -188,14 +187,14 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
return ccs_write_addr(sensor, 0x3328, 0x80);
}
-static int jt8ev1_init(struct smiapp_sensor *sensor)
+static int jt8ev1_init(struct ccs_sensor *sensor)
{
sensor->pll.flags |= SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE;
return 0;
}
-const struct smiapp_quirk smiapp_jt8ev1_quirk = {
+const struct ccs_quirk smiapp_jt8ev1_quirk = {
.limits = jt8ev1_limits,
.post_poweron = jt8ev1_post_poweron,
.pre_streamon = jt8ev1_pre_streamon,
@@ -203,13 +202,13 @@ const struct smiapp_quirk smiapp_jt8ev1_quirk = {
.init = jt8ev1_init,
};
-static int tcm8500md_limits(struct smiapp_sensor *sensor)
+static int tcm8500md_limits(struct ccs_sensor *sensor)
{
ccs_replace_limit(sensor, CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0, 2700000);
return 0;
}
-const struct smiapp_quirk smiapp_tcm8500md_quirk = {
+const struct ccs_quirk smiapp_tcm8500md_quirk = {
.limits = tcm8500md_limits,
};
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.h b/drivers/media/i2c/smiapp/ccs-quirk.h
similarity index 59%
rename from drivers/media/i2c/smiapp/smiapp-quirk.h
rename to drivers/media/i2c/smiapp/ccs-quirk.h
index 8a479f17cd19..d208379158f2 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.h
+++ b/drivers/media/i2c/smiapp/ccs-quirk.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * drivers/media/i2c/smiapp/smiapp-quirk.h
+ * drivers/media/i2c/smiapp/ccs-quirk.h
*
* Generic driver for SMIA/SMIA++ compliant camera modules
*
@@ -8,13 +8,13 @@
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
-#ifndef __SMIAPP_QUIRK__
-#define __SMIAPP_QUIRK__
+#ifndef __CCS_QUIRK__
+#define __CCS_QUIRK__
-struct smiapp_sensor;
+struct ccs_sensor;
/**
- * struct smiapp_quirk - quirks for sensors that deviate from SMIA++ standard
+ * struct ccs_quirk - quirks for sensors that deviate from SMIA++ standard
*
* @limits: Replace sensor->limits with values which can't be read from
* sensor registers. Called the first time the sensor is powered up.
@@ -36,43 +36,43 @@ struct smiapp_sensor;
* access may be done by the caller (default read
* value is zero), else negative error code on error
*/
-struct smiapp_quirk {
- int (*limits)(struct smiapp_sensor *sensor);
- int (*post_poweron)(struct smiapp_sensor *sensor);
- int (*pre_streamon)(struct smiapp_sensor *sensor);
- int (*post_streamoff)(struct smiapp_sensor *sensor);
- unsigned long (*pll_flags)(struct smiapp_sensor *sensor);
- int (*init)(struct smiapp_sensor *sensor);
- int (*reg_access)(struct smiapp_sensor *sensor, bool write, u32 *reg,
+struct ccs_quirk {
+ int (*limits)(struct ccs_sensor *sensor);
+ int (*post_poweron)(struct ccs_sensor *sensor);
+ int (*pre_streamon)(struct ccs_sensor *sensor);
+ int (*post_streamoff)(struct ccs_sensor *sensor);
+ unsigned long (*pll_flags)(struct ccs_sensor *sensor);
+ int (*init)(struct ccs_sensor *sensor);
+ int (*reg_access)(struct ccs_sensor *sensor, bool write, u32 *reg,
u32 *val);
unsigned long flags;
};
-#define SMIAPP_QUIRK_FLAG_8BIT_READ_ONLY (1 << 0)
+#define CCS_QUIRK_FLAG_8BIT_READ_ONLY (1 << 0)
-struct smiapp_reg_8 {
+struct ccs_reg_8 {
u16 reg;
u8 val;
};
-#define SMIAPP_MK_QUIRK_REG_8(_reg, _val) \
+#define CCS_MK_QUIRK_REG_8(_reg, _val) \
{ \
.reg = (u16)_reg, \
.val = _val, \
}
-#define smiapp_call_quirk(sensor, _quirk, ...) \
+#define ccs_call_quirk(sensor, _quirk, ...) \
((sensor)->minfo.quirk && \
(sensor)->minfo.quirk->_quirk ? \
(sensor)->minfo.quirk->_quirk(sensor, ##__VA_ARGS__) : 0)
-#define smiapp_needs_quirk(sensor, _quirk) \
+#define ccs_needs_quirk(sensor, _quirk) \
((sensor)->minfo.quirk ? \
(sensor)->minfo.quirk->flags & _quirk : 0)
-extern const struct smiapp_quirk smiapp_jt8ev1_quirk;
-extern const struct smiapp_quirk smiapp_imx125es_quirk;
-extern const struct smiapp_quirk smiapp_jt8ew9_quirk;
-extern const struct smiapp_quirk smiapp_tcm8500md_quirk;
+extern const struct ccs_quirk smiapp_jt8ev1_quirk;
+extern const struct ccs_quirk smiapp_imx125es_quirk;
+extern const struct ccs_quirk smiapp_jt8ew9_quirk;
+extern const struct ccs_quirk smiapp_tcm8500md_quirk;
-#endif /* __SMIAPP_QUIRK__ */
+#endif /* __CCS_QUIRK__ */
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.c b/drivers/media/i2c/smiapp/ccs-reg-access.c
similarity index 79%
rename from drivers/media/i2c/smiapp/smiapp-regs.c
rename to drivers/media/i2c/smiapp/ccs-reg-access.c
index 173d9f8fe56c..4e6d212473fc 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.c
+++ b/drivers/media/i2c/smiapp/ccs-reg-access.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp/smiapp-regs.c
+ * drivers/media/i2c/smiapp/ccs-regs.c
*
* Generic driver for SMIA/SMIA++ compliant camera modules
*
@@ -13,8 +13,7 @@
#include <linux/delay.h>
#include <linux/i2c.h>
-#include "smiapp.h"
-#include "smiapp-regs.h"
+#include "ccs.h"
static uint32_t float_to_u32_mul_1000000(struct i2c_client *client,
uint32_t phloat)
@@ -66,7 +65,7 @@ static uint32_t float_to_u32_mul_1000000(struct i2c_client *client,
* Read a 8/16/32-bit i2c register. The value is returned in 'val'.
* Returns zero if successful, or non-zero otherwise.
*/
-static int ____ccs_read_addr(struct smiapp_sensor *sensor, u16 reg, u16 len,
+static int ____ccs_read_addr(struct ccs_sensor *sensor, u16 reg, u16 len,
u32 *val)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
@@ -113,7 +112,7 @@ static int ____ccs_read_addr(struct smiapp_sensor *sensor, u16 reg, u16 len,
}
/* Read a register using 8-bit access only. */
-static int ____ccs_read_addr_8only(struct smiapp_sensor *sensor, u16 reg,
+static int ____ccs_read_addr_8only(struct ccs_sensor *sensor, u16 reg,
u16 len, u32 *val)
{
unsigned int i;
@@ -147,7 +146,7 @@ unsigned int ccs_reg_width(u32 reg)
* Read a 8/16/32-bit i2c register. The value is returned in 'val'.
* Returns zero if successful, or non-zero otherwise.
*/
-static int __ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val,
+static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val,
bool only8)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
@@ -155,11 +154,10 @@ static int __ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val,
int rval;
if (!only8)
- rval = ____ccs_read_addr(sensor, SMIAPP_REG_ADDR(reg), len,
- val);
+ rval = ____ccs_read_addr(sensor, CCS_REG_ADDR(reg), len, val);
else
- rval = ____ccs_read_addr_8only(sensor, SMIAPP_REG_ADDR(reg),
- len, val);
+ rval = ____ccs_read_addr_8only(sensor, CCS_REG_ADDR(reg), len,
+ val);
if (rval < 0)
return rval;
@@ -169,21 +167,20 @@ static int __ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val,
return 0;
}
-int ccs_read_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val)
+int ccs_read_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val)
{
return __ccs_read_addr(
sensor, reg, val,
- smiapp_needs_quirk(sensor,
- SMIAPP_QUIRK_FLAG_8BIT_READ_ONLY));
+ ccs_needs_quirk(sensor, CCS_QUIRK_FLAG_8BIT_READ_ONLY));
}
-static int ccs_read_addr_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val,
+static int ccs_read_addr_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val,
bool force8)
{
int rval;
*val = 0;
- rval = smiapp_call_quirk(sensor, reg_access, false, ®, val);
+ rval = ccs_call_quirk(sensor, reg_access, false, ®, val);
if (rval == -ENOIOCTLCMD)
return 0;
if (rval < 0)
@@ -195,17 +192,17 @@ static int ccs_read_addr_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val,
return ccs_read_addr_no_quirk(sensor, reg, val);
}
-int ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val)
+int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val)
{
return ccs_read_addr_quirk(sensor, reg, val, false);
}
-int ccs_read_addr_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val)
+int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val)
{
return ccs_read_addr_quirk(sensor, reg, val, true);
}
-int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
+int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
struct i2c_msg msg;
@@ -222,7 +219,7 @@ int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
msg.len = 2 + len;
msg.buf = data;
- put_unaligned_be16(SMIAPP_REG_ADDR(reg), data);
+ put_unaligned_be16(CCS_REG_ADDR(reg), data);
put_unaligned_be32(val << (8 * (sizeof(val) - len)), data + 2);
for (retries = 0; retries < 5; retries++) {
@@ -245,7 +242,7 @@ int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
dev_err(&client->dev,
"wrote 0x%x to offset 0x%x error %d\n", val,
- SMIAPP_REG_ADDR(reg), r);
+ CCS_REG_ADDR(reg), r);
return r;
}
@@ -254,11 +251,11 @@ int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
* Write to a 8/16-bit register.
* Returns zero if successful, or non-zero otherwise.
*/
-int ccs_write_addr(struct smiapp_sensor *sensor, u32 reg, u32 val)
+int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val)
{
int rval;
- rval = smiapp_call_quirk(sensor, reg_access, true, ®, &val);
+ rval = ccs_call_quirk(sensor, reg_access, true, ®, &val);
if (rval == -ENOIOCTLCMD)
return 0;
if (rval < 0)
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/ccs-reg-access.h
similarity index 55%
rename from drivers/media/i2c/smiapp/smiapp-regs.h
rename to drivers/media/i2c/smiapp/ccs-reg-access.h
index 5df794f65dfc..76ac036a9538 100644
--- a/drivers/media/i2c/smiapp/smiapp-regs.h
+++ b/drivers/media/i2c/smiapp/ccs-reg-access.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * include/media/smiapp/smiapp-regs.h
+ * include/media/smiapp/ccs-regs.h
*
* Generic driver for SMIA/SMIA++ compliant camera modules
*
@@ -16,15 +16,15 @@
#include "ccs-regs.h"
-#define SMIAPP_REG_ADDR(reg) ((u16)reg)
+#define CCS_REG_ADDR(reg) ((u16)reg)
-struct smiapp_sensor;
+struct ccs_sensor;
-int ccs_read_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int ccs_read_addr_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val);
-int ccs_write_addr(struct smiapp_sensor *sensor, u32 reg, u32 val);
+int ccs_read_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val);
+int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val);
unsigned int ccs_reg_width(u32 reg);
diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/ccs.h
similarity index 65%
rename from drivers/media/i2c/smiapp/smiapp.h
rename to drivers/media/i2c/smiapp/ccs.h
index c6e4e05a7522..20b1125d87dc 100644
--- a/drivers/media/i2c/smiapp/smiapp.h
+++ b/drivers/media/i2c/smiapp/ccs.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * drivers/media/i2c/smiapp/smiapp.h
+ * drivers/media/i2c/smiapp/ccs.h
*
* Generic driver for SMIA/SMIA++ compliant camera modules
*
@@ -8,19 +8,18 @@
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
-#ifndef __SMIAPP_PRIV_H_
-#define __SMIAPP_PRIV_H_
+#ifndef __CCS_H__
+#define __CCS_H__
#include <linux/mutex.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
+#include "ccs-quirk.h"
#include "ccs-regs.h"
-
-#include "smiapp-pll.h"
+#include "ccs-reg-access.h"
+#include "../smiapp-pll.h"
#include "smiapp-reg-defs.h"
-#include "smiapp-regs.h"
-#include "smiapp-quirk.h"
/*
* Standard SMIA++ constants
@@ -41,12 +40,13 @@
(1000 + (SMIAPP_RESET_DELAY_CLOCKS * 1000 \
+ (clk) / 1000 - 1) / ((clk) / 1000))
-#define SMIAPP_COLOUR_COMPONENTS 4
+#define CCS_COLOUR_COMPONENTS 4
-#define SMIAPP_NAME "smiapp"
+#define SMIAPP_NAME "smiapp"
+#define CCS_NAME "ccs"
-#define SMIAPP_DFL_I2C_ADDR (0x20 >> 1) /* Default I2C Address */
-#define SMIAPP_ALT_I2C_ADDR (0x6e >> 1) /* Alternate I2C Address */
+#define CCS_DFL_I2C_ADDR (0x20 >> 1) /* Default I2C Address */
+#define CCS_ALT_I2C_ADDR (0x6e >> 1) /* Alternate I2C Address */
/*
* Sometimes due to board layout considerations the camera module can be
@@ -54,12 +54,12 @@
* corrected by giving a default H-FLIP and V-FLIP in the sensor readout.
* FIXME: rotation also changes the bayer pattern.
*/
-enum smiapp_module_board_orient {
- SMIAPP_MODULE_BOARD_ORIENT_0 = 0,
- SMIAPP_MODULE_BOARD_ORIENT_180,
+enum ccs_module_board_orient {
+ CCS_MODULE_BOARD_ORIENT_0 = 0,
+ CCS_MODULE_BOARD_ORIENT_180,
};
-struct smiapp_flash_strobe_parms {
+struct ccs_flash_strobe_parms {
u8 mode;
u32 strobe_width_high_us;
u16 strobe_delay;
@@ -67,7 +67,7 @@ struct smiapp_flash_strobe_parms {
u8 trigger;
};
-struct smiapp_hwconfig {
+struct ccs_hwconfig {
/*
* Change the cci address if i2c_addr_alt is set.
* Both default and alternate cci addr need to be present
@@ -78,19 +78,19 @@ struct smiapp_hwconfig {
uint32_t ext_clk; /* sensor external clk */
unsigned int lanes; /* Number of CSI-2 lanes */
- uint32_t csi_signalling_mode; /* SMIAPP_CSI_SIGNALLING_MODE_* */
+ uint32_t csi_signalling_mode; /* CCS_CSI_SIGNALLING_MODE_* */
uint64_t *op_sys_clock;
- enum smiapp_module_board_orient module_board_orient;
+ enum ccs_module_board_orient module_board_orient;
- struct smiapp_flash_strobe_parms *strobe_setup;
+ struct ccs_flash_strobe_parms *strobe_setup;
};
-struct smiapp_quirk;
+struct ccs_quirk;
-#define SMIAPP_MODULE_IDENT_FLAG_REV_LE (1 << 0)
+#define CCS_MODULE_IDENT_FLAG_REV_LE (1 << 0)
-struct smiapp_module_ident {
+struct ccs_module_ident {
u16 mipi_manufacturer_id;
u16 model_id;
u8 smia_manufacturer_id;
@@ -99,10 +99,10 @@ struct smiapp_module_ident {
u8 flags;
char *name;
- const struct smiapp_quirk *quirk;
+ const struct ccs_quirk *quirk;
};
-struct smiapp_module_info {
+struct ccs_module_info {
u32 smia_manufacturer_id;
u32 mipi_manufacturer_id;
u32 model_id;
@@ -126,10 +126,10 @@ struct smiapp_module_info {
u32 smiapp_profile;
char *name;
- const struct smiapp_quirk *quirk;
+ const struct ccs_quirk *quirk;
};
-#define SMIAPP_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \
+#define CCS_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \
{ .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
@@ -137,22 +137,22 @@ struct smiapp_module_info {
.name = _name, \
.quirk = _quirk, }
-#define SMIAPP_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \
+#define CCS_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \
{ .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
- .flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \
+ .flags = CCS_MODULE_IDENT_FLAG_REV_LE, \
.name = _name, \
.quirk = _quirk, }
-#define SMIAPP_IDENT_L(manufacturer, model, rev, _name) \
+#define CCS_IDENT_L(manufacturer, model, rev, _name) \
{ .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
- .flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \
+ .flags = CCS_MODULE_IDENT_FLAG_REV_LE, \
.name = _name, }
-#define SMIAPP_IDENT_Q(manufacturer, model, rev, _name, _quirk) \
+#define CCS_IDENT_Q(manufacturer, model, rev, _name, _quirk) \
{ .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
@@ -160,49 +160,49 @@ struct smiapp_module_info {
.name = _name, \
.quirk = _quirk, }
-#define SMIAPP_IDENT(manufacturer, model, rev, _name) \
+#define CCS_IDENT(manufacturer, model, rev, _name) \
{ .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = 0, \
.name = _name, }
-struct smiapp_csi_data_format {
+struct ccs_csi_data_format {
u32 code;
u8 width;
u8 compressed;
u8 pixel_order;
};
-#define SMIAPP_SUBDEVS 3
+#define CCS_SUBDEVS 3
-#define SMIAPP_PA_PAD_SRC 0
-#define SMIAPP_PAD_SINK 0
-#define SMIAPP_PAD_SRC 1
-#define SMIAPP_PADS 2
+#define CCS_PA_PAD_SRC 0
+#define CCS_PAD_SINK 0
+#define CCS_PAD_SRC 1
+#define CCS_PADS 2
-struct smiapp_binning_subtype {
+struct ccs_binning_subtype {
u8 horizontal:4;
u8 vertical:4;
} __packed;
-struct smiapp_subdev {
+struct ccs_subdev {
struct v4l2_subdev sd;
- struct media_pad pads[SMIAPP_PADS];
+ struct media_pad pads[CCS_PADS];
struct v4l2_rect sink_fmt;
- struct v4l2_rect crop[SMIAPP_PADS];
+ struct v4l2_rect crop[CCS_PADS];
struct v4l2_rect compose; /* compose on sink */
unsigned short sink_pad;
unsigned short source_pad;
int npads;
- struct smiapp_sensor *sensor;
+ struct ccs_sensor *sensor;
struct v4l2_ctrl_handler ctrl_handler;
};
/*
- * struct smiapp_sensor - Main device structure
+ * struct ccs_sensor - Main device structure
*/
-struct smiapp_sensor {
+struct ccs_sensor {
/*
* "mutex" is used to serialise access to all fields here
* except v4l2_ctrls at the end of the struct. "mutex" is also
@@ -210,22 +210,22 @@ struct smiapp_sensor {
* information.
*/
struct mutex mutex;
- struct smiapp_subdev ssds[SMIAPP_SUBDEVS];
+ struct ccs_subdev ssds[CCS_SUBDEVS];
u32 ssds_used;
- struct smiapp_subdev *src;
- struct smiapp_subdev *binner;
- struct smiapp_subdev *scaler;
- struct smiapp_subdev *pixel_array;
- struct smiapp_hwconfig *hwcfg;
+ struct ccs_subdev *src;
+ struct ccs_subdev *binner;
+ struct ccs_subdev *scaler;
+ struct ccs_subdev *pixel_array;
+ struct ccs_hwconfig *hwcfg;
struct regulator *vana;
struct clk *ext_clk;
struct gpio_desc *xshutdown;
void *ccs_limits;
u8 nbinning_subtypes;
- struct smiapp_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1];
+ struct ccs_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1];
u32 mbus_frame_fmts;
- const struct smiapp_csi_data_format *csi_format;
- const struct smiapp_csi_data_format *internal_csi_format;
+ const struct ccs_csi_data_format *csi_format;
+ const struct ccs_csi_data_format *internal_csi_format;
u32 default_mbus_frame_fmts;
int default_pixel_order;
@@ -246,7 +246,7 @@ struct smiapp_sensor {
bool dev_init_done;
u8 compressed_min_bpp;
- struct smiapp_module_info minfo;
+ struct ccs_module_info minfo;
struct smiapp_pll pll;
@@ -265,16 +265,16 @@ struct smiapp_sensor {
struct v4l2_ctrl *link_freq;
struct v4l2_ctrl *pixel_rate_csi;
/* test pattern colour components */
- struct v4l2_ctrl *test_data[SMIAPP_COLOUR_COMPONENTS];
+ struct v4l2_ctrl *test_data[CCS_COLOUR_COMPONENTS];
};
-#define to_smiapp_subdev(_sd) \
- container_of(_sd, struct smiapp_subdev, sd)
+#define to_ccs_subdev(_sd) \
+ container_of(_sd, struct ccs_subdev, sd)
-#define to_smiapp_sensor(_sd) \
- (to_smiapp_subdev(_sd)->sensor)
+#define to_ccs_sensor(_sd) \
+ (to_ccs_subdev(_sd)->sensor)
-void ccs_replace_limit(struct smiapp_sensor *sensor,
+void ccs_replace_limit(struct ccs_sensor *sensor,
unsigned int limit, unsigned int offset, u32 val);
-#endif /* __SMIAPP_PRIV_H_ */
+#endif /* __CCS_H__ */
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 18/29] smiapp: Differentiate CCS sensors from SMIA in subdev naming
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (16 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 17/29] smiapp: Internal rename to CCS Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 19/29] smiapp: Rename as "ccs" Sakari Ailus
` (10 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Call CCS compliant sensors as "ccs" instead of "smiapp" in absence of a
device specific name. This is done based on the value of the manufacturer
ID register that is only present in CCS.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/smiapp/ccs-core.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/media/i2c/smiapp/ccs-core.c b/drivers/media/i2c/smiapp/ccs-core.c
index f9dbf1407a33..30c4d8edce9d 100644
--- a/drivers/media/i2c/smiapp/ccs-core.c
+++ b/drivers/media/i2c/smiapp/ccs-core.c
@@ -2437,8 +2437,6 @@ static int ccs_identify_module(struct ccs_sensor *sensor)
unsigned int i;
int rval = 0;
- minfo->name = SMIAPP_NAME;
-
/* Module info */
rval = ccs_read(sensor, MODULE_MANUFACTURER_ID,
&minfo->mipi_manufacturer_id);
@@ -2528,15 +2526,18 @@ static int ccs_identify_module(struct ccs_sensor *sensor)
"sensor revision 0x%2.2x firmware version 0x%2.2x\n",
minfo->sensor_revision_number, minfo->sensor_firmware_version);
- if (minfo->ccs_version)
+ if (minfo->ccs_version) {
dev_dbg(&client->dev, "MIPI CCS version %u.%u",
(minfo->ccs_version & CCS_MIPI_CCS_VERSION_MAJOR_MASK)
>> CCS_MIPI_CCS_VERSION_MAJOR_SHIFT,
(minfo->ccs_version & CCS_MIPI_CCS_VERSION_MINOR_MASK));
- else
+ minfo->name = CCS_NAME;
+ } else {
dev_dbg(&client->dev,
"smia version %2.2d smiapp version %2.2d\n",
minfo->smia_version, minfo->smiapp_version);
+ minfo->name = SMIAPP_NAME;
+ }
/*
* Some modules have bad data in the lvalues below. Hope the
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 19/29] smiapp: Rename as "ccs"
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (17 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 18/29] smiapp: Differentiate CCS sensors from SMIA in subdev naming Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 20/29] ccs: Remove profile concept Sakari Ailus
` (9 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Rename the "smiapp" driver as "ccs". MIPI CCS is the contemporary standard
for raw Bayer camera sensors. The driver retains support for the SMIA++
and SMIA compliant camera sensors. A module alias is added for old user
space using "smiapp" module name.
Add Intel copyright while at it.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
MAINTAINERS | 22 +++++++++----------
drivers/media/i2c/Kconfig | 2 +-
drivers/media/i2c/Makefile | 2 +-
drivers/media/i2c/{smiapp => ccs}/Kconfig | 7 +++---
drivers/media/i2c/{smiapp => ccs}/Makefile | 4 ++--
drivers/media/i2c/{smiapp => ccs}/ccs-core.c | 6 +++--
.../media/i2c/{smiapp => ccs}/ccs-limits.c | 0
.../media/i2c/{smiapp => ccs}/ccs-limits.h | 0
drivers/media/i2c/{smiapp => ccs}/ccs-quirk.c | 5 +++--
drivers/media/i2c/{smiapp => ccs}/ccs-quirk.h | 5 +++--
.../i2c/{smiapp => ccs}/ccs-reg-access.c | 5 +++--
.../i2c/{smiapp => ccs}/ccs-reg-access.h | 5 +++--
drivers/media/i2c/{smiapp => ccs}/ccs-regs.h | 0
drivers/media/i2c/{smiapp => ccs}/ccs.h | 3 ++-
.../i2c/{smiapp => ccs}/smiapp-reg-defs.h | 3 ++-
15 files changed, 39 insertions(+), 30 deletions(-)
rename drivers/media/i2c/{smiapp => ccs}/Kconfig (55%)
rename drivers/media/i2c/{smiapp => ccs}/Makefile (57%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-core.c (99%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-limits.c (100%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-limits.h (100%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-quirk.c (97%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-quirk.h (94%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-reg-access.c (97%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-reg-access.h (86%)
rename drivers/media/i2c/{smiapp => ccs}/ccs-regs.h (100%)
rename drivers/media/i2c/{smiapp => ccs}/ccs.h (98%)
rename drivers/media/i2c/{smiapp => ccs}/smiapp-reg-defs.h (99%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1a5455e1c664..c6771cfd84d4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11662,6 +11662,17 @@ M: Oliver Neukum <oliver@neukum.org>
S: Maintained
F: drivers/usb/image/microtek.*
+MIPI CCS, SMIA AND SMIA++ IMAGE SENSOR DRIVER
+M: Sakari Ailus <sakari.ailus@linux.intel.com>
+L: linux-media@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
+F: Documentation/driver-api/media/drivers/ccs/
+F: drivers/media/i2c/ccs/
+F: drivers/media/i2c/smiapp-pll.c
+F: drivers/media/i2c/smiapp-pll.h
+F: include/uapi/linux/smiapp.h
+
MIPS
M: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
L: linux-mips@vger.kernel.org
@@ -16130,17 +16141,6 @@ S: Maintained
F: drivers/firmware/smccc/
F: include/linux/arm-smccc.h
-SMIA AND SMIA++ IMAGE SENSOR DRIVER
-M: Sakari Ailus <sakari.ailus@linux.intel.com>
-L: linux-media@vger.kernel.org
-S: Maintained
-F: Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
-F: Documentation/driver-api/media/drivers/ccs/
-F: drivers/media/i2c/smiapp-pll.c
-F: drivers/media/i2c/smiapp-pll.h
-F: drivers/media/i2c/smiapp/
-F: include/uapi/linux/smiapp.h
-
SMM665 HARDWARE MONITOR DRIVER
M: Guenter Roeck <linux@roeck-us.net>
L: linux-hwmon@vger.kernel.org
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index c64326ca331c..41a8b6189259 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -1233,7 +1233,7 @@ config VIDEO_S5K5BAF
This is a V4L2 sensor driver for Samsung S5K5BAF 2M
camera sensor with an embedded SoC image signal processor.
-source "drivers/media/i2c/smiapp/Kconfig"
+source "drivers/media/i2c/ccs/Kconfig"
source "drivers/media/i2c/et8ek8/Kconfig"
config VIDEO_S5C73M3
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index f0a77473979d..cb0be09e38bd 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -2,7 +2,7 @@
msp3400-objs := msp3400-driver.o msp3400-kthreads.o
obj-$(CONFIG_VIDEO_MSP3400) += msp3400.o
-obj-$(CONFIG_VIDEO_SMIAPP) += smiapp/
+obj-$(CONFIG_VIDEO_CCS) += ccs/
obj-$(CONFIG_VIDEO_ET8EK8) += et8ek8/
obj-$(CONFIG_VIDEO_CX25840) += cx25840/
obj-$(CONFIG_VIDEO_M5MOLS) += m5mols/
diff --git a/drivers/media/i2c/smiapp/Kconfig b/drivers/media/i2c/ccs/Kconfig
similarity index 55%
rename from drivers/media/i2c/smiapp/Kconfig
rename to drivers/media/i2c/ccs/Kconfig
index 6893b532824f..b4f8b10da420 100644
--- a/drivers/media/i2c/smiapp/Kconfig
+++ b/drivers/media/i2c/ccs/Kconfig
@@ -1,10 +1,11 @@
# SPDX-License-Identifier: GPL-2.0-only
-config VIDEO_SMIAPP
- tristate "SMIA++/SMIA sensor support"
+config VIDEO_CCS
+ tristate "MIPI CCS/SMIA++/SMIA sensor support"
depends on I2C && VIDEO_V4L2 && HAVE_CLK
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select VIDEO_SMIAPP_PLL
select V4L2_FWNODE
help
- This is a generic driver for SMIA++/SMIA camera modules.
+ This is a generic driver for MIPI CCS, SMIA++ and SMIA compliant
+ camera sensors.
diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/ccs/Makefile
similarity index 57%
rename from drivers/media/i2c/smiapp/Makefile
rename to drivers/media/i2c/ccs/Makefile
index c9d300b5d2bc..08dd4e948fb0 100644
--- a/drivers/media/i2c/smiapp/Makefile
+++ b/drivers/media/i2c/ccs/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-smiapp-objs += ccs-core.o ccs-reg-access.o \
+ccs-objs += ccs-core.o ccs-reg-access.o \
ccs-quirk.o ccs-limits.o
-obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o
+obj-$(CONFIG_VIDEO_CCS) += ccs.o
ccflags-y += -I $(srctree)/drivers/media/i2c
diff --git a/drivers/media/i2c/smiapp/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
similarity index 99%
rename from drivers/media/i2c/smiapp/ccs-core.c
rename to drivers/media/i2c/ccs/ccs-core.c
index 30c4d8edce9d..2dfb26cb3a40 100644
--- a/drivers/media/i2c/smiapp/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp/ccs-core.c
+ * drivers/media/i2c/ccs/ccs-core.c
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2010--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*
@@ -3298,3 +3299,4 @@ module_exit(ccs_module_cleanup);
MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ camera sensor driver");
MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("smiapp");
diff --git a/drivers/media/i2c/smiapp/ccs-limits.c b/drivers/media/i2c/ccs/ccs-limits.c
similarity index 100%
rename from drivers/media/i2c/smiapp/ccs-limits.c
rename to drivers/media/i2c/ccs/ccs-limits.c
diff --git a/drivers/media/i2c/smiapp/ccs-limits.h b/drivers/media/i2c/ccs/ccs-limits.h
similarity index 100%
rename from drivers/media/i2c/smiapp/ccs-limits.h
rename to drivers/media/i2c/ccs/ccs-limits.h
diff --git a/drivers/media/i2c/smiapp/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c
similarity index 97%
rename from drivers/media/i2c/smiapp/ccs-quirk.c
rename to drivers/media/i2c/ccs/ccs-quirk.c
index 6c48d0901952..5a24da1d7aa9 100644
--- a/drivers/media/i2c/smiapp/ccs-quirk.c
+++ b/drivers/media/i2c/ccs/ccs-quirk.c
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp/ccs-quirk.c
+ * drivers/media/i2c/ccs/ccs-quirk.c
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
diff --git a/drivers/media/i2c/smiapp/ccs-quirk.h b/drivers/media/i2c/ccs/ccs-quirk.h
similarity index 94%
rename from drivers/media/i2c/smiapp/ccs-quirk.h
rename to drivers/media/i2c/ccs/ccs-quirk.h
index d208379158f2..3e7779e2fc4b 100644
--- a/drivers/media/i2c/smiapp/ccs-quirk.h
+++ b/drivers/media/i2c/ccs/ccs-quirk.h
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * drivers/media/i2c/smiapp/ccs-quirk.h
+ * drivers/media/i2c/ccs/ccs-quirk.h
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
diff --git a/drivers/media/i2c/smiapp/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
similarity index 97%
rename from drivers/media/i2c/smiapp/ccs-reg-access.c
rename to drivers/media/i2c/ccs/ccs-reg-access.c
index 4e6d212473fc..a8e9a235bfb3 100644
--- a/drivers/media/i2c/smiapp/ccs-reg-access.c
+++ b/drivers/media/i2c/ccs/ccs-reg-access.c
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp/ccs-regs.c
+ * drivers/media/i2c/ccs/ccs-reg-access.c
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
diff --git a/drivers/media/i2c/smiapp/ccs-reg-access.h b/drivers/media/i2c/ccs/ccs-reg-access.h
similarity index 86%
rename from drivers/media/i2c/smiapp/ccs-reg-access.h
rename to drivers/media/i2c/ccs/ccs-reg-access.h
index 76ac036a9538..9fdf5659ed09 100644
--- a/drivers/media/i2c/smiapp/ccs-reg-access.h
+++ b/drivers/media/i2c/ccs/ccs-reg-access.h
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * include/media/smiapp/ccs-regs.h
+ * include/media/ccs/ccs-reg-access.h
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
diff --git a/drivers/media/i2c/smiapp/ccs-regs.h b/drivers/media/i2c/ccs/ccs-regs.h
similarity index 100%
rename from drivers/media/i2c/smiapp/ccs-regs.h
rename to drivers/media/i2c/ccs/ccs-regs.h
diff --git a/drivers/media/i2c/smiapp/ccs.h b/drivers/media/i2c/ccs/ccs.h
similarity index 98%
rename from drivers/media/i2c/smiapp/ccs.h
rename to drivers/media/i2c/ccs/ccs.h
index 20b1125d87dc..7f6ed95b7b78 100644
--- a/drivers/media/i2c/smiapp/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -2,8 +2,9 @@
/*
* drivers/media/i2c/smiapp/ccs.h
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2010--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
diff --git a/drivers/media/i2c/smiapp/smiapp-reg-defs.h b/drivers/media/i2c/ccs/smiapp-reg-defs.h
similarity index 99%
rename from drivers/media/i2c/smiapp/smiapp-reg-defs.h
rename to drivers/media/i2c/ccs/smiapp-reg-defs.h
index 06b69b1ab55f..e80c110ebf3a 100644
--- a/drivers/media/i2c/smiapp/smiapp-reg-defs.h
+++ b/drivers/media/i2c/ccs/smiapp-reg-defs.h
@@ -2,8 +2,9 @@
/*
* drivers/media/i2c/smiapp/smiapp-reg-defs.h
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 20/29] ccs: Remove profile concept
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (18 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 19/29] smiapp: Rename as "ccs" Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 21/29] ccs: Give all subdevs a function Sakari Ailus
` (8 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
The driver doesn't do anything tangible with profiles. Remove the notion,
and use the capabilities directly.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 23 ++++++-----------------
drivers/media/i2c/ccs/ccs.h | 2 --
2 files changed, 6 insertions(+), 19 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 2dfb26cb3a40..cc3a81200050 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -377,7 +377,7 @@ static int ccs_pll_configure(struct ccs_sensor *sensor)
rval = ccs_write(sensor, REQUESTED_LINK_RATE,
DIV_ROUND_UP(pll->op.sys_clk_freq_hz,
1000000 / 256 / 256));
- if (rval < 0 || sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
+ if (rval < 0 || sensor->pll.flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)
return rval;
rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op.pix_clk_div);
@@ -3096,23 +3096,17 @@ static int ccs_probe(struct i2c_client *client)
}
}
- /* We consider this as profile 0 sensor if any of these are zero. */
if (!CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV) ||
!CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV) ||
!CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV) ||
!CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
- sensor->minfo.smiapp_profile = SMIAPP_PROFILE_0;
+ /* No OP clock branch */
+ sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS;
} else if (CCS_LIM(sensor, SCALING_CAPABILITY)
- != CCS_SCALING_CAPABILITY_NONE) {
- if (CCS_LIM(sensor, SCALING_CAPABILITY)
- == CCS_SCALING_CAPABILITY_HORIZONTAL)
- sensor->minfo.smiapp_profile = SMIAPP_PROFILE_1;
- else
- sensor->minfo.smiapp_profile = SMIAPP_PROFILE_2;
- sensor->scaler = &sensor->ssds[sensor->ssds_used];
- sensor->ssds_used++;
- } else if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE ||
+ CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
== CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
+ /* We have a scaler or digital crop. */
sensor->scaler = &sensor->ssds[sensor->ssds_used];
sensor->ssds_used++;
}
@@ -3128,16 +3122,11 @@ static int ccs_probe(struct i2c_client *client)
sensor->pll.csi2.lanes = sensor->hwcfg->lanes;
sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
- /* Profile 0 sensors have no separate OP clock branch. */
- if (sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
- sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS;
ccs_create_subdev(sensor, sensor->scaler, " scaler", 2);
ccs_create_subdev(sensor, sensor->binner, " binner", 2);
ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1);
- dev_dbg(&client->dev, "profile %d\n", sensor->minfo.smiapp_profile);
-
sensor->pixel_array->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
rval = ccs_init_controls(sensor);
diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
index 7f6ed95b7b78..8933f3d40fa5 100644
--- a/drivers/media/i2c/ccs/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -124,8 +124,6 @@ struct ccs_module_info {
u32 smiapp_version;
u32 ccs_version;
- u32 smiapp_profile;
-
char *name;
const struct ccs_quirk *quirk;
};
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 21/29] ccs: Give all subdevs a function
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (19 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 20/29] ccs: Remove profile concept Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 22/29] dt-bindings: nokia,smia: Fix link-frequencies documentation Sakari Ailus
` (7 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
This removes a warning at driver probe time telling that one or two
entities have no function set. The function used for both the binner and
scaler is the scaler.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index cc3a81200050..bddfee637f33 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -2685,7 +2685,7 @@ static void ccs_cleanup(struct ccs_sensor *sensor)
static void ccs_create_subdev(struct ccs_sensor *sensor,
struct ccs_subdev *ssd, const char *name,
- unsigned short num_pads)
+ unsigned short num_pads, u32 function)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
@@ -2696,6 +2696,7 @@ static void ccs_create_subdev(struct ccs_sensor *sensor,
v4l2_subdev_init(&ssd->sd, &ccs_ops);
ssd->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ ssd->sd.entity.function = function;
ssd->sensor = sensor;
ssd->npads = num_pads;
@@ -3123,11 +3124,12 @@ static int ccs_probe(struct i2c_client *client)
sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
- ccs_create_subdev(sensor, sensor->scaler, " scaler", 2);
- ccs_create_subdev(sensor, sensor->binner, " binner", 2);
- ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1);
-
- sensor->pixel_array->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
+ ccs_create_subdev(sensor, sensor->scaler, " scaler", 2,
+ MEDIA_ENT_F_CAM_SENSOR);
+ ccs_create_subdev(sensor, sensor->binner, " binner", 2,
+ MEDIA_ENT_F_PROC_VIDEO_SCALER);
+ ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1,
+ MEDIA_ENT_F_PROC_VIDEO_SCALER);
rval = ccs_init_controls(sensor);
if (rval < 0)
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 22/29] dt-bindings: nokia,smia: Fix link-frequencies documentation
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (20 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 21/29] ccs: Give all subdevs a function Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 23/29] dt-bindings: nokia,smia: Make vana-supply optional Sakari Ailus
` (6 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
The link-frequencies property belongs to the endpoint, not to the node
representing the device.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/media/i2c/nokia,smia.txt | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
index 10ece8108081..6c45c79ef91f 100644
--- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
+++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
@@ -20,8 +20,6 @@ Mandatory properties
dependent).
- clocks: External clock to the sensor
- clock-frequency: Frequency of the external clock to the sensor
-- link-frequencies: List of allowed data link frequencies. An array of
- 64-bit elements.
Optional properties
@@ -39,6 +37,8 @@ Endpoint node mandatory properties
----------------------------------
- data-lanes: <1..n>
+- link-frequencies: List of allowed data link frequencies. An array of
+ 64-bit elements.
Example
@@ -55,11 +55,13 @@ Example
clocks = <&omap3_isp 0>;
clock-frequency = <9600000>;
nokia,nvm-size = <512>; /* 8 * 64 */
- link-frequencies = /bits/ 64 <199200000 210000000 499200000>;
port {
smiapp_ep: endpoint {
data-lanes = <1 2>;
remote-endpoint = <&csi2a_ep>;
+ link-frequencies =
+ /bits/ 64 <199200000 210000000
+ 499200000>;
};
};
};
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 23/29] dt-bindings: nokia,smia: Make vana-supply optional
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (21 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 22/29] dt-bindings: nokia,smia: Fix link-frequencies documentation Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 24/29] dt-bindings: nokia,smia: Remove nokia,nvm-size property Sakari Ailus
` (5 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
vana-supply is optional in the spec, therefore make it optional in
bindings, too.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/media/i2c/nokia,smia.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
index 6c45c79ef91f..5ea4f799877b 100644
--- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
+++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
@@ -16,8 +16,6 @@ Mandatory properties
- compatible: "nokia,smia"
- reg: I2C address (0x10, or an alternative address)
-- vana-supply: Analogue voltage supply (VANA), typically 2,8 volts (sensor
- dependent).
- clocks: External clock to the sensor
- clock-frequency: Frequency of the external clock to the sensor
@@ -31,6 +29,8 @@ Optional properties
- rotation: Integer property; valid values are 0 (sensor mounted upright)
and 180 (sensor mounted upside down). See
../video-interfaces.txt .
+- vana-supply: Analogue voltage supply (VANA), typically 2,8 volts (sensor
+ dependent).
Endpoint node mandatory properties
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 24/29] dt-bindings: nokia,smia: Remove nokia,nvm-size property
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (22 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 23/29] dt-bindings: nokia,smia: Make vana-supply optional Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 25/29] dt-bindings: nokia,smia: Convert to YAML Sakari Ailus
` (4 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
nokia,nvm-size property was removed from the bindings but it was left in
the example. Remove it from the example, too.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/media/i2c/nokia,smia.txt | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
index 5ea4f799877b..5f39a7070c51 100644
--- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
+++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
@@ -54,7 +54,6 @@ Example
vana-supply = <&vaux3>;
clocks = <&omap3_isp 0>;
clock-frequency = <9600000>;
- nokia,nvm-size = <512>; /* 8 * 64 */
port {
smiapp_ep: endpoint {
data-lanes = <1 2>;
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 25/29] dt-bindings: nokia,smia: Convert to YAML
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (23 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 24/29] dt-bindings: nokia,smia: Remove nokia,nvm-size property Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 26/29] dt-bindings: nokia,smia: Use better active polarity for reset Sakari Ailus
` (3 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Convert nokia,smia DT bindings to YAML.
Also add explicit license to bindings.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/media/i2c/nokia,smia.txt | 67 -----------
.../bindings/media/i2c/nokia,smia.yaml | 106 ++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 107 insertions(+), 68 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
create mode 100644 Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
deleted file mode 100644
index 5f39a7070c51..000000000000
--- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-SMIA/SMIA++ sensor
-
-SMIA (Standard Mobile Imaging Architecture) is an image sensor standard
-defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension
-of that. These definitions are valid for both types of sensors.
-
-More detailed documentation can be found in
-Documentation/devicetree/bindings/media/video-interfaces.txt .
-
-The device node should contain a "port" node which may contain one or more
-endpoint nodes, in accordance with video interface bindings defined in
-Documentation/devicetree/bindings/media/video-interfaces.txt .
-
-Mandatory properties
---------------------
-
-- compatible: "nokia,smia"
-- reg: I2C address (0x10, or an alternative address)
-- clocks: External clock to the sensor
-- clock-frequency: Frequency of the external clock to the sensor
-
-
-Optional properties
--------------------
-
-- reset-gpios: XSHUTDOWN GPIO
-- flash-leds: See ../video-interfaces.txt
-- lens-focus: See ../video-interfaces.txt
-- rotation: Integer property; valid values are 0 (sensor mounted upright)
- and 180 (sensor mounted upside down). See
- ../video-interfaces.txt .
-- vana-supply: Analogue voltage supply (VANA), typically 2,8 volts (sensor
- dependent).
-
-
-Endpoint node mandatory properties
-----------------------------------
-
-- data-lanes: <1..n>
-- link-frequencies: List of allowed data link frequencies. An array of
- 64-bit elements.
-
-
-Example
--------
-
-&i2c2 {
- clock-frequency = <400000>;
-
- camera-sensor@10 {
- compatible = "nokia,smia";
- reg = <0x10>;
- reset-gpios = <&gpio3 20 0>;
- vana-supply = <&vaux3>;
- clocks = <&omap3_isp 0>;
- clock-frequency = <9600000>;
- port {
- smiapp_ep: endpoint {
- data-lanes = <1 2>;
- remote-endpoint = <&csi2a_ep>;
- link-frequencies =
- /bits/ 64 <199200000 210000000
- 499200000>;
- };
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml b/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
new file mode 100644
index 000000000000..ee552489fa2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2014--2020 Intel Corporation
+
+$id: http://devicetree.org/schemas/media/i2c/nokia,smia.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SMIA/SMIA++ sensor
+
+maintainers:
+ - Sakari Ailus <sakari.ailus@linux.intel.com>
+
+description:
+
+ SMIA (Standard Mobile Imaging Architecture) is an image sensor standard
+ defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension of
+ that. These definitions are valid for both types of sensors.
+
+ More detailed documentation can be found in
+ Documentation/devicetree/bindings/media/video-interfaces.txt .
+
+properties:
+ compatible:
+ const: nokia,smia
+
+ reg:
+ maxItems: 1
+
+ vana-supply:
+ description: Analogue voltage supply (VANA), typically 2,8 volts (sensor
+ dependent).
+ maxItems: 1
+
+ clocks:
+ description: External clock to the sensor.
+ maxItems: 1
+
+ clock-frequency:
+ description: Frequency of the external clock to the sensor in Hz.
+
+ reset-gpios:
+ description: Reset GPIO. Also commonly called XSHUTDOWN in hardware
+ documentation.
+ maxItems: 1
+
+ flash-leds:
+ description: Flash LED phandles. See ../video-interfaces.txt for details.
+
+ lens-focus:
+ description: Lens focus controller phandles. See ../video-interfaces.txt
+ for details.
+
+ rotation:
+ description: Rotation of the sensor. See ../video-interfaces.txt for
+ details.
+ enum: [ 0, 180 ]
+
+ port:
+ type: object
+ properties:
+ endpoint:
+ type: object
+ properties:
+ link-frequencies:
+ $ref: /schemas/types.yaml#/definitions/uint64-array
+ description: List of allowed data link frequencies.
+ data-lanes:
+ minItems: 1
+ maxItems: 8
+ required:
+ - link-frequencies
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - clock-frequency
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clock-frequency = <400000>;
+
+ camera-sensor@10 {
+ compatible = "nokia,smia";
+ reg = <0x10>;
+ reset-gpios = <&gpio3 20 0>;
+ vana-supply = <&vaux3>;
+ clocks = <&omap3_isp 0>;
+ clock-frequency = <9600000>;
+ port {
+ smiapp_ep: endpoint {
+ data-lanes = <1 2>;
+ remote-endpoint = <&csi2a_ep>;
+ link-frequencies = /bits/ 64 <199200000 210000000
+ 499200000>;
+ };
+ };
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index c6771cfd84d4..17be5c0e532e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11666,7 +11666,7 @@ MIPI CCS, SMIA AND SMIA++ IMAGE SENSOR DRIVER
M: Sakari Ailus <sakari.ailus@linux.intel.com>
L: linux-media@vger.kernel.org
S: Maintained
-F: Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
+F: Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
F: Documentation/driver-api/media/drivers/ccs/
F: drivers/media/i2c/ccs/
F: drivers/media/i2c/smiapp-pll.c
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 26/29] dt-bindings: nokia,smia: Use better active polarity for reset
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (24 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 25/29] dt-bindings: nokia,smia: Convert to YAML Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 27/29] dt-bindings: nokia,smia: Amend SMIA bindings with MIPI CCS support Sakari Ailus
` (2 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Generally reset signal is active low on camera sensors. The example had it
high. Make it low, and use GPIO_ACTIVE_LOW in gpio.h for that.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml b/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
index ee552489fa2b..47df08338a42 100644
--- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
@@ -80,6 +80,8 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/gpio/gpio.h>
+
i2c2 {
#address-cells = <1>;
#size-cells = <0>;
@@ -89,7 +91,7 @@ examples:
camera-sensor@10 {
compatible = "nokia,smia";
reg = <0x10>;
- reset-gpios = <&gpio3 20 0>;
+ reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
vana-supply = <&vaux3>;
clocks = <&omap3_isp 0>;
clock-frequency = <9600000>;
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 27/29] dt-bindings: nokia,smia: Amend SMIA bindings with MIPI CCS support
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (25 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 26/29] dt-bindings: nokia,smia: Use better active polarity for reset Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 28/29] dt-bindings: mipi-ccs: Add bus-type for C-PHY support Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 29/29] ccs: Request for "reset" GPIO Sakari Ailus
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
Amend the existing SMIA bindings by adding MIPI CCS support, with separate
compatible strings for CCS 1.0 and CCS 1.1. Rename the old bindings
accordingly as CCS is the current standard.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../i2c/{nokia,smia.yaml => mipi-ccs.yaml} | 23 ++++++++++++++-----
MAINTAINERS | 2 +-
2 files changed, 18 insertions(+), 7 deletions(-)
rename Documentation/devicetree/bindings/media/i2c/{nokia,smia.yaml => mipi-ccs.yaml} (81%)
diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
similarity index 81%
rename from Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
rename to Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
index 47df08338a42..a386ee246956 100644
--- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
@@ -1,26 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2014--2020 Intel Corporation
-$id: http://devicetree.org/schemas/media/i2c/nokia,smia.yaml#
+$id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: SMIA/SMIA++ sensor
+title: MIPI CCS, SMIA++ and SMIA compliant camera sensors
maintainers:
- Sakari Ailus <sakari.ailus@linux.intel.com>
description:
+ CCS (Camera Command Set) is a raw Bayer camera sensor standard defined by the
+ MIPI Alliance; see
+ <URL:https://www.mipi.org/specifications/camera-command-set>.
+
SMIA (Standard Mobile Imaging Architecture) is an image sensor standard
defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension of
- that. These definitions are valid for both types of sensors.
+ that.
More detailed documentation can be found in
Documentation/devicetree/bindings/media/video-interfaces.txt .
properties:
compatible:
- const: nokia,smia
+ oneOf:
+ - items:
+ - const: mipi-ccs-1.1
+ - const: mipi-ccs
+ - items:
+ - const: mipi-ccs-1.0
+ - const: mipi-ccs
+ - const: nokia,smia
reg:
maxItems: 1
@@ -89,14 +100,14 @@ examples:
clock-frequency = <400000>;
camera-sensor@10 {
- compatible = "nokia,smia";
+ compatible = "mipi-ccs-1.0", "mipi-ccs";
reg = <0x10>;
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
vana-supply = <&vaux3>;
clocks = <&omap3_isp 0>;
clock-frequency = <9600000>;
port {
- smiapp_ep: endpoint {
+ ccs_ep: endpoint {
data-lanes = <1 2>;
remote-endpoint = <&csi2a_ep>;
link-frequencies = /bits/ 64 <199200000 210000000
diff --git a/MAINTAINERS b/MAINTAINERS
index 17be5c0e532e..75db4b32fc8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11666,7 +11666,7 @@ MIPI CCS, SMIA AND SMIA++ IMAGE SENSOR DRIVER
M: Sakari Ailus <sakari.ailus@linux.intel.com>
L: linux-media@vger.kernel.org
S: Maintained
-F: Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml
+F: Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
F: Documentation/driver-api/media/drivers/ccs/
F: drivers/media/i2c/ccs/
F: drivers/media/i2c/smiapp-pll.c
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 28/29] dt-bindings: mipi-ccs: Add bus-type for C-PHY support
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (26 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 27/29] dt-bindings: nokia,smia: Amend SMIA bindings with MIPI CCS support Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
2020-11-27 10:33 ` [PATCH v2 29/29] ccs: Request for "reset" GPIO Sakari Ailus
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
The bus-type property is required for C-PHY support. Add it, including
values for CCP2 and CSI-2 D-PHY.
Also require the bus-type property. Effectively all new sensors are MIPI
D-PHY or C-PHY that cannot be told apart without the bus-type property.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/media/i2c/mipi-ccs.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
index a386ee246956..1d90767a6196 100644
--- a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
@@ -77,9 +77,17 @@ properties:
data-lanes:
minItems: 1
maxItems: 8
+ bus-type:
+ description: The type of the data bus.
+ oneOf:
+ - const: 1 # CSI-2 C-PHY
+ - const: 3 # CCP2
+ - const: 4 # CSI-2 D-PHY
+
required:
- link-frequencies
- data-lanes
+ - bus-type
required:
- compatible
@@ -112,6 +120,7 @@ examples:
remote-endpoint = <&csi2a_ep>;
link-frequencies = /bits/ 64 <199200000 210000000
499200000>;
+ bus-type = <4>;
};
};
};
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v2 29/29] ccs: Request for "reset" GPIO
2020-11-27 10:32 [PATCH v2 00/29] Linux CCS driver preparation Sakari Ailus
` (27 preceding siblings ...)
2020-11-27 10:33 ` [PATCH v2 28/29] dt-bindings: mipi-ccs: Add bus-type for C-PHY support Sakari Ailus
@ 2020-11-27 10:33 ` Sakari Ailus
28 siblings, 0 replies; 32+ messages in thread
From: Sakari Ailus @ 2020-11-27 10:33 UTC (permalink / raw)
To: linux-media; +Cc: hverkuil, mchehab
The DT bindings documented "reset-gpios" property but the driver never
made use of it. Instead it used a GPIO called "xshutdown", with apprently
wrong polarity.
Fix this by requesting "reset" GPIO with the right polarity first, and if
that fails, then request "xshutdown" GPIO with the old polarity. This way
it works for new users as expected while if someone, somewhere, depended
on "xshutdown" GPIO, that continues to work as well.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/i2c/ccs/ccs-core.c | 14 ++++++++++++--
drivers/media/i2c/ccs/ccs.h | 1 +
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index bddfee637f33..69e7990c65f3 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -1295,6 +1295,7 @@ static int ccs_power_on(struct device *dev)
}
usleep_range(1000, 1000);
+ gpiod_set_value(sensor->reset, 0);
gpiod_set_value(sensor->xshutdown, 1);
sleep = SMIAPP_RESET_DELAY(sensor->hwcfg->ext_clk);
@@ -1381,6 +1382,7 @@ static int ccs_power_on(struct device *dev)
return 0;
out_cci_addr_fail:
+ gpiod_set_value(sensor->reset, 1);
gpiod_set_value(sensor->xshutdown, 0);
clk_disable_unprepare(sensor->ext_clk);
@@ -1407,6 +1409,7 @@ static int ccs_power_off(struct device *dev)
if (sensor->hwcfg->i2c_addr_alt)
ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
+ gpiod_set_value(sensor->reset, 1);
gpiod_set_value(sensor->xshutdown, 0);
clk_disable_unprepare(sensor->ext_clk);
usleep_range(5000, 5000);
@@ -3008,8 +3011,15 @@ static int ccs_probe(struct i2c_client *client)
return -EINVAL;
}
- sensor->xshutdown = devm_gpiod_get_optional(&client->dev, "xshutdown",
- GPIOD_OUT_LOW);
+ sensor->reset = devm_gpiod_get_optional(&client->dev, "reset",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(sensor->reset))
+ return PTR_ERR(sensor->reset);
+ /* Support old users that may have used "xshutdown" property. */
+ if (!sensor->reset)
+ sensor->xshutdown = devm_gpiod_get_optional(&client->dev,
+ "xshutdown",
+ GPIOD_OUT_LOW);
if (IS_ERR(sensor->xshutdown))
return PTR_ERR(sensor->xshutdown);
diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
index 8933f3d40fa5..bfe39e02f5e9 100644
--- a/drivers/media/i2c/ccs/ccs.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -219,6 +219,7 @@ struct ccs_sensor {
struct regulator *vana;
struct clk *ext_clk;
struct gpio_desc *xshutdown;
+ struct gpio_desc *reset;
void *ccs_limits;
u8 nbinning_subtypes;
struct ccs_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1];
--
2.27.0
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