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From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 04/15] coresight: etm4x: Fix accesses to TRCCIDCTLR1
Date: Fri, 27 Nov 2020 10:52:45 -0700	[thread overview]
Message-ID: <20201127175256.1092685-5-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20201127175256.1092685-1-mathieu.poirier@linaro.org>

From: Suzuki K Poulose <suzuki.poulose@arm.com>

The TRCCIDCTLR1 is only implemented if TRCIDR4.NUMCIDC > 4.
Don't touch the register if it is not implemented.

Cc: stable@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index e67365d1ce28..af0ab2f44865 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -187,7 +187,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 		writeq_relaxed(config->ctxid_pid[i],
 			       drvdata->base + TRCCIDCVRn(i));
 	writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
-	writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
+	if (drvdata->numcidc > 4)
+		writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
 
 	for (i = 0; i < drvdata->numvmidc; i++)
 		writeq_relaxed(config->vmid_val[i],
@@ -1241,7 +1242,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
 		state->trcvmidcvr[i] = readq(drvdata->base + TRCVMIDCVRn(i));
 
 	state->trccidcctlr0 = readl(drvdata->base + TRCCIDCCTLR0);
-	state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
+	if (drvdata->numcidc > 4)
+		state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
 
 	state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR0);
 	if (drvdata->numvmidc > 4)
@@ -1352,7 +1354,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
 			       drvdata->base + TRCVMIDCVRn(i));
 
 	writel_relaxed(state->trccidcctlr0, drvdata->base + TRCCIDCCTLR0);
-	writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1);
+	if (drvdata->numcidc > 4)
+		writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1);
 
 	writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR0);
 	if (drvdata->numvmidc > 4)
-- 
2.25.1


WARNING: multiple messages have this Message-ID
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 04/15] coresight: etm4x: Fix accesses to TRCCIDCTLR1
Date: Fri, 27 Nov 2020 10:52:45 -0700	[thread overview]
Message-ID: <20201127175256.1092685-5-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20201127175256.1092685-1-mathieu.poirier@linaro.org>

From: Suzuki K Poulose <suzuki.poulose@arm.com>

The TRCCIDCTLR1 is only implemented if TRCIDR4.NUMCIDC > 4.
Don't touch the register if it is not implemented.

Cc: stable@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index e67365d1ce28..af0ab2f44865 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -187,7 +187,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 		writeq_relaxed(config->ctxid_pid[i],
 			       drvdata->base + TRCCIDCVRn(i));
 	writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
-	writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
+	if (drvdata->numcidc > 4)
+		writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
 
 	for (i = 0; i < drvdata->numvmidc; i++)
 		writeq_relaxed(config->vmid_val[i],
@@ -1241,7 +1242,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
 		state->trcvmidcvr[i] = readq(drvdata->base + TRCVMIDCVRn(i));
 
 	state->trccidcctlr0 = readl(drvdata->base + TRCCIDCCTLR0);
-	state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
+	if (drvdata->numcidc > 4)
+		state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
 
 	state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR0);
 	if (drvdata->numvmidc > 4)
@@ -1352,7 +1354,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
 			       drvdata->base + TRCVMIDCVRn(i));
 
 	writel_relaxed(state->trccidcctlr0, drvdata->base + TRCCIDCCTLR0);
-	writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1);
+	if (drvdata->numcidc > 4)
+		writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1);
 
 	writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR0);
 	if (drvdata->numvmidc > 4)
-- 
2.25.1


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  parent reply	other threads:[~2020-11-27 17:53 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-27 17:52 [PATCH 00/15] coresight: Patches for v5.11 Mathieu Poirier
2020-11-27 17:52 ` Mathieu Poirier
2020-11-27 17:52 ` [PATCH 01/15] coresight: etm4x: Skip setting LPOVERRIDE bit for qcom,skip-power-up Mathieu Poirier
2020-11-27 17:52   ` [PATCH 01/15] coresight: etm4x: Skip setting LPOVERRIDE bit for qcom, skip-power-up Mathieu Poirier
2020-11-27 17:52 ` [PATCH 02/15] coresight: core: Remove unneeded semicolon Mathieu Poirier
2020-11-27 17:52   ` Mathieu Poirier
2020-11-27 17:52 ` [PATCH 03/15] coresight: etm4x: Fix accesses to TRCVMIDCTLR1 Mathieu Poirier
2020-11-27 17:52   ` Mathieu Poirier
2020-11-27 17:52 ` Mathieu Poirier [this message]
2020-11-27 17:52   ` [PATCH 04/15] coresight: etm4x: Fix accesses to TRCCIDCTLR1 Mathieu Poirier
2020-11-27 17:52 ` [PATCH 05/15] coresight: etm4x: Update TRCIDR3.NUMPROCS handling to match v4.2 Mathieu Poirier
2020-11-27 17:52   ` Mathieu Poirier
2020-11-27 17:52 ` [PATCH 06/15] coresight: etm4x: Fix accesses to TRCPROCSELR Mathieu Poirier
2020-11-27 17:52   ` Mathieu Poirier
2020-11-27 17:52 ` [PATCH 07/15] coresight: etm4x: Handle TRCVIPCSSCTLR accesses Mathieu Poirier
2020-11-27 17:52   ` Mathieu Poirier
2020-11-27 17:52 ` [PATCH 08/15] coresight: Remove unnecessary THIS_MODULE of funnel and replicator driver Mathieu Poirier
2020-11-27 17:52   ` Mathieu Poirier
2020-11-27 17:52 ` [PATCH 09/15] coresight: tmc-etf: Fix NULL ptr dereference in tmc_enable_etf_sink_perf() Mathieu Poirier
2020-11-27 17:52   ` Mathieu Poirier
2020-11-27 17:52 ` [PATCH 10/15] coresight: etb10: Fix possible NULL ptr dereference in etb_enable_perf() Mathieu Poirier
2020-11-27 17:52   ` Mathieu Poirier
2020-11-27 17:52 ` [PATCH 11/15] coresight: tmc-etr: Assign boolean values to a bool variable Mathieu Poirier
2020-11-27 17:52   ` Mathieu Poirier
2020-11-27 17:52 ` [PATCH 12/15] coresight: tmc-etr: Check if page is valid before dma_map_page() Mathieu Poirier
2020-11-27 17:52   ` Mathieu Poirier
2020-11-27 17:52 ` [PATCH 13/15] coresight: Fix W=1 warnings in core framework Mathieu Poirier
2020-11-27 17:52   ` Mathieu Poirier
2020-11-27 17:52 ` [PATCH 14/15] coresight-tpiu: Fix W=1 warning in TPIU driver Mathieu Poirier
2020-11-27 17:52   ` Mathieu Poirier
2020-11-27 17:52 ` [PATCH 15/15] coresight-stm: Fix W=1 warning in STM driver Mathieu Poirier
2020-11-27 17:52   ` Mathieu Poirier

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