* [PATCH 0/2] RFC: Precise TSC migration
@ 2020-11-30 13:38 ` Maxim Levitsky
0 siblings, 0 replies; 6+ messages in thread
From: Maxim Levitsky @ 2020-11-30 13:38 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Marcelo Tosatti, Paolo Bonzini,
Michael S. Tsirkin, Cornelia Huck, Eduardo Habkost, kvm,
Maxim Levitsky
Note that to use this feature you need the kernel patches which are
posted to LKML and kvm@vger.kernel.org
Currently the feature is disabled by default, and enabled with
x-precise-tsc cpu feature.
Also I changed the TSC and TSC adjust read/write code to go though a special
function kvm_get_tsc/kvm_set_tsc regardless of enablement of this feature.
The side effect of this is that now we upload to the kernel the TSC_ADJUST
msr only on KVM_PUT_RESET_STATE reset level.
This shouldn't matter as I don't think that qemu changes this msr on its own.
For migration I added new state field 'tsc_nsec_info', where I save the
'nsec since epoch' timestamp, which is the only new thing that was added to the
migration state.
First patch in this series is temporary and it just updates the kernel
headers to make qemu compile.
When the feature is merged to the kernel, a kernel header sync will bring
the same changes to the qemu, making this patch unnecessary.
Best regards,
Maxim Levitsky
Maxim Levitsky (2):
Update the kernel headers for 5.10-rc5 + TSC
Implement support for precise TSC migration
include/standard-headers/asm-x86/kvm_para.h | 1 +
linux-headers/asm-x86/kvm.h | 2 +
linux-headers/linux/kvm.h | 70 +++++++++-
target/i386/cpu.c | 1 +
target/i386/cpu.h | 4 +
target/i386/kvm.c | 141 ++++++++++++++++----
target/i386/machine.c | 20 +++
7 files changed, 211 insertions(+), 28 deletions(-)
--
2.26.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 0/2] RFC: Precise TSC migration
@ 2020-11-30 13:38 ` Maxim Levitsky
0 siblings, 0 replies; 6+ messages in thread
From: Maxim Levitsky @ 2020-11-30 13:38 UTC (permalink / raw)
To: qemu-devel
Cc: Marcelo Tosatti, Eduardo Habkost, kvm, Michael S. Tsirkin,
Cornelia Huck, Richard Henderson, Maxim Levitsky, Paolo Bonzini
Note that to use this feature you need the kernel patches which are
posted to LKML and kvm@vger.kernel.org
Currently the feature is disabled by default, and enabled with
x-precise-tsc cpu feature.
Also I changed the TSC and TSC adjust read/write code to go though a special
function kvm_get_tsc/kvm_set_tsc regardless of enablement of this feature.
The side effect of this is that now we upload to the kernel the TSC_ADJUST
msr only on KVM_PUT_RESET_STATE reset level.
This shouldn't matter as I don't think that qemu changes this msr on its own.
For migration I added new state field 'tsc_nsec_info', where I save the
'nsec since epoch' timestamp, which is the only new thing that was added to the
migration state.
First patch in this series is temporary and it just updates the kernel
headers to make qemu compile.
When the feature is merged to the kernel, a kernel header sync will bring
the same changes to the qemu, making this patch unnecessary.
Best regards,
Maxim Levitsky
Maxim Levitsky (2):
Update the kernel headers for 5.10-rc5 + TSC
Implement support for precise TSC migration
include/standard-headers/asm-x86/kvm_para.h | 1 +
linux-headers/asm-x86/kvm.h | 2 +
linux-headers/linux/kvm.h | 70 +++++++++-
target/i386/cpu.c | 1 +
target/i386/cpu.h | 4 +
target/i386/kvm.c | 141 ++++++++++++++++----
target/i386/machine.c | 20 +++
7 files changed, 211 insertions(+), 28 deletions(-)
--
2.26.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] Update the kernel headers for 5.10-rc5 + TSC
2020-11-30 13:38 ` Maxim Levitsky
@ 2020-11-30 13:38 ` Maxim Levitsky
-1 siblings, 0 replies; 6+ messages in thread
From: Maxim Levitsky @ 2020-11-30 13:38 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Marcelo Tosatti, Paolo Bonzini,
Michael S. Tsirkin, Cornelia Huck, Eduardo Habkost, kvm,
Maxim Levitsky
Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
---
include/standard-headers/asm-x86/kvm_para.h | 1 +
| 2 +
| 70 ++++++++++++++++++++-
3 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/include/standard-headers/asm-x86/kvm_para.h b/include/standard-headers/asm-x86/kvm_para.h
index 07877d3295..215d01b4ec 100644
--- a/include/standard-headers/asm-x86/kvm_para.h
+++ b/include/standard-headers/asm-x86/kvm_para.h
@@ -32,6 +32,7 @@
#define KVM_FEATURE_POLL_CONTROL 12
#define KVM_FEATURE_PV_SCHED_YIELD 13
#define KVM_FEATURE_ASYNC_PF_INT 14
+#define KVM_FEATURE_MSI_EXT_DEST_ID 15
#define KVM_HINTS_REALTIME 0
--git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h
index 89e5f3d1bb..2a60fc6674 100644
--- a/linux-headers/asm-x86/kvm.h
+++ b/linux-headers/asm-x86/kvm.h
@@ -12,6 +12,7 @@
#define KVM_PIO_PAGE_OFFSET 1
#define KVM_COALESCED_MMIO_PAGE_OFFSET 2
+#define KVM_DIRTY_LOG_PAGE_OFFSET 64
#define DE_VECTOR 0
#define DB_VECTOR 1
@@ -403,6 +404,7 @@ struct kvm_sync_regs {
#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2)
#define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3)
#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4)
+#define KVM_X86_QUIRK_TSC_HOST_ACCESS (1 << 5)
#define KVM_STATE_NESTED_FORMAT_VMX 0
#define KVM_STATE_NESTED_FORMAT_SVM 1
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 56ce14ad20..55dd0f563c 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -250,6 +250,7 @@ struct kvm_hyperv_exit {
#define KVM_EXIT_ARM_NISV 28
#define KVM_EXIT_X86_RDMSR 29
#define KVM_EXIT_X86_WRMSR 30
+#define KVM_EXIT_DIRTY_RING_FULL 31
/* For KVM_EXIT_INTERNAL_ERROR */
/* Emulate instruction failed. */
@@ -1053,6 +1054,9 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_X86_USER_SPACE_MSR 188
#define KVM_CAP_X86_MSR_FILTER 189
#define KVM_CAP_ENFORCE_PV_FEATURE_CPUID 190
+#define KVM_CAP_SYS_HYPERV_CPUID 191
+#define KVM_CAP_DIRTY_LOG_RING 192
+#define KVM_CAP_PRECISE_TSC 193
#ifdef KVM_CAP_IRQ_ROUTING
@@ -1166,6 +1170,15 @@ struct kvm_clock_data {
__u32 pad[9];
};
+
+#define KVM_TSC_STATE_TSC_ADJUST_VALID 1
+struct kvm_tsc_state {
+ __u32 flags;
+ __u64 nsec;
+ __u64 tsc;
+ __u64 tsc_adjust;
+};
+
/* For KVM_CAP_SW_TLB */
#define KVM_MMU_FSL_BOOKE_NOHV 0
@@ -1511,7 +1524,7 @@ struct kvm_enc_region {
/* Available with KVM_CAP_MANUAL_DIRTY_LOG_PROTECT_2 */
#define KVM_CLEAR_DIRTY_LOG _IOWR(KVMIO, 0xc0, struct kvm_clear_dirty_log)
-/* Available with KVM_CAP_HYPERV_CPUID */
+/* Available with KVM_CAP_HYPERV_CPUID (vcpu) / KVM_CAP_SYS_HYPERV_CPUID (system) */
#define KVM_GET_SUPPORTED_HV_CPUID _IOWR(KVMIO, 0xc1, struct kvm_cpuid2)
/* Available with KVM_CAP_ARM_SVE */
@@ -1557,6 +1570,13 @@ struct kvm_pv_cmd {
/* Available with KVM_CAP_X86_MSR_FILTER */
#define KVM_X86_SET_MSR_FILTER _IOW(KVMIO, 0xc6, struct kvm_msr_filter)
+/* Available with KVM_CAP_DIRTY_LOG_RING */
+#define KVM_RESET_DIRTY_RINGS _IO(KVMIO, 0xc7)
+
+/* Available with KVM_CAP_PRECISE_TSC*/
+#define KVM_SET_TSC_STATE _IOW(KVMIO, 0xc8, struct kvm_tsc_state)
+#define KVM_GET_TSC_STATE _IOR(KVMIO, 0xc9, struct kvm_tsc_state)
+
/* Secure Encrypted Virtualization command */
enum sev_cmd_id {
/* Guest initialization commands */
@@ -1710,4 +1730,52 @@ struct kvm_hyperv_eventfd {
#define KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE (1 << 0)
#define KVM_DIRTY_LOG_INITIALLY_SET (1 << 1)
+/*
+ * Arch needs to define the macro after implementing the dirty ring
+ * feature. KVM_DIRTY_LOG_PAGE_OFFSET should be defined as the
+ * starting page offset of the dirty ring structures.
+ */
+#ifndef KVM_DIRTY_LOG_PAGE_OFFSET
+#define KVM_DIRTY_LOG_PAGE_OFFSET 0
+#endif
+
+/*
+ * KVM dirty GFN flags, defined as:
+ *
+ * |---------------+---------------+--------------|
+ * | bit 1 (reset) | bit 0 (dirty) | Status |
+ * |---------------+---------------+--------------|
+ * | 0 | 0 | Invalid GFN |
+ * | 0 | 1 | Dirty GFN |
+ * | 1 | X | GFN to reset |
+ * |---------------+---------------+--------------|
+ *
+ * Lifecycle of a dirty GFN goes like:
+ *
+ * dirtied harvested reset
+ * 00 -----------> 01 -------------> 1X -------+
+ * ^ |
+ * | |
+ * +------------------------------------------+
+ *
+ * The userspace program is only responsible for the 01->1X state
+ * conversion after harvesting an entry. Also, it must not skip any
+ * dirty bits, so that dirty bits are always harvested in sequence.
+ */
+#define KVM_DIRTY_GFN_F_DIRTY BIT(0)
+#define KVM_DIRTY_GFN_F_RESET BIT(1)
+#define KVM_DIRTY_GFN_F_MASK 0x3
+
+/*
+ * KVM dirty rings should be mapped at KVM_DIRTY_LOG_PAGE_OFFSET of
+ * per-vcpu mmaped regions as an array of struct kvm_dirty_gfn. The
+ * size of the gfn buffer is decided by the first argument when
+ * enabling KVM_CAP_DIRTY_LOG_RING.
+ */
+struct kvm_dirty_gfn {
+ __u32 flags;
+ __u32 slot;
+ __u64 offset;
+};
+
#endif /* __LINUX_KVM_H */
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 1/2] Update the kernel headers for 5.10-rc5 + TSC
@ 2020-11-30 13:38 ` Maxim Levitsky
0 siblings, 0 replies; 6+ messages in thread
From: Maxim Levitsky @ 2020-11-30 13:38 UTC (permalink / raw)
To: qemu-devel
Cc: Marcelo Tosatti, Eduardo Habkost, kvm, Michael S. Tsirkin,
Cornelia Huck, Richard Henderson, Maxim Levitsky, Paolo Bonzini
Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
---
include/standard-headers/asm-x86/kvm_para.h | 1 +
| 2 +
| 70 ++++++++++++++++++++-
3 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/include/standard-headers/asm-x86/kvm_para.h b/include/standard-headers/asm-x86/kvm_para.h
index 07877d3295..215d01b4ec 100644
--- a/include/standard-headers/asm-x86/kvm_para.h
+++ b/include/standard-headers/asm-x86/kvm_para.h
@@ -32,6 +32,7 @@
#define KVM_FEATURE_POLL_CONTROL 12
#define KVM_FEATURE_PV_SCHED_YIELD 13
#define KVM_FEATURE_ASYNC_PF_INT 14
+#define KVM_FEATURE_MSI_EXT_DEST_ID 15
#define KVM_HINTS_REALTIME 0
--git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h
index 89e5f3d1bb..2a60fc6674 100644
--- a/linux-headers/asm-x86/kvm.h
+++ b/linux-headers/asm-x86/kvm.h
@@ -12,6 +12,7 @@
#define KVM_PIO_PAGE_OFFSET 1
#define KVM_COALESCED_MMIO_PAGE_OFFSET 2
+#define KVM_DIRTY_LOG_PAGE_OFFSET 64
#define DE_VECTOR 0
#define DB_VECTOR 1
@@ -403,6 +404,7 @@ struct kvm_sync_regs {
#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2)
#define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3)
#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4)
+#define KVM_X86_QUIRK_TSC_HOST_ACCESS (1 << 5)
#define KVM_STATE_NESTED_FORMAT_VMX 0
#define KVM_STATE_NESTED_FORMAT_SVM 1
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 56ce14ad20..55dd0f563c 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -250,6 +250,7 @@ struct kvm_hyperv_exit {
#define KVM_EXIT_ARM_NISV 28
#define KVM_EXIT_X86_RDMSR 29
#define KVM_EXIT_X86_WRMSR 30
+#define KVM_EXIT_DIRTY_RING_FULL 31
/* For KVM_EXIT_INTERNAL_ERROR */
/* Emulate instruction failed. */
@@ -1053,6 +1054,9 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_X86_USER_SPACE_MSR 188
#define KVM_CAP_X86_MSR_FILTER 189
#define KVM_CAP_ENFORCE_PV_FEATURE_CPUID 190
+#define KVM_CAP_SYS_HYPERV_CPUID 191
+#define KVM_CAP_DIRTY_LOG_RING 192
+#define KVM_CAP_PRECISE_TSC 193
#ifdef KVM_CAP_IRQ_ROUTING
@@ -1166,6 +1170,15 @@ struct kvm_clock_data {
__u32 pad[9];
};
+
+#define KVM_TSC_STATE_TSC_ADJUST_VALID 1
+struct kvm_tsc_state {
+ __u32 flags;
+ __u64 nsec;
+ __u64 tsc;
+ __u64 tsc_adjust;
+};
+
/* For KVM_CAP_SW_TLB */
#define KVM_MMU_FSL_BOOKE_NOHV 0
@@ -1511,7 +1524,7 @@ struct kvm_enc_region {
/* Available with KVM_CAP_MANUAL_DIRTY_LOG_PROTECT_2 */
#define KVM_CLEAR_DIRTY_LOG _IOWR(KVMIO, 0xc0, struct kvm_clear_dirty_log)
-/* Available with KVM_CAP_HYPERV_CPUID */
+/* Available with KVM_CAP_HYPERV_CPUID (vcpu) / KVM_CAP_SYS_HYPERV_CPUID (system) */
#define KVM_GET_SUPPORTED_HV_CPUID _IOWR(KVMIO, 0xc1, struct kvm_cpuid2)
/* Available with KVM_CAP_ARM_SVE */
@@ -1557,6 +1570,13 @@ struct kvm_pv_cmd {
/* Available with KVM_CAP_X86_MSR_FILTER */
#define KVM_X86_SET_MSR_FILTER _IOW(KVMIO, 0xc6, struct kvm_msr_filter)
+/* Available with KVM_CAP_DIRTY_LOG_RING */
+#define KVM_RESET_DIRTY_RINGS _IO(KVMIO, 0xc7)
+
+/* Available with KVM_CAP_PRECISE_TSC*/
+#define KVM_SET_TSC_STATE _IOW(KVMIO, 0xc8, struct kvm_tsc_state)
+#define KVM_GET_TSC_STATE _IOR(KVMIO, 0xc9, struct kvm_tsc_state)
+
/* Secure Encrypted Virtualization command */
enum sev_cmd_id {
/* Guest initialization commands */
@@ -1710,4 +1730,52 @@ struct kvm_hyperv_eventfd {
#define KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE (1 << 0)
#define KVM_DIRTY_LOG_INITIALLY_SET (1 << 1)
+/*
+ * Arch needs to define the macro after implementing the dirty ring
+ * feature. KVM_DIRTY_LOG_PAGE_OFFSET should be defined as the
+ * starting page offset of the dirty ring structures.
+ */
+#ifndef KVM_DIRTY_LOG_PAGE_OFFSET
+#define KVM_DIRTY_LOG_PAGE_OFFSET 0
+#endif
+
+/*
+ * KVM dirty GFN flags, defined as:
+ *
+ * |---------------+---------------+--------------|
+ * | bit 1 (reset) | bit 0 (dirty) | Status |
+ * |---------------+---------------+--------------|
+ * | 0 | 0 | Invalid GFN |
+ * | 0 | 1 | Dirty GFN |
+ * | 1 | X | GFN to reset |
+ * |---------------+---------------+--------------|
+ *
+ * Lifecycle of a dirty GFN goes like:
+ *
+ * dirtied harvested reset
+ * 00 -----------> 01 -------------> 1X -------+
+ * ^ |
+ * | |
+ * +------------------------------------------+
+ *
+ * The userspace program is only responsible for the 01->1X state
+ * conversion after harvesting an entry. Also, it must not skip any
+ * dirty bits, so that dirty bits are always harvested in sequence.
+ */
+#define KVM_DIRTY_GFN_F_DIRTY BIT(0)
+#define KVM_DIRTY_GFN_F_RESET BIT(1)
+#define KVM_DIRTY_GFN_F_MASK 0x3
+
+/*
+ * KVM dirty rings should be mapped at KVM_DIRTY_LOG_PAGE_OFFSET of
+ * per-vcpu mmaped regions as an array of struct kvm_dirty_gfn. The
+ * size of the gfn buffer is decided by the first argument when
+ * enabling KVM_CAP_DIRTY_LOG_RING.
+ */
+struct kvm_dirty_gfn {
+ __u32 flags;
+ __u32 slot;
+ __u64 offset;
+};
+
#endif /* __LINUX_KVM_H */
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] Implement support for precise TSC migration
2020-11-30 13:38 ` Maxim Levitsky
@ 2020-11-30 13:38 ` Maxim Levitsky
-1 siblings, 0 replies; 6+ messages in thread
From: Maxim Levitsky @ 2020-11-30 13:38 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Marcelo Tosatti, Paolo Bonzini,
Michael S. Tsirkin, Cornelia Huck, Eduardo Habkost, kvm,
Maxim Levitsky
Currently to enable it, you need to set x-precise-tsc=on
for each vcpu.
Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
---
target/i386/cpu.c | 1 +
target/i386/cpu.h | 4 ++
target/i386/kvm.c | 141 ++++++++++++++++++++++++++++++++++--------
target/i386/machine.c | 20 ++++++
4 files changed, 139 insertions(+), 27 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5a8c96072e..3c82864930 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7231,6 +7231,7 @@ static Property x86_cpu_properties[] = {
false),
DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
true),
+ DEFINE_PROP_BOOL("x-precise-tsc", X86CPU, precise_tsc, false),
DEFINE_PROP_END_OF_LIST()
};
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 88e8586f8f..fd355057b8 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1460,6 +1460,7 @@ typedef struct CPUX86State {
uint64_t tsc_adjust;
uint64_t tsc_deadline;
uint64_t tsc_aux;
+ uint64_t tsc_ns_timestamp;
uint64_t xcr0;
@@ -1743,6 +1744,9 @@ struct X86CPU {
/* Number of physical address bits supported */
uint32_t phys_bits;
+ /* Use KVM_GET_TSC_PRECISE/KVM_SET_TSC_PRECISE to access IA32_TSC */
+ bool precise_tsc;
+
/* in order to simplify APIC support, we leave this pointer to the
user */
struct DeviceState *apic_state;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index a2934dda02..f0488aa6cc 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -121,6 +121,7 @@ static int has_xsave;
static int has_xcrs;
static int has_pit_state2;
static int has_exception_payload;
+static int has_precise_tsc;
static bool has_msr_mcg_ext_ctl;
@@ -196,31 +197,109 @@ static int kvm_get_tsc(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
- struct {
- struct kvm_msrs info;
- struct kvm_msr_entry entries[1];
- } msr_data = {};
int ret;
if (env->tsc_valid) {
return 0;
}
- memset(&msr_data, 0, sizeof(msr_data));
- msr_data.info.nmsrs = 1;
- msr_data.entries[0].index = MSR_IA32_TSC;
- env->tsc_valid = !runstate_is_running();
+ if (cpu->precise_tsc) {
+ struct kvm_tsc_state tsc_state;
- ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
- if (ret < 0) {
- return ret;
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_TSC_STATE, &tsc_state);
+ if (ret < 0) {
+ return ret;
+ }
+
+ env->tsc = tsc_state.tsc;
+ if (tsc_state.flags & KVM_TSC_STATE_TSC_ADJUST_VALID) {
+ env->tsc_adjust = tsc_state.tsc_adjust;
+ }
+ env->tsc_ns_timestamp = tsc_state.nsec;
+
+ } else {
+ struct {
+ struct kvm_msrs info;
+ struct kvm_msr_entry entries[2];
+ } msr_data = {};
+
+ memset(&msr_data, 0, sizeof(msr_data));
+ msr_data.info.nmsrs = 1;
+ msr_data.entries[0].index = MSR_IA32_TSC;
+
+ if (has_msr_tsc_adjust) {
+ msr_data.info.nmsrs++;
+ msr_data.entries[1].index = MSR_TSC_ADJUST;
+ }
+
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
+ if (ret < 0) {
+ return ret;
+ }
+
+ assert(ret == msr_data.info.nmsrs);
+
+ env->tsc = msr_data.entries[0].data;
+ if (has_msr_tsc_adjust) {
+ env->tsc_adjust = msr_data.entries[1].data;
+ }
}
- assert(ret == 1);
- env->tsc = msr_data.entries[0].data;
+ env->tsc_valid = !runstate_is_running();
return 0;
}
+static int kvm_set_tsc(CPUState *cs)
+{
+ int ret;
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ if (cpu->precise_tsc) {
+ struct kvm_tsc_state tsc_state;
+
+ memset(&tsc_state, 0, sizeof(tsc_state));
+
+ tsc_state.tsc = env->tsc;
+ tsc_state.nsec = env->tsc_ns_timestamp;
+
+ if (has_msr_tsc_adjust) {
+ tsc_state.tsc_adjust = env->tsc_adjust;
+ tsc_state.flags |= KVM_TSC_STATE_TSC_ADJUST_VALID;
+ }
+
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_TSC_STATE, &tsc_state);
+ if (ret < 0) {
+ return ret;
+ }
+
+ } else {
+ struct {
+ struct kvm_msrs info;
+ struct kvm_msr_entry entries[2];
+ } msr_data = {};
+
+ memset(&msr_data, 0, sizeof(msr_data));
+ msr_data.info.nmsrs = 1;
+ msr_data.entries[0].index = MSR_IA32_TSC;
+ msr_data.entries[0].data = env->tsc;
+
+ if (has_msr_tsc_adjust) {
+ msr_data.info.nmsrs++;
+ msr_data.entries[1].index = MSR_TSC_ADJUST;
+ msr_data.entries[1].data = env->tsc_adjust;
+ }
+
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
+ if (ret < 0) {
+ return ret;
+ }
+
+ assert(ret == msr_data.info.nmsrs);
+ }
+ return ret;
+}
+
static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
{
kvm_get_tsc(cpu);
@@ -1780,6 +1859,13 @@ int kvm_arch_init_vcpu(CPUState *cs)
}
}
+ if (cpu->precise_tsc) {
+ if (!kvm_check_extension(cs->kvm_state, KVM_CAP_PRECISE_TSC)) {
+ error_report("kvm: Precise TSC is not supported by the host's KVM");
+ return -ENOTSUP;
+ }
+ }
+
if (cpu->vmware_cpuid_freq
/* Guests depend on 0x40000000 to detect this feature, so only expose
* it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
@@ -2196,6 +2282,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
int ret;
+
+
/* Work around for kernel header with a typo. TODO: fix header and drop. */
#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
@@ -2215,6 +2303,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
}
}
+ has_precise_tsc = kvm_check_extension(s, KVM_CAP_PRECISE_TSC);
+
return 0;
}
@@ -2756,9 +2846,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
if (has_msr_tsc_aux) {
kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
}
- if (has_msr_tsc_adjust) {
- kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
- }
if (has_msr_misc_enable) {
kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
env->msr_ia32_misc_enable);
@@ -2802,7 +2889,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
* for normal writeback. Limit them to reset or full state updates.
*/
if (level >= KVM_PUT_RESET_STATE) {
- kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
@@ -3142,9 +3228,6 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_tsc_aux) {
kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
}
- if (has_msr_tsc_adjust) {
- kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
- }
if (has_msr_tsc_deadline) {
kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
}
@@ -3178,10 +3261,6 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_virt_ssbd) {
kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
}
- if (!env->tsc_valid) {
- kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
- env->tsc_valid = !runstate_is_running();
- }
#ifdef TARGET_X86_64
if (lm_capable_kernel) {
@@ -3385,9 +3464,6 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_TSC_AUX:
env->tsc_aux = msrs[i].data;
break;
- case MSR_TSC_ADJUST:
- env->tsc_adjust = msrs[i].data;
- break;
case MSR_IA32_TSCDEADLINE:
env->tsc_deadline = msrs[i].data;
break;
@@ -3995,6 +4071,11 @@ int kvm_arch_put_registers(CPUState *cpu, int level)
if (ret < 0) {
return ret;
}
+
+ ret = kvm_set_tsc(cpu);
+ if (ret < 0) {
+ return ret;
+ }
}
ret = kvm_put_tscdeadline_msr(x86_cpu);
@@ -4064,6 +4145,12 @@ int kvm_arch_get_registers(CPUState *cs)
if (ret < 0) {
goto out;
}
+
+ ret = kvm_get_tsc(cs);
+ if (ret < 0) {
+ goto out;
+ }
+
ret = 0;
out:
cpu_sync_bndcs_hflags(&cpu->env);
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 233e46bb70..4f4296a3e4 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -1359,6 +1359,25 @@ static const VMStateDescription vmstate_msr_tsx_ctrl = {
}
};
+
+static bool tsc_info_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ return cpu->precise_tsc;
+}
+
+static const VMStateDescription vmstate_tsc_info = {
+ .name = "cpu/tsc_nsec_info",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = tsc_info_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(env.tsc_ns_timestamp, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+
VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -1493,6 +1512,7 @@ VMStateDescription vmstate_x86_cpu = {
#endif
#ifdef CONFIG_KVM
&vmstate_nested_state,
+ &vmstate_tsc_info,
#endif
&vmstate_msr_tsx_ctrl,
NULL
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] Implement support for precise TSC migration
@ 2020-11-30 13:38 ` Maxim Levitsky
0 siblings, 0 replies; 6+ messages in thread
From: Maxim Levitsky @ 2020-11-30 13:38 UTC (permalink / raw)
To: qemu-devel
Cc: Marcelo Tosatti, Eduardo Habkost, kvm, Michael S. Tsirkin,
Cornelia Huck, Richard Henderson, Maxim Levitsky, Paolo Bonzini
Currently to enable it, you need to set x-precise-tsc=on
for each vcpu.
Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
---
target/i386/cpu.c | 1 +
target/i386/cpu.h | 4 ++
target/i386/kvm.c | 141 ++++++++++++++++++++++++++++++++++--------
target/i386/machine.c | 20 ++++++
4 files changed, 139 insertions(+), 27 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5a8c96072e..3c82864930 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7231,6 +7231,7 @@ static Property x86_cpu_properties[] = {
false),
DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
true),
+ DEFINE_PROP_BOOL("x-precise-tsc", X86CPU, precise_tsc, false),
DEFINE_PROP_END_OF_LIST()
};
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 88e8586f8f..fd355057b8 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1460,6 +1460,7 @@ typedef struct CPUX86State {
uint64_t tsc_adjust;
uint64_t tsc_deadline;
uint64_t tsc_aux;
+ uint64_t tsc_ns_timestamp;
uint64_t xcr0;
@@ -1743,6 +1744,9 @@ struct X86CPU {
/* Number of physical address bits supported */
uint32_t phys_bits;
+ /* Use KVM_GET_TSC_PRECISE/KVM_SET_TSC_PRECISE to access IA32_TSC */
+ bool precise_tsc;
+
/* in order to simplify APIC support, we leave this pointer to the
user */
struct DeviceState *apic_state;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index a2934dda02..f0488aa6cc 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -121,6 +121,7 @@ static int has_xsave;
static int has_xcrs;
static int has_pit_state2;
static int has_exception_payload;
+static int has_precise_tsc;
static bool has_msr_mcg_ext_ctl;
@@ -196,31 +197,109 @@ static int kvm_get_tsc(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
- struct {
- struct kvm_msrs info;
- struct kvm_msr_entry entries[1];
- } msr_data = {};
int ret;
if (env->tsc_valid) {
return 0;
}
- memset(&msr_data, 0, sizeof(msr_data));
- msr_data.info.nmsrs = 1;
- msr_data.entries[0].index = MSR_IA32_TSC;
- env->tsc_valid = !runstate_is_running();
+ if (cpu->precise_tsc) {
+ struct kvm_tsc_state tsc_state;
- ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
- if (ret < 0) {
- return ret;
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_TSC_STATE, &tsc_state);
+ if (ret < 0) {
+ return ret;
+ }
+
+ env->tsc = tsc_state.tsc;
+ if (tsc_state.flags & KVM_TSC_STATE_TSC_ADJUST_VALID) {
+ env->tsc_adjust = tsc_state.tsc_adjust;
+ }
+ env->tsc_ns_timestamp = tsc_state.nsec;
+
+ } else {
+ struct {
+ struct kvm_msrs info;
+ struct kvm_msr_entry entries[2];
+ } msr_data = {};
+
+ memset(&msr_data, 0, sizeof(msr_data));
+ msr_data.info.nmsrs = 1;
+ msr_data.entries[0].index = MSR_IA32_TSC;
+
+ if (has_msr_tsc_adjust) {
+ msr_data.info.nmsrs++;
+ msr_data.entries[1].index = MSR_TSC_ADJUST;
+ }
+
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
+ if (ret < 0) {
+ return ret;
+ }
+
+ assert(ret == msr_data.info.nmsrs);
+
+ env->tsc = msr_data.entries[0].data;
+ if (has_msr_tsc_adjust) {
+ env->tsc_adjust = msr_data.entries[1].data;
+ }
}
- assert(ret == 1);
- env->tsc = msr_data.entries[0].data;
+ env->tsc_valid = !runstate_is_running();
return 0;
}
+static int kvm_set_tsc(CPUState *cs)
+{
+ int ret;
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ if (cpu->precise_tsc) {
+ struct kvm_tsc_state tsc_state;
+
+ memset(&tsc_state, 0, sizeof(tsc_state));
+
+ tsc_state.tsc = env->tsc;
+ tsc_state.nsec = env->tsc_ns_timestamp;
+
+ if (has_msr_tsc_adjust) {
+ tsc_state.tsc_adjust = env->tsc_adjust;
+ tsc_state.flags |= KVM_TSC_STATE_TSC_ADJUST_VALID;
+ }
+
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_TSC_STATE, &tsc_state);
+ if (ret < 0) {
+ return ret;
+ }
+
+ } else {
+ struct {
+ struct kvm_msrs info;
+ struct kvm_msr_entry entries[2];
+ } msr_data = {};
+
+ memset(&msr_data, 0, sizeof(msr_data));
+ msr_data.info.nmsrs = 1;
+ msr_data.entries[0].index = MSR_IA32_TSC;
+ msr_data.entries[0].data = env->tsc;
+
+ if (has_msr_tsc_adjust) {
+ msr_data.info.nmsrs++;
+ msr_data.entries[1].index = MSR_TSC_ADJUST;
+ msr_data.entries[1].data = env->tsc_adjust;
+ }
+
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
+ if (ret < 0) {
+ return ret;
+ }
+
+ assert(ret == msr_data.info.nmsrs);
+ }
+ return ret;
+}
+
static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
{
kvm_get_tsc(cpu);
@@ -1780,6 +1859,13 @@ int kvm_arch_init_vcpu(CPUState *cs)
}
}
+ if (cpu->precise_tsc) {
+ if (!kvm_check_extension(cs->kvm_state, KVM_CAP_PRECISE_TSC)) {
+ error_report("kvm: Precise TSC is not supported by the host's KVM");
+ return -ENOTSUP;
+ }
+ }
+
if (cpu->vmware_cpuid_freq
/* Guests depend on 0x40000000 to detect this feature, so only expose
* it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
@@ -2196,6 +2282,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
int ret;
+
+
/* Work around for kernel header with a typo. TODO: fix header and drop. */
#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
@@ -2215,6 +2303,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
}
}
+ has_precise_tsc = kvm_check_extension(s, KVM_CAP_PRECISE_TSC);
+
return 0;
}
@@ -2756,9 +2846,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
if (has_msr_tsc_aux) {
kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
}
- if (has_msr_tsc_adjust) {
- kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
- }
if (has_msr_misc_enable) {
kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
env->msr_ia32_misc_enable);
@@ -2802,7 +2889,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
* for normal writeback. Limit them to reset or full state updates.
*/
if (level >= KVM_PUT_RESET_STATE) {
- kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
@@ -3142,9 +3228,6 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_tsc_aux) {
kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
}
- if (has_msr_tsc_adjust) {
- kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
- }
if (has_msr_tsc_deadline) {
kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
}
@@ -3178,10 +3261,6 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_virt_ssbd) {
kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
}
- if (!env->tsc_valid) {
- kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
- env->tsc_valid = !runstate_is_running();
- }
#ifdef TARGET_X86_64
if (lm_capable_kernel) {
@@ -3385,9 +3464,6 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_TSC_AUX:
env->tsc_aux = msrs[i].data;
break;
- case MSR_TSC_ADJUST:
- env->tsc_adjust = msrs[i].data;
- break;
case MSR_IA32_TSCDEADLINE:
env->tsc_deadline = msrs[i].data;
break;
@@ -3995,6 +4071,11 @@ int kvm_arch_put_registers(CPUState *cpu, int level)
if (ret < 0) {
return ret;
}
+
+ ret = kvm_set_tsc(cpu);
+ if (ret < 0) {
+ return ret;
+ }
}
ret = kvm_put_tscdeadline_msr(x86_cpu);
@@ -4064,6 +4145,12 @@ int kvm_arch_get_registers(CPUState *cs)
if (ret < 0) {
goto out;
}
+
+ ret = kvm_get_tsc(cs);
+ if (ret < 0) {
+ goto out;
+ }
+
ret = 0;
out:
cpu_sync_bndcs_hflags(&cpu->env);
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 233e46bb70..4f4296a3e4 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -1359,6 +1359,25 @@ static const VMStateDescription vmstate_msr_tsx_ctrl = {
}
};
+
+static bool tsc_info_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ return cpu->precise_tsc;
+}
+
+static const VMStateDescription vmstate_tsc_info = {
+ .name = "cpu/tsc_nsec_info",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = tsc_info_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(env.tsc_ns_timestamp, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+
VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -1493,6 +1512,7 @@ VMStateDescription vmstate_x86_cpu = {
#endif
#ifdef CONFIG_KVM
&vmstate_nested_state,
+ &vmstate_tsc_info,
#endif
&vmstate_msr_tsx_ctrl,
NULL
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-11-30 13:41 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-30 13:38 [PATCH 0/2] RFC: Precise TSC migration Maxim Levitsky
2020-11-30 13:38 ` Maxim Levitsky
2020-11-30 13:38 ` [PATCH 1/2] Update the kernel headers for 5.10-rc5 + TSC Maxim Levitsky
2020-11-30 13:38 ` Maxim Levitsky
2020-11-30 13:38 ` [PATCH 2/2] Implement support for precise TSC migration Maxim Levitsky
2020-11-30 13:38 ` Maxim Levitsky
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