* [PATCH v2] arm64: mte: Fix typo in macro definition
@ 2020-11-30 17:07 ` Vincenzo Frascino
0 siblings, 0 replies; 6+ messages in thread
From: Vincenzo Frascino @ 2020-11-30 17:07 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kasan-dev
Cc: Vincenzo Frascino, Catalin Marinas, Will Deacon
UL in the definition of SYS_TFSR_EL1_TF1 was misspelled causing
compilation issues when trying to implement in kernel MTE async
mode.
Fix the macro correcting the typo.
Note: MTE async mode will be introduced with a future series.
Fixes: c058b1c4a5ea ("arm64: mte: system register definitions")
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
arch/arm64/include/asm/sysreg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index e2ef4c2edf06..801861d05426 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -987,7 +987,7 @@
#define SYS_TFSR_EL1_TF0_SHIFT 0
#define SYS_TFSR_EL1_TF1_SHIFT 1
#define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
-#define SYS_TFSR_EL1_TF1 (UK(2) << SYS_TFSR_EL1_TF1_SHIFT)
+#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
#define SYS_MPIDR_SAFE_VAL (BIT(31))
--
2.29.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2] arm64: mte: Fix typo in macro definition
@ 2020-11-30 17:07 ` Vincenzo Frascino
0 siblings, 0 replies; 6+ messages in thread
From: Vincenzo Frascino @ 2020-11-30 17:07 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, kasan-dev
Cc: Catalin Marinas, Vincenzo Frascino, Will Deacon
UL in the definition of SYS_TFSR_EL1_TF1 was misspelled causing
compilation issues when trying to implement in kernel MTE async
mode.
Fix the macro correcting the typo.
Note: MTE async mode will be introduced with a future series.
Fixes: c058b1c4a5ea ("arm64: mte: system register definitions")
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
arch/arm64/include/asm/sysreg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index e2ef4c2edf06..801861d05426 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -987,7 +987,7 @@
#define SYS_TFSR_EL1_TF0_SHIFT 0
#define SYS_TFSR_EL1_TF1_SHIFT 1
#define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
-#define SYS_TFSR_EL1_TF1 (UK(2) << SYS_TFSR_EL1_TF1_SHIFT)
+#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
#define SYS_MPIDR_SAFE_VAL (BIT(31))
--
2.29.2
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: mte: Fix typo in macro definition
2020-11-30 17:07 ` Vincenzo Frascino
@ 2020-11-30 17:13 ` Catalin Marinas
-1 siblings, 0 replies; 6+ messages in thread
From: Catalin Marinas @ 2020-11-30 17:13 UTC (permalink / raw)
To: Vincenzo Frascino; +Cc: linux-arm-kernel, linux-kernel, kasan-dev, Will Deacon
On Mon, Nov 30, 2020 at 05:07:09PM +0000, Vincenzo Frascino wrote:
> UL in the definition of SYS_TFSR_EL1_TF1 was misspelled causing
> compilation issues when trying to implement in kernel MTE async
> mode.
>
> Fix the macro correcting the typo.
>
> Note: MTE async mode will be introduced with a future series.
>
> Fixes: c058b1c4a5ea ("arm64: mte: system register definitions")
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
> arch/arm64/include/asm/sysreg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index e2ef4c2edf06..801861d05426 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -987,7 +987,7 @@
> #define SYS_TFSR_EL1_TF0_SHIFT 0
> #define SYS_TFSR_EL1_TF1_SHIFT 1
> #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
> -#define SYS_TFSR_EL1_TF1 (UK(2) << SYS_TFSR_EL1_TF1_SHIFT)
> +#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
I think we should first rename it to EU and then fix it properly ;).
While nothing breaks without this patch currently, we should merge it as
a fix.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Thanks.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: mte: Fix typo in macro definition
@ 2020-11-30 17:13 ` Catalin Marinas
0 siblings, 0 replies; 6+ messages in thread
From: Catalin Marinas @ 2020-11-30 17:13 UTC (permalink / raw)
To: Vincenzo Frascino; +Cc: kasan-dev, Will Deacon, linux-kernel, linux-arm-kernel
On Mon, Nov 30, 2020 at 05:07:09PM +0000, Vincenzo Frascino wrote:
> UL in the definition of SYS_TFSR_EL1_TF1 was misspelled causing
> compilation issues when trying to implement in kernel MTE async
> mode.
>
> Fix the macro correcting the typo.
>
> Note: MTE async mode will be introduced with a future series.
>
> Fixes: c058b1c4a5ea ("arm64: mte: system register definitions")
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
> arch/arm64/include/asm/sysreg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index e2ef4c2edf06..801861d05426 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -987,7 +987,7 @@
> #define SYS_TFSR_EL1_TF0_SHIFT 0
> #define SYS_TFSR_EL1_TF1_SHIFT 1
> #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
> -#define SYS_TFSR_EL1_TF1 (UK(2) << SYS_TFSR_EL1_TF1_SHIFT)
> +#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
I think we should first rename it to EU and then fix it properly ;).
While nothing breaks without this patch currently, we should merge it as
a fix.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Thanks.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: mte: Fix typo in macro definition
2020-11-30 17:07 ` Vincenzo Frascino
@ 2020-11-30 17:46 ` Will Deacon
-1 siblings, 0 replies; 6+ messages in thread
From: Will Deacon @ 2020-11-30 17:46 UTC (permalink / raw)
To: linux-kernel, kasan-dev, linux-arm-kernel, Vincenzo Frascino
Cc: catalin.marinas, kernel-team, Will Deacon
On Mon, 30 Nov 2020 17:07:09 +0000, Vincenzo Frascino wrote:
> UL in the definition of SYS_TFSR_EL1_TF1 was misspelled causing
> compilation issues when trying to implement in kernel MTE async
> mode.
>
> Fix the macro correcting the typo.
>
> Note: MTE async mode will be introduced with a future series.
Applied to arm64 (for-next/fixes), thanks!
[1/1] arm64: mte: Fix typo in macro definition
https://git.kernel.org/arm64/c/9e5344e0ffc3
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: mte: Fix typo in macro definition
@ 2020-11-30 17:46 ` Will Deacon
0 siblings, 0 replies; 6+ messages in thread
From: Will Deacon @ 2020-11-30 17:46 UTC (permalink / raw)
To: linux-kernel, kasan-dev, linux-arm-kernel, Vincenzo Frascino
Cc: catalin.marinas, kernel-team, Will Deacon
On Mon, 30 Nov 2020 17:07:09 +0000, Vincenzo Frascino wrote:
> UL in the definition of SYS_TFSR_EL1_TF1 was misspelled causing
> compilation issues when trying to implement in kernel MTE async
> mode.
>
> Fix the macro correcting the typo.
>
> Note: MTE async mode will be introduced with a future series.
Applied to arm64 (for-next/fixes), thanks!
[1/1] arm64: mte: Fix typo in macro definition
https://git.kernel.org/arm64/c/9e5344e0ffc3
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-11-30 17:47 UTC | newest]
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2020-11-30 17:07 [PATCH v2] arm64: mte: Fix typo in macro definition Vincenzo Frascino
2020-11-30 17:07 ` Vincenzo Frascino
2020-11-30 17:13 ` Catalin Marinas
2020-11-30 17:13 ` Catalin Marinas
2020-11-30 17:46 ` Will Deacon
2020-11-30 17:46 ` Will Deacon
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