From: Borislav Petkov <bp@alien8.de>
To: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Arvind Sankar <nivedita@alum.mit.edu>,
x86@kernel.org, Kim Phillips <kim.phillips@amd.com>,
Yazen Ghannam <yazen.ghannam@amd.com>, Pu Wen <puwen@hygon.cn>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86/cpu/amd: Remove dead code for TSEG region remapping
Date: Wed, 2 Dec 2020 19:10:08 +0100 [thread overview]
Message-ID: <20201202181008.GI2951@zn.tnic> (raw)
In-Reply-To: <b726e0d7-7dfb-d902-652f-8aab4bf43e89@amd.com>
On Wed, Dec 02, 2020 at 11:58:15AM -0600, Tom Lendacky wrote:
> I believe this is geared towards performance. If the TSEG base address is
> not 2MB aligned, then hardware has to break down a 2MB TLB entry if the OS
> references the memory within the 2MB page that is before the TSEG base
> address. This can occur whenever the 2MB TLB entry is re-installed because
> of TLB flushes, etc.
And if this gets reinstated properly, then that explanation belongs over
it because nothing else explains what that thing did. So thanks for
digging it out.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2020-12-02 18:10 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-27 17:13 [PATCH] x86/cpu/amd: Remove dead code for TSEG region remapping Arvind Sankar
2020-11-27 17:27 ` Borislav Petkov
2020-12-02 17:58 ` Tom Lendacky
2020-12-02 18:10 ` Borislav Petkov [this message]
2020-12-02 22:32 ` Arvind Sankar
2020-12-03 8:48 ` Borislav Petkov
2020-12-03 16:14 ` Arvind Sankar
2020-12-03 16:44 ` Borislav Petkov
2020-12-08 18:12 ` [tip: x86/cpu] " tip-bot2 for Arvind Sankar
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