* [PATCH 0/5] xhci features for usb-next @ 2020-12-08 9:29 Mathias Nyman 2020-12-08 9:29 ` [PATCH 1/5] usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK Mathias Nyman ` (4 more replies) 0 siblings, 5 replies; 8+ messages in thread From: Mathias Nyman @ 2020-12-08 9:29 UTC (permalink / raw) To: gregkh; +Cc: linux-usb, Mathias Nyman Hi Greg A few patches for usb-next, a bit late in the cycle but nice if they can make 5.11. -Mathias Hans de Goede (1): xhci-pci: Allow host runtime PM as default for Intel Alpine Ridge LP Li Jun (1): xhci: Give USB2 ports time to enter U3 in bus suspend Mika Westerberg (1): xhci-pci: Allow host runtime PM as default for Intel Maple Ridge xHCI Tejas Joglekar (2): usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK usb: xhci: Use temporary buffer to consolidate SG drivers/usb/host/xhci-hub.c | 4 ++ drivers/usb/host/xhci-pci.c | 6 +- drivers/usb/host/xhci-plat.c | 3 + drivers/usb/host/xhci-ring.c | 2 +- drivers/usb/host/xhci.c | 129 ++++++++++++++++++++++++++++++++++- drivers/usb/host/xhci.h | 5 ++ 6 files changed, 146 insertions(+), 3 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/5] usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK 2020-12-08 9:29 [PATCH 0/5] xhci features for usb-next Mathias Nyman @ 2020-12-08 9:29 ` Mathias Nyman 2020-12-08 9:29 ` [PATCH 2/5] usb: xhci: Use temporary buffer to consolidate SG Mathias Nyman ` (3 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: Mathias Nyman @ 2020-12-08 9:29 UTC (permalink / raw) To: gregkh; +Cc: linux-usb, Tejas Joglekar, Tejas Joglekar, Mathias Nyman From: Tejas Joglekar <Tejas.Joglekar@synopsys.com> This commit uses the private data passed by parent device to set the quirk for Synopsys xHC. This patch fixes the SNPS xHC hang issue when the data is scattered across small buffers which does not make atleast MPS size for given TRB cache size of SNPS xHC. Signed-off-by: Tejas Joglekar <joglekar@synopsys.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> --- drivers/usb/host/xhci-plat.c | 3 +++ drivers/usb/host/xhci.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c index aa2d35f98200..4d34f6005381 100644 --- a/drivers/usb/host/xhci-plat.c +++ b/drivers/usb/host/xhci-plat.c @@ -333,6 +333,9 @@ static int xhci_plat_probe(struct platform_device *pdev) if (priv && (priv->quirks & XHCI_SKIP_PHY_INIT)) hcd->skip_phy_initialization = 1; + if (priv && (priv->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK)) + xhci->quirks |= XHCI_SG_TRB_CACHE_SIZE_QUIRK; + ret = usb_add_hcd(hcd, irq, IRQF_SHARED); if (ret) goto disable_usb_phy; diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index ebb359ebb261..d90c0d5df3b3 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1878,6 +1878,7 @@ struct xhci_hcd { #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36) #define XHCI_SKIP_PHY_INIT BIT_ULL(37) #define XHCI_DISABLE_SPARSE BIT_ULL(38) +#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) unsigned int num_active_eps; unsigned int limit_active_eps; -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/5] usb: xhci: Use temporary buffer to consolidate SG 2020-12-08 9:29 [PATCH 0/5] xhci features for usb-next Mathias Nyman 2020-12-08 9:29 ` [PATCH 1/5] usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK Mathias Nyman @ 2020-12-08 9:29 ` Mathias Nyman 2020-12-08 9:29 ` [PATCH 3/5] xhci-pci: Allow host runtime PM as default for Intel Alpine Ridge LP Mathias Nyman ` (2 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: Mathias Nyman @ 2020-12-08 9:29 UTC (permalink / raw) To: gregkh; +Cc: linux-usb, Tejas Joglekar, Tejas Joglekar, Mathias Nyman From: Tejas Joglekar <Tejas.Joglekar@synopsys.com> The Synopsys xHC has an internal TRB cache of size TRB_CACHE_SIZE for each endpoint. The default value for TRB_CACHE_SIZE is 16 for SS and 8 for HS. The controller loads and updates the TRB cache from the transfer ring in system memory whenever the driver issues a start transfer or update transfer command. For chained TRBs, the Synopsys xHC requires that the total amount of bytes for all TRBs loaded in the TRB cache be greater than or equal to 1 MPS. Or the chain ends within the TRB cache (with a last TRB). If this requirement is not met, the controller will not be able to send or receive a packet and it will hang causing a driver timeout and error. This can be a problem if a class driver queues SG requests with many small-buffer entries. The XHCI driver will create a chained TRB for each entry which may trigger this issue. This patch adds logic to the XHCI driver to detect and prevent this from happening. For every (TRB_CACHE_SIZE - 2), we check the total buffer size of the SG list and if the last window of (TRB_CACHE_SIZE - 2) SG list length and we don't make up at least 1 MPS, we create a temporary buffer to consolidate full SG list into the buffer. We check at (TRB_CACHE_SIZE - 2) window because it is possible that there would be a link and/or event data TRB that take up to 2 of the cache entries. We discovered this issue with devices on other platforms but have not yet come across any device that triggers this on Linux. But it could be a real problem now or in the future. All it takes is N number of small chained TRBs. And other instances of the Synopsys IP may have smaller values for the TRB_CACHE_SIZE which would exacerbate the problem. Signed-off-by: Tejas Joglekar <joglekar@synopsys.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> --- drivers/usb/host/xhci-ring.c | 2 +- drivers/usb/host/xhci.c | 129 ++++++++++++++++++++++++++++++++++- drivers/usb/host/xhci.h | 4 ++ 3 files changed, 133 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 167dae117f73..6d4dae5e5f21 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -3325,7 +3325,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, full_len = urb->transfer_buffer_length; /* If we have scatter/gather list, we use it. */ - if (urb->num_sgs) { + if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) { num_sgs = urb->num_mapped_sgs; sg = urb->sg; addr = (u64) sg_dma_address(sg); diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index d4a8d0efbbc4..5b0b5f1bb40d 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -1259,6 +1259,108 @@ EXPORT_SYMBOL_GPL(xhci_resume); /*-------------------------------------------------------------------------*/ +static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb) +{ + void *temp; + int ret = 0; + unsigned int buf_len; + enum dma_data_direction dir; + + dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; + buf_len = urb->transfer_buffer_length; + + temp = kzalloc_node(buf_len, GFP_ATOMIC, + dev_to_node(hcd->self.sysdev)); + + if (usb_urb_dir_out(urb)) + sg_pcopy_to_buffer(urb->sg, urb->num_sgs, + temp, buf_len, 0); + + urb->transfer_buffer = temp; + urb->transfer_dma = dma_map_single(hcd->self.sysdev, + urb->transfer_buffer, + urb->transfer_buffer_length, + dir); + + if (dma_mapping_error(hcd->self.sysdev, + urb->transfer_dma)) { + ret = -EAGAIN; + kfree(temp); + } else { + urb->transfer_flags |= URB_DMA_MAP_SINGLE; + } + + return ret; +} + +static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd, + struct urb *urb) +{ + bool ret = false; + unsigned int i; + unsigned int len = 0; + unsigned int trb_size; + unsigned int max_pkt; + struct scatterlist *sg; + struct scatterlist *tail_sg; + + tail_sg = urb->sg; + max_pkt = usb_endpoint_maxp(&urb->ep->desc); + + if (!urb->num_sgs) + return ret; + + if (urb->dev->speed >= USB_SPEED_SUPER) + trb_size = TRB_CACHE_SIZE_SS; + else + trb_size = TRB_CACHE_SIZE_HS; + + if (urb->transfer_buffer_length != 0 && + !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) { + for_each_sg(urb->sg, sg, urb->num_sgs, i) { + len = len + sg->length; + if (i > trb_size - 2) { + len = len - tail_sg->length; + if (len < max_pkt) { + ret = true; + break; + } + + tail_sg = sg_next(tail_sg); + } + } + } + return ret; +} + +static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb) +{ + unsigned int len; + unsigned int buf_len; + enum dma_data_direction dir; + + dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; + + buf_len = urb->transfer_buffer_length; + + if (IS_ENABLED(CONFIG_HAS_DMA) && + (urb->transfer_flags & URB_DMA_MAP_SINGLE)) + dma_unmap_single(hcd->self.sysdev, + urb->transfer_dma, + urb->transfer_buffer_length, + dir); + + if (usb_urb_dir_in(urb)) + len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, + urb->transfer_buffer, + buf_len, + 0); + + urb->transfer_flags &= ~URB_DMA_MAP_SINGLE; + kfree(urb->transfer_buffer); + urb->transfer_buffer = NULL; +} + /* * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT), * we'll copy the actual data into the TRB address register. This is limited to @@ -1268,13 +1370,37 @@ EXPORT_SYMBOL_GPL(xhci_resume); static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) { + struct xhci_hcd *xhci; + + xhci = hcd_to_xhci(hcd); + if (xhci_urb_suitable_for_idt(urb)) return 0; + if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) { + if (xhci_urb_temp_buffer_required(hcd, urb)) + return xhci_map_temp_buffer(hcd, urb); + } return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); } -/* +static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) +{ + struct xhci_hcd *xhci; + bool unmap_temp_buf = false; + + xhci = hcd_to_xhci(hcd); + + if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE)) + unmap_temp_buf = true; + + if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf) + xhci_unmap_temp_buf(hcd, urb); + else + usb_hcd_unmap_urb_for_dma(hcd, urb); +} + +/** * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and * HCDs. Find the index for an endpoint given its descriptor. Use the return * value to right shift 1 for the bitmask. @@ -5329,6 +5455,7 @@ static const struct hc_driver xhci_hc_driver = { * managing i/o requests and associated device resources */ .map_urb_for_dma = xhci_map_urb_for_dma, + .unmap_urb_for_dma = xhci_unmap_urb_for_dma, .urb_enqueue = xhci_urb_enqueue, .urb_dequeue = xhci_urb_dequeue, .alloc_dev = xhci_alloc_dev, diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index d90c0d5df3b3..25e57bc9c3cc 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1330,6 +1330,10 @@ enum xhci_setup_dev { #define TRB_SIA (1<<31) #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) +/* TRB cache size for xHC with TRB cache */ +#define TRB_CACHE_SIZE_HS 8 +#define TRB_CACHE_SIZE_SS 16 + struct xhci_generic_trb { __le32 field[4]; }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/5] xhci-pci: Allow host runtime PM as default for Intel Alpine Ridge LP 2020-12-08 9:29 [PATCH 0/5] xhci features for usb-next Mathias Nyman 2020-12-08 9:29 ` [PATCH 1/5] usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK Mathias Nyman 2020-12-08 9:29 ` [PATCH 2/5] usb: xhci: Use temporary buffer to consolidate SG Mathias Nyman @ 2020-12-08 9:29 ` Mathias Nyman 2020-12-08 9:29 ` [PATCH 4/5] xhci-pci: Allow host runtime PM as default for Intel Maple Ridge xHCI Mathias Nyman 2020-12-08 9:29 ` [PATCH 5/5] xhci: Give USB2 ports time to enter U3 in bus suspend Mathias Nyman 4 siblings, 0 replies; 8+ messages in thread From: Mathias Nyman @ 2020-12-08 9:29 UTC (permalink / raw) To: gregkh; +Cc: linux-usb, Hans de Goede, stable, Mika Westerberg, Mathias Nyman From: Hans de Goede <hdegoede@redhat.com> The xHCI controller on Alpine Ridge LP keeps the whole Thunderbolt controller awake if the host controller is not allowed to sleep. This is the case even if no USB devices are connected to the host. Add the Intel Alpine Ridge LP product-id to the list of product-ids for which we allow runtime PM by default. Fixes: 2815ef7fe4d4 ("xhci-pci: allow host runtime PM as default for Intel Alpine and Titan Ridge") Cc: <stable@vger.kernel.org> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> --- drivers/usb/host/xhci-pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index bf89172c43ca..5f94d7edeb37 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -47,6 +47,7 @@ #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 +#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 @@ -232,6 +233,7 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) if (pdev->vendor == PCI_VENDOR_ID_INTEL && (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || + pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/5] xhci-pci: Allow host runtime PM as default for Intel Maple Ridge xHCI 2020-12-08 9:29 [PATCH 0/5] xhci features for usb-next Mathias Nyman ` (2 preceding siblings ...) 2020-12-08 9:29 ` [PATCH 3/5] xhci-pci: Allow host runtime PM as default for Intel Alpine Ridge LP Mathias Nyman @ 2020-12-08 9:29 ` Mathias Nyman 2020-12-08 9:39 ` Greg KH 2020-12-08 9:29 ` [PATCH 5/5] xhci: Give USB2 ports time to enter U3 in bus suspend Mathias Nyman 4 siblings, 1 reply; 8+ messages in thread From: Mathias Nyman @ 2020-12-08 9:29 UTC (permalink / raw) To: gregkh; +Cc: linux-usb, Mika Westerberg, Mathias Nyman From: Mika Westerberg <mika.westerberg@linux.intel.com> Intel Maple Ridge is successor of Titan Ridge Thunderbolt controller. As Titan Ridge this one also includes xHCI host controller. In order to safe energy we should put it to low power state by default when idle. For this reason allow host runtime PM for Maple Ridge. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> --- drivers/usb/host/xhci-pci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 5f94d7edeb37..84da8406d5b4 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -56,6 +56,7 @@ #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 +#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba @@ -240,7 +241,8 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || - pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI)) + pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || + pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; if (pdev->vendor == PCI_VENDOR_ID_ETRON && -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 4/5] xhci-pci: Allow host runtime PM as default for Intel Maple Ridge xHCI 2020-12-08 9:29 ` [PATCH 4/5] xhci-pci: Allow host runtime PM as default for Intel Maple Ridge xHCI Mathias Nyman @ 2020-12-08 9:39 ` Greg KH 2020-12-08 11:21 ` Mathias Nyman 0 siblings, 1 reply; 8+ messages in thread From: Greg KH @ 2020-12-08 9:39 UTC (permalink / raw) To: Mathias Nyman; +Cc: linux-usb, Mika Westerberg On Tue, Dec 08, 2020 at 11:29:11AM +0200, Mathias Nyman wrote: > From: Mika Westerberg <mika.westerberg@linux.intel.com> > > Intel Maple Ridge is successor of Titan Ridge Thunderbolt controller. As > Titan Ridge this one also includes xHCI host controller. In order to > safe energy we should put it to low power state by default when idle. > For this reason allow host runtime PM for Maple Ridge. > > Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> > Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> > --- > drivers/usb/host/xhci-pci.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Should this be backported to stable kernels too? thanks, greg k-h ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 4/5] xhci-pci: Allow host runtime PM as default for Intel Maple Ridge xHCI 2020-12-08 9:39 ` Greg KH @ 2020-12-08 11:21 ` Mathias Nyman 0 siblings, 0 replies; 8+ messages in thread From: Mathias Nyman @ 2020-12-08 11:21 UTC (permalink / raw) To: Greg KH; +Cc: linux-usb, Mika Westerberg On 8.12.2020 11.39, Greg KH wrote: > On Tue, Dec 08, 2020 at 11:29:11AM +0200, Mathias Nyman wrote: >> From: Mika Westerberg <mika.westerberg@linux.intel.com> >> >> Intel Maple Ridge is successor of Titan Ridge Thunderbolt controller. As >> Titan Ridge this one also includes xHCI host controller. In order to >> safe energy we should put it to low power state by default when idle. >> For this reason allow host runtime PM for Maple Ridge. >> >> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> >> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> >> --- >> drivers/usb/host/xhci-pci.c | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) > > Should this be backported to stable kernels too? I guess that wouldn't hurt. Hardware is fresh but distros probably base their releases on older stable kernels. This would enable xhci runtime pm as default on those as well Thanks Mathias ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 5/5] xhci: Give USB2 ports time to enter U3 in bus suspend 2020-12-08 9:29 [PATCH 0/5] xhci features for usb-next Mathias Nyman ` (3 preceding siblings ...) 2020-12-08 9:29 ` [PATCH 4/5] xhci-pci: Allow host runtime PM as default for Intel Maple Ridge xHCI Mathias Nyman @ 2020-12-08 9:29 ` Mathias Nyman 4 siblings, 0 replies; 8+ messages in thread From: Mathias Nyman @ 2020-12-08 9:29 UTC (permalink / raw) To: gregkh; +Cc: linux-usb, Li Jun, stable, Mathias Nyman From: Li Jun <jun.li@nxp.com> If a USB2 device wakeup is not enabled/supported the link state may still be in U0 in xhci_bus_suspend(), where it's then manually put to suspended U3 state. Just as with selective suspend the device needs time to enter U3 suspend before continuing with further suspend operations (e.g. system suspend), otherwise we may enter system suspend with link state in U0. [commit message rewording -Mathias] Cc: <stable@vger.kernel.org> Signed-off-by: Li Jun <jun.li@nxp.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> --- drivers/usb/host/xhci-hub.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c index c799ca5361d4..74c497fd3476 100644 --- a/drivers/usb/host/xhci-hub.c +++ b/drivers/usb/host/xhci-hub.c @@ -1712,6 +1712,10 @@ int xhci_bus_suspend(struct usb_hcd *hcd) hcd->state = HC_STATE_SUSPENDED; bus_state->next_statechange = jiffies + msecs_to_jiffies(10); spin_unlock_irqrestore(&xhci->lock, flags); + + if (bus_state->bus_suspended) + usleep_range(5000, 10000); + return 0; } -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-12-08 11:21 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-12-08 9:29 [PATCH 0/5] xhci features for usb-next Mathias Nyman 2020-12-08 9:29 ` [PATCH 1/5] usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK Mathias Nyman 2020-12-08 9:29 ` [PATCH 2/5] usb: xhci: Use temporary buffer to consolidate SG Mathias Nyman 2020-12-08 9:29 ` [PATCH 3/5] xhci-pci: Allow host runtime PM as default for Intel Alpine Ridge LP Mathias Nyman 2020-12-08 9:29 ` [PATCH 4/5] xhci-pci: Allow host runtime PM as default for Intel Maple Ridge xHCI Mathias Nyman 2020-12-08 9:39 ` Greg KH 2020-12-08 11:21 ` Mathias Nyman 2020-12-08 9:29 ` [PATCH 5/5] xhci: Give USB2 ports time to enter U3 in bus suspend Mathias Nyman
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