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* [PATCH] drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for raven
@ 2020-12-09  2:06 Changfeng.Zhu
  2020-12-09  2:19 ` Deucher, Alexander
  0 siblings, 1 reply; 3+ messages in thread
From: Changfeng.Zhu @ 2020-12-09  2:06 UTC (permalink / raw)
  To: amd-gfx, Ray.Huang; +Cc: changzhu

From: changzhu <Changfeng.Zhu@amd.com>

From: Changfeng <Changfeng.Zhu@amd.com>

When using old WORKLOAD_PPLIB setting in smu10.h, there is problem that
it can't be able to switch to mak gpu clk during compute workload.
It needs to update WORKLOAD_PPLIB setting to fix this issue.

Change-Id: Id2160a7b4a6cb8808d100de25e999714a7ccaebd
Signed-off-by: Changfeng <Changfeng.Zhu@amd.com>
---
 drivers/gpu/drm/amd/pm/inc/smu10.h                 | 14 ++++++--------
 .../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c   |  9 +++------
 2 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu10.h b/drivers/gpu/drm/amd/pm/inc/smu10.h
index b96520528240..9e837a5014c5 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu10.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu10.h
@@ -136,14 +136,12 @@
 #define FEATURE_CORE_CSTATES_MASK     (1 << FEATURE_CORE_CSTATES_BIT)
 
 /* Workload bits */
-#define WORKLOAD_DEFAULT_BIT              0
-#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
-#define WORKLOAD_PPLIB_POWER_SAVING_BIT   2
-#define WORKLOAD_PPLIB_VIDEO_BIT          3
-#define WORKLOAD_PPLIB_VR_BIT             4
-#define WORKLOAD_PPLIB_COMPUTE_BIT        5
-#define WORKLOAD_PPLIB_CUSTOM_BIT         6
-#define WORKLOAD_PPLIB_COUNT              7
+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
+#define WORKLOAD_PPLIB_VIDEO_BIT          2
+#define WORKLOAD_PPLIB_VR_BIT             3
+#define WORKLOAD_PPLIB_COMPUTE_BIT        4
+#define WORKLOAD_PPLIB_CUSTOM_BIT         5
+#define WORKLOAD_PPLIB_COUNT              6
 
 typedef struct {
 	/* MP1_EXT_SCRATCH0 */
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 04226b1544e4..e57e64bbacdc 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -1298,15 +1298,9 @@ static int conv_power_profile_to_pplib_workload(int power_profile)
 	int pplib_workload = 0;
 
 	switch (power_profile) {
-	case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
-		pplib_workload = WORKLOAD_DEFAULT_BIT;
-		break;
 	case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
 		pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
 		break;
-	case PP_SMC_POWER_PROFILE_POWERSAVING:
-		pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
-		break;
 	case PP_SMC_POWER_PROFILE_VIDEO:
 		pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
 		break;
@@ -1316,6 +1310,9 @@ static int conv_power_profile_to_pplib_workload(int power_profile)
 	case PP_SMC_POWER_PROFILE_COMPUTE:
 		pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
 		break;
+	case PP_SMC_POWER_PROFILE_CUSTOM:
+		pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
+		break;
 	}
 
 	return pplib_workload;
-- 
2.17.1

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for raven
  2020-12-09  2:06 [PATCH] drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for raven Changfeng.Zhu
@ 2020-12-09  2:19 ` Deucher, Alexander
  2020-12-09  2:49   ` Huang Rui
  0 siblings, 1 reply; 3+ messages in thread
From: Deucher, Alexander @ 2020-12-09  2:19 UTC (permalink / raw)
  To: Zhu, Changfeng, amd-gfx, Huang, Ray


[-- Attachment #1.1: Type: text/plain, Size: 4075 bytes --]

[AMD Official Use Only - Internal Distribution Only]

Acked-by: Alex Deucher <alexander.deucher@amd.com>

________________________________
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Changfeng.Zhu <changfeng.zhu@amd.com>
Sent: Tuesday, December 8, 2020 9:06 PM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Huang, Ray <Ray.Huang@amd.com>
Cc: Zhu, Changfeng <Changfeng.Zhu@amd.com>
Subject: [PATCH] drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for raven

From: changzhu <Changfeng.Zhu@amd.com>

From: Changfeng <Changfeng.Zhu@amd.com>

When using old WORKLOAD_PPLIB setting in smu10.h, there is problem that
it can't be able to switch to mak gpu clk during compute workload.
It needs to update WORKLOAD_PPLIB setting to fix this issue.

Change-Id: Id2160a7b4a6cb8808d100de25e999714a7ccaebd
Signed-off-by: Changfeng <Changfeng.Zhu@amd.com>
---
 drivers/gpu/drm/amd/pm/inc/smu10.h                 | 14 ++++++--------
 .../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c   |  9 +++------
 2 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu10.h b/drivers/gpu/drm/amd/pm/inc/smu10.h
index b96520528240..9e837a5014c5 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu10.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu10.h
@@ -136,14 +136,12 @@
 #define FEATURE_CORE_CSTATES_MASK     (1 << FEATURE_CORE_CSTATES_BIT)

 /* Workload bits */
-#define WORKLOAD_DEFAULT_BIT              0
-#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
-#define WORKLOAD_PPLIB_POWER_SAVING_BIT   2
-#define WORKLOAD_PPLIB_VIDEO_BIT          3
-#define WORKLOAD_PPLIB_VR_BIT             4
-#define WORKLOAD_PPLIB_COMPUTE_BIT        5
-#define WORKLOAD_PPLIB_CUSTOM_BIT         6
-#define WORKLOAD_PPLIB_COUNT              7
+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
+#define WORKLOAD_PPLIB_VIDEO_BIT          2
+#define WORKLOAD_PPLIB_VR_BIT             3
+#define WORKLOAD_PPLIB_COMPUTE_BIT        4
+#define WORKLOAD_PPLIB_CUSTOM_BIT         5
+#define WORKLOAD_PPLIB_COUNT              6

 typedef struct {
         /* MP1_EXT_SCRATCH0 */
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 04226b1544e4..e57e64bbacdc 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -1298,15 +1298,9 @@ static int conv_power_profile_to_pplib_workload(int power_profile)
         int pplib_workload = 0;

         switch (power_profile) {
-       case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
-               pplib_workload = WORKLOAD_DEFAULT_BIT;
-               break;
         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
                 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
                 break;
-       case PP_SMC_POWER_PROFILE_POWERSAVING:
-               pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
-               break;
         case PP_SMC_POWER_PROFILE_VIDEO:
                 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
                 break;
@@ -1316,6 +1310,9 @@ static int conv_power_profile_to_pplib_workload(int power_profile)
         case PP_SMC_POWER_PROFILE_COMPUTE:
                 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
                 break;
+       case PP_SMC_POWER_PROFILE_CUSTOM:
+               pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
+               break;
         }

         return pplib_workload;
--
2.17.1

_______________________________________________
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amd-gfx@lists.freedesktop.org
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[-- Attachment #1.2: Type: text/html, Size: 7896 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for raven
  2020-12-09  2:19 ` Deucher, Alexander
@ 2020-12-09  2:49   ` Huang Rui
  0 siblings, 0 replies; 3+ messages in thread
From: Huang Rui @ 2020-12-09  2:49 UTC (permalink / raw)
  To: Deucher, Alexander; +Cc: amd-gfx, Zhu, Changfeng

Reviewed-by: Huang Rui <ray.huang@amd.com>

On Wed, Dec 09, 2020 at 10:19:24AM +0800, Deucher, Alexander wrote:
>    [AMD Official Use Only - Internal Distribution Only]
> 
>    Acked-by: Alex Deucher <alexander.deucher@amd.com>
>      __________________________________________________________________
> 
>    From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of
>    Changfeng.Zhu <changfeng.zhu@amd.com>
>    Sent: Tuesday, December 8, 2020 9:06 PM
>    To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>;
>    Huang, Ray <Ray.Huang@amd.com>
>    Cc: Zhu, Changfeng <Changfeng.Zhu@amd.com>
>    Subject: [PATCH] drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for
>    raven
> 
>    From: changzhu <Changfeng.Zhu@amd.com>
>    From: Changfeng <Changfeng.Zhu@amd.com>
>    When using old WORKLOAD_PPLIB setting in smu10.h, there is problem that
>    it can't be able to switch to mak gpu clk during compute workload.
>    It needs to update WORKLOAD_PPLIB setting to fix this issue.
>    Change-Id: Id2160a7b4a6cb8808d100de25e999714a7ccaebd
>    Signed-off-by: Changfeng <Changfeng.Zhu@amd.com>
>    ---
>     drivers/gpu/drm/amd/pm/inc/smu10.h                 | 14 ++++++--------
>     .../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c   |  9 +++------
>     2 files changed, 9 insertions(+), 14 deletions(-)
>    diff --git a/drivers/gpu/drm/amd/pm/inc/smu10.h
>    b/drivers/gpu/drm/amd/pm/inc/smu10.h
>    index b96520528240..9e837a5014c5 100644
>    --- a/drivers/gpu/drm/amd/pm/inc/smu10.h
>    +++ b/drivers/gpu/drm/amd/pm/inc/smu10.h
>    @@ -136,14 +136,12 @@
>     #define FEATURE_CORE_CSTATES_MASK     (1 << FEATURE_CORE_CSTATES_BIT)
> 
>     /* Workload bits */
>    -#define WORKLOAD_DEFAULT_BIT              0
>    -#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
>    -#define WORKLOAD_PPLIB_POWER_SAVING_BIT   2
>    -#define WORKLOAD_PPLIB_VIDEO_BIT          3
>    -#define WORKLOAD_PPLIB_VR_BIT             4
>    -#define WORKLOAD_PPLIB_COMPUTE_BIT        5
>    -#define WORKLOAD_PPLIB_CUSTOM_BIT         6
>    -#define WORKLOAD_PPLIB_COUNT              7
>    +#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
>    +#define WORKLOAD_PPLIB_VIDEO_BIT          2
>    +#define WORKLOAD_PPLIB_VR_BIT             3
>    +#define WORKLOAD_PPLIB_COMPUTE_BIT        4
>    +#define WORKLOAD_PPLIB_CUSTOM_BIT         5
>    +#define WORKLOAD_PPLIB_COUNT              6
> 
>     typedef struct {
>             /* MP1_EXT_SCRATCH0 */
>    diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
>    b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
>    index 04226b1544e4..e57e64bbacdc 100644
>    --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
>    +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
>    @@ -1298,15 +1298,9 @@ static int
>    conv_power_profile_to_pplib_workload(int power_profile)
>             int pplib_workload = 0;
> 
>             switch (power_profile) {
>    -       case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
>    -               pplib_workload = WORKLOAD_DEFAULT_BIT;
>    -               break;
>             case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
>                     pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
>                     break;
>    -       case PP_SMC_POWER_PROFILE_POWERSAVING:
>    -               pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
>    -               break;
>             case PP_SMC_POWER_PROFILE_VIDEO:
>                     pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
>                     break;
>    @@ -1316,6 +1310,9 @@ static int
>    conv_power_profile_to_pplib_workload(int power_profile)
>             case PP_SMC_POWER_PROFILE_COMPUTE:
>                     pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
>                     break;
>    +       case PP_SMC_POWER_PROFILE_CUSTOM:
>    +               pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
>    +               break;
>             }
> 
>             return pplib_workload;
>    --
>    2.17.1
>    _______________________________________________
>    amd-gfx mailing list
>    amd-gfx@lists.freedesktop.org
>    [1]https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
>    sts.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Ca
>    lexander.deucher%40amd.com%7C2f57b9a4012a424d574908d89be7299b%7C3dd8961
>    fe4884e608e11a82d994e183d%7C0%7C0%7C637430764514589029%7CUnknown%7CTWFp
>    bGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0
>    %3D%7C1000&amp;sdata=OWntFjcijTjJa0Qrsi7YTvrEWQcIXM8dHsXxhOaKsng%3D&amp
>    ;reserved=0
> 
> References
> 
>    1. https://nam11.safelinks.protection.outlook.com/?url=https://lists.freedesktop.org/mailman/listinfo/amd-gfx&amp;data=04|01|alexander.deucher@amd.com|2f57b9a4012a424d574908d89be7299b|3dd8961fe4884e608e11a82d994e183d|0|0|637430764514589029|Unknown|TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0=|1000&amp;sdata=OWntFjcijTjJa0Qrsi7YTvrEWQcIXM8dHsXxhOaKsng=&amp;reserved=0
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^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-12-09  2:50 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-09  2:06 [PATCH] drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for raven Changfeng.Zhu
2020-12-09  2:19 ` Deucher, Alexander
2020-12-09  2:49   ` Huang Rui

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