* [Intel-gfx] [PATCH] drm/i915/gt: Rearrange snb workarounds
@ 2020-12-09 13:42 Chris Wilson
2020-12-09 15:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Chris Wilson @ 2020-12-09 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 67 ++++++++++-----------
1 file changed, 33 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b5339a36d256..50cfe82f18a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -823,40 +823,6 @@ ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
static void
snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
- wa_masked_en(wal,
- _3D_CHICKEN,
- _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
-
- /* WaDisable_RenderCache_OperationalFlush:snb */
- wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
-
- /*
- * BSpec recommends 8x4 when MSAA is used,
- * however in practice 16x4 seems fastest.
- *
- * Note that PS/WM thread counts depend on the WIZ hashing
- * disable bit, which we don't touch here, but it's good
- * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
- */
- wa_add(wal,
- GEN6_GT_MODE, 0,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
- GEN6_WIZ_HASHING_16x4);
-
- wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB);
-
- wa_masked_en(wal,
- _3D_CHICKEN3,
- /* WaStripsFansDisableFastClipPerformanceFix:snb */
- _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL |
- /*
- * Bspec says:
- * "This bit must be set if 3DSTATE_CLIP clip mode is set
- * to normal and 3DSTATE_SF number of SF output attributes
- * is more than 16."
- */
- _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH);
}
static void
@@ -2008,6 +1974,39 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GFX_MODE,
GFX_TLB_INVALIDATE_EXPLICIT);
+ /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
+ wa_masked_en(wal,
+ _3D_CHICKEN,
+ _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
+
+ wa_masked_en(wal,
+ _3D_CHICKEN3,
+ /* WaStripsFansDisableFastClipPerformanceFix:snb */
+ _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL |
+ /*
+ * Bspec says:
+ * "This bit must be set if 3DSTATE_CLIP clip mode is set
+ * to normal and 3DSTATE_SF number of SF output attributes
+ * is more than 16."
+ */
+ _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH);
+
+ /*
+ * BSpec recommends 8x4 when MSAA is used,
+ * however in practice 16x4 seems fastest.
+ *
+ * Note that PS/WM thread counts depend on the WIZ hashing
+ * disable bit, which we don't touch here, but it's good
+ * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+ */
+ wa_add(wal,
+ GEN6_GT_MODE, 0,
+ _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
+ GEN6_WIZ_HASHING_16x4);
+
+ /* WaDisable_RenderCache_OperationalFlush:snb */
+ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
+
/*
* From the Sandybridge PRM, volume 1 part 3, page 24:
* "If this bit is set, STCunit will have LRA as replacement
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Rearrange snb workarounds
2020-12-09 13:42 [Intel-gfx] [PATCH] drm/i915/gt: Rearrange snb workarounds Chris Wilson
@ 2020-12-09 15:01 ` Patchwork
2020-12-09 16:16 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-12-10 10:36 ` [Intel-gfx] [PATCH] " Mika Kuoppala
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-12-09 15:01 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4272 bytes --]
== Series Details ==
Series: drm/i915/gt: Rearrange snb workarounds
URL : https://patchwork.freedesktop.org/series/84729/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9464 -> Patchwork_19092
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/index.html
Known issues
------------
Here are the changes found in Patchwork_19092 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@userptr:
- fi-byt-j1900: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/fi-byt-j1900/igt@amdgpu/amd_basic@userptr.html
* igt@prime_vgem@basic-fence-flip:
- fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][4] ([i915#2029] / [i915#2722])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [INCOMPLETE][5] ([i915#142] / [i915#2405]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
- fi-kbl-guc: [FAIL][7] ([i915#579]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050: [DMESG-FAIL][9] ([i915#2675]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@sanitycheck:
- fi-kbl-7500u: [DMESG-WARN][11] ([i915#2605]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/fi-kbl-7500u/igt@i915_selftest@live@sanitycheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/fi-kbl-7500u/igt@i915_selftest@live@sanitycheck.html
* igt@vgem_basic@create:
- fi-tgl-y: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/fi-tgl-y/igt@vgem_basic@create.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/fi-tgl-y/igt@vgem_basic@create.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[i915#2675]: https://gitlab.freedesktop.org/drm/intel/issues/2675
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (43 -> 40)
------------------------------
Missing (3): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9464 -> Patchwork_19092
CI-20190529: 20190529
CI_DRM_9464: a2561d7ce07920c1fc05013c87d21d3c8b05149f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5885: d99f644b1868b9c92435b05ebfafa230721cd677 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19092: be2ef59506aad3f024417ad8cedfd53ad76cb5d1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
be2ef59506aa drm/i915/gt: Rearrange snb workarounds
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/index.html
[-- Attachment #1.2: Type: text/html, Size: 5127 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Rearrange snb workarounds
2020-12-09 13:42 [Intel-gfx] [PATCH] drm/i915/gt: Rearrange snb workarounds Chris Wilson
2020-12-09 15:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
@ 2020-12-09 16:16 ` Patchwork
2020-12-10 10:36 ` [Intel-gfx] [PATCH] " Mika Kuoppala
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-12-09 16:16 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 12798 bytes --]
== Series Details ==
Series: drm/i915/gt: Rearrange snb workarounds
URL : https://patchwork.freedesktop.org/series/84729/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9464_full -> Patchwork_19092_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_19092_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_params@no-vebox:
- shard-skl: NOTRUN -> [SKIP][1] ([fdo#109271]) +38 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-skl1/igt@gem_exec_params@no-vebox.html
* igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][2] ([i915#2389])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-iclb4/igt@gem_exec_reloc@basic-many-active@vcs1.html
* igt@gem_exec_whisper@basic-contexts-forked:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([i915#1895])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-iclb2/igt@gem_exec_whisper@basic-contexts-forked.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-iclb1/igt@gem_exec_whisper@basic-contexts-forked.html
* igt@gem_exec_whisper@basic-queues-forked:
- shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([i915#1895] / [i915#2405])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-iclb1/igt@gem_exec_whisper@basic-queues-forked.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-iclb8/igt@gem_exec_whisper@basic-queues-forked.html
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +4 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-skl1/igt@kms_chamelium@dp-hpd-storm-disable.html
* igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen:
- shard-skl: [PASS][8] -> [FAIL][9] ([i915#54]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][10] -> [FAIL][11] ([i915#2346] / [i915#533])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2346])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-tglb8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-skl1/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#52] / [i915#54])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-glk1/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-glk2/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#1188]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][19] ([fdo#108145] / [i915#265]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][20] -> [FAIL][21] ([fdo#108145] / [i915#265])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#109441]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
#### Possible fixes ####
* igt@gem_exec_gttfill@engines@rcs0:
- shard-glk: [DMESG-WARN][24] ([i915#118] / [i915#95]) -> [PASS][25] +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-glk4/igt@gem_exec_gttfill@engines@rcs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-glk4/igt@gem_exec_gttfill@engines@rcs0.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [FAIL][26] ([i915#2597]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-tglb5/igt@kms_async_flips@test-time-stamp.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-tglb2/igt@kms_async_flips@test-time-stamp.html
* igt@kms_color@pipe-c-ctm-0-75:
- shard-skl: [DMESG-WARN][28] ([i915#1982]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl4/igt@kms_color@pipe-c-ctm-0-75.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-skl8/igt@kms_color@pipe-c-ctm-0-75.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-random:
- shard-skl: [FAIL][30] ([i915#54]) -> [PASS][31] +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [INCOMPLETE][32] ([i915#300]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-skl: [FAIL][34] ([i915#2346]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [FAIL][36] ([i915#2122]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][38] ([fdo#109642] / [fdo#111068]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-iclb5/igt@kms_psr2_su@frontbuffer.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [SKIP][40] ([fdo#109441]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-iclb7/igt@kms_psr@psr2_sprite_render.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
* igt@perf@polling-parameterized:
- shard-apl: [FAIL][42] ([i915#1542]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-apl4/igt@perf@polling-parameterized.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-apl2/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][44] ([i915#2684]) -> [WARN][45] ([i915#2681] / [i915#2684])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][46] ([i915#1804] / [i915#2684]) -> [WARN][47] ([i915#2684])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@runner@aborted:
- shard-glk: ([FAIL][48], [FAIL][49]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#483] / [k.org#202321]) -> ([FAIL][50], [FAIL][51]) ([i915#1814] / [i915#2295] / [i915#2722] / [k.org#202321])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-glk7/igt@runner@aborted.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9464/shard-glk4/igt@runner@aborted.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-glk2/igt@runner@aborted.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/shard-glk1/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1895]: https://gitlab.freedesktop.org/drm/intel/issues/1895
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2597]: https://gitlab.freedesktop.org/drm/intel/issues/2597
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9464 -> Patchwork_19092
CI-20190529: 20190529
CI_DRM_9464: a2561d7ce07920c1fc05013c87d21d3c8b05149f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5885: d99f644b1868b9c92435b05ebfafa230721cd677 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19092: be2ef59506aad3f024417ad8cedfd53ad76cb5d1 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19092/index.html
[-- Attachment #1.2: Type: text/html, Size: 15432 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Rearrange snb workarounds
2020-12-09 13:42 [Intel-gfx] [PATCH] drm/i915/gt: Rearrange snb workarounds Chris Wilson
2020-12-09 15:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-12-09 16:16 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-12-10 10:36 ` Mika Kuoppala
2020-12-10 10:41 ` Chris Wilson
2 siblings, 1 reply; 6+ messages in thread
From: Mika Kuoppala @ 2020-12-10 10:36 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Some rcs0 workarounds were being incorrectly applied to the GT, and so
> we failed to restore the expected register settings after a reset.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 67 ++++++++++-----------
> 1 file changed, 33 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index b5339a36d256..50cfe82f18a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -823,40 +823,6 @@ ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> static void
> snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> - /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
> - wa_masked_en(wal,
> - _3D_CHICKEN,
> - _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
> -
> - /* WaDisable_RenderCache_OperationalFlush:snb */
> - wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
> -
> - /*
> - * BSpec recommends 8x4 when MSAA is used,
> - * however in practice 16x4 seems fastest.
> - *
> - * Note that PS/WM thread counts depend on the WIZ hashing
> - * disable bit, which we don't touch here, but it's good
> - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> - */
> - wa_add(wal,
> - GEN6_GT_MODE, 0,
> - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
> - GEN6_WIZ_HASHING_16x4);
> -
> - wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB);
Where did this go?
-Mika
> -
> - wa_masked_en(wal,
> - _3D_CHICKEN3,
> - /* WaStripsFansDisableFastClipPerformanceFix:snb */
> - _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL |
> - /*
> - * Bspec says:
> - * "This bit must be set if 3DSTATE_CLIP clip mode is set
> - * to normal and 3DSTATE_SF number of SF output attributes
> - * is more than 16."
> - */
> - _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH);
> }
>
> static void
> @@ -2008,6 +1974,39 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> GFX_MODE,
> GFX_TLB_INVALIDATE_EXPLICIT);
>
> + /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
> + wa_masked_en(wal,
> + _3D_CHICKEN,
> + _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
> +
> + wa_masked_en(wal,
> + _3D_CHICKEN3,
> + /* WaStripsFansDisableFastClipPerformanceFix:snb */
> + _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL |
> + /*
> + * Bspec says:
> + * "This bit must be set if 3DSTATE_CLIP clip mode is set
> + * to normal and 3DSTATE_SF number of SF output attributes
> + * is more than 16."
> + */
> + _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH);
> +
> + /*
> + * BSpec recommends 8x4 when MSAA is used,
> + * however in practice 16x4 seems fastest.
> + *
> + * Note that PS/WM thread counts depend on the WIZ hashing
> + * disable bit, which we don't touch here, but it's good
> + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> + */
> + wa_add(wal,
> + GEN6_GT_MODE, 0,
> + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
> + GEN6_WIZ_HASHING_16x4);
> +
> + /* WaDisable_RenderCache_OperationalFlush:snb */
> + wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
> +
> /*
> * From the Sandybridge PRM, volume 1 part 3, page 24:
> * "If this bit is set, STCunit will have LRA as replacement
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Rearrange snb workarounds
2020-12-10 10:36 ` [Intel-gfx] [PATCH] " Mika Kuoppala
@ 2020-12-10 10:41 ` Chris Wilson
2020-12-10 13:19 ` Mika Kuoppala
0 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2020-12-10 10:41 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2020-12-10 10:36:07)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > Some rcs0 workarounds were being incorrectly applied to the GT, and so
> > we failed to restore the expected register settings after a reset.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 67 ++++++++++-----------
> > 1 file changed, 33 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index b5339a36d256..50cfe82f18a9 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -823,40 +823,6 @@ ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > static void
> > snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > {
> > - /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
> > - wa_masked_en(wal,
> > - _3D_CHICKEN,
> > - _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
> > -
> > - /* WaDisable_RenderCache_OperationalFlush:snb */
> > - wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
> > -
> > - /*
> > - * BSpec recommends 8x4 when MSAA is used,
> > - * however in practice 16x4 seems fastest.
> > - *
> > - * Note that PS/WM thread counts depend on the WIZ hashing
> > - * disable bit, which we don't touch here, but it's good
> > - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> > - */
> > - wa_add(wal,
> > - GEN6_GT_MODE, 0,
> > - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
> > - GEN6_WIZ_HASHING_16x4);
> > -
> > - wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB);
>
> Where did this go?
It was already in rcs_engine_wa
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Rearrange snb workarounds
2020-12-10 10:41 ` Chris Wilson
@ 2020-12-10 13:19 ` Mika Kuoppala
0 siblings, 0 replies; 6+ messages in thread
From: Mika Kuoppala @ 2020-12-10 13:19 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2020-12-10 10:36:07)
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>>
>> > Some rcs0 workarounds were being incorrectly applied to the GT, and so
>> > we failed to restore the expected register settings after a reset.
>> >
>> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> > ---
>> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 67 ++++++++++-----------
>> > 1 file changed, 33 insertions(+), 34 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > index b5339a36d256..50cfe82f18a9 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > @@ -823,40 +823,6 @@ ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> > static void
>> > snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> > {
>> > - /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
>> > - wa_masked_en(wal,
>> > - _3D_CHICKEN,
>> > - _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
>> > -
>> > - /* WaDisable_RenderCache_OperationalFlush:snb */
>> > - wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
>> > -
>> > - /*
>> > - * BSpec recommends 8x4 when MSAA is used,
>> > - * however in practice 16x4 seems fastest.
>> > - *
>> > - * Note that PS/WM thread counts depend on the WIZ hashing
>> > - * disable bit, which we don't touch here, but it's good
>> > - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
>> > - */
>> > - wa_add(wal,
>> > - GEN6_GT_MODE, 0,
>> > - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
>> > - GEN6_WIZ_HASHING_16x4);
>> > -
>> > - wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB);
>>
>> Where did this go?
>
> It was already in rcs_engine_wa
Yes it was.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> -Chris
_______________________________________________
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-12-10 13:21 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-09 13:42 [Intel-gfx] [PATCH] drm/i915/gt: Rearrange snb workarounds Chris Wilson
2020-12-09 15:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-12-09 16:16 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-12-10 10:36 ` [Intel-gfx] [PATCH] " Mika Kuoppala
2020-12-10 10:41 ` Chris Wilson
2020-12-10 13:19 ` Mika Kuoppala
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