* [Intel-gfx] [PATCH 02/21] drm/i915/gt: Wean workaround selftests off GEM context
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 17:04 ` Mika Kuoppala
2020-12-10 8:02 ` [Intel-gfx] [PATCH 03/21] drm/i915/gt: Replace direct submit with direct call to tasklet Chris Wilson
` (24 subsequent siblings)
25 siblings, 1 reply; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
The workarounds are tied to the GT and we should derive the tests local
to the GT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../gpu/drm/i915/gt/selftest_workarounds.c | 189 ++++++++----------
1 file changed, 88 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 61a0532d0f3d..703b77207a47 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -95,8 +95,9 @@ reference_lists_fini(struct intel_gt *gt, struct wa_lists *lists)
}
static struct drm_i915_gem_object *
-read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
+read_nonprivs(struct intel_context *ce)
{
+ struct intel_engine_cs *engine = ce->engine;
const u32 base = engine->mmio_base;
struct drm_i915_gem_object *result;
struct i915_request *rq;
@@ -130,7 +131,7 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
if (err)
goto err_obj;
- rq = igt_request_alloc(ctx, engine);
+ rq = intel_context_create_request(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto err_pin;
@@ -145,7 +146,7 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
goto err_req;
srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
- if (INTEL_GEN(ctx->i915) >= 8)
+ if (INTEL_GEN(engine->i915) >= 8)
srm++;
cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
@@ -200,16 +201,16 @@ print_results(const struct intel_engine_cs *engine, const u32 *results)
}
}
-static int check_whitelist(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
+static int check_whitelist(struct intel_context *ce)
{
+ struct intel_engine_cs *engine = ce->engine;
struct drm_i915_gem_object *results;
struct intel_wedge_me wedge;
u32 *vaddr;
int err;
int i;
- results = read_nonprivs(ctx, engine);
+ results = read_nonprivs(ce);
if (IS_ERR(results))
return PTR_ERR(results);
@@ -293,8 +294,7 @@ static int check_whitelist_across_reset(struct intel_engine_cs *engine,
int (*reset)(struct intel_engine_cs *),
const char *name)
{
- struct drm_i915_private *i915 = engine->i915;
- struct i915_gem_context *ctx, *tmp;
+ struct intel_context *ce, *tmp;
struct igt_spinner spin;
intel_wakeref_t wakeref;
int err;
@@ -302,15 +302,15 @@ static int check_whitelist_across_reset(struct intel_engine_cs *engine,
pr_info("Checking %d whitelisted registers on %s (RING_NONPRIV) [%s]\n",
engine->whitelist.count, engine->name, name);
- ctx = kernel_context(i915);
- if (IS_ERR(ctx))
- return PTR_ERR(ctx);
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
err = igt_spinner_init(&spin, engine->gt);
if (err)
goto out_ctx;
- err = check_whitelist(ctx, engine);
+ err = check_whitelist(ce);
if (err) {
pr_err("Invalid whitelist *before* %s reset!\n", name);
goto out_spin;
@@ -330,22 +330,22 @@ static int check_whitelist_across_reset(struct intel_engine_cs *engine,
goto out_spin;
}
- err = check_whitelist(ctx, engine);
+ err = check_whitelist(ce);
if (err) {
pr_err("Whitelist not preserved in context across %s reset!\n",
name);
goto out_spin;
}
- tmp = kernel_context(i915);
+ tmp = intel_context_create(engine);
if (IS_ERR(tmp)) {
err = PTR_ERR(tmp);
goto out_spin;
}
- kernel_context_close(ctx);
- ctx = tmp;
+ intel_context_put(ce);
+ ce = tmp;
- err = check_whitelist(ctx, engine);
+ err = check_whitelist(ce);
if (err) {
pr_err("Invalid whitelist *after* %s reset in fresh context!\n",
name);
@@ -355,7 +355,7 @@ static int check_whitelist_across_reset(struct intel_engine_cs *engine,
out_spin:
igt_spinner_fini(&spin);
out_ctx:
- kernel_context_close(ctx);
+ intel_context_put(ce);
return err;
}
@@ -786,15 +786,15 @@ static int live_reset_whitelist(void *arg)
return err;
}
-static int read_whitelisted_registers(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine,
+static int read_whitelisted_registers(struct intel_context *ce,
struct i915_vma *results)
{
+ struct intel_engine_cs *engine = ce->engine;
struct i915_request *rq;
int i, err = 0;
u32 srm, *cs;
- rq = igt_request_alloc(ctx, engine);
+ rq = intel_context_create_request(ce);
if (IS_ERR(rq))
return PTR_ERR(rq);
@@ -807,7 +807,7 @@ static int read_whitelisted_registers(struct i915_gem_context *ctx,
goto err_req;
srm = MI_STORE_REGISTER_MEM;
- if (INTEL_GEN(ctx->i915) >= 8)
+ if (INTEL_GEN(engine->i915) >= 8)
srm++;
cs = intel_ring_begin(rq, 4 * engine->whitelist.count);
@@ -834,18 +834,15 @@ static int read_whitelisted_registers(struct i915_gem_context *ctx,
return request_add_sync(rq, err);
}
-static int scrub_whitelisted_registers(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
+static int scrub_whitelisted_registers(struct intel_context *ce)
{
- struct i915_address_space *vm;
+ struct intel_engine_cs *engine = ce->engine;
struct i915_request *rq;
struct i915_vma *batch;
int i, err = 0;
u32 *cs;
- vm = i915_gem_context_get_vm_rcu(ctx);
- batch = create_batch(vm);
- i915_vm_put(vm);
+ batch = create_batch(ce->vm);
if (IS_ERR(batch))
return PTR_ERR(batch);
@@ -873,7 +870,7 @@ static int scrub_whitelisted_registers(struct i915_gem_context *ctx,
i915_gem_object_flush_map(batch->obj);
intel_gt_chipset_flush(engine->gt);
- rq = igt_request_alloc(ctx, engine);
+ rq = intel_context_create_request(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto err_unpin;
@@ -1016,7 +1013,6 @@ static int live_isolated_whitelist(void *arg)
{
struct intel_gt *gt = arg;
struct {
- struct i915_gem_context *ctx;
struct i915_vma *scratch[2];
} client[2] = {};
struct intel_engine_cs *engine;
@@ -1032,61 +1028,55 @@ static int live_isolated_whitelist(void *arg)
return 0;
for (i = 0; i < ARRAY_SIZE(client); i++) {
- struct i915_address_space *vm;
- struct i915_gem_context *c;
-
- c = kernel_context(gt->i915);
- if (IS_ERR(c)) {
- err = PTR_ERR(c);
- goto err;
- }
-
- vm = i915_gem_context_get_vm_rcu(c);
-
- client[i].scratch[0] = create_scratch(vm, 1024);
+ client[i].scratch[0] = create_scratch(gt->vm, 1024);
if (IS_ERR(client[i].scratch[0])) {
err = PTR_ERR(client[i].scratch[0]);
- i915_vm_put(vm);
- kernel_context_close(c);
goto err;
}
- client[i].scratch[1] = create_scratch(vm, 1024);
+ client[i].scratch[1] = create_scratch(gt->vm, 1024);
if (IS_ERR(client[i].scratch[1])) {
err = PTR_ERR(client[i].scratch[1]);
i915_vma_unpin_and_release(&client[i].scratch[0], 0);
- i915_vm_put(vm);
- kernel_context_close(c);
goto err;
}
-
- client[i].ctx = c;
- i915_vm_put(vm);
}
for_each_engine(engine, gt, id) {
+ struct intel_context *ce[2];
+
if (!engine->kernel_context->vm)
continue;
if (!whitelist_writable_count(engine))
continue;
+ ce[0] = intel_context_create(engine);
+ if (IS_ERR(ce[0])) {
+ err = PTR_ERR(ce[0]);
+ break;
+ }
+ ce[1] = intel_context_create(engine);
+ if (IS_ERR(ce[1])) {
+ err = PTR_ERR(ce[1]);
+ intel_context_put(ce[0]);
+ break;
+ }
+
/* Read default values */
- err = read_whitelisted_registers(client[0].ctx, engine,
- client[0].scratch[0]);
+ err = read_whitelisted_registers(ce[0], client[0].scratch[0]);
if (err)
- goto err;
+ goto err_ce;
/* Try to overwrite registers (should only affect ctx0) */
- err = scrub_whitelisted_registers(client[0].ctx, engine);
+ err = scrub_whitelisted_registers(ce[0]);
if (err)
- goto err;
+ goto err_ce;
/* Read values from ctx1, we expect these to be defaults */
- err = read_whitelisted_registers(client[1].ctx, engine,
- client[1].scratch[0]);
+ err = read_whitelisted_registers(ce[1], client[1].scratch[0]);
if (err)
- goto err;
+ goto err_ce;
/* Verify that both reads return the same default values */
err = check_whitelisted_registers(engine,
@@ -1094,31 +1084,29 @@ static int live_isolated_whitelist(void *arg)
client[1].scratch[0],
result_eq);
if (err)
- goto err;
+ goto err_ce;
/* Read back the updated values in ctx0 */
- err = read_whitelisted_registers(client[0].ctx, engine,
- client[0].scratch[1]);
+ err = read_whitelisted_registers(ce[0], client[0].scratch[1]);
if (err)
- goto err;
+ goto err_ce;
/* User should be granted privilege to overwhite regs */
err = check_whitelisted_registers(engine,
client[0].scratch[0],
client[0].scratch[1],
result_neq);
+err_ce:
+ intel_context_put(ce[1]);
+ intel_context_put(ce[0]);
if (err)
- goto err;
+ break;
}
err:
for (i = 0; i < ARRAY_SIZE(client); i++) {
- if (!client[i].ctx)
- break;
-
i915_vma_unpin_and_release(&client[i].scratch[1], 0);
i915_vma_unpin_and_release(&client[i].scratch[0], 0);
- kernel_context_close(client[i].ctx);
}
if (igt_flush_test(gt->i915))
@@ -1128,18 +1116,21 @@ static int live_isolated_whitelist(void *arg)
}
static bool
-verify_wa_lists(struct i915_gem_context *ctx, struct wa_lists *lists,
+verify_wa_lists(struct intel_gt *gt, struct wa_lists *lists,
const char *str)
{
- struct drm_i915_private *i915 = ctx->i915;
- struct i915_gem_engines_iter it;
- struct intel_context *ce;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
bool ok = true;
- ok &= wa_list_verify(&i915->uncore, &lists->gt_wa_list, str);
+ ok &= wa_list_verify(gt->uncore, &lists->gt_wa_list, str);
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce;
- for_each_gem_engine(ce, i915_gem_context_engines(ctx), it) {
- enum intel_engine_id id = ce->engine->id;
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return false;
ok &= engine_wa_list_verify(ce,
&lists->engine[id].wa_list,
@@ -1148,6 +1139,8 @@ verify_wa_lists(struct i915_gem_context *ctx, struct wa_lists *lists,
ok &= engine_wa_list_verify(ce,
&lists->engine[id].ctx_wa_list,
str) == 0;
+
+ intel_context_put(ce);
}
return ok;
@@ -1157,7 +1150,6 @@ static int
live_gpu_reset_workarounds(void *arg)
{
struct intel_gt *gt = arg;
- struct i915_gem_context *ctx;
intel_wakeref_t wakeref;
struct wa_lists lists;
bool ok;
@@ -1165,12 +1157,6 @@ live_gpu_reset_workarounds(void *arg)
if (!intel_has_gpu_reset(gt))
return 0;
- ctx = kernel_context(gt->i915);
- if (IS_ERR(ctx))
- return PTR_ERR(ctx);
-
- i915_gem_context_lock_engines(ctx);
-
pr_info("Verifying after GPU reset...\n");
igt_global_reset_lock(gt);
@@ -1178,17 +1164,15 @@ live_gpu_reset_workarounds(void *arg)
reference_lists_init(gt, &lists);
- ok = verify_wa_lists(ctx, &lists, "before reset");
+ ok = verify_wa_lists(gt, &lists, "before reset");
if (!ok)
goto out;
intel_gt_reset(gt, ALL_ENGINES, "live_workarounds");
- ok = verify_wa_lists(ctx, &lists, "after reset");
+ ok = verify_wa_lists(gt, &lists, "after reset");
out:
- i915_gem_context_unlock_engines(ctx);
- kernel_context_close(ctx);
reference_lists_fini(gt, &lists);
intel_runtime_pm_put(gt->uncore->rpm, wakeref);
igt_global_reset_unlock(gt);
@@ -1200,8 +1184,8 @@ static int
live_engine_reset_workarounds(void *arg)
{
struct intel_gt *gt = arg;
- struct i915_gem_engines_iter it;
- struct i915_gem_context *ctx;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
struct intel_context *ce;
struct igt_spinner spin;
struct i915_request *rq;
@@ -1212,30 +1196,30 @@ live_engine_reset_workarounds(void *arg)
if (!intel_has_reset_engine(gt))
return 0;
- ctx = kernel_context(gt->i915);
- if (IS_ERR(ctx))
- return PTR_ERR(ctx);
-
igt_global_reset_lock(gt);
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
reference_lists_init(gt, &lists);
- for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
- struct intel_engine_cs *engine = ce->engine;
+ for_each_engine(engine, gt, id) {
bool ok;
pr_info("Verifying after %s reset...\n", engine->name);
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce)) {
+ ret = PTR_ERR(ce);
+ break;
+ }
- ok = verify_wa_lists(ctx, &lists, "before reset");
+ ok = verify_wa_lists(gt, &lists, "before reset");
if (!ok) {
ret = -ESRCH;
goto err;
}
- intel_engine_reset(engine, "live_workarounds");
+ intel_engine_reset(engine, "live_workarounds:idle");
- ok = verify_wa_lists(ctx, &lists, "after idle reset");
+ ok = verify_wa_lists(gt, &lists, "after idle reset");
if (!ok) {
ret = -ESRCH;
goto err;
@@ -1259,23 +1243,26 @@ live_engine_reset_workarounds(void *arg)
goto err;
}
- intel_engine_reset(engine, "live_workarounds");
+ intel_engine_reset(engine, "live_workarounds:active");
igt_spinner_end(&spin);
igt_spinner_fini(&spin);
- ok = verify_wa_lists(ctx, &lists, "after busy reset");
+ ok = verify_wa_lists(gt, &lists, "after busy reset");
if (!ok) {
ret = -ESRCH;
goto err;
}
- }
+
err:
- i915_gem_context_unlock_engines(ctx);
+ intel_context_put(ce);
+ if (ret)
+ break;
+ }
+
reference_lists_fini(gt, &lists);
intel_runtime_pm_put(gt->uncore->rpm, wakeref);
igt_global_reset_unlock(gt);
- kernel_context_close(ctx);
igt_flush_test(gt->i915);
--
2.20.1
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^ permalink raw reply related [flat|nested] 38+ messages in thread* Re: [Intel-gfx] [PATCH 02/21] drm/i915/gt: Wean workaround selftests off GEM context
2020-12-10 8:02 ` [Intel-gfx] [PATCH 02/21] drm/i915/gt: Wean workaround selftests off GEM context Chris Wilson
@ 2020-12-10 17:04 ` Mika Kuoppala
0 siblings, 0 replies; 38+ messages in thread
From: Mika Kuoppala @ 2020-12-10 17:04 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> The workarounds are tied to the GT and we should derive the tests local
> to the GT.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> .../gpu/drm/i915/gt/selftest_workarounds.c | 189 ++++++++----------
> 1 file changed, 88 insertions(+), 101 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> index 61a0532d0f3d..703b77207a47 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> @@ -95,8 +95,9 @@ reference_lists_fini(struct intel_gt *gt, struct wa_lists *lists)
> }
>
> static struct drm_i915_gem_object *
> -read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
> +read_nonprivs(struct intel_context *ce)
> {
> + struct intel_engine_cs *engine = ce->engine;
> const u32 base = engine->mmio_base;
> struct drm_i915_gem_object *result;
> struct i915_request *rq;
> @@ -130,7 +131,7 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
> if (err)
> goto err_obj;
>
> - rq = igt_request_alloc(ctx, engine);
> + rq = intel_context_create_request(ce);
> if (IS_ERR(rq)) {
> err = PTR_ERR(rq);
> goto err_pin;
> @@ -145,7 +146,7 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
> goto err_req;
>
> srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
> - if (INTEL_GEN(ctx->i915) >= 8)
> + if (INTEL_GEN(engine->i915) >= 8)
> srm++;
>
> cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
> @@ -200,16 +201,16 @@ print_results(const struct intel_engine_cs *engine, const u32 *results)
> }
> }
>
> -static int check_whitelist(struct i915_gem_context *ctx,
> - struct intel_engine_cs *engine)
> +static int check_whitelist(struct intel_context *ce)
> {
> + struct intel_engine_cs *engine = ce->engine;
> struct drm_i915_gem_object *results;
> struct intel_wedge_me wedge;
> u32 *vaddr;
> int err;
> int i;
>
> - results = read_nonprivs(ctx, engine);
> + results = read_nonprivs(ce);
> if (IS_ERR(results))
> return PTR_ERR(results);
>
> @@ -293,8 +294,7 @@ static int check_whitelist_across_reset(struct intel_engine_cs *engine,
> int (*reset)(struct intel_engine_cs *),
> const char *name)
> {
> - struct drm_i915_private *i915 = engine->i915;
> - struct i915_gem_context *ctx, *tmp;
> + struct intel_context *ce, *tmp;
> struct igt_spinner spin;
> intel_wakeref_t wakeref;
> int err;
> @@ -302,15 +302,15 @@ static int check_whitelist_across_reset(struct intel_engine_cs *engine,
> pr_info("Checking %d whitelisted registers on %s (RING_NONPRIV) [%s]\n",
> engine->whitelist.count, engine->name, name);
>
> - ctx = kernel_context(i915);
> - if (IS_ERR(ctx))
> - return PTR_ERR(ctx);
> + ce = intel_context_create(engine);
> + if (IS_ERR(ce))
> + return PTR_ERR(ce);
>
> err = igt_spinner_init(&spin, engine->gt);
> if (err)
> goto out_ctx;
>
> - err = check_whitelist(ctx, engine);
> + err = check_whitelist(ce);
> if (err) {
> pr_err("Invalid whitelist *before* %s reset!\n", name);
> goto out_spin;
> @@ -330,22 +330,22 @@ static int check_whitelist_across_reset(struct intel_engine_cs *engine,
> goto out_spin;
> }
>
> - err = check_whitelist(ctx, engine);
> + err = check_whitelist(ce);
> if (err) {
> pr_err("Whitelist not preserved in context across %s reset!\n",
> name);
> goto out_spin;
> }
>
> - tmp = kernel_context(i915);
> + tmp = intel_context_create(engine);
> if (IS_ERR(tmp)) {
> err = PTR_ERR(tmp);
> goto out_spin;
> }
> - kernel_context_close(ctx);
> - ctx = tmp;
> + intel_context_put(ce);
> + ce = tmp;
>
> - err = check_whitelist(ctx, engine);
> + err = check_whitelist(ce);
> if (err) {
> pr_err("Invalid whitelist *after* %s reset in fresh context!\n",
> name);
> @@ -355,7 +355,7 @@ static int check_whitelist_across_reset(struct intel_engine_cs *engine,
> out_spin:
> igt_spinner_fini(&spin);
> out_ctx:
> - kernel_context_close(ctx);
> + intel_context_put(ce);
> return err;
> }
>
> @@ -786,15 +786,15 @@ static int live_reset_whitelist(void *arg)
> return err;
> }
>
> -static int read_whitelisted_registers(struct i915_gem_context *ctx,
> - struct intel_engine_cs *engine,
> +static int read_whitelisted_registers(struct intel_context *ce,
> struct i915_vma *results)
> {
> + struct intel_engine_cs *engine = ce->engine;
> struct i915_request *rq;
> int i, err = 0;
> u32 srm, *cs;
>
> - rq = igt_request_alloc(ctx, engine);
> + rq = intel_context_create_request(ce);
> if (IS_ERR(rq))
> return PTR_ERR(rq);
>
> @@ -807,7 +807,7 @@ static int read_whitelisted_registers(struct i915_gem_context *ctx,
> goto err_req;
>
> srm = MI_STORE_REGISTER_MEM;
> - if (INTEL_GEN(ctx->i915) >= 8)
> + if (INTEL_GEN(engine->i915) >= 8)
> srm++;
>
> cs = intel_ring_begin(rq, 4 * engine->whitelist.count);
> @@ -834,18 +834,15 @@ static int read_whitelisted_registers(struct i915_gem_context *ctx,
> return request_add_sync(rq, err);
> }
>
> -static int scrub_whitelisted_registers(struct i915_gem_context *ctx,
> - struct intel_engine_cs *engine)
> +static int scrub_whitelisted_registers(struct intel_context *ce)
> {
> - struct i915_address_space *vm;
> + struct intel_engine_cs *engine = ce->engine;
> struct i915_request *rq;
> struct i915_vma *batch;
> int i, err = 0;
> u32 *cs;
>
> - vm = i915_gem_context_get_vm_rcu(ctx);
> - batch = create_batch(vm);
> - i915_vm_put(vm);
> + batch = create_batch(ce->vm);
> if (IS_ERR(batch))
> return PTR_ERR(batch);
>
> @@ -873,7 +870,7 @@ static int scrub_whitelisted_registers(struct i915_gem_context *ctx,
> i915_gem_object_flush_map(batch->obj);
> intel_gt_chipset_flush(engine->gt);
>
> - rq = igt_request_alloc(ctx, engine);
> + rq = intel_context_create_request(ce);
> if (IS_ERR(rq)) {
> err = PTR_ERR(rq);
> goto err_unpin;
> @@ -1016,7 +1013,6 @@ static int live_isolated_whitelist(void *arg)
> {
> struct intel_gt *gt = arg;
> struct {
> - struct i915_gem_context *ctx;
> struct i915_vma *scratch[2];
> } client[2] = {};
> struct intel_engine_cs *engine;
> @@ -1032,61 +1028,55 @@ static int live_isolated_whitelist(void *arg)
> return 0;
>
> for (i = 0; i < ARRAY_SIZE(client); i++) {
> - struct i915_address_space *vm;
> - struct i915_gem_context *c;
> -
> - c = kernel_context(gt->i915);
> - if (IS_ERR(c)) {
> - err = PTR_ERR(c);
> - goto err;
> - }
> -
> - vm = i915_gem_context_get_vm_rcu(c);
> -
> - client[i].scratch[0] = create_scratch(vm, 1024);
> + client[i].scratch[0] = create_scratch(gt->vm, 1024);
> if (IS_ERR(client[i].scratch[0])) {
> err = PTR_ERR(client[i].scratch[0]);
> - i915_vm_put(vm);
> - kernel_context_close(c);
> goto err;
> }
>
> - client[i].scratch[1] = create_scratch(vm, 1024);
> + client[i].scratch[1] = create_scratch(gt->vm, 1024);
> if (IS_ERR(client[i].scratch[1])) {
> err = PTR_ERR(client[i].scratch[1]);
> i915_vma_unpin_and_release(&client[i].scratch[0], 0);
> - i915_vm_put(vm);
> - kernel_context_close(c);
> goto err;
> }
> -
> - client[i].ctx = c;
> - i915_vm_put(vm);
> }
>
> for_each_engine(engine, gt, id) {
> + struct intel_context *ce[2];
> +
> if (!engine->kernel_context->vm)
> continue;
>
> if (!whitelist_writable_count(engine))
> continue;
>
> + ce[0] = intel_context_create(engine);
> + if (IS_ERR(ce[0])) {
> + err = PTR_ERR(ce[0]);
> + break;
> + }
> + ce[1] = intel_context_create(engine);
> + if (IS_ERR(ce[1])) {
> + err = PTR_ERR(ce[1]);
> + intel_context_put(ce[0]);
> + break;
> + }
> +
> /* Read default values */
> - err = read_whitelisted_registers(client[0].ctx, engine,
> - client[0].scratch[0]);
> + err = read_whitelisted_registers(ce[0], client[0].scratch[0]);
> if (err)
> - goto err;
> + goto err_ce;
>
> /* Try to overwrite registers (should only affect ctx0) */
> - err = scrub_whitelisted_registers(client[0].ctx, engine);
> + err = scrub_whitelisted_registers(ce[0]);
> if (err)
> - goto err;
> + goto err_ce;
>
> /* Read values from ctx1, we expect these to be defaults */
> - err = read_whitelisted_registers(client[1].ctx, engine,
> - client[1].scratch[0]);
> + err = read_whitelisted_registers(ce[1], client[1].scratch[0]);
> if (err)
> - goto err;
> + goto err_ce;
>
> /* Verify that both reads return the same default values */
> err = check_whitelisted_registers(engine,
> @@ -1094,31 +1084,29 @@ static int live_isolated_whitelist(void *arg)
> client[1].scratch[0],
> result_eq);
> if (err)
> - goto err;
> + goto err_ce;
>
> /* Read back the updated values in ctx0 */
> - err = read_whitelisted_registers(client[0].ctx, engine,
> - client[0].scratch[1]);
> + err = read_whitelisted_registers(ce[0], client[0].scratch[1]);
> if (err)
> - goto err;
> + goto err_ce;
>
> /* User should be granted privilege to overwhite regs */
> err = check_whitelisted_registers(engine,
> client[0].scratch[0],
> client[0].scratch[1],
> result_neq);
> +err_ce:
> + intel_context_put(ce[1]);
> + intel_context_put(ce[0]);
> if (err)
> - goto err;
> + break;
> }
>
> err:
> for (i = 0; i < ARRAY_SIZE(client); i++) {
> - if (!client[i].ctx)
> - break;
> -
> i915_vma_unpin_and_release(&client[i].scratch[1], 0);
> i915_vma_unpin_and_release(&client[i].scratch[0], 0);
> - kernel_context_close(client[i].ctx);
> }
>
> if (igt_flush_test(gt->i915))
> @@ -1128,18 +1116,21 @@ static int live_isolated_whitelist(void *arg)
> }
>
> static bool
> -verify_wa_lists(struct i915_gem_context *ctx, struct wa_lists *lists,
> +verify_wa_lists(struct intel_gt *gt, struct wa_lists *lists,
> const char *str)
> {
> - struct drm_i915_private *i915 = ctx->i915;
> - struct i915_gem_engines_iter it;
> - struct intel_context *ce;
> + struct intel_engine_cs *engine;
> + enum intel_engine_id id;
> bool ok = true;
>
> - ok &= wa_list_verify(&i915->uncore, &lists->gt_wa_list, str);
> + ok &= wa_list_verify(gt->uncore, &lists->gt_wa_list, str);
> +
> + for_each_engine(engine, gt, id) {
> + struct intel_context *ce;
>
> - for_each_gem_engine(ce, i915_gem_context_engines(ctx), it) {
> - enum intel_engine_id id = ce->engine->id;
> + ce = intel_context_create(engine);
> + if (IS_ERR(ce))
> + return false;
>
> ok &= engine_wa_list_verify(ce,
> &lists->engine[id].wa_list,
> @@ -1148,6 +1139,8 @@ verify_wa_lists(struct i915_gem_context *ctx, struct wa_lists *lists,
> ok &= engine_wa_list_verify(ce,
> &lists->engine[id].ctx_wa_list,
> str) == 0;
> +
> + intel_context_put(ce);
> }
>
> return ok;
> @@ -1157,7 +1150,6 @@ static int
> live_gpu_reset_workarounds(void *arg)
> {
> struct intel_gt *gt = arg;
> - struct i915_gem_context *ctx;
> intel_wakeref_t wakeref;
> struct wa_lists lists;
> bool ok;
> @@ -1165,12 +1157,6 @@ live_gpu_reset_workarounds(void *arg)
> if (!intel_has_gpu_reset(gt))
> return 0;
>
> - ctx = kernel_context(gt->i915);
> - if (IS_ERR(ctx))
> - return PTR_ERR(ctx);
> -
> - i915_gem_context_lock_engines(ctx);
> -
> pr_info("Verifying after GPU reset...\n");
>
> igt_global_reset_lock(gt);
> @@ -1178,17 +1164,15 @@ live_gpu_reset_workarounds(void *arg)
>
> reference_lists_init(gt, &lists);
>
> - ok = verify_wa_lists(ctx, &lists, "before reset");
> + ok = verify_wa_lists(gt, &lists, "before reset");
> if (!ok)
> goto out;
>
> intel_gt_reset(gt, ALL_ENGINES, "live_workarounds");
>
> - ok = verify_wa_lists(ctx, &lists, "after reset");
> + ok = verify_wa_lists(gt, &lists, "after reset");
>
> out:
> - i915_gem_context_unlock_engines(ctx);
> - kernel_context_close(ctx);
> reference_lists_fini(gt, &lists);
> intel_runtime_pm_put(gt->uncore->rpm, wakeref);
> igt_global_reset_unlock(gt);
> @@ -1200,8 +1184,8 @@ static int
> live_engine_reset_workarounds(void *arg)
> {
> struct intel_gt *gt = arg;
> - struct i915_gem_engines_iter it;
> - struct i915_gem_context *ctx;
> + struct intel_engine_cs *engine;
> + enum intel_engine_id id;
> struct intel_context *ce;
> struct igt_spinner spin;
> struct i915_request *rq;
> @@ -1212,30 +1196,30 @@ live_engine_reset_workarounds(void *arg)
> if (!intel_has_reset_engine(gt))
> return 0;
>
> - ctx = kernel_context(gt->i915);
> - if (IS_ERR(ctx))
> - return PTR_ERR(ctx);
> -
> igt_global_reset_lock(gt);
> wakeref = intel_runtime_pm_get(gt->uncore->rpm);
>
> reference_lists_init(gt, &lists);
>
> - for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> - struct intel_engine_cs *engine = ce->engine;
> + for_each_engine(engine, gt, id) {
> bool ok;
>
> pr_info("Verifying after %s reset...\n", engine->name);
> + ce = intel_context_create(engine);
> + if (IS_ERR(ce)) {
> + ret = PTR_ERR(ce);
> + break;
> + }
>
> - ok = verify_wa_lists(ctx, &lists, "before reset");
> + ok = verify_wa_lists(gt, &lists, "before reset");
> if (!ok) {
> ret = -ESRCH;
> goto err;
> }
>
> - intel_engine_reset(engine, "live_workarounds");
> + intel_engine_reset(engine, "live_workarounds:idle");
>
> - ok = verify_wa_lists(ctx, &lists, "after idle reset");
> + ok = verify_wa_lists(gt, &lists, "after idle reset");
> if (!ok) {
> ret = -ESRCH;
> goto err;
> @@ -1259,23 +1243,26 @@ live_engine_reset_workarounds(void *arg)
> goto err;
> }
>
> - intel_engine_reset(engine, "live_workarounds");
> + intel_engine_reset(engine, "live_workarounds:active");
>
> igt_spinner_end(&spin);
> igt_spinner_fini(&spin);
>
> - ok = verify_wa_lists(ctx, &lists, "after busy reset");
> + ok = verify_wa_lists(gt, &lists, "after busy reset");
> if (!ok) {
> ret = -ESRCH;
> goto err;
> }
> - }
> +
> err:
> - i915_gem_context_unlock_engines(ctx);
> + intel_context_put(ce);
> + if (ret)
> + break;
> + }
> +
> reference_lists_fini(gt, &lists);
> intel_runtime_pm_put(gt->uncore->rpm, wakeref);
> igt_global_reset_unlock(gt);
> - kernel_context_close(ctx);
>
> igt_flush_test(gt->i915);
>
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 03/21] drm/i915/gt: Replace direct submit with direct call to tasklet
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 02/21] drm/i915/gt: Wean workaround selftests off GEM context Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 04/21] drm/i915/gt: Use virtual_engine during execlists_dequeue Chris Wilson
` (23 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Rather than having special case code for opportunistically calling
process_csb() and performing a direct submit while holding the engine
spinlock for submitting the request, simply call the tasklet directly.
This allows us to retain the direct submission path, including the CS
draining to allow fast/immediate submissions, without requiring any
duplicated code paths, and most importantly greatly simplifying the
control flow by removing reentrancy. This will enable us to close a few
races in the virtual engines in the next few patches.
The trickiest part here is to ensure that paired operations (such as
schedule_in/schedule_out) remain under consistent locking domains,
e.g. when pulled outside of the engine->active.lock
v2: Use bh kicking, see commit 3c53776e29f8 ("Mark HI and TASKLET
softirq synchronous").
v3: Update engine-reset to be tasklet aware
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 +++--
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +-
.../drm/i915/gt/intel_execlists_submission.c | 140 +++++++-----------
drivers/gpu/drm/i915/gt/intel_reset.c | 60 +++++---
drivers/gpu/drm/i915/gt/intel_reset.h | 2 +
drivers/gpu/drm/i915/gt/selftest_context.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 27 ++--
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 7 +-
drivers/gpu/drm/i915/gt/selftest_reset.c | 8 +-
drivers/gpu/drm/i915/i915_request.c | 12 +-
drivers/gpu/drm/i915/i915_request.h | 1 +
drivers/gpu/drm/i915/i915_scheduler.c | 4 -
drivers/gpu/drm/i915/selftests/i915_request.c | 6 +-
drivers/gpu/drm/i915/selftests/igt_spinner.c | 3 +
15 files changed, 162 insertions(+), 150 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 97ceaf7116e8..71bd052628f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1003,32 +1003,39 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine)
return READ_ONCE(engine->props.stop_timeout_ms);
}
-int intel_engine_stop_cs(struct intel_engine_cs *engine)
+static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
+ int fast_timeout_us,
+ int slow_timeout_ms)
{
struct intel_uncore *uncore = engine->uncore;
- const u32 base = engine->mmio_base;
- const i915_reg_t mode = RING_MI_MODE(base);
+ const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
int err;
+ intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
+ err = __intel_wait_for_register_fw(engine->uncore, mode,
+ MODE_IDLE, MODE_IDLE,
+ fast_timeout_us,
+ slow_timeout_ms,
+ NULL);
+
+ /* A final mmio read to let GPU writes be hopefully flushed to memory */
+ intel_uncore_posting_read_fw(uncore, mode);
+ return err;
+}
+
+int intel_engine_stop_cs(struct intel_engine_cs *engine)
+{
+ int err = 0;
+
if (INTEL_GEN(engine->i915) < 3)
return -ENODEV;
ENGINE_TRACE(engine, "\n");
-
- intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
-
- err = 0;
- if (__intel_wait_for_register_fw(uncore,
- mode, MODE_IDLE, MODE_IDLE,
- 1000, stop_timeout(engine),
- NULL)) {
+ if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n");
err = -ETIMEDOUT;
}
- /* A final mmio read to let GPU writes be hopefully flushed to memory */
- intel_uncore_posting_read_fw(uncore, mode);
-
return err;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 499b09cb4acf..99574378047f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -136,7 +136,7 @@ __queue_and_release_pm(struct i915_request *rq,
list_add_tail(&tl->link, &timelines->active_list);
/* Hand the request over to HW and so engine_retire() */
- __i915_request_queue(rq, NULL);
+ __i915_request_queue_bh(rq);
/* Let new submissions commence (and maybe retire this timeline) */
__intel_wakeref_defer_park(&engine->wakeref);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index ee6312601c56..e71eef157231 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -183,7 +183,8 @@ struct intel_engine_execlists {
* Reserve the upper 16b for tracking internal errors.
*/
u32 error_interrupt;
-#define ERROR_CSB BIT(31)
+#define ERROR_CSB BIT(31)
+#define ERROR_PREEMPT BIT(30)
/**
* @reset_ccid: Active CCID [EXECLISTS_STATUS_HI] at the time of reset
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index dcecc2887891..157a8f18d41e 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1349,8 +1349,7 @@ __execlists_schedule_in(struct i915_request *rq)
return engine;
}
-static inline struct i915_request *
-execlists_schedule_in(struct i915_request *rq, int idx)
+static inline void execlists_schedule_in(struct i915_request *rq, int idx)
{
struct intel_context * const ce = rq->context;
struct intel_engine_cs *old;
@@ -1367,7 +1366,6 @@ execlists_schedule_in(struct i915_request *rq, int idx)
} while (!try_cmpxchg(&ce->inflight, &old, ptr_inc(old)));
GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
- return i915_request_get(rq);
}
static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
@@ -2042,8 +2040,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
struct intel_engine_execlists * const execlists = &engine->execlists;
struct i915_request **port = execlists->pending;
struct i915_request ** const last_port = port + execlists->port_mask;
- struct i915_request * const *active;
- struct i915_request *last;
+ struct i915_request *last = *execlists->active;
struct rb_node *rb;
bool submit = false;
@@ -2069,6 +2066,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* and context switches) submission.
*/
+ spin_lock(&engine->active.lock);
+
for (rb = rb_first_cached(&execlists->virtual); rb; ) {
struct virtual_engine *ve =
rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
@@ -2096,10 +2095,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* the active context to interject the preemption request,
* i.e. we will retrigger preemption following the ack in case
* of trouble.
- */
- active = READ_ONCE(execlists->active);
-
- /*
+ *
* In theory we can skip over completed contexts that have not
* yet been processed by events (as those events are in flight):
*
@@ -2111,7 +2107,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* completed and barf.
*/
- if ((last = *active)) {
+ if (last) {
if (i915_request_completed(last)) {
goto check_secondary;
} else if (need_preempt(engine, last, rb)) {
@@ -2184,6 +2180,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* Even if ELSP[1] is occupied and not worthy
* of timeslices, our queue might be.
*/
+ spin_unlock(&engine->active.lock);
start_timeslice(engine, queue_prio(execlists));
return;
}
@@ -2219,6 +2216,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
if (last && !can_merge_rq(last, rq)) {
spin_unlock(&ve->base.active.lock);
+ spin_unlock(&engine->active.lock);
start_timeslice(engine, rq_prio(rq));
return; /* leave this for another sibling */
}
@@ -2336,8 +2334,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
if (__i915_request_submit(rq)) {
if (!merge) {
- *port = execlists_schedule_in(last, port - execlists->pending);
- port++;
+ *port++ = i915_request_get(last);
last = NULL;
}
@@ -2356,8 +2353,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
rb_erase_cached(&p->node, &execlists->queue);
i915_priolist_free(p);
}
-
done:
+ *port++ = i915_request_get(last);
+
/*
* Here be a bit of magic! Or sleight-of-hand, whichever you prefer.
*
@@ -2375,36 +2373,45 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* interrupt for secondary ports).
*/
execlists->queue_priority_hint = queue_prio(execlists);
+ spin_unlock(&engine->active.lock);
if (submit) {
- *port = execlists_schedule_in(last, port - execlists->pending);
- execlists->switch_priority_hint =
- switch_prio(engine, *execlists->pending);
-
/*
* Skip if we ended up with exactly the same set of requests,
* e.g. trying to timeslice a pair of ordered contexts
*/
- if (!memcmp(active, execlists->pending,
- (port - execlists->pending + 1) * sizeof(*port))) {
- do
- execlists_schedule_out(fetch_and_zero(port));
- while (port-- != execlists->pending);
-
+ if (!memcmp(execlists->active,
+ execlists->pending,
+ (port - execlists->pending) * sizeof(*port)))
goto skip_submit;
- }
- clear_ports(port + 1, last_port - port);
+
+ *port = NULL;
+ while (port-- != execlists->pending)
+ execlists_schedule_in(*port, port - execlists->pending);
+
+ execlists->switch_priority_hint =
+ switch_prio(engine, *execlists->pending);
WRITE_ONCE(execlists->yield, -1);
- set_preempt_timeout(engine, *active);
+ set_preempt_timeout(engine, *execlists->active);
execlists_submit_ports(engine);
} else {
start_timeslice(engine, execlists->queue_priority_hint);
skip_submit:
ring_set_paused(engine, 0);
+ while (port-- != execlists->pending)
+ i915_request_put(*port);
+ *execlists->pending = NULL;
}
}
+static void execlists_dequeue_irq(struct intel_engine_cs *engine)
+{
+ local_irq_disable(); /* Suspend interrupts across request submission */
+ execlists_dequeue(engine);
+ local_irq_enable(); /* flush irq_work (e.g. breadcrumb enabling) */
+}
+
static void
cancel_port_requests(struct intel_engine_execlists * const execlists)
{
@@ -2747,16 +2754,6 @@ static void process_csb(struct intel_engine_cs *engine)
invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
}
-static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
-{
- lockdep_assert_held(&engine->active.lock);
- if (!READ_ONCE(engine->execlists.pending[0])) {
- rcu_read_lock(); /* protect peeking at execlists->active */
- execlists_dequeue(engine);
- rcu_read_unlock();
- }
-}
-
static void __execlists_hold(struct i915_request *rq)
{
LIST_HEAD(list);
@@ -3148,7 +3145,7 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine)
if (!timer_expired(t))
return false;
- return READ_ONCE(engine->execlists.pending[0]);
+ return engine->execlists.pending[0];
}
/*
@@ -3158,10 +3155,14 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine)
static void execlists_submission_tasklet(unsigned long data)
{
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
- bool timeout = preempt_timeout(engine);
process_csb(engine);
+ if (unlikely(preempt_timeout(engine))) {
+ cancel_timer(&engine->execlists.preempt);
+ engine->execlists.error_interrupt |= ERROR_PREEMPT;
+ }
+
if (unlikely(READ_ONCE(engine->execlists.error_interrupt))) {
const char *msg;
@@ -3170,6 +3171,8 @@ static void execlists_submission_tasklet(unsigned long data)
msg = "CS error"; /* thrown by a user payload */
else if (engine->execlists.error_interrupt & ERROR_CSB)
msg = "invalid CSB event";
+ else if (engine->execlists.error_interrupt & ERROR_PREEMPT)
+ msg = "preemption time out";
else
msg = "internal error";
@@ -3177,19 +3180,8 @@ static void execlists_submission_tasklet(unsigned long data)
execlists_reset(engine, msg);
}
- if (!READ_ONCE(engine->execlists.pending[0]) || timeout) {
- unsigned long flags;
-
- spin_lock_irqsave(&engine->active.lock, flags);
- __execlists_submission_tasklet(engine);
- spin_unlock_irqrestore(&engine->active.lock, flags);
-
- /* Recheck after serialising with direct-submission */
- if (unlikely(timeout && preempt_timeout(engine))) {
- cancel_timer(&engine->execlists.preempt);
- execlists_reset(engine, "preemption time out");
- }
- }
+ if (!engine->execlists.pending[0])
+ execlists_dequeue_irq(engine);
}
static void __execlists_kick(struct intel_engine_execlists *execlists)
@@ -3220,26 +3212,16 @@ static void queue_request(struct intel_engine_cs *engine,
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
}
-static void __submit_queue_imm(struct intel_engine_cs *engine)
-{
- struct intel_engine_execlists * const execlists = &engine->execlists;
-
- if (reset_in_progress(execlists))
- return; /* defer until we restart the engine following reset */
-
- __execlists_submission_tasklet(engine);
-}
-
-static void submit_queue(struct intel_engine_cs *engine,
+static bool submit_queue(struct intel_engine_cs *engine,
const struct i915_request *rq)
{
struct intel_engine_execlists *execlists = &engine->execlists;
if (rq_prio(rq) <= execlists->queue_priority_hint)
- return;
+ return false;
execlists->queue_priority_hint = rq_prio(rq);
- __submit_queue_imm(engine);
+ return true;
}
static bool ancestor_on_hold(const struct intel_engine_cs *engine,
@@ -3249,25 +3231,11 @@ static bool ancestor_on_hold(const struct intel_engine_cs *engine,
return !list_empty(&engine->active.hold) && hold_request(rq);
}
-static void flush_csb(struct intel_engine_cs *engine)
-{
- struct intel_engine_execlists *el = &engine->execlists;
-
- if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) {
- if (!reset_in_progress(el))
- process_csb(engine);
- tasklet_unlock(&el->tasklet);
- }
-}
-
static void execlists_submit_request(struct i915_request *request)
{
struct intel_engine_cs *engine = request->engine;
unsigned long flags;
- /* Hopefully we clear execlists->pending[] to let us through */
- flush_csb(engine);
-
/* Will be called from irq-context when using foreign fences. */
spin_lock_irqsave(&engine->active.lock, flags);
@@ -3281,7 +3249,8 @@ static void execlists_submit_request(struct i915_request *request)
GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
GEM_BUG_ON(list_empty(&request->sched.link));
- submit_queue(engine, request);
+ if (submit_queue(engine, request))
+ __execlists_kick(&engine->execlists);
}
spin_unlock_irqrestore(&engine->active.lock, flags);
@@ -4146,7 +4115,6 @@ static int execlists_resume(struct intel_engine_cs *engine)
static void execlists_reset_prepare(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
- unsigned long flags;
ENGINE_TRACE(engine, "depth<-%d\n",
atomic_read(&execlists->tasklet.count));
@@ -4163,10 +4131,6 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
__tasklet_disable_sync_once(&execlists->tasklet);
GEM_BUG_ON(!reset_in_progress(execlists));
- /* And flush any current direct submission. */
- spin_lock_irqsave(&engine->active.lock, flags);
- spin_unlock_irqrestore(&engine->active.lock, flags);
-
/*
* We stop engines, otherwise we might get failed reset and a
* dead gpu (on elk). Also as modern gpu as kbl can suffer
@@ -4411,12 +4375,12 @@ static void execlists_reset_finish(struct intel_engine_cs *engine)
* to sleep before we restart and reload a context.
*/
GEM_BUG_ON(!reset_in_progress(execlists));
- if (!RB_EMPTY_ROOT(&execlists->queue.rb_root))
- execlists->tasklet.func(execlists->tasklet.data);
+ GEM_BUG_ON(engine->execlists.pending[0]);
+ /* And kick in case we missed a new request submission. */
if (__tasklet_enable(&execlists->tasklet))
- /* And kick in case we missed a new request submission. */
- tasklet_hi_schedule(&execlists->tasklet);
+ __execlists_kick(execlists);
+
ENGINE_TRACE(engine, "depth->%d\n",
atomic_read(&execlists->tasklet.count));
}
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 000d63588e9e..b85b6f3dcd60 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -40,20 +40,19 @@ static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
intel_uncore_rmw_fw(uncore, reg, clr, 0);
}
-static void engine_skip_context(struct i915_request *rq)
+static void skip_context(struct i915_request *rq)
{
- struct intel_engine_cs *engine = rq->engine;
struct intel_context *hung_ctx = rq->context;
- if (!i915_request_is_active(rq))
- return;
+ list_for_each_entry_from_rcu(rq, &hung_ctx->timeline->requests, link) {
+ if (!i915_request_is_active(rq))
+ return;
- lockdep_assert_held(&engine->active.lock);
- list_for_each_entry_continue(rq, &engine->active.requests, sched.link)
if (rq->context == hung_ctx) {
i915_request_set_error_once(rq, -EIO);
__i915_request_skip(rq);
}
+ }
}
static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
@@ -160,7 +159,7 @@ void __i915_request_reset(struct i915_request *rq, bool guilty)
i915_request_set_error_once(rq, -EIO);
__i915_request_skip(rq);
if (mark_guilty(rq))
- engine_skip_context(rq);
+ skip_context(rq);
} else {
i915_request_set_error_once(rq, -EAGAIN);
mark_innocent(rq);
@@ -753,8 +752,10 @@ static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
if (err)
return err;
+ local_bh_disable();
for_each_engine(engine, gt, id)
__intel_engine_reset(engine, stalled_mask & engine->mask);
+ local_bh_enable();
intel_ggtt_restore_fences(gt->ggtt);
@@ -832,9 +833,11 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
set_bit(I915_WEDGED, >->reset.flags);
/* Mark all executing requests as skipped */
+ local_bh_disable();
for_each_engine(engine, gt, id)
if (engine->reset.cancel)
engine->reset.cancel(engine);
+ local_bh_enable();
reset_finish(gt, awake);
@@ -1109,20 +1112,7 @@ static inline int intel_gt_reset_engine(struct intel_engine_cs *engine)
return __intel_gt_reset(engine->gt, engine->mask);
}
-/**
- * intel_engine_reset - reset GPU engine to recover from a hang
- * @engine: engine to reset
- * @msg: reason for GPU reset; or NULL for no drm_notice()
- *
- * Reset a specific GPU engine. Useful if a hang is detected.
- * Returns zero on successful reset or otherwise an error code.
- *
- * Procedure is:
- * - identifies the request that caused the hang and it is dropped
- * - reset engine (which will force the engine to idle)
- * - re-init/configure engine
- */
-int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
+int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg)
{
struct intel_gt *gt = engine->gt;
bool uses_guc = intel_engine_in_guc_submission_mode(engine);
@@ -1172,6 +1162,30 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
return ret;
}
+/**
+ * intel_engine_reset - reset GPU engine to recover from a hang
+ * @engine: engine to reset
+ * @msg: reason for GPU reset; or NULL for no drm_notice()
+ *
+ * Reset a specific GPU engine. Useful if a hang is detected.
+ * Returns zero on successful reset or otherwise an error code.
+ *
+ * Procedure is:
+ * - identifies the request that caused the hang and it is dropped
+ * - reset engine (which will force the engine to idle)
+ * - re-init/configure engine
+ */
+int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
+{
+ int err;
+
+ local_bh_disable();
+ err = __intel_engine_reset_bh(engine, msg);
+ local_bh_enable();
+
+ return err;
+}
+
static void intel_gt_reset_global(struct intel_gt *gt,
u32 engine_mask,
const char *reason)
@@ -1258,18 +1272,20 @@ void intel_gt_handle_error(struct intel_gt *gt,
* single reset fails.
*/
if (intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
+ local_bh_disable();
for_each_engine_masked(engine, gt, engine_mask, tmp) {
BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
>->reset.flags))
continue;
- if (intel_engine_reset(engine, msg) == 0)
+ if (__intel_engine_reset_bh(engine, msg) == 0)
engine_mask &= ~engine->mask;
clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
>->reset.flags);
}
+ local_bh_enable();
}
if (!engine_mask)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
index a0eec7c11c0c..7dbf5cc8a333 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -34,6 +34,8 @@ void intel_gt_reset(struct intel_gt *gt,
const char *reason);
int intel_engine_reset(struct intel_engine_cs *engine,
const char *reason);
+int __intel_engine_reset_bh(struct intel_engine_cs *engine,
+ const char *reason);
void __i915_request_reset(struct i915_request *rq, bool guilty);
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c b/drivers/gpu/drm/i915/gt/selftest_context.c
index 1f4020e906a8..db738d400168 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -25,7 +25,7 @@ static int request_sync(struct i915_request *rq)
/* Opencode i915_request_add() so we can keep the timeline locked. */
__i915_request_commit(rq);
rq->sched.attr.priority = I915_PRIORITY_BARRIER;
- __i915_request_queue(rq, NULL);
+ __i915_request_queue_bh(rq);
timeout = i915_request_wait(rq, 0, HZ / 10);
if (timeout < 0)
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 95d41c01d0e0..37cb51c3f4f6 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -623,8 +623,10 @@ static int live_hold_reset(void *arg)
/* We have our request executing, now remove it and reset */
+ local_bh_disable();
if (test_and_set_bit(I915_RESET_ENGINE + id,
>->reset.flags)) {
+ local_bh_enable();
intel_gt_set_wedged(gt);
err = -EBUSY;
goto out;
@@ -638,12 +640,13 @@ static int live_hold_reset(void *arg)
execlists_hold(engine, rq);
GEM_BUG_ON(!i915_request_on_hold(rq));
- intel_engine_reset(engine, NULL);
+ __intel_engine_reset_bh(engine, NULL);
GEM_BUG_ON(rq->fence.error != -EIO);
tasklet_enable(&engine->execlists.tasklet);
clear_and_wake_up_bit(I915_RESET_ENGINE + id,
>->reset.flags);
+ local_bh_enable();
/* Check that we do not resubmit the held request */
if (!i915_request_wait(rq, 0, HZ / 5)) {
@@ -4569,8 +4572,10 @@ static int reset_virtual_engine(struct intel_gt *gt,
GEM_BUG_ON(engine == ve->engine);
/* Take ownership of the reset and tasklet */
+ local_bh_disable();
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
>->reset.flags)) {
+ local_bh_enable();
intel_gt_set_wedged(gt);
err = -EBUSY;
goto out_heartbeat;
@@ -4590,12 +4595,13 @@ static int reset_virtual_engine(struct intel_gt *gt,
execlists_hold(engine, rq);
GEM_BUG_ON(!i915_request_on_hold(rq));
- intel_engine_reset(engine, NULL);
+ __intel_engine_reset_bh(engine, NULL);
GEM_BUG_ON(rq->fence.error != -EIO);
/* Release our grasp on the engine, letting CS flow again */
tasklet_enable(&engine->execlists.tasklet);
clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id, >->reset.flags);
+ local_bh_enable();
/* Check that we do not resubmit the held request */
i915_request_get(rq);
@@ -6242,16 +6248,17 @@ static void garbage_reset(struct intel_engine_cs *engine,
const unsigned int bit = I915_RESET_ENGINE + engine->id;
unsigned long *lock = &engine->gt->reset.flags;
- if (test_and_set_bit(bit, lock))
- return;
-
- tasklet_disable(&engine->execlists.tasklet);
+ local_bh_disable();
+ if (!test_and_set_bit(bit, lock)) {
+ tasklet_disable(&engine->execlists.tasklet);
- if (!rq->fence.error)
- intel_engine_reset(engine, NULL);
+ if (!rq->fence.error)
+ __intel_engine_reset_bh(engine, NULL);
- tasklet_enable(&engine->execlists.tasklet);
- clear_and_wake_up_bit(bit, lock);
+ tasklet_enable(&engine->execlists.tasklet);
+ clear_and_wake_up_bit(bit, lock);
+ }
+ local_bh_enable();
}
static struct i915_request *garbage(struct intel_context *ce,
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index fb5ebf930ab2..c28d1fcad673 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1576,12 +1576,17 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine,
engine->name, mode, p->name);
tasklet_disable(t);
+ if (strcmp(p->name, "softirq"))
+ local_bh_disable();
p->critical_section_begin();
- err = intel_engine_reset(engine, NULL);
+ err = __intel_engine_reset_bh(engine, NULL);
p->critical_section_end();
+ if (strcmp(p->name, "softirq"))
+ local_bh_enable();
tasklet_enable(t);
+ tasklet_hi_schedule(t);
if (err)
pr_err("i915_reset_engine(%s:%s) failed under %s\n",
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
index ef5aeebbeeb0..4dbd5bc840c3 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -326,11 +326,16 @@ static int igt_atomic_engine_reset(void *arg)
for (p = igt_atomic_phases; p->name; p++) {
GEM_TRACE("intel_engine_reset(%s) under %s\n",
engine->name, p->name);
+ if (strcmp(p->name, "softirq"))
+ local_bh_disable();
p->critical_section_begin();
- err = intel_engine_reset(engine, NULL);
+ err = __intel_engine_reset_bh(engine, NULL);
p->critical_section_end();
+ if (strcmp(p->name, "softirq"))
+ local_bh_enable();
+
if (err) {
pr_err("intel_engine_reset(%s) failed under %s\n",
engine->name, p->name);
@@ -340,6 +345,7 @@ static int igt_atomic_engine_reset(void *arg)
intel_engine_pm_put(engine);
tasklet_enable(&engine->execlists.tasklet);
+ tasklet_hi_schedule(&engine->execlists.tasklet);
if (err)
break;
}
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index a9db1376b996..e4dad3aa69ff 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1583,6 +1583,12 @@ struct i915_request *__i915_request_commit(struct i915_request *rq)
return __i915_request_add_to_timeline(rq);
}
+void __i915_request_queue_bh(struct i915_request *rq)
+{
+ i915_sw_fence_commit(&rq->semaphore);
+ i915_sw_fence_commit(&rq->submit);
+}
+
void __i915_request_queue(struct i915_request *rq,
const struct i915_sched_attr *attr)
{
@@ -1599,8 +1605,10 @@ void __i915_request_queue(struct i915_request *rq,
*/
if (attr && rq->engine->schedule)
rq->engine->schedule(rq, attr);
- i915_sw_fence_commit(&rq->semaphore);
- i915_sw_fence_commit(&rq->submit);
+
+ local_bh_disable();
+ __i915_request_queue_bh(rq);
+ local_bh_enable(); /* kick tasklets */
}
void i915_request_add(struct i915_request *rq)
diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
index 92e4320c50c4..c528ab33c9bd 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -315,6 +315,7 @@ void __i915_request_skip(struct i915_request *rq);
struct i915_request *__i915_request_commit(struct i915_request *request);
void __i915_request_queue(struct i915_request *rq,
const struct i915_sched_attr *attr);
+void __i915_request_queue_bh(struct i915_request *rq);
bool i915_request_retire(struct i915_request *rq);
void i915_request_retire_upto(struct i915_request *rq);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index b9cf9931ebd7..318e359bf5c3 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -458,14 +458,10 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node,
if (!dep)
return -ENOMEM;
- local_bh_disable();
-
if (!__i915_sched_node_add_dependency(node, signal, dep,
flags | I915_DEPENDENCY_ALLOC))
i915_dependency_free(dep);
- local_bh_enable(); /* kick submission tasklet */
-
return 0;
}
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
index e424a6d1a68c..b8c5920d1ff3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -1932,9 +1932,7 @@ static int measure_inter_request(struct intel_context *ce)
intel_ring_advance(rq, cs);
i915_request_add(rq);
}
- local_bh_disable();
i915_sw_fence_commit(submit);
- local_bh_enable();
intel_engine_flush_submission(ce->engine);
heap_fence_put(submit);
@@ -2220,11 +2218,9 @@ static int measure_completion(struct intel_context *ce)
intel_ring_advance(rq, cs);
dma_fence_add_callback(&rq->fence, &cb.base, signal_cb);
-
- local_bh_disable();
i915_request_add(rq);
- local_bh_enable();
+ intel_engine_flush_submission(ce->engine);
if (wait_for(READ_ONCE(sema[i]) == -1, 50)) {
err = -EIO;
goto err;
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index ec0ecb4e4ca6..e09ce8067b9c 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -219,6 +219,9 @@ void igt_spinner_fini(struct igt_spinner *spin)
bool igt_wait_for_spinner(struct igt_spinner *spin, struct i915_request *rq)
{
+ if (i915_request_is_ready(rq))
+ intel_engine_flush_submission(rq->engine);
+
return !(wait_for_us(i915_seqno_passed(hws_seqno(spin, rq),
rq->fence.seqno),
100) &&
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 38+ messages in thread* [Intel-gfx] [PATCH 04/21] drm/i915/gt: Use virtual_engine during execlists_dequeue
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 02/21] drm/i915/gt: Wean workaround selftests off GEM context Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 03/21] drm/i915/gt: Replace direct submit with direct call to tasklet Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 05/21] drm/i915/gt: Decouple inflight virtual engines Chris Wilson
` (22 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Rather than going back and forth between the rb_node entry and the
virtual_engine type, store the ve local and reuse it. As the
container_of conversion from rb_node to virtual_engine requires a
variable offset, performing that conversion just once shaves off a bit
of code.
v2: Keep a single virtual engine lookup, for typical use.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
.../drm/i915/gt/intel_execlists_submission.c | 239 ++++++++----------
1 file changed, 105 insertions(+), 134 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 157a8f18d41e..8e83e60492af 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -425,9 +425,15 @@ static int queue_prio(const struct intel_engine_execlists *execlists)
return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used);
}
+static int virtual_prio(const struct intel_engine_execlists *el)
+{
+ struct rb_node *rb = rb_first_cached(&el->virtual);
+
+ return rb ? rb_entry(rb, struct ve_node, rb)->prio : INT_MIN;
+}
+
static inline bool need_preempt(const struct intel_engine_cs *engine,
- const struct i915_request *rq,
- struct rb_node *rb)
+ const struct i915_request *rq)
{
int last_prio;
@@ -464,25 +470,6 @@ static inline bool need_preempt(const struct intel_engine_cs *engine,
rq_prio(list_next_entry(rq, sched.link)) > last_prio)
return true;
- if (rb) {
- struct virtual_engine *ve =
- rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
- bool preempt = false;
-
- if (engine == ve->siblings[0]) { /* only preempt one sibling */
- struct i915_request *next;
-
- rcu_read_lock();
- next = READ_ONCE(ve->request);
- if (next)
- preempt = rq_prio(next) > last_prio;
- rcu_read_unlock();
- }
-
- if (preempt)
- return preempt;
- }
-
/*
* If the inflight context did not trigger the preemption, then maybe
* it was the set of queued requests? Pick the highest priority in
@@ -493,7 +480,8 @@ static inline bool need_preempt(const struct intel_engine_cs *engine,
* ELSP[0] or ELSP[1] as, thanks again to PI, if it was the same
* context, it's priority would not exceed ELSP[0] aka last_prio.
*/
- return queue_prio(&engine->execlists) > last_prio;
+ return max(virtual_prio(&engine->execlists),
+ queue_prio(&engine->execlists)) > last_prio;
}
__maybe_unused static inline bool
@@ -1781,6 +1769,35 @@ static bool virtual_matches(const struct virtual_engine *ve,
return true;
}
+static struct virtual_engine *
+first_virtual_engine(struct intel_engine_cs *engine)
+{
+ struct intel_engine_execlists *el = &engine->execlists;
+ struct rb_node *rb = rb_first_cached(&el->virtual);
+
+ while (rb) {
+ struct virtual_engine *ve =
+ rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
+ struct i915_request *rq = READ_ONCE(ve->request);
+
+ /* lazily cleanup after another engine handled rq */
+ if (!rq) {
+ rb_erase_cached(rb, &el->virtual);
+ RB_CLEAR_NODE(rb);
+ rb = rb_first_cached(&el->virtual);
+ continue;
+ }
+
+ if (!virtual_matches(ve, rq, engine)) {
+ rb = rb_next(rb);
+ continue;
+ }
+ return ve;
+ }
+
+ return NULL;
+}
+
static void virtual_xfer_context(struct virtual_engine *ve,
struct intel_engine_cs *engine)
{
@@ -1869,32 +1886,15 @@ static void defer_active(struct intel_engine_cs *engine)
static bool
need_timeslice(const struct intel_engine_cs *engine,
- const struct i915_request *rq,
- const struct rb_node *rb)
+ const struct i915_request *rq)
{
int hint;
if (!intel_engine_has_timeslices(engine))
return false;
- hint = engine->execlists.queue_priority_hint;
-
- if (rb) {
- const struct virtual_engine *ve =
- rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
- const struct intel_engine_cs *inflight =
- intel_context_inflight(&ve->context);
-
- if (!inflight || inflight == engine) {
- struct i915_request *next;
-
- rcu_read_lock();
- next = READ_ONCE(ve->request);
- if (next)
- hint = max(hint, rq_prio(next));
- rcu_read_unlock();
- }
- }
+ hint = max(engine->execlists.queue_priority_hint,
+ virtual_prio(&engine->execlists));
if (!list_is_last(&rq->sched.link, &engine->active.requests))
hint = max(hint, rq_prio(list_next_entry(rq, sched.link)));
@@ -2041,6 +2041,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
struct i915_request **port = execlists->pending;
struct i915_request ** const last_port = port + execlists->port_mask;
struct i915_request *last = *execlists->active;
+ struct virtual_engine *ve;
struct rb_node *rb;
bool submit = false;
@@ -2068,26 +2069,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
spin_lock(&engine->active.lock);
- for (rb = rb_first_cached(&execlists->virtual); rb; ) {
- struct virtual_engine *ve =
- rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
- struct i915_request *rq = READ_ONCE(ve->request);
-
- if (!rq) { /* lazily cleanup after another engine handled rq */
- rb_erase_cached(rb, &execlists->virtual);
- RB_CLEAR_NODE(rb);
- rb = rb_first_cached(&execlists->virtual);
- continue;
- }
-
- if (!virtual_matches(ve, rq, engine)) {
- rb = rb_next(rb);
- continue;
- }
-
- break;
- }
-
/*
* If the queue is higher priority than the last
* request in the currently active context, submit afresh.
@@ -2110,7 +2091,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
if (last) {
if (i915_request_completed(last)) {
goto check_secondary;
- } else if (need_preempt(engine, last, rb)) {
+ } else if (need_preempt(engine, last)) {
ENGINE_TRACE(engine,
"preempting last=%llx:%lld, prio=%d, hint=%d\n",
last->fence.context,
@@ -2136,7 +2117,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
__unwind_incomplete_requests(engine);
last = NULL;
- } else if (need_timeslice(engine, last, rb) &&
+ } else if (need_timeslice(engine, last) &&
timeslice_expired(execlists, last)) {
ENGINE_TRACE(engine,
"expired last=%llx:%lld, prio=%d, hint=%d, yield?=%s\n",
@@ -2187,96 +2168,86 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
}
}
- while (rb) { /* XXX virtual is always taking precedence */
- struct virtual_engine *ve =
- rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
+ /* XXX virtual is always taking precedence */
+ while ((ve = first_virtual_engine(engine))) {
struct i915_request *rq;
spin_lock(&ve->base.active.lock);
rq = ve->request;
- if (unlikely(!rq)) { /* lost the race to a sibling */
- spin_unlock(&ve->base.active.lock);
- rb_erase_cached(rb, &execlists->virtual);
- RB_CLEAR_NODE(rb);
- rb = rb_first_cached(&execlists->virtual);
- continue;
- }
+ if (unlikely(!rq)) /* lost the race to a sibling */
+ goto unlock;
- GEM_BUG_ON(rq != ve->request);
GEM_BUG_ON(rq->engine != &ve->base);
GEM_BUG_ON(rq->context != &ve->context);
- if (rq_prio(rq) >= queue_prio(execlists)) {
- if (!virtual_matches(ve, rq, engine)) {
- spin_unlock(&ve->base.active.lock);
- rb = rb_next(rb);
- continue;
- }
+ if (unlikely(rq_prio(rq) < queue_prio(execlists))) {
+ spin_unlock(&ve->base.active.lock);
+ break;
+ }
- if (last && !can_merge_rq(last, rq)) {
- spin_unlock(&ve->base.active.lock);
- spin_unlock(&engine->active.lock);
- start_timeslice(engine, rq_prio(rq));
- return; /* leave this for another sibling */
- }
+ GEM_BUG_ON(!virtual_matches(ve, rq, engine));
- ENGINE_TRACE(engine,
- "virtual rq=%llx:%lld%s, new engine? %s\n",
- rq->fence.context,
- rq->fence.seqno,
- i915_request_completed(rq) ? "!" :
- i915_request_started(rq) ? "*" :
- "",
- yesno(engine != ve->siblings[0]));
-
- WRITE_ONCE(ve->request, NULL);
- WRITE_ONCE(ve->base.execlists.queue_priority_hint,
- INT_MIN);
- rb_erase_cached(rb, &execlists->virtual);
- RB_CLEAR_NODE(rb);
+ if (last && !can_merge_rq(last, rq)) {
+ spin_unlock(&ve->base.active.lock);
+ spin_unlock(&engine->active.lock);
+ start_timeslice(engine, rq_prio(rq));
+ return; /* leave this for another sibling */
+ }
- GEM_BUG_ON(!(rq->execution_mask & engine->mask));
- WRITE_ONCE(rq->engine, engine);
+ ENGINE_TRACE(engine,
+ "virtual rq=%llx:%lld%s, new engine? %s\n",
+ rq->fence.context,
+ rq->fence.seqno,
+ i915_request_completed(rq) ? "!" :
+ i915_request_started(rq) ? "*" :
+ "",
+ yesno(engine != ve->siblings[0]));
- if (__i915_request_submit(rq)) {
- /*
- * Only after we confirm that we will submit
- * this request (i.e. it has not already
- * completed), do we want to update the context.
- *
- * This serves two purposes. It avoids
- * unnecessary work if we are resubmitting an
- * already completed request after timeslicing.
- * But more importantly, it prevents us altering
- * ve->siblings[] on an idle context, where
- * we may be using ve->siblings[] in
- * virtual_context_enter / virtual_context_exit.
- */
- virtual_xfer_context(ve, engine);
- GEM_BUG_ON(ve->siblings[0] != engine);
+ WRITE_ONCE(ve->request, NULL);
+ WRITE_ONCE(ve->base.execlists.queue_priority_hint, INT_MIN);
- submit = true;
- last = rq;
- }
- i915_request_put(rq);
+ rb = &ve->nodes[engine->id].rb;
+ rb_erase_cached(rb, &execlists->virtual);
+ RB_CLEAR_NODE(rb);
+
+ GEM_BUG_ON(!(rq->execution_mask & engine->mask));
+ WRITE_ONCE(rq->engine, engine);
+ if (__i915_request_submit(rq)) {
/*
- * Hmm, we have a bunch of virtual engine requests,
- * but the first one was already completed (thanks
- * preempt-to-busy!). Keep looking at the veng queue
- * until we have no more relevant requests (i.e.
- * the normal submit queue has higher priority).
+ * Only after we confirm that we will submit
+ * this request (i.e. it has not already
+ * completed), do we want to update the context.
+ *
+ * This serves two purposes. It avoids
+ * unnecessary work if we are resubmitting an
+ * already completed request after timeslicing.
+ * But more importantly, it prevents us altering
+ * ve->siblings[] on an idle context, where
+ * we may be using ve->siblings[] in
+ * virtual_context_enter / virtual_context_exit.
*/
- if (!submit) {
- spin_unlock(&ve->base.active.lock);
- rb = rb_first_cached(&execlists->virtual);
- continue;
- }
+ virtual_xfer_context(ve, engine);
+ GEM_BUG_ON(ve->siblings[0] != engine);
+
+ submit = true;
+ last = rq;
}
+ i915_request_put(rq);
+unlock:
spin_unlock(&ve->base.active.lock);
- break;
+
+ /*
+ * Hmm, we have a bunch of virtual engine requests,
+ * but the first one was already completed (thanks
+ * preempt-to-busy!). Keep looking at the veng queue
+ * until we have no more relevant requests (i.e.
+ * the normal submit queue has higher priority).
+ */
+ if (submit)
+ break;
}
while ((rb = rb_first_cached(&execlists->queue))) {
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 38+ messages in thread* [Intel-gfx] [PATCH 05/21] drm/i915/gt: Decouple inflight virtual engines
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (2 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 04/21] drm/i915/gt: Use virtual_engine during execlists_dequeue Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 06/21] drm/i915/gt: Defer schedule_out until after the next dequeue Chris Wilson
` (21 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Once a virtual engine has been bound to a sibling, it will remain bound
until we finally schedule out the last active request. We can not rebind
the context to a new sibling while it is inflight as the context save
will conflict, hence we wait. As we cannot then use any other sibliing
while the context is inflight, only kick the bound sibling while it
inflight and upon scheduling out the kick the rest (so that we can swap
engines on timeslicing if the previously bound engine becomes
oversubscribed).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../drm/i915/gt/intel_execlists_submission.c | 28 ++++++++-----------
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 8e83e60492af..174c3f5f2e81 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1359,9 +1359,8 @@ static inline void execlists_schedule_in(struct i915_request *rq, int idx)
static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
{
struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
- struct i915_request *next = READ_ONCE(ve->request);
- if (next == rq || (next && next->execution_mask & ~rq->execution_mask))
+ if (READ_ONCE(ve->request))
tasklet_hi_schedule(&ve->base.execlists.tasklet);
}
@@ -1781,17 +1780,13 @@ first_virtual_engine(struct intel_engine_cs *engine)
struct i915_request *rq = READ_ONCE(ve->request);
/* lazily cleanup after another engine handled rq */
- if (!rq) {
+ if (!rq || !virtual_matches(ve, rq, engine)) {
rb_erase_cached(rb, &el->virtual);
RB_CLEAR_NODE(rb);
rb = rb_first_cached(&el->virtual);
continue;
}
- if (!virtual_matches(ve, rq, engine)) {
- rb = rb_next(rb);
- continue;
- }
return ve;
}
@@ -4968,7 +4963,6 @@ static void virtual_submission_tasklet(unsigned long data)
if (unlikely(!mask))
return;
- local_irq_disable();
for (n = 0; n < ve->num_siblings; n++) {
struct intel_engine_cs *sibling = READ_ONCE(ve->siblings[n]);
struct ve_node * const node = &ve->nodes[sibling->id];
@@ -4978,20 +4972,19 @@ static void virtual_submission_tasklet(unsigned long data)
if (!READ_ONCE(ve->request))
break; /* already handled by a sibling's tasklet */
+ spin_lock_irq(&sibling->active.lock);
+
if (unlikely(!(mask & sibling->mask))) {
if (!RB_EMPTY_NODE(&node->rb)) {
- spin_lock(&sibling->active.lock);
rb_erase_cached(&node->rb,
&sibling->execlists.virtual);
RB_CLEAR_NODE(&node->rb);
- spin_unlock(&sibling->active.lock);
}
- continue;
- }
- spin_lock(&sibling->active.lock);
+ goto unlock_engine;
+ }
- if (!RB_EMPTY_NODE(&node->rb)) {
+ if (unlikely(!RB_EMPTY_NODE(&node->rb))) {
/*
* Cheat and avoid rebalancing the tree if we can
* reuse this node in situ.
@@ -5031,9 +5024,12 @@ static void virtual_submission_tasklet(unsigned long data)
if (first && prio > sibling->execlists.queue_priority_hint)
tasklet_hi_schedule(&sibling->execlists.tasklet);
- spin_unlock(&sibling->active.lock);
+unlock_engine:
+ spin_unlock_irq(&sibling->active.lock);
+
+ if (intel_context_inflight(&ve->context))
+ break;
}
- local_irq_enable();
}
static void virtual_submit_request(struct i915_request *rq)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 38+ messages in thread* [Intel-gfx] [PATCH 06/21] drm/i915/gt: Defer schedule_out until after the next dequeue
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (3 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 05/21] drm/i915/gt: Decouple inflight virtual engines Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 07/21] drm/i915/gt: Remove virtual breadcrumb before transfer Chris Wilson
` (20 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Inside schedule_out, we do extra work upon idling the context, such as
updating the runtime, kicking off retires, kicking virtual engines.
However, if we are in a series of processing single requests per
contexts, we may find ourselves scheduling out the context, only to
immediately schedule it back in during dequeue. This is just extra work
that we can avoid if we keep the context marked as inflight across the
dequeue. This becomes more significant later on for minimising virtual
engine misses.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +-
.../drm/i915/gt/intel_execlists_submission.c | 121 +++++++++++-------
2 files changed, 80 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 52fa9c132746..10830eeab0f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -58,8 +58,8 @@ struct intel_context {
struct intel_engine_cs *engine;
struct intel_engine_cs *inflight;
-#define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 2)
-#define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 2)
+#define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 3)
+#define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 3)
struct i915_address_space *vm;
struct i915_gem_context __rcu *gem_context;
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 174c3f5f2e81..d278c4445496 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2017,19 +2017,6 @@ static void set_preempt_timeout(struct intel_engine_cs *engine,
active_preempt_timeout(engine, rq));
}
-static inline void clear_ports(struct i915_request **ports, int count)
-{
- memset_p((void **)ports, NULL, count);
-}
-
-static inline void
-copy_ports(struct i915_request **dst, struct i915_request **src, int count)
-{
- /* A memcpy_p() would be very useful here! */
- while (count--)
- WRITE_ONCE(*dst++, *src++); /* avoid write tearing */
-}
-
static void execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -2378,18 +2365,32 @@ static void execlists_dequeue_irq(struct intel_engine_cs *engine)
local_irq_enable(); /* flush irq_work (e.g. breadcrumb enabling) */
}
-static void
-cancel_port_requests(struct intel_engine_execlists * const execlists)
+static inline void clear_ports(struct i915_request **ports, int count)
+{
+ memset_p((void **)ports, NULL, count);
+}
+
+static inline void
+copy_ports(struct i915_request **dst, struct i915_request **src, int count)
+{
+ /* A memcpy_p() would be very useful here! */
+ while (count--)
+ WRITE_ONCE(*dst++, *src++); /* avoid write tearing */
+}
+
+static struct i915_request **
+cancel_port_requests(struct intel_engine_execlists * const execlists,
+ struct i915_request **inactive)
{
struct i915_request * const *port;
for (port = execlists->pending; *port; port++)
- execlists_schedule_out(*port);
+ *inactive++ = *port;
clear_ports(execlists->pending, ARRAY_SIZE(execlists->pending));
/* Mark the end of active before we overwrite *active */
for (port = xchg(&execlists->active, execlists->pending); *port; port++)
- execlists_schedule_out(*port);
+ *inactive++ = *port;
clear_ports(execlists->inflight, ARRAY_SIZE(execlists->inflight));
smp_wmb(); /* complete the seqlock for execlists_active() */
@@ -2399,6 +2400,8 @@ cancel_port_requests(struct intel_engine_execlists * const execlists)
GEM_BUG_ON(execlists->pending[0]);
cancel_timer(&execlists->timer);
cancel_timer(&execlists->preempt);
+
+ return inactive;
}
static inline void
@@ -2526,7 +2529,8 @@ csb_read(const struct intel_engine_cs *engine, u64 * const csb)
return entry;
}
-static void process_csb(struct intel_engine_cs *engine)
+static struct i915_request **
+process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
u64 * const buf = execlists->csb_status;
@@ -2555,7 +2559,7 @@ static void process_csb(struct intel_engine_cs *engine)
head = execlists->csb_head;
tail = READ_ONCE(*execlists->csb_write);
if (unlikely(head == tail))
- return;
+ return inactive;
/*
* We will consume all events from HW, or at least pretend to.
@@ -2635,7 +2639,7 @@ static void process_csb(struct intel_engine_cs *engine)
/* cancel old inflight, prepare for switch */
trace_ports(execlists, "preempted", old);
while (*old)
- execlists_schedule_out(*old++);
+ *inactive++ = *old++;
/* switch pending to inflight */
GEM_BUG_ON(!assert_pending_valid(execlists, "promote"));
@@ -2697,7 +2701,7 @@ static void process_csb(struct intel_engine_cs *engine)
regs[CTX_RING_TAIL]);
}
- execlists_schedule_out(*execlists->active++);
+ *inactive++ = *execlists->active++;
GEM_BUG_ON(execlists->active - execlists->inflight >
execlists_num_ports(execlists));
@@ -2718,6 +2722,15 @@ static void process_csb(struct intel_engine_cs *engine)
* invalidation before.
*/
invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
+
+ return inactive;
+}
+
+static void post_process_csb(struct i915_request **port,
+ struct i915_request **last)
+{
+ while (port != last)
+ execlists_schedule_out(*port++);
}
static void __execlists_hold(struct i915_request *rq)
@@ -2993,8 +3006,8 @@ active_context(struct intel_engine_cs *engine, u32 ccid)
for (port = el->active; (rq = *port); port++) {
if (rq->context->lrc.ccid == ccid) {
ENGINE_TRACE(engine,
- "ccid found at active:%zd\n",
- port - el->active);
+ "ccid:%x found at active:%zd\n",
+ ccid, port - el->active);
return rq;
}
}
@@ -3002,8 +3015,8 @@ active_context(struct intel_engine_cs *engine, u32 ccid)
for (port = el->pending; (rq = *port); port++) {
if (rq->context->lrc.ccid == ccid) {
ENGINE_TRACE(engine,
- "ccid found at pending:%zd\n",
- port - el->pending);
+ "ccid:%x found at pending:%zd\n",
+ ccid, port - el->pending);
return rq;
}
}
@@ -3121,8 +3134,11 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine)
static void execlists_submission_tasklet(unsigned long data)
{
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
+ struct i915_request *post[2 * EXECLIST_MAX_PORTS];
+ struct i915_request **inactive;
- process_csb(engine);
+ inactive = process_csb(engine, post);
+ GEM_BUG_ON(inactive - post > ARRAY_SIZE(post));
if (unlikely(preempt_timeout(engine))) {
cancel_timer(&engine->execlists.preempt);
@@ -3148,6 +3164,8 @@ static void execlists_submission_tasklet(unsigned long data)
if (!engine->execlists.pending[0])
execlists_dequeue_irq(engine);
+
+ post_process_csb(post, inactive);
}
static void __execlists_kick(struct intel_engine_execlists *execlists)
@@ -4044,8 +4062,6 @@ static void enable_execlists(struct intel_engine_cs *engine)
ENGINE_POSTING_READ(engine, RING_HWS_PGA);
enable_error_interrupt(engine);
-
- engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
}
static bool unexpected_starting_state(struct intel_engine_cs *engine)
@@ -4134,22 +4150,29 @@ static void __execlists_reset_reg_state(const struct intel_context *ce,
__reset_stop_ring(regs, engine);
}
-static void __execlists_reset(struct intel_engine_cs *engine, bool stalled)
+static struct i915_request **reset_csb(struct intel_engine_cs *engine,
+ struct i915_request **inactive)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
- struct intel_context *ce;
- struct i915_request *rq;
- u32 head;
mb(); /* paranoia: read the CSB pointers from after the reset */
clflush(execlists->csb_write);
mb();
- process_csb(engine); /* drain preemption events */
+ inactive = process_csb(engine, inactive); /* drain preemption events */
/* Following the reset, we need to reload the CSB read/write pointers */
reset_csb_pointers(engine);
+ return inactive;
+}
+
+static void execlists_reset_active(struct intel_engine_cs *engine, bool stalled)
+{
+ struct intel_context *ce;
+ struct i915_request *rq;
+ u32 head;
+
/*
* Save the currently executing context, even if we completed
* its request, it was still running at the time of the
@@ -4157,7 +4180,7 @@ static void __execlists_reset(struct intel_engine_cs *engine, bool stalled)
*/
rq = active_context(engine, engine->execlists.reset_ccid);
if (!rq)
- goto unwind;
+ return;
ce = rq->context;
GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
@@ -4220,11 +4243,20 @@ static void __execlists_reset(struct intel_engine_cs *engine, bool stalled)
__execlists_reset_reg_state(ce, engine);
__execlists_update_reg_state(ce, engine, head);
ce->lrc.desc |= CTX_DESC_FORCE_RESTORE; /* paranoid: GPU was reset! */
+}
-unwind:
- /* Push back any incomplete requests for replay after the reset. */
- cancel_port_requests(execlists);
- __unwind_incomplete_requests(engine);
+static void execlists_reset_csb(struct intel_engine_cs *engine, bool stalled)
+{
+ struct intel_engine_execlists * const execlists = &engine->execlists;
+ struct i915_request *post[2 * EXECLIST_MAX_PORTS];
+ struct i915_request **inactive;
+
+ inactive = reset_csb(engine, post);
+
+ execlists_reset_active(engine, true);
+
+ inactive = cancel_port_requests(execlists, inactive);
+ post_process_csb(post, inactive);
}
static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled)
@@ -4233,10 +4265,12 @@ static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled)
ENGINE_TRACE(engine, "\n");
- spin_lock_irqsave(&engine->active.lock, flags);
-
- __execlists_reset(engine, stalled);
+ /* Process the csb, find the guilty context and throw away */
+ execlists_reset_csb(engine, stalled);
+ /* Push back any incomplete requests for replay after the reset. */
+ spin_lock_irqsave(&engine->active.lock, flags);
+ __unwind_incomplete_requests(engine);
spin_unlock_irqrestore(&engine->active.lock, flags);
}
@@ -4271,9 +4305,9 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine)
* submission's irq state, we also wish to remind ourselves that
* it is irq state.)
*/
- spin_lock_irqsave(&engine->active.lock, flags);
+ execlists_reset_csb(engine, true);
- __execlists_reset(engine, true);
+ spin_lock_irqsave(&engine->active.lock, flags);
/* Mark all executing requests as skipped. */
list_for_each_entry(rq, &engine->active.requests, sched.link)
@@ -4540,6 +4574,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
else
execlists->csb_size = GEN11_CSB_ENTRIES;
+ engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
if (INTEL_GEN(engine->i915) >= 11) {
execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
--
2.20.1
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^ permalink raw reply related [flat|nested] 38+ messages in thread* [Intel-gfx] [PATCH 07/21] drm/i915/gt: Remove virtual breadcrumb before transfer
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (4 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 06/21] drm/i915/gt: Defer schedule_out until after the next dequeue Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 08/21] drm/i915/gt: Shrink the critical section for irq signaling Chris Wilson
` (19 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
The issue with stale virtual breadcrumbs remain. Now we have the problem
that if the irq-signaler is still referencing the stale breadcrumb as we
transfer it to a new sibling, the list becomes spaghetti. This is a very
small window, but that doesn't stop it being hit infrequently. To
prevent the lists being tangled (the iterator starting on one engine's
b->signalers but walking onto another list), always decouple the virtual
breadcrumb on schedule-out and make sure that the walker has stepped out
of the lists.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 5 +++--
.../gpu/drm/i915/gt/intel_execlists_submission.c | 15 +++++++++++++++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index 00918300f53f..63900edbde88 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -454,15 +454,16 @@ void i915_request_cancel_breadcrumb(struct i915_request *rq)
{
struct intel_breadcrumbs *b = READ_ONCE(rq->engine)->breadcrumbs;
struct intel_context *ce = rq->context;
+ unsigned long flags;
bool release;
if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags))
return;
- spin_lock(&ce->signal_lock);
+ spin_lock_irqsave(&ce->signal_lock, flags);
list_del_rcu(&rq->signal_link);
release = remove_signaling_context(b, ce);
- spin_unlock(&ce->signal_lock);
+ spin_unlock_irqrestore(&ce->signal_lock, flags);
if (release)
intel_context_put(ce);
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index d278c4445496..192ec4041d7a 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1359,6 +1359,21 @@ static inline void execlists_schedule_in(struct i915_request *rq, int idx)
static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
{
struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
+ struct intel_engine_cs *engine = rq->engine;
+
+ /* Flush concurrent rcu iterators in signal_irq_work */
+ if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) {
+ /*
+ * After this point, the rq may be transferred to a new
+ * sibling, so before we clear ce->inflight make sure that
+ * the context has been removed from the b->signalers and
+ * furthermore we need to make sure that the concurrent
+ * iterator in signal_irq_work is no longer following
+ * ce->signal_link.
+ */
+ i915_request_cancel_breadcrumb(rq);
+ irq_work_sync(&engine->breadcrumbs->irq_work);
+ }
if (READ_ONCE(ve->request))
tasklet_hi_schedule(&ve->base.execlists.tasklet);
--
2.20.1
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^ permalink raw reply related [flat|nested] 38+ messages in thread* [Intel-gfx] [PATCH 08/21] drm/i915/gt: Shrink the critical section for irq signaling
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (5 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 07/21] drm/i915/gt: Remove virtual breadcrumb before transfer Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 09/21] drm/i915/gt: Resubmit the virtual engine on schedule-out Chris Wilson
` (18 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Let's only wait for the list iterator when decoupling the virtual
breadcrumb, as the signaling of all the requests may take a long time,
during which we do not want to keep the tasklet spinning.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 2 ++
drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 3 ++-
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index 63900edbde88..ac1e5f6c3c2c 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -239,6 +239,7 @@ static void signal_irq_work(struct irq_work *work)
intel_breadcrumbs_disarm_irq(b);
rcu_read_lock();
+ atomic_inc(&b->signaler_active);
list_for_each_entry_rcu(ce, &b->signalers, signal_link) {
struct i915_request *rq;
@@ -274,6 +275,7 @@ static void signal_irq_work(struct irq_work *work)
}
}
}
+ atomic_dec(&b->signaler_active);
rcu_read_unlock();
llist_for_each_safe(signal, sn, signal) {
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h b/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
index a74bb3062bd8..f672053d694d 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
@@ -35,6 +35,7 @@ struct intel_breadcrumbs {
spinlock_t signalers_lock; /* protects the list of signalers */
struct list_head signalers;
struct llist_head signaled_requests;
+ atomic_t signaler_active;
spinlock_t irq_lock; /* protects the interrupt from hardirq context */
struct irq_work irq_work; /* for use from inside irq_lock */
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 192ec4041d7a..9dcd650805fa 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1372,7 +1372,8 @@ static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
* ce->signal_link.
*/
i915_request_cancel_breadcrumb(rq);
- irq_work_sync(&engine->breadcrumbs->irq_work);
+ while (atomic_read(&engine->breadcrumbs->signaler_active))
+ cpu_relax();
}
if (READ_ONCE(ve->request))
--
2.20.1
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^ permalink raw reply related [flat|nested] 38+ messages in thread* [Intel-gfx] [PATCH 09/21] drm/i915/gt: Resubmit the virtual engine on schedule-out
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (6 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 08/21] drm/i915/gt: Shrink the critical section for irq signaling Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 10/21] drm/i915/gt: Simplify virtual engine handling for execlists_hold() Chris Wilson
` (17 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Having recognised that we do not change the sibling until we schedule
out, we can then defer the decision to resubmit the virtual engine from
the unwind of the active queue to scheduling out of the virtual context.
This improves our resilence in virtual engine scheduling, and should
eliminate the rare cases of gem_exec_balance failing.
By keeping the unwind order intact on the local engine, we can preserve
data dependency ordering while doing a preempt-to-busy pass until we
have determined the new ELSP. This means that if we try to timeslice
between a virtual engine and a data-dependent ordinary request, the pair
will maintain their relative ordering and we will avoid the
resubmission, cancelling the timeslicing until further change.
The dilemma though is that we then may end up in a situation where the
'demotion' of the virtual request to an ordinary request in the engine
queue results in filling the ELSP[] with virtual requests instead of
spreading the load across the engines. To compensate for this, we mark
each virtual request and refuse to resubmit a virtual request in the
secondary ELSP slots, thus forcing subsequent virtual requests to be
scheduled out after timeslicing. By delaying the decision until we
schedule out, we will avoid unnecessary resubmission.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2079
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2098
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
.../drm/i915/gt/intel_execlists_submission.c | 122 +++++++++++-------
drivers/gpu/drm/i915/gt/selftest_execlists.c | 2 +-
2 files changed, 77 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9dcd650805fa..b1003486e169 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1082,38 +1082,23 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine)
__i915_request_unsubmit(rq);
- /*
- * Push the request back into the queue for later resubmission.
- * If this request is not native to this physical engine (i.e.
- * it came from a virtual source), push it back onto the virtual
- * engine so that it can be moved across onto another physical
- * engine as load dictates.
- */
- if (likely(rq->execution_mask == engine->mask)) {
- GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
- if (rq_prio(rq) != prio) {
- prio = rq_prio(rq);
- pl = i915_sched_lookup_priolist(engine, prio);
- }
- GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
-
- list_move(&rq->sched.link, pl);
- set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
+ GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
+ if (rq_prio(rq) != prio) {
+ prio = rq_prio(rq);
+ pl = i915_sched_lookup_priolist(engine, prio);
+ }
+ GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
- /* Check in case we rollback so far we wrap [size/2] */
- if (intel_ring_direction(rq->ring,
- rq->tail,
- rq->ring->tail + 8) > 0)
- rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE;
+ list_move(&rq->sched.link, pl);
+ set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
- active = rq;
- } else {
- struct intel_engine_cs *owner = rq->context->engine;
+ /* Check in case we rollback so far we wrap [size/2] */
+ if (intel_ring_direction(rq->ring,
+ rq->tail,
+ rq->ring->tail + 8) > 0)
+ rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE;
- WRITE_ONCE(rq->engine, owner);
- owner->submit_request(rq);
- active = NULL;
- }
+ active = rq;
}
return active;
@@ -1356,6 +1341,20 @@ static inline void execlists_schedule_in(struct i915_request *rq, int idx)
GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
}
+static void
+resubmit_virtual_request(struct i915_request *rq, struct virtual_engine *ve)
+{
+ struct intel_engine_cs *engine = rq->engine;
+
+ spin_lock_irq(&engine->active.lock);
+
+ clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
+ WRITE_ONCE(rq->engine, &ve->base);
+ ve->base.submit_request(rq);
+
+ spin_unlock_irq(&engine->active.lock);
+}
+
static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
{
struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
@@ -1376,6 +1375,16 @@ static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
cpu_relax();
}
+ /*
+ * This engine is now too busy to run this virtual request, so
+ * see if we can find an alternative engine for it to execute on.
+ * Once a request has become bonded to this engine, we treat it the
+ * same as other native request.
+ */
+ if (i915_request_in_priority_queue(rq) &&
+ rq->execution_mask != engine->mask)
+ resubmit_virtual_request(rq, ve);
+
if (READ_ONCE(ve->request))
tasklet_hi_schedule(&ve->base.execlists.tasklet);
}
@@ -1621,6 +1630,20 @@ assert_pending_valid(const struct intel_engine_execlists *execlists,
}
sentinel = i915_request_has_sentinel(rq);
+ /*
+ * We want virtual requests to only be in the first slot so
+ * that they are never stuck behind a hog and can be immediately
+ * transferred onto the next idle engine.
+ */
+ if (rq->execution_mask != engine->mask &&
+ port != execlists->pending) {
+ GEM_TRACE_ERR("%s: virtual engine:%llx not in prime position[%zd]\n",
+ engine->name,
+ ce->timeline->fence_context,
+ port - execlists->pending);
+ return false;
+ }
+
/* Hold tightly onto the lock to prevent concurrent retires! */
if (!spin_trylock_irqsave(&rq->lock, flags))
continue;
@@ -2287,6 +2310,15 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
if (i915_request_has_sentinel(last))
goto done;
+ /*
+ * We avoid submitting virtual requests into
+ * the secondary ports so that we can migrate
+ * the request immediately to another engine
+ * rather than wait for the primary request.
+ */
+ if (rq->execution_mask != engine->mask)
+ goto done;
+
/*
* If GVT overrides us we only ever submit
* port[0], leaving port[1] empty. Note that we
@@ -5086,7 +5118,6 @@ static void virtual_submission_tasklet(unsigned long data)
static void virtual_submit_request(struct i915_request *rq)
{
struct virtual_engine *ve = to_virtual_engine(rq->engine);
- struct i915_request *old;
unsigned long flags;
ENGINE_TRACE(&ve->base, "rq=%llx:%lld\n",
@@ -5097,28 +5128,27 @@ static void virtual_submit_request(struct i915_request *rq)
spin_lock_irqsave(&ve->base.active.lock, flags);
- old = ve->request;
- if (old) { /* background completion event from preempt-to-busy */
- GEM_BUG_ON(!i915_request_completed(old));
- __i915_request_submit(old);
- i915_request_put(old);
- }
-
+ /* By the time we resubmit a request, it may be completed */
if (i915_request_completed(rq)) {
__i915_request_submit(rq);
+ goto unlock;
+ }
- ve->base.execlists.queue_priority_hint = INT_MIN;
- ve->request = NULL;
- } else {
- ve->base.execlists.queue_priority_hint = rq_prio(rq);
- ve->request = i915_request_get(rq);
+ if (ve->request) { /* background completion from preempt-to-busy */
+ GEM_BUG_ON(!i915_request_completed(ve->request));
+ __i915_request_submit(ve->request);
+ i915_request_put(ve->request);
+ }
- GEM_BUG_ON(!list_empty(virtual_queue(ve)));
- list_move_tail(&rq->sched.link, virtual_queue(ve));
+ ve->base.execlists.queue_priority_hint = rq_prio(rq);
+ ve->request = i915_request_get(rq);
- tasklet_hi_schedule(&ve->base.execlists.tasklet);
- }
+ GEM_BUG_ON(!list_empty(virtual_queue(ve)));
+ list_move_tail(&rq->sched.link, virtual_queue(ve));
+ tasklet_hi_schedule(&ve->base.execlists.tasklet);
+
+unlock:
spin_unlock_irqrestore(&ve->base.active.lock, flags);
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 37cb51c3f4f6..fbbd8343d7f6 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -4589,7 +4589,7 @@ static int reset_virtual_engine(struct intel_gt *gt,
spin_lock_irq(&engine->active.lock);
__unwind_incomplete_requests(engine);
spin_unlock_irq(&engine->active.lock);
- GEM_BUG_ON(rq->engine != ve->engine);
+ GEM_BUG_ON(rq->engine != engine);
/* Reset the engine while keeping our active request on hold */
execlists_hold(engine, rq);
--
2.20.1
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^ permalink raw reply related [flat|nested] 38+ messages in thread* [Intel-gfx] [PATCH 10/21] drm/i915/gt: Simplify virtual engine handling for execlists_hold()
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (7 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 09/21] drm/i915/gt: Resubmit the virtual engine on schedule-out Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 11/21] drm/i915/gt: ce->inflight updates are now serialised Chris Wilson
` (16 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Now that the tasklet completely controls scheduling of the requests, and
we postpone scheduling out the old requests, we can keep a hanging
virtual request bound to the engine on which it hung, and remove it from
te queue. On release, it will be returned to the same engine and remain
in its queue until it is scheduled; after which point it will become
eligible for transfer to a sibling. Instead, we could opt to resubmit the
request along the virtual engine on unhold, making it eligible for load
balancing immediately -- but that seems like a pointless optimisation
for a hanging context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../drm/i915/gt/intel_execlists_submission.c | 29 -------------------
1 file changed, 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index b1003486e169..f6dab29b6439 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2833,35 +2833,6 @@ static bool execlists_hold(struct intel_engine_cs *engine,
goto unlock;
}
- if (rq->engine != engine) { /* preempted virtual engine */
- struct virtual_engine *ve = to_virtual_engine(rq->engine);
-
- /*
- * intel_context_inflight() is only protected by virtue
- * of process_csb() being called only by the tasklet (or
- * directly from inside reset while the tasklet is suspended).
- * Assert that neither of those are allowed to run while we
- * poke at the request queues.
- */
- GEM_BUG_ON(!reset_in_progress(&engine->execlists));
-
- /*
- * An unsubmitted request along a virtual engine will
- * remain on the active (this) engine until we are able
- * to process the context switch away (and so mark the
- * context as no longer in flight). That cannot have happened
- * yet, otherwise we would not be hanging!
- */
- spin_lock(&ve->base.active.lock);
- GEM_BUG_ON(intel_context_inflight(rq->context) != engine);
- GEM_BUG_ON(ve->request != rq);
- ve->request = NULL;
- spin_unlock(&ve->base.active.lock);
- i915_request_put(rq);
-
- rq->engine = engine;
- }
-
/*
* Transfer this request onto the hold queue to prevent it
* being resumbitted to HW (and potentially completed) before we have
--
2.20.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 38+ messages in thread* [Intel-gfx] [PATCH 11/21] drm/i915/gt: ce->inflight updates are now serialised
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (8 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 10/21] drm/i915/gt: Simplify virtual engine handling for execlists_hold() Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 12/21] drm/i915/gem: Drop free_work for GEM contexts Chris Wilson
` (15 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Since schedule-in and schedule-out are now both always under the tasklet
bitlock, we can reduce the individual atomic operations to simple
instructions and worry less.
This notably eliminates the race observed with intel_context_inflight in
__engine_unpark().
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2583
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
.../drm/i915/gt/intel_execlists_submission.c | 52 +++++++++----------
1 file changed, 25 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index f6dab29b6439..8285de82c929 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1302,11 +1302,11 @@ __execlists_schedule_in(struct i915_request *rq)
ce->lrc.ccid = ce->tag;
} else {
/* We don't need a strict matching tag, just different values */
- unsigned int tag = ffs(READ_ONCE(engine->context_tag));
+ unsigned int tag = __ffs(engine->context_tag);
- GEM_BUG_ON(tag == 0 || tag >= BITS_PER_LONG);
- clear_bit(tag - 1, &engine->context_tag);
- ce->lrc.ccid = tag << (GEN11_SW_CTX_ID_SHIFT - 32);
+ GEM_BUG_ON(tag >= BITS_PER_LONG);
+ __clear_bit(tag, &engine->context_tag);
+ ce->lrc.ccid = (1 + tag) << (GEN11_SW_CTX_ID_SHIFT - 32);
BUILD_BUG_ON(BITS_PER_LONG > GEN12_MAX_CONTEXT_HW_ID);
}
@@ -1319,6 +1319,8 @@ __execlists_schedule_in(struct i915_request *rq)
execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
intel_engine_context_in(engine);
+ CE_TRACE(ce, "schedule-in, ccid:%x\n", ce->lrc.ccid);
+
return engine;
}
@@ -1330,13 +1332,10 @@ static inline void execlists_schedule_in(struct i915_request *rq, int idx)
GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine));
trace_i915_request_in(rq, idx);
- old = READ_ONCE(ce->inflight);
- do {
- if (!old) {
- WRITE_ONCE(ce->inflight, __execlists_schedule_in(rq));
- break;
- }
- } while (!try_cmpxchg(&ce->inflight, &old, ptr_inc(old)));
+ old = ce->inflight;
+ if (!old)
+ old = __execlists_schedule_in(rq);
+ WRITE_ONCE(ce->inflight, ptr_inc(old));
GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
}
@@ -1389,12 +1388,11 @@ static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
tasklet_hi_schedule(&ve->base.execlists.tasklet);
}
-static inline void
-__execlists_schedule_out(struct i915_request *rq,
- struct intel_engine_cs * const engine,
- unsigned int ccid)
+static inline void __execlists_schedule_out(struct i915_request *rq)
{
struct intel_context * const ce = rq->context;
+ struct intel_engine_cs * const engine = rq->engine;
+ unsigned int ccid;
/*
* NB process_csb() is not under the engine->active.lock and hence
@@ -1402,6 +1400,8 @@ __execlists_schedule_out(struct i915_request *rq,
* refrain from doing non-trivial work here.
*/
+ CE_TRACE(ce, "schedule-out, ccid:%x\n", ce->lrc.ccid);
+
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
execlists_check_context(ce, engine, "after");
@@ -1413,12 +1413,13 @@ __execlists_schedule_out(struct i915_request *rq,
i915_request_completed(rq))
intel_engine_add_retire(engine, ce->timeline);
+ ccid = ce->lrc.ccid;
ccid >>= GEN11_SW_CTX_ID_SHIFT - 32;
ccid &= GEN12_MAX_CONTEXT_HW_ID;
if (ccid < BITS_PER_LONG) {
GEM_BUG_ON(ccid == 0);
GEM_BUG_ON(test_bit(ccid - 1, &engine->context_tag));
- set_bit(ccid - 1, &engine->context_tag);
+ __set_bit(ccid - 1, &engine->context_tag);
}
intel_context_update_runtime(ce);
@@ -1439,26 +1440,23 @@ __execlists_schedule_out(struct i915_request *rq,
*/
if (ce->engine != engine)
kick_siblings(rq, ce);
-
- intel_context_put(ce);
}
static inline void
execlists_schedule_out(struct i915_request *rq)
{
struct intel_context * const ce = rq->context;
- struct intel_engine_cs *cur, *old;
- u32 ccid;
trace_i915_request_out(rq);
- ccid = rq->context->lrc.ccid;
- old = READ_ONCE(ce->inflight);
- do
- cur = ptr_unmask_bits(old, 2) ? ptr_dec(old) : NULL;
- while (!try_cmpxchg(&ce->inflight, &old, cur));
- if (!cur)
- __execlists_schedule_out(rq, old, ccid);
+ GEM_BUG_ON(!ce->inflight);
+ ce->inflight = ptr_dec(ce->inflight);
+ if (!intel_context_inflight_count(ce)) {
+ GEM_BUG_ON(ce->inflight != rq->engine);
+ __execlists_schedule_out(rq);
+ WRITE_ONCE(ce->inflight, NULL);
+ intel_context_put(ce);
+ }
i915_request_put(rq);
}
--
2.20.1
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^ permalink raw reply related [flat|nested] 38+ messages in thread* [Intel-gfx] [PATCH 12/21] drm/i915/gem: Drop free_work for GEM contexts
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (9 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 11/21] drm/i915/gt: ce->inflight updates are now serialised Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 18:50 ` Matthew Brost
2020-12-10 8:02 ` [Intel-gfx] [PATCH 13/21] drm/i915/gt: Track the overall awake/busy time Chris Wilson
` (14 subsequent siblings)
25 siblings, 1 reply; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
The free_list and worker was introduced in commit 5f09a9c8ab6b ("drm/i915:
Allow contexts to be unreferenced locklessly"), but subsequently made
redundant by the removal of the last sleeping lock in commit 2935ed5339c4
("drm/i915: Remove logical HW ID"). As we can now free the GEM context
immediately from any context, remove the deferral of the free_list
v2: Lift removing the context from the global list into close().
Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 +++----------------
drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 -
.../gpu/drm/i915/gem/i915_gem_context_types.h | 1 -
drivers/gpu/drm/i915/i915_drv.h | 3 -
drivers/gpu/drm/i915/i915_gem.c | 2 -
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 -
6 files changed, 8 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ad136d009d9b..738a07b3583c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -334,13 +334,12 @@ static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
return e;
}
-static void i915_gem_context_free(struct i915_gem_context *ctx)
+void i915_gem_context_release(struct kref *ref)
{
- GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
+ struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
- spin_lock(&ctx->i915->gem.contexts.lock);
- list_del(&ctx->link);
- spin_unlock(&ctx->i915->gem.contexts.lock);
+ trace_i915_context_free(ctx);
+ GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
mutex_destroy(&ctx->engines_mutex);
mutex_destroy(&ctx->lut_mutex);
@@ -354,37 +353,6 @@ static void i915_gem_context_free(struct i915_gem_context *ctx)
kfree_rcu(ctx, rcu);
}
-static void contexts_free_all(struct llist_node *list)
-{
- struct i915_gem_context *ctx, *cn;
-
- llist_for_each_entry_safe(ctx, cn, list, free_link)
- i915_gem_context_free(ctx);
-}
-
-static void contexts_flush_free(struct i915_gem_contexts *gc)
-{
- contexts_free_all(llist_del_all(&gc->free_list));
-}
-
-static void contexts_free_worker(struct work_struct *work)
-{
- struct i915_gem_contexts *gc =
- container_of(work, typeof(*gc), free_work);
-
- contexts_flush_free(gc);
-}
-
-void i915_gem_context_release(struct kref *ref)
-{
- struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
- struct i915_gem_contexts *gc = &ctx->i915->gem.contexts;
-
- trace_i915_context_free(ctx);
- if (llist_add(&ctx->free_link, &gc->free_list))
- schedule_work(&gc->free_work);
-}
-
static inline struct i915_gem_engines *
__context_engines_static(const struct i915_gem_context *ctx)
{
@@ -633,6 +601,10 @@ static void context_close(struct i915_gem_context *ctx)
*/
lut_close(ctx);
+ spin_lock(&ctx->i915->gem.contexts.lock);
+ list_del(&ctx->link);
+ spin_unlock(&ctx->i915->gem.contexts.lock);
+
mutex_unlock(&ctx->mutex);
/*
@@ -850,9 +822,6 @@ i915_gem_create_context(struct drm_i915_private *i915, unsigned int flags)
!HAS_EXECLISTS(i915))
return ERR_PTR(-EINVAL);
- /* Reap the stale contexts */
- contexts_flush_free(&i915->gem.contexts);
-
ctx = __create_context(i915);
if (IS_ERR(ctx))
return ctx;
@@ -897,9 +866,6 @@ static void init_contexts(struct i915_gem_contexts *gc)
{
spin_lock_init(&gc->lock);
INIT_LIST_HEAD(&gc->list);
-
- INIT_WORK(&gc->free_work, contexts_free_worker);
- init_llist_head(&gc->free_list);
}
void i915_gem_init__contexts(struct drm_i915_private *i915)
@@ -907,12 +873,6 @@ void i915_gem_init__contexts(struct drm_i915_private *i915)
init_contexts(&i915->gem.contexts);
}
-void i915_gem_driver_release__contexts(struct drm_i915_private *i915)
-{
- flush_work(&i915->gem.contexts.free_work);
- rcu_barrier(); /* and flush the left over RCU frees */
-}
-
static int gem_context_register(struct i915_gem_context *ctx,
struct drm_i915_file_private *fpriv,
u32 *id)
@@ -986,7 +946,6 @@ int i915_gem_context_open(struct drm_i915_private *i915,
void i915_gem_context_close(struct drm_file *file)
{
struct drm_i915_file_private *file_priv = file->driver_priv;
- struct drm_i915_private *i915 = file_priv->dev_priv;
struct i915_address_space *vm;
struct i915_gem_context *ctx;
unsigned long idx;
@@ -998,8 +957,6 @@ void i915_gem_context_close(struct drm_file *file)
xa_for_each(&file_priv->vm_xa, idx, vm)
i915_vm_put(vm);
xa_destroy(&file_priv->vm_xa);
-
- contexts_flush_free(&i915->gem.contexts);
}
int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index a133f92bbedb..b5c908f3f4f2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -110,7 +110,6 @@ i915_gem_context_clear_user_engines(struct i915_gem_context *ctx)
/* i915_gem_context.c */
void i915_gem_init__contexts(struct drm_i915_private *i915);
-void i915_gem_driver_release__contexts(struct drm_i915_private *i915);
int i915_gem_context_open(struct drm_i915_private *i915,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index ae14ca24a11f..1449f54924e0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -108,7 +108,6 @@ struct i915_gem_context {
/** link: place with &drm_i915_private.context_list */
struct list_head link;
- struct llist_node free_link;
/**
* @ref: reference count
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5d04b282c060..c2d0156e8a5d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1172,9 +1172,6 @@ struct drm_i915_private {
struct i915_gem_contexts {
spinlock_t lock; /* locks list */
struct list_head list;
-
- struct llist_head free_list;
- struct work_struct free_work;
} contexts;
/*
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 58276694c848..17a4636ee542 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1207,8 +1207,6 @@ void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
void i915_gem_driver_release(struct drm_i915_private *dev_priv)
{
- i915_gem_driver_release__contexts(dev_priv);
-
intel_gt_driver_release(&dev_priv->gt);
intel_wa_list_free(&dev_priv->gt_wa_list);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index e946bd2087d8..0188f877cab2 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -64,8 +64,6 @@ static void mock_device_release(struct drm_device *dev)
mock_device_flush(i915);
intel_gt_driver_remove(&i915->gt);
- i915_gem_driver_release__contexts(i915);
-
i915_gem_drain_workqueue(i915);
i915_gem_drain_freed_objects(i915);
--
2.20.1
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 38+ messages in thread* Re: [Intel-gfx] [PATCH 12/21] drm/i915/gem: Drop free_work for GEM contexts
2020-12-10 8:02 ` [Intel-gfx] [PATCH 12/21] drm/i915/gem: Drop free_work for GEM contexts Chris Wilson
@ 2020-12-10 18:50 ` Matthew Brost
0 siblings, 0 replies; 38+ messages in thread
From: Matthew Brost @ 2020-12-10 18:50 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Dec 10, 2020 at 08:02:31AM +0000, Chris Wilson wrote:
> The free_list and worker was introduced in commit 5f09a9c8ab6b ("drm/i915:
> Allow contexts to be unreferenced locklessly"), but subsequently made
> redundant by the removal of the last sleeping lock in commit 2935ed5339c4
> ("drm/i915: Remove logical HW ID"). As we can now free the GEM context
> immediately from any context, remove the deferral of the free_list
>
> v2: Lift removing the context from the global list into close().
>
> Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 +++----------------
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 -
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 1 -
> drivers/gpu/drm/i915/i915_drv.h | 3 -
> drivers/gpu/drm/i915/i915_gem.c | 2 -
> .../gpu/drm/i915/selftests/mock_gem_device.c | 2 -
> 6 files changed, 8 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index ad136d009d9b..738a07b3583c 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -334,13 +334,12 @@ static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
> return e;
> }
>
> -static void i915_gem_context_free(struct i915_gem_context *ctx)
> +void i915_gem_context_release(struct kref *ref)
> {
> - GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
> + struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
>
> - spin_lock(&ctx->i915->gem.contexts.lock);
> - list_del(&ctx->link);
> - spin_unlock(&ctx->i915->gem.contexts.lock);
> + trace_i915_context_free(ctx);
> + GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
>
> mutex_destroy(&ctx->engines_mutex);
> mutex_destroy(&ctx->lut_mutex);
> @@ -354,37 +353,6 @@ static void i915_gem_context_free(struct i915_gem_context *ctx)
> kfree_rcu(ctx, rcu);
> }
>
> -static void contexts_free_all(struct llist_node *list)
> -{
> - struct i915_gem_context *ctx, *cn;
> -
> - llist_for_each_entry_safe(ctx, cn, list, free_link)
> - i915_gem_context_free(ctx);
> -}
> -
> -static void contexts_flush_free(struct i915_gem_contexts *gc)
> -{
> - contexts_free_all(llist_del_all(&gc->free_list));
> -}
> -
> -static void contexts_free_worker(struct work_struct *work)
> -{
> - struct i915_gem_contexts *gc =
> - container_of(work, typeof(*gc), free_work);
> -
> - contexts_flush_free(gc);
> -}
> -
> -void i915_gem_context_release(struct kref *ref)
> -{
> - struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
> - struct i915_gem_contexts *gc = &ctx->i915->gem.contexts;
> -
> - trace_i915_context_free(ctx);
> - if (llist_add(&ctx->free_link, &gc->free_list))
> - schedule_work(&gc->free_work);
> -}
> -
> static inline struct i915_gem_engines *
> __context_engines_static(const struct i915_gem_context *ctx)
> {
> @@ -633,6 +601,10 @@ static void context_close(struct i915_gem_context *ctx)
> */
> lut_close(ctx);
>
> + spin_lock(&ctx->i915->gem.contexts.lock);
> + list_del(&ctx->link);
> + spin_unlock(&ctx->i915->gem.contexts.lock);
> +
> mutex_unlock(&ctx->mutex);
>
> /*
> @@ -850,9 +822,6 @@ i915_gem_create_context(struct drm_i915_private *i915, unsigned int flags)
> !HAS_EXECLISTS(i915))
> return ERR_PTR(-EINVAL);
>
> - /* Reap the stale contexts */
> - contexts_flush_free(&i915->gem.contexts);
> -
> ctx = __create_context(i915);
> if (IS_ERR(ctx))
> return ctx;
> @@ -897,9 +866,6 @@ static void init_contexts(struct i915_gem_contexts *gc)
> {
> spin_lock_init(&gc->lock);
> INIT_LIST_HEAD(&gc->list);
> -
> - INIT_WORK(&gc->free_work, contexts_free_worker);
> - init_llist_head(&gc->free_list);
> }
>
> void i915_gem_init__contexts(struct drm_i915_private *i915)
> @@ -907,12 +873,6 @@ void i915_gem_init__contexts(struct drm_i915_private *i915)
> init_contexts(&i915->gem.contexts);
> }
>
> -void i915_gem_driver_release__contexts(struct drm_i915_private *i915)
> -{
> - flush_work(&i915->gem.contexts.free_work);
> - rcu_barrier(); /* and flush the left over RCU frees */
> -}
> -
> static int gem_context_register(struct i915_gem_context *ctx,
> struct drm_i915_file_private *fpriv,
> u32 *id)
> @@ -986,7 +946,6 @@ int i915_gem_context_open(struct drm_i915_private *i915,
> void i915_gem_context_close(struct drm_file *file)
> {
> struct drm_i915_file_private *file_priv = file->driver_priv;
> - struct drm_i915_private *i915 = file_priv->dev_priv;
> struct i915_address_space *vm;
> struct i915_gem_context *ctx;
> unsigned long idx;
> @@ -998,8 +957,6 @@ void i915_gem_context_close(struct drm_file *file)
> xa_for_each(&file_priv->vm_xa, idx, vm)
> i915_vm_put(vm);
> xa_destroy(&file_priv->vm_xa);
> -
> - contexts_flush_free(&i915->gem.contexts);
> }
>
> int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index a133f92bbedb..b5c908f3f4f2 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -110,7 +110,6 @@ i915_gem_context_clear_user_engines(struct i915_gem_context *ctx)
>
> /* i915_gem_context.c */
> void i915_gem_init__contexts(struct drm_i915_private *i915);
> -void i915_gem_driver_release__contexts(struct drm_i915_private *i915);
>
> int i915_gem_context_open(struct drm_i915_private *i915,
> struct drm_file *file);
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index ae14ca24a11f..1449f54924e0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -108,7 +108,6 @@ struct i915_gem_context {
>
> /** link: place with &drm_i915_private.context_list */
> struct list_head link;
> - struct llist_node free_link;
>
> /**
> * @ref: reference count
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5d04b282c060..c2d0156e8a5d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1172,9 +1172,6 @@ struct drm_i915_private {
> struct i915_gem_contexts {
> spinlock_t lock; /* locks list */
> struct list_head list;
> -
> - struct llist_head free_list;
> - struct work_struct free_work;
> } contexts;
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 58276694c848..17a4636ee542 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1207,8 +1207,6 @@ void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
>
> void i915_gem_driver_release(struct drm_i915_private *dev_priv)
> {
> - i915_gem_driver_release__contexts(dev_priv);
> -
> intel_gt_driver_release(&dev_priv->gt);
>
> intel_wa_list_free(&dev_priv->gt_wa_list);
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index e946bd2087d8..0188f877cab2 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -64,8 +64,6 @@ static void mock_device_release(struct drm_device *dev)
> mock_device_flush(i915);
> intel_gt_driver_remove(&i915->gt);
>
> - i915_gem_driver_release__contexts(i915);
> -
> i915_gem_drain_workqueue(i915);
> i915_gem_drain_freed_objects(i915);
>
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 13/21] drm/i915/gt: Track the overall awake/busy time
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (10 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 12/21] drm/i915/gem: Drop free_work for GEM contexts Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 14/21] drm/i915: Encode fence specific waitqueue behaviour into the wait.flags Chris Wilson
` (13 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Since we wake the GT up before executing a request, and go to sleep as
soon as it is retired, the GT wake time not only represents how long the
device is powered up, but also provides a summary, albeit an overestimate,
of the device runtime (i.e. the rc0 time to compare against rc6 time).
v2: s/busy/awake/
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 5 ++-
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 49 ++++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 2 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 24 ++++++++++++
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++-
drivers/gpu/drm/i915/i915_pmu.c | 6 +++
include/uapi/drm/i915_drm.h | 1 +
7 files changed, 89 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 174a24553322..8975717ace06 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -11,6 +11,7 @@
#include "i915_drv.h"
#include "intel_gt.h"
#include "intel_gt_clock_utils.h"
+#include "intel_gt_pm.h"
#include "intel_llc.h"
#include "intel_rc6.h"
#include "intel_rps.h"
@@ -558,7 +559,9 @@ static int rps_boost_show(struct seq_file *m, void *data)
seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
- seq_printf(m, "GPU busy? %s\n", yesno(gt->awake));
+ seq_printf(m, "GPU busy? %s, %llums\n",
+ yesno(gt->awake),
+ ktime_to_ms(intel_gt_get_awake_time(gt)));
seq_printf(m, "Boosts outstanding? %d\n",
atomic_read(&rps->num_waiters));
seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 274aa0dd7050..c94e8ac884eb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -39,6 +39,28 @@ static void user_forcewake(struct intel_gt *gt, bool suspend)
intel_gt_pm_put(gt);
}
+static void runtime_begin(struct intel_gt *gt)
+{
+ local_irq_disable();
+ write_seqcount_begin(>->stats.lock);
+ gt->stats.start = ktime_get();
+ gt->stats.active = true;
+ write_seqcount_end(>->stats.lock);
+ local_irq_enable();
+}
+
+static void runtime_end(struct intel_gt *gt)
+{
+ local_irq_disable();
+ write_seqcount_begin(>->stats.lock);
+ gt->stats.active = false;
+ gt->stats.total =
+ ktime_add(gt->stats.total,
+ ktime_sub(ktime_get(), gt->stats.start));
+ write_seqcount_end(>->stats.lock);
+ local_irq_enable();
+}
+
static int __gt_unpark(struct intel_wakeref *wf)
{
struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref);
@@ -67,6 +89,7 @@ static int __gt_unpark(struct intel_wakeref *wf)
i915_pmu_gt_unparked(i915);
intel_gt_unpark_requests(gt);
+ runtime_begin(gt);
return 0;
}
@@ -79,6 +102,7 @@ static int __gt_park(struct intel_wakeref *wf)
GT_TRACE(gt, "\n");
+ runtime_end(gt);
intel_gt_park_requests(gt);
i915_vma_parked(gt);
@@ -106,6 +130,7 @@ static const struct intel_wakeref_ops wf_ops = {
void intel_gt_pm_init_early(struct intel_gt *gt)
{
intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
+ seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
}
void intel_gt_pm_init(struct intel_gt *gt)
@@ -339,6 +364,30 @@ int intel_gt_runtime_resume(struct intel_gt *gt)
return intel_uc_runtime_resume(>->uc);
}
+static ktime_t __intel_gt_get_awake_time(const struct intel_gt *gt)
+{
+ ktime_t total = gt->stats.total;
+
+ if (gt->stats.active)
+ total = ktime_add(total,
+ ktime_sub(ktime_get(), gt->stats.start));
+
+ return total;
+}
+
+ktime_t intel_gt_get_awake_time(const struct intel_gt *gt)
+{
+ unsigned int seq;
+ ktime_t total;
+
+ do {
+ seq = read_seqcount_begin(>->stats.lock);
+ total = __intel_gt_get_awake_time(gt);
+ } while (read_seqcount_retry(>->stats.lock, seq));
+
+ return total;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_gt_pm.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index 60f0e2fbe55c..63846a856e7e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -58,6 +58,8 @@ int intel_gt_resume(struct intel_gt *gt);
void intel_gt_runtime_suspend(struct intel_gt *gt);
int intel_gt_runtime_resume(struct intel_gt *gt);
+ktime_t intel_gt_get_awake_time(const struct intel_gt *gt);
+
static inline bool is_mock_gt(const struct intel_gt *gt)
{
return I915_SELFTEST_ONLY(gt->awake == -ENODEV);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6d39a4a11bf3..c7bde529feab 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -87,6 +87,30 @@ struct intel_gt {
u32 pm_guc_events;
+ struct {
+ bool active;
+
+ /**
+ * @lock: Lock protecting the below fields.
+ */
+ seqcount_mutex_t lock;
+
+ /**
+ * @total: Total time this engine was busy.
+ *
+ * Accumulated time not counting the most recent block in cases
+ * where engine is currently busy (active > 0).
+ */
+ ktime_t total;
+
+ /**
+ * @start: Timestamp of the last idle to active transition.
+ *
+ * Idle is defined as active == 0, active is active > 0.
+ */
+ ktime_t start;
+ } stats;
+
struct intel_engine_cs *engine[I915_NUM_ENGINES];
struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
[MAX_ENGINE_INSTANCE + 1];
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f48df3545e39..c72160e3702f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -858,9 +858,10 @@ static int i915_engine_info(struct seq_file *m, void *unused)
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
- seq_printf(m, "GT awake? %s [%d]\n",
+ seq_printf(m, "GT awake? %s [%d], %llums\n",
yesno(i915->gt.awake),
- atomic_read(&i915->gt.wakeref.count));
+ atomic_read(&i915->gt.wakeref.count),
+ ktime_to_ms(intel_gt_get_awake_time(&i915->gt)));
seq_printf(m, "CS timestamp frequency: %u Hz\n",
RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 97bb4aaa5236..fc762eec9601 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -516,6 +516,8 @@ config_status(struct drm_i915_private *i915, u64 config)
if (!HAS_RC6(i915))
return -ENODEV;
break;
+ case I915_PMU_GT_AWAKE:
+ break;
default:
return -ENOENT;
}
@@ -623,6 +625,9 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
case I915_PMU_RC6_RESIDENCY:
val = get_rc6(&i915->gt);
break;
+ case I915_PMU_GT_AWAKE:
+ val = ktime_to_ns(intel_gt_get_awake_time(&i915->gt));
+ break;
}
}
@@ -938,6 +943,7 @@ create_event_attributes(struct i915_pmu *pmu)
__event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency", "M"),
__event(I915_PMU_INTERRUPTS, "interrupts", NULL),
__event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"),
+ __event(I915_PMU_GT_AWAKE, "awake", "ns"),
};
static const struct {
enum drm_i915_pmu_engine_sample sample;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6edcb2b6c708..04abd1ee89bf 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -177,6 +177,7 @@ enum drm_i915_pmu_engine_sample {
#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
+#define I915_PMU_GT_AWAKE __I915_PMU_OTHER(4)
#define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 38+ messages in thread* [Intel-gfx] [PATCH 14/21] drm/i915: Encode fence specific waitqueue behaviour into the wait.flags
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (11 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 13/21] drm/i915/gt: Track the overall awake/busy time Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 15/21] drm/i915/gt: Track all timelines created using the HWSP Chris Wilson
` (12 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Use the wait_queue_entry.flags to denote the special fence behaviour
(flattening continuations along fence chains, and for propagating
errors) rather than trying to detect ordinary waiters by their
functions.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_sw_fence.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c
index 038d4c6884c5..2744558f3050 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -18,10 +18,15 @@
#define I915_SW_FENCE_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
#endif
-#define I915_SW_FENCE_FLAG_ALLOC BIT(3) /* after WQ_FLAG_* for safety */
-
static DEFINE_SPINLOCK(i915_sw_fence_lock);
+#define WQ_FLAG_BITS \
+ BITS_PER_TYPE(typeof_member(struct wait_queue_entry, flags))
+
+/* after WQ_FLAG_* for safety */
+#define I915_SW_FENCE_FLAG_FENCE BIT(WQ_FLAG_BITS - 1)
+#define I915_SW_FENCE_FLAG_ALLOC BIT(WQ_FLAG_BITS - 2)
+
enum {
DEBUG_FENCE_IDLE = 0,
DEBUG_FENCE_NOTIFY,
@@ -154,10 +159,10 @@ static void __i915_sw_fence_wake_up_all(struct i915_sw_fence *fence,
spin_lock_irqsave_nested(&x->lock, flags, 1 + !!continuation);
if (continuation) {
list_for_each_entry_safe(pos, next, &x->head, entry) {
- if (pos->func == autoremove_wake_function)
- pos->func(pos, TASK_NORMAL, 0, continuation);
- else
+ if (pos->flags & I915_SW_FENCE_FLAG_FENCE)
list_move_tail(&pos->entry, continuation);
+ else
+ pos->func(pos, TASK_NORMAL, 0, continuation);
}
} else {
LIST_HEAD(extra);
@@ -166,9 +171,9 @@ static void __i915_sw_fence_wake_up_all(struct i915_sw_fence *fence,
list_for_each_entry_safe(pos, next, &x->head, entry) {
int wake_flags;
- wake_flags = fence->error;
- if (pos->func == autoremove_wake_function)
- wake_flags = 0;
+ wake_flags = 0;
+ if (pos->flags & I915_SW_FENCE_FLAG_FENCE)
+ wake_flags = fence->error;
pos->func(pos, TASK_NORMAL, wake_flags, &extra);
}
@@ -332,8 +337,8 @@ static int __i915_sw_fence_await_sw_fence(struct i915_sw_fence *fence,
struct i915_sw_fence *signaler,
wait_queue_entry_t *wq, gfp_t gfp)
{
+ unsigned int pending;
unsigned long flags;
- int pending;
debug_fence_assert(fence);
might_sleep_if(gfpflags_allow_blocking(gfp));
@@ -349,7 +354,7 @@ static int __i915_sw_fence_await_sw_fence(struct i915_sw_fence *fence,
if (unlikely(i915_sw_fence_check_if_after(fence, signaler)))
return -EINVAL;
- pending = 0;
+ pending = I915_SW_FENCE_FLAG_FENCE;
if (!wq) {
wq = kmalloc(sizeof(*wq), gfp);
if (!wq) {
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 38+ messages in thread* [Intel-gfx] [PATCH 15/21] drm/i915/gt: Track all timelines created using the HWSP
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (12 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 14/21] drm/i915: Encode fence specific waitqueue behaviour into the wait.flags Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 18:28 ` Matthew Brost
2020-12-10 8:02 ` [Intel-gfx] [PATCH 16/21] drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb Chris Wilson
` (11 subsequent siblings)
25 siblings, 1 reply; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
We assume that the contents of the HWSP are lost across suspend, and so
upon resume we must restore critical values such as the timeline seqno.
Keep track of every timeline allocated that uses the HWSP as its storage
and so we can then reset all seqno values by walking that list.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 ++++-
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 6 ++++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
.../drm/i915/gt/intel_execlists_submission.c | 11 ++++--
.../gpu/drm/i915/gt/intel_ring_submission.c | 35 +++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_timeline.h | 13 +++++--
.../gpu/drm/i915/gt/intel_timeline_types.h | 2 ++
7 files changed, 71 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 71bd052628f4..6c08e74edcae 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -648,6 +648,8 @@ static int init_status_page(struct intel_engine_cs *engine)
void *vaddr;
int ret;
+ INIT_LIST_HEAD(&engine->status_page.timelines);
+
/*
* Though the HWS register does support 36bit addresses, historically
* we have had hangs and corruption reported due to wild writes if
@@ -936,6 +938,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
fput(engine->default_state);
if (engine->kernel_context) {
+ list_del(&engine->kernel_context->timeline->engine_link);
intel_context_unpin(engine->kernel_context);
intel_context_put(engine->kernel_context);
}
@@ -1281,8 +1284,12 @@ void intel_engines_reset_default_submission(struct intel_gt *gt)
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine(engine, gt, id)
+ for_each_engine(engine, gt, id) {
+ if (engine->sanitize)
+ engine->sanitize(engine);
+
engine->set_default_submission(engine);
+ }
}
bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 99574378047f..1e5bad0b9a82 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -60,6 +60,12 @@ static int __engine_unpark(struct intel_wakeref *wf)
/* Scrub the context image after our loss of control */
ce->ops->reset(ce);
+
+ CE_TRACE(ce, "reset { seqno:%x, *hwsp:%x, ring:%x }\n",
+ ce->timeline->seqno,
+ READ_ONCE(*ce->timeline->hwsp_seqno),
+ ce->ring->emit);
+ GEM_BUG_ON(ce->timeline->seqno != *ce->timeline->hwsp_seqno);
}
if (engine->unpark)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index e71eef157231..c28f4e190fe6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -68,6 +68,7 @@ typedef u8 intel_engine_mask_t;
#define ALL_ENGINES ((intel_engine_mask_t)~0ul)
struct intel_hw_status_page {
+ struct list_head timelines;
struct i915_vma *vma;
u32 *addr;
};
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 8285de82c929..8bff0559a6a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3508,7 +3508,6 @@ static int execlists_context_alloc(struct intel_context *ce)
static void execlists_context_reset(struct intel_context *ce)
{
- CE_TRACE(ce, "reset\n");
GEM_BUG_ON(!intel_context_is_pinned(ce));
intel_ring_reset(ce->ring, ce->ring->emit);
@@ -3985,6 +3984,14 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
GEM_BUG_ON(READ_ONCE(*execlists->csb_write) != reset_value);
}
+static void sanitize_hwsp(struct intel_engine_cs *engine)
+{
+ struct intel_timeline *tl;
+
+ list_for_each_entry(tl, &engine->status_page.timelines, engine_link)
+ intel_timeline_reset_seqno(tl);
+}
+
static void execlists_sanitize(struct intel_engine_cs *engine)
{
GEM_BUG_ON(execlists_active(&engine->execlists));
@@ -4008,7 +4015,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
* that may be lost on resume/initialisation, and so we need to
* reset the value in the HWSP.
*/
- intel_timeline_reset_seqno(engine->kernel_context->timeline);
+ sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 1959e3e5b8e9..3848d40ead89 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -321,6 +321,39 @@ static int xcs_resume(struct intel_engine_cs *engine)
return ret;
}
+static void sanitize_hwsp(struct intel_engine_cs *engine)
+{
+ struct intel_timeline *tl;
+
+ list_for_each_entry(tl, &engine->status_page.timelines, engine_link)
+ intel_timeline_reset_seqno(tl);
+}
+
+static void xcs_sanitize(struct intel_engine_cs *engine)
+{
+ /*
+ * Poison residual state on resume, in case the suspend didn't!
+ *
+ * We have to assume that across suspend/resume (or other loss
+ * of control) that the contents of our pinned buffers has been
+ * lost, replaced by garbage. Since this doesn't always happen,
+ * let's poison such state so that we more quickly spot when
+ * we falsely assume it has been preserved.
+ */
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+ memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE);
+
+ /*
+ * The kernel_context HWSP is stored in the status_page. As above,
+ * that may be lost on resume/initialisation, and so we need to
+ * reset the value in the HWSP.
+ */
+ sanitize_hwsp(engine);
+
+ /* And scrub the dirty cachelines for the HWSP */
+ clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+}
+
static void reset_prepare(struct intel_engine_cs *engine)
{
struct intel_uncore *uncore = engine->uncore;
@@ -1070,6 +1103,8 @@ static void setup_common(struct intel_engine_cs *engine)
setup_irq(engine);
engine->resume = xcs_resume;
+ engine->sanitize = xcs_sanitize;
+
engine->reset.prepare = reset_prepare;
engine->reset.rewind = reset_rewind;
engine->reset.cancel = reset_cancel;
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h
index 634acebd0c4b..1ee680d31801 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
@@ -48,9 +48,16 @@ static inline struct intel_timeline *
intel_timeline_create_from_engine(struct intel_engine_cs *engine,
unsigned int offset)
{
- return __intel_timeline_create(engine->gt,
- engine->status_page.vma,
- offset);
+ struct intel_timeline *tl;
+
+ tl = __intel_timeline_create(engine->gt,
+ engine->status_page.vma,
+ offset);
+ if (IS_ERR(tl))
+ return tl;
+
+ list_add_tail(&tl->engine_link, &engine->status_page.timelines);
+ return tl;
}
static inline struct intel_timeline *
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
index 4474f487f589..e360f50706bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
@@ -84,6 +84,8 @@ struct intel_timeline {
struct list_head link;
struct intel_gt *gt;
+ struct list_head engine_link;
+
struct kref kref;
struct rcu_head rcu;
};
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 38+ messages in thread* Re: [Intel-gfx] [PATCH 15/21] drm/i915/gt: Track all timelines created using the HWSP
2020-12-10 8:02 ` [Intel-gfx] [PATCH 15/21] drm/i915/gt: Track all timelines created using the HWSP Chris Wilson
@ 2020-12-10 18:28 ` Matthew Brost
0 siblings, 0 replies; 38+ messages in thread
From: Matthew Brost @ 2020-12-10 18:28 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Dec 10, 2020 at 08:02:34AM +0000, Chris Wilson wrote:
> We assume that the contents of the HWSP are lost across suspend, and so
> upon resume we must restore critical values such as the timeline seqno.
> Keep track of every timeline allocated that uses the HWSP as its storage
> and so we can then reset all seqno values by walking that list.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 ++++-
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 6 ++++
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
> .../drm/i915/gt/intel_execlists_submission.c | 11 ++++--
> .../gpu/drm/i915/gt/intel_ring_submission.c | 35 +++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_timeline.h | 13 +++++--
> .../gpu/drm/i915/gt/intel_timeline_types.h | 2 ++
> 7 files changed, 71 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 71bd052628f4..6c08e74edcae 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -648,6 +648,8 @@ static int init_status_page(struct intel_engine_cs *engine)
> void *vaddr;
> int ret;
>
> + INIT_LIST_HEAD(&engine->status_page.timelines);
> +
> /*
> * Though the HWS register does support 36bit addresses, historically
> * we have had hangs and corruption reported due to wild writes if
> @@ -936,6 +938,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
> fput(engine->default_state);
>
> if (engine->kernel_context) {
> + list_del(&engine->kernel_context->timeline->engine_link);
> intel_context_unpin(engine->kernel_context);
> intel_context_put(engine->kernel_context);
> }
> @@ -1281,8 +1284,12 @@ void intel_engines_reset_default_submission(struct intel_gt *gt)
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
>
> - for_each_engine(engine, gt, id)
> + for_each_engine(engine, gt, id) {
> + if (engine->sanitize)
> + engine->sanitize(engine);
> +
> engine->set_default_submission(engine);
> + }
> }
>
> bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> index 99574378047f..1e5bad0b9a82 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> @@ -60,6 +60,12 @@ static int __engine_unpark(struct intel_wakeref *wf)
>
> /* Scrub the context image after our loss of control */
> ce->ops->reset(ce);
> +
> + CE_TRACE(ce, "reset { seqno:%x, *hwsp:%x, ring:%x }\n",
> + ce->timeline->seqno,
> + READ_ONCE(*ce->timeline->hwsp_seqno),
> + ce->ring->emit);
> + GEM_BUG_ON(ce->timeline->seqno != *ce->timeline->hwsp_seqno);
> }
>
> if (engine->unpark)
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index e71eef157231..c28f4e190fe6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -68,6 +68,7 @@ typedef u8 intel_engine_mask_t;
> #define ALL_ENGINES ((intel_engine_mask_t)~0ul)
>
> struct intel_hw_status_page {
> + struct list_head timelines;
> struct i915_vma *vma;
> u32 *addr;
> };
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 8285de82c929..8bff0559a6a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3508,7 +3508,6 @@ static int execlists_context_alloc(struct intel_context *ce)
>
> static void execlists_context_reset(struct intel_context *ce)
> {
> - CE_TRACE(ce, "reset\n");
> GEM_BUG_ON(!intel_context_is_pinned(ce));
>
> intel_ring_reset(ce->ring, ce->ring->emit);
> @@ -3985,6 +3984,14 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
> GEM_BUG_ON(READ_ONCE(*execlists->csb_write) != reset_value);
> }
>
> +static void sanitize_hwsp(struct intel_engine_cs *engine)
> +{
> + struct intel_timeline *tl;
> +
> + list_for_each_entry(tl, &engine->status_page.timelines, engine_link)
> + intel_timeline_reset_seqno(tl);
> +}
> +
> static void execlists_sanitize(struct intel_engine_cs *engine)
> {
> GEM_BUG_ON(execlists_active(&engine->execlists));
> @@ -4008,7 +4015,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
> * that may be lost on resume/initialisation, and so we need to
> * reset the value in the HWSP.
> */
> - intel_timeline_reset_seqno(engine->kernel_context->timeline);
> + sanitize_hwsp(engine);
>
> /* And scrub the dirty cachelines for the HWSP */
> clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 1959e3e5b8e9..3848d40ead89 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -321,6 +321,39 @@ static int xcs_resume(struct intel_engine_cs *engine)
> return ret;
> }
>
> +static void sanitize_hwsp(struct intel_engine_cs *engine)
> +{
> + struct intel_timeline *tl;
> +
> + list_for_each_entry(tl, &engine->status_page.timelines, engine_link)
> + intel_timeline_reset_seqno(tl);
> +}
> +
> +static void xcs_sanitize(struct intel_engine_cs *engine)
> +{
> + /*
> + * Poison residual state on resume, in case the suspend didn't!
> + *
> + * We have to assume that across suspend/resume (or other loss
> + * of control) that the contents of our pinned buffers has been
> + * lost, replaced by garbage. Since this doesn't always happen,
> + * let's poison such state so that we more quickly spot when
> + * we falsely assume it has been preserved.
> + */
> + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> + memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE);
> +
> + /*
> + * The kernel_context HWSP is stored in the status_page. As above,
> + * that may be lost on resume/initialisation, and so we need to
> + * reset the value in the HWSP.
> + */
> + sanitize_hwsp(engine);
> +
> + /* And scrub the dirty cachelines for the HWSP */
> + clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
> +}
> +
> static void reset_prepare(struct intel_engine_cs *engine)
> {
> struct intel_uncore *uncore = engine->uncore;
> @@ -1070,6 +1103,8 @@ static void setup_common(struct intel_engine_cs *engine)
> setup_irq(engine);
>
> engine->resume = xcs_resume;
> + engine->sanitize = xcs_sanitize;
> +
> engine->reset.prepare = reset_prepare;
> engine->reset.rewind = reset_rewind;
> engine->reset.cancel = reset_cancel;
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h
> index 634acebd0c4b..1ee680d31801 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.h
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
> @@ -48,9 +48,16 @@ static inline struct intel_timeline *
> intel_timeline_create_from_engine(struct intel_engine_cs *engine,
> unsigned int offset)
> {
> - return __intel_timeline_create(engine->gt,
> - engine->status_page.vma,
> - offset);
> + struct intel_timeline *tl;
> +
> + tl = __intel_timeline_create(engine->gt,
> + engine->status_page.vma,
> + offset);
> + if (IS_ERR(tl))
> + return tl;
> +
> + list_add_tail(&tl->engine_link, &engine->status_page.timelines);
> + return tl;
> }
>
> static inline struct intel_timeline *
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> index 4474f487f589..e360f50706bf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> @@ -84,6 +84,8 @@ struct intel_timeline {
> struct list_head link;
> struct intel_gt *gt;
>
> + struct list_head engine_link;
> +
> struct kref kref;
> struct rcu_head rcu;
> };
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 16/21] drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (13 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 15/21] drm/i915/gt: Track all timelines created using the HWSP Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 17/21] drm/i915/gt: Track timeline GGTT offset separately from subpage offset Chris Wilson
` (10 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
In preparation for removing the has_initial_breadcrumb field, add a
helper function for the existing callers.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_timeline.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_timeline.h | 6 ++++++
drivers/gpu/drm/i915/gt/selftest_timeline.c | 5 +++--
5 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 9c6f0ebfa3cf..ebf043692eef 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -354,7 +354,7 @@ int gen8_emit_init_breadcrumb(struct i915_request *rq)
u32 *cs;
GEM_BUG_ON(i915_request_has_initial_breadcrumb(rq));
- if (!i915_request_timeline(rq)->has_initial_breadcrumb)
+ if (!intel_timeline_has_initial_breadcrumb(i915_request_timeline(rq)))
return 0;
cs = intel_ring_begin(rq, 6);
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 3848d40ead89..23155eeb5d3f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -979,7 +979,7 @@ static int ring_request_alloc(struct i915_request *request)
int ret;
GEM_BUG_ON(!intel_context_is_pinned(request->context));
- GEM_BUG_ON(i915_request_timeline(request)->has_initial_breadcrumb);
+ GEM_BUG_ON(intel_timeline_has_initial_breadcrumb(i915_request_timeline(request)));
/*
* Flush enough space to reduce the likelihood of waiting after
@@ -1304,7 +1304,7 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine)
err = PTR_ERR(timeline);
goto err;
}
- GEM_BUG_ON(timeline->has_initial_breadcrumb);
+ GEM_BUG_ON(intel_timeline_has_initial_breadcrumb(timeline));
err = intel_timeline_pin(timeline, NULL);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 512afacd2bdc..ddc8e1b4f3b8 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -428,14 +428,14 @@ void intel_timeline_exit(struct intel_timeline *tl)
static u32 timeline_advance(struct intel_timeline *tl)
{
GEM_BUG_ON(!atomic_read(&tl->pin_count));
- GEM_BUG_ON(tl->seqno & tl->has_initial_breadcrumb);
+ GEM_BUG_ON(tl->seqno & intel_timeline_has_initial_breadcrumb(tl));
- return tl->seqno += 1 + tl->has_initial_breadcrumb;
+ return tl->seqno += 1 + intel_timeline_has_initial_breadcrumb(tl);
}
static void timeline_rollback(struct intel_timeline *tl)
{
- tl->seqno -= 1 + tl->has_initial_breadcrumb;
+ tl->seqno -= 1 + intel_timeline_has_initial_breadcrumb(tl);
}
static noinline int
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h
index 1ee680d31801..deb71a8dbd43 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
@@ -73,6 +73,12 @@ static inline void intel_timeline_put(struct intel_timeline *timeline)
kref_put(&timeline->kref, __intel_timeline_free);
}
+static inline bool
+intel_timeline_has_initial_breadcrumb(const struct intel_timeline *tl)
+{
+ return tl->has_initial_breadcrumb;
+}
+
static inline int __intel_timeline_sync_set(struct intel_timeline *tl,
u64 context, u32 seqno)
{
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index e4285d5a0360..a6ff9d1605aa 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -665,7 +665,7 @@ static int live_hwsp_wrap(void *arg)
if (IS_ERR(tl))
return PTR_ERR(tl);
- if (!tl->has_initial_breadcrumb || !tl->hwsp_cacheline)
+ if (!intel_timeline_has_initial_breadcrumb(tl) || !tl->hwsp_cacheline)
goto out_free;
err = intel_timeline_pin(tl, NULL);
@@ -1234,7 +1234,8 @@ static int live_hwsp_rollover_user(void *arg)
goto out;
tl = ce->timeline;
- if (!tl->has_initial_breadcrumb || !tl->hwsp_cacheline)
+ if (!intel_timeline_has_initial_breadcrumb(tl) ||
+ !tl->hwsp_cacheline)
goto out;
timeline_rollback(tl);
--
2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 38+ messages in thread* [Intel-gfx] [PATCH 17/21] drm/i915/gt: Track timeline GGTT offset separately from subpage offset
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (14 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 16/21] drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 21:37 ` Matthew Brost
2020-12-10 8:02 ` [Intel-gfx] [PATCH 18/21] drm/i915/gt: Add timeline "mode" Chris Wilson
` (9 subsequent siblings)
25 siblings, 1 reply; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Currently we know that the timeline status page is at most a page in
size, and so we can preserve the lower 12bits of the offset when
relocating the status page in the GGTT. If we want to use a larger
object, such as the context state, we may not necessarily use a position
within the first page and so need more than 12b.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 4 ++--
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_timeline.c | 17 +++++++----------
drivers/gpu/drm/i915/gt/intel_timeline_types.h | 1 +
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_timeline.c | 16 ++++++++--------
8 files changed, 23 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
index ce38d1bcaba3..2f59dd3bdc18 100644
--- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
@@ -161,7 +161,7 @@ u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_CS_STALL);
- *cs++ = i915_request_active_timeline(rq)->hwsp_offset |
+ *cs++ = i915_request_active_timeline(rq)->ggtt_offset |
PIPE_CONTROL_GLOBAL_GTT;
*cs++ = rq->fence.seqno;
@@ -359,7 +359,7 @@ u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_GLOBAL_GTT_IVB |
PIPE_CONTROL_CS_STALL);
- *cs++ = i915_request_active_timeline(rq)->hwsp_offset;
+ *cs++ = i915_request_active_timeline(rq)->ggtt_offset;
*cs++ = rq->fence.seqno;
*cs++ = MI_USER_INTERRUPT;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index ebf043692eef..ed88dc4de72c 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -346,7 +346,7 @@ static u32 hwsp_offset(const struct i915_request *rq)
if (cl)
return cl->ggtt_offset;
- return rcu_dereference_protected(rq->timeline, 1)->hwsp_offset;
+ return rcu_dereference_protected(rq->timeline, 1)->ggtt_offset;
}
int gen8_emit_init_breadcrumb(struct i915_request *rq)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 6c08e74edcae..55856c230779 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1340,7 +1340,7 @@ static int print_ring(char *buf, int sz, struct i915_request *rq)
len = scnprintf(buf, sz,
"ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
i915_ggtt_offset(rq->ring->vma),
- tl ? tl->hwsp_offset : 0,
+ tl ? tl->ggtt_offset : 0,
hwsp_seqno(rq),
DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
1000 * 1000));
@@ -1679,7 +1679,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (tl) {
drm_printf(m, "\t\tring->hwsp: 0x%08x\n",
- tl->hwsp_offset);
+ tl->ggtt_offset);
intel_timeline_put(tl);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index ddc8e1b4f3b8..cb20fcbb326b 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -338,13 +338,11 @@ int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww)
if (err)
return err;
- tl->hwsp_offset =
- i915_ggtt_offset(tl->hwsp_ggtt) +
- offset_in_page(tl->hwsp_offset);
+ tl->ggtt_offset = i915_ggtt_offset(tl->hwsp_ggtt) + tl->hwsp_offset;
GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
- tl->fence_context, tl->hwsp_offset);
+ tl->fence_context, tl->ggtt_offset);
- cacheline_acquire(tl->hwsp_cacheline, tl->hwsp_offset);
+ cacheline_acquire(tl->hwsp_cacheline, tl->ggtt_offset);
if (atomic_fetch_inc(&tl->pin_count)) {
cacheline_release(tl->hwsp_cacheline);
__i915_vma_unpin(tl->hwsp_ggtt);
@@ -512,14 +510,13 @@ __intel_timeline_get_seqno(struct intel_timeline *tl,
vaddr = page_mask_bits(cl->vaddr);
tl->hwsp_offset = cacheline * CACHELINE_BYTES;
- tl->hwsp_seqno =
- memset(vaddr + tl->hwsp_offset, 0, CACHELINE_BYTES);
+ tl->hwsp_seqno = memset(vaddr + tl->hwsp_offset, 0, CACHELINE_BYTES);
- tl->hwsp_offset += i915_ggtt_offset(vma);
+ tl->ggtt_offset = i915_ggtt_offset(vma) + tl->hwsp_offset;
GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
- tl->fence_context, tl->hwsp_offset);
+ tl->fence_context, tl->ggtt_offset);
- cacheline_acquire(cl, tl->hwsp_offset);
+ cacheline_acquire(cl, tl->ggtt_offset);
tl->hwsp_cacheline = cl;
*seqno = timeline_advance(tl);
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
index e360f50706bf..f187c5aac11c 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
@@ -48,6 +48,7 @@ struct intel_timeline {
const u32 *hwsp_seqno;
struct i915_vma *hwsp_ggtt;
u32 hwsp_offset;
+ u32 ggtt_offset;
struct intel_timeline_cacheline *hwsp_cacheline;
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 729c3c7b11e2..0a676d938c15 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -53,7 +53,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
cmd++;
*cs++ = cmd;
*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
- *cs++ = i915_request_timeline(rq)->hwsp_offset + slot * sizeof(u32);
+ *cs++ = i915_request_timeline(rq)->ggtt_offset + slot * sizeof(u32);
*cs++ = 0;
intel_ring_advance(rq, cs);
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 64ef5ee5decf..9733f657c265 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -137,7 +137,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
*cs++ = cmd;
*cs++ = i915_mmio_reg_offset(GEN8_RC6_CTX_INFO);
- *cs++ = ce->timeline->hwsp_offset + 8;
+ *cs++ = ce->timeline->ggtt_offset + 8;
*cs++ = 0;
intel_ring_advance(rq, cs);
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index a6ff9d1605aa..6f355c8a4f81 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -468,7 +468,7 @@ tl_write(struct intel_timeline *tl, struct intel_engine_cs *engine, u32 value)
i915_request_get(rq);
- err = emit_ggtt_store_dw(rq, tl->hwsp_offset, value);
+ err = emit_ggtt_store_dw(rq, tl->ggtt_offset, value);
i915_request_add(rq);
if (err) {
i915_request_put(rq);
@@ -564,7 +564,7 @@ static int live_hwsp_engine(void *arg)
if (!err && READ_ONCE(*tl->hwsp_seqno) != n) {
GEM_TRACE_ERR("Invalid seqno:%lu stored in timeline %llu @ %x, found 0x%x\n",
- n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);
+ n, tl->fence_context, tl->ggtt_offset, *tl->hwsp_seqno);
GEM_TRACE_DUMP();
err = -EINVAL;
}
@@ -636,7 +636,7 @@ static int live_hwsp_alternate(void *arg)
if (!err && READ_ONCE(*tl->hwsp_seqno) != n) {
GEM_TRACE_ERR("Invalid seqno:%lu stored in timeline %llu @ %x, found 0x%x\n",
- n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);
+ n, tl->fence_context, tl->ggtt_offset, *tl->hwsp_seqno);
GEM_TRACE_DUMP();
err = -EINVAL;
}
@@ -696,9 +696,9 @@ static int live_hwsp_wrap(void *arg)
goto out;
}
pr_debug("seqno[0]:%08x, hwsp_offset:%08x\n",
- seqno[0], tl->hwsp_offset);
+ seqno[0], tl->ggtt_offset);
- err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[0]);
+ err = emit_ggtt_store_dw(rq, tl->ggtt_offset, seqno[0]);
if (err) {
i915_request_add(rq);
goto out;
@@ -713,9 +713,9 @@ static int live_hwsp_wrap(void *arg)
goto out;
}
pr_debug("seqno[1]:%08x, hwsp_offset:%08x\n",
- seqno[1], tl->hwsp_offset);
+ seqno[1], tl->ggtt_offset);
- err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[1]);
+ err = emit_ggtt_store_dw(rq, tl->ggtt_offset, seqno[1]);
if (err) {
i915_request_add(rq);
goto out;
@@ -1343,7 +1343,7 @@ static int live_hwsp_recycle(void *arg)
if (READ_ONCE(*tl->hwsp_seqno) != count) {
GEM_TRACE_ERR("Invalid seqno:%lu stored in timeline %llu @ %x found 0x%x\n",
count, tl->fence_context,
- tl->hwsp_offset, *tl->hwsp_seqno);
+ tl->ggtt_offset, *tl->hwsp_seqno);
GEM_TRACE_DUMP();
err = -EINVAL;
}
--
2.20.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 38+ messages in thread* Re: [Intel-gfx] [PATCH 17/21] drm/i915/gt: Track timeline GGTT offset separately from subpage offset
2020-12-10 8:02 ` [Intel-gfx] [PATCH 17/21] drm/i915/gt: Track timeline GGTT offset separately from subpage offset Chris Wilson
@ 2020-12-10 21:37 ` Matthew Brost
0 siblings, 0 replies; 38+ messages in thread
From: Matthew Brost @ 2020-12-10 21:37 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Dec 10, 2020 at 08:02:36AM +0000, Chris Wilson wrote:
> Currently we know that the timeline status page is at most a page in
> size, and so we can preserve the lower 12bits of the offset when
> relocating the status page in the GGTT. If we want to use a larger
> object, such as the context state, we may not necessarily use a position
> within the first page and so need more than 12b.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 4 ++--
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_timeline.c | 17 +++++++----------
> drivers/gpu/drm/i915/gt/intel_timeline_types.h | 1 +
> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_rc6.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 16 ++++++++--------
> 8 files changed, 23 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
> index ce38d1bcaba3..2f59dd3bdc18 100644
> --- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
> @@ -161,7 +161,7 @@ u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> PIPE_CONTROL_DC_FLUSH_ENABLE |
> PIPE_CONTROL_QW_WRITE |
> PIPE_CONTROL_CS_STALL);
> - *cs++ = i915_request_active_timeline(rq)->hwsp_offset |
> + *cs++ = i915_request_active_timeline(rq)->ggtt_offset |
> PIPE_CONTROL_GLOBAL_GTT;
> *cs++ = rq->fence.seqno;
>
> @@ -359,7 +359,7 @@ u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> PIPE_CONTROL_QW_WRITE |
> PIPE_CONTROL_GLOBAL_GTT_IVB |
> PIPE_CONTROL_CS_STALL);
> - *cs++ = i915_request_active_timeline(rq)->hwsp_offset;
> + *cs++ = i915_request_active_timeline(rq)->ggtt_offset;
> *cs++ = rq->fence.seqno;
>
> *cs++ = MI_USER_INTERRUPT;
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index ebf043692eef..ed88dc4de72c 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -346,7 +346,7 @@ static u32 hwsp_offset(const struct i915_request *rq)
> if (cl)
> return cl->ggtt_offset;
>
> - return rcu_dereference_protected(rq->timeline, 1)->hwsp_offset;
> + return rcu_dereference_protected(rq->timeline, 1)->ggtt_offset;
> }
>
> int gen8_emit_init_breadcrumb(struct i915_request *rq)
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 6c08e74edcae..55856c230779 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1340,7 +1340,7 @@ static int print_ring(char *buf, int sz, struct i915_request *rq)
> len = scnprintf(buf, sz,
> "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
> i915_ggtt_offset(rq->ring->vma),
> - tl ? tl->hwsp_offset : 0,
> + tl ? tl->ggtt_offset : 0,
> hwsp_seqno(rq),
> DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
> 1000 * 1000));
> @@ -1679,7 +1679,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>
> if (tl) {
> drm_printf(m, "\t\tring->hwsp: 0x%08x\n",
> - tl->hwsp_offset);
> + tl->ggtt_offset);
> intel_timeline_put(tl);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
> index ddc8e1b4f3b8..cb20fcbb326b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
> @@ -338,13 +338,11 @@ int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww)
> if (err)
> return err;
>
> - tl->hwsp_offset =
> - i915_ggtt_offset(tl->hwsp_ggtt) +
> - offset_in_page(tl->hwsp_offset);
> + tl->ggtt_offset = i915_ggtt_offset(tl->hwsp_ggtt) + tl->hwsp_offset;
> GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
> - tl->fence_context, tl->hwsp_offset);
> + tl->fence_context, tl->ggtt_offset);
>
> - cacheline_acquire(tl->hwsp_cacheline, tl->hwsp_offset);
> + cacheline_acquire(tl->hwsp_cacheline, tl->ggtt_offset);
> if (atomic_fetch_inc(&tl->pin_count)) {
> cacheline_release(tl->hwsp_cacheline);
> __i915_vma_unpin(tl->hwsp_ggtt);
> @@ -512,14 +510,13 @@ __intel_timeline_get_seqno(struct intel_timeline *tl,
>
> vaddr = page_mask_bits(cl->vaddr);
> tl->hwsp_offset = cacheline * CACHELINE_BYTES;
> - tl->hwsp_seqno =
> - memset(vaddr + tl->hwsp_offset, 0, CACHELINE_BYTES);
> + tl->hwsp_seqno = memset(vaddr + tl->hwsp_offset, 0, CACHELINE_BYTES);
>
> - tl->hwsp_offset += i915_ggtt_offset(vma);
> + tl->ggtt_offset = i915_ggtt_offset(vma) + tl->hwsp_offset;
> GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
> - tl->fence_context, tl->hwsp_offset);
> + tl->fence_context, tl->ggtt_offset);
>
> - cacheline_acquire(cl, tl->hwsp_offset);
> + cacheline_acquire(cl, tl->ggtt_offset);
> tl->hwsp_cacheline = cl;
>
> *seqno = timeline_advance(tl);
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> index e360f50706bf..f187c5aac11c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> @@ -48,6 +48,7 @@ struct intel_timeline {
> const u32 *hwsp_seqno;
> struct i915_vma *hwsp_ggtt;
> u32 hwsp_offset;
> + u32 ggtt_offset;
>
> struct intel_timeline_cacheline *hwsp_cacheline;
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> index 729c3c7b11e2..0a676d938c15 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> @@ -53,7 +53,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
> cmd++;
> *cs++ = cmd;
> *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
> - *cs++ = i915_request_timeline(rq)->hwsp_offset + slot * sizeof(u32);
> + *cs++ = i915_request_timeline(rq)->ggtt_offset + slot * sizeof(u32);
> *cs++ = 0;
>
> intel_ring_advance(rq, cs);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> index 64ef5ee5decf..9733f657c265 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> @@ -137,7 +137,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
>
> *cs++ = cmd;
> *cs++ = i915_mmio_reg_offset(GEN8_RC6_CTX_INFO);
> - *cs++ = ce->timeline->hwsp_offset + 8;
> + *cs++ = ce->timeline->ggtt_offset + 8;
> *cs++ = 0;
> intel_ring_advance(rq, cs);
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> index a6ff9d1605aa..6f355c8a4f81 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> @@ -468,7 +468,7 @@ tl_write(struct intel_timeline *tl, struct intel_engine_cs *engine, u32 value)
>
> i915_request_get(rq);
>
> - err = emit_ggtt_store_dw(rq, tl->hwsp_offset, value);
> + err = emit_ggtt_store_dw(rq, tl->ggtt_offset, value);
> i915_request_add(rq);
> if (err) {
> i915_request_put(rq);
> @@ -564,7 +564,7 @@ static int live_hwsp_engine(void *arg)
>
> if (!err && READ_ONCE(*tl->hwsp_seqno) != n) {
> GEM_TRACE_ERR("Invalid seqno:%lu stored in timeline %llu @ %x, found 0x%x\n",
> - n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);
> + n, tl->fence_context, tl->ggtt_offset, *tl->hwsp_seqno);
> GEM_TRACE_DUMP();
> err = -EINVAL;
> }
> @@ -636,7 +636,7 @@ static int live_hwsp_alternate(void *arg)
>
> if (!err && READ_ONCE(*tl->hwsp_seqno) != n) {
> GEM_TRACE_ERR("Invalid seqno:%lu stored in timeline %llu @ %x, found 0x%x\n",
> - n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);
> + n, tl->fence_context, tl->ggtt_offset, *tl->hwsp_seqno);
> GEM_TRACE_DUMP();
> err = -EINVAL;
> }
> @@ -696,9 +696,9 @@ static int live_hwsp_wrap(void *arg)
> goto out;
> }
> pr_debug("seqno[0]:%08x, hwsp_offset:%08x\n",
> - seqno[0], tl->hwsp_offset);
> + seqno[0], tl->ggtt_offset);
>
> - err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[0]);
> + err = emit_ggtt_store_dw(rq, tl->ggtt_offset, seqno[0]);
> if (err) {
> i915_request_add(rq);
> goto out;
> @@ -713,9 +713,9 @@ static int live_hwsp_wrap(void *arg)
> goto out;
> }
> pr_debug("seqno[1]:%08x, hwsp_offset:%08x\n",
> - seqno[1], tl->hwsp_offset);
> + seqno[1], tl->ggtt_offset);
>
> - err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[1]);
> + err = emit_ggtt_store_dw(rq, tl->ggtt_offset, seqno[1]);
> if (err) {
> i915_request_add(rq);
> goto out;
> @@ -1343,7 +1343,7 @@ static int live_hwsp_recycle(void *arg)
> if (READ_ONCE(*tl->hwsp_seqno) != count) {
> GEM_TRACE_ERR("Invalid seqno:%lu stored in timeline %llu @ %x found 0x%x\n",
> count, tl->fence_context,
> - tl->hwsp_offset, *tl->hwsp_seqno);
> + tl->ggtt_offset, *tl->hwsp_seqno);
> GEM_TRACE_DUMP();
> err = -EINVAL;
> }
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 18/21] drm/i915/gt: Add timeline "mode"
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (15 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 17/21] drm/i915/gt: Track timeline GGTT offset separately from subpage offset Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 19:28 ` Matthew Brost
2020-12-10 8:02 ` [Intel-gfx] [PATCH 19/21] drm/i915/gt: Use indices for writing into relative timelines Chris Wilson
` (8 subsequent siblings)
25 siblings, 1 reply; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Explicitly differentiate between the absolute and relative timelines,
and the global HWSP and ppHWSP relative offsets. When using a timeline
that is relative to a known status page, we can replace the absolute
addressing in the commands with indexed variants.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 21 ++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_timeline.h | 2 +-
.../gpu/drm/i915/gt/intel_timeline_types.h | 10 +++++++--
3 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index cb20fcbb326b..da0a9659557a 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -229,7 +229,6 @@ static int intel_timeline_init(struct intel_timeline *timeline,
timeline->gt = gt;
- timeline->has_initial_breadcrumb = !hwsp;
timeline->hwsp_cacheline = NULL;
if (!hwsp) {
@@ -246,13 +245,29 @@ static int intel_timeline_init(struct intel_timeline *timeline,
return PTR_ERR(cl);
}
+ timeline->mode = INTEL_TIMELINE_ABSOLUTE;
timeline->hwsp_cacheline = cl;
timeline->hwsp_offset = cacheline * CACHELINE_BYTES;
vaddr = page_mask_bits(cl->vaddr);
} else {
- timeline->hwsp_offset = offset;
- vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WB);
+ int preferred;
+
+ if (offset & INTEL_TIMELINE_CONTEXT) {
+ timeline->mode = INTEL_TIMELINE_CONTEXT;
+ timeline->hwsp_offset =
+ offset & ~INTEL_TIMELINE_CONTEXT;
+ preferred = i915_coherent_map_type(gt->i915);
+ } else {
+ timeline->mode = INTEL_TIMELINE_GLOBAL;
+ timeline->hwsp_offset = offset;
+ preferred = I915_MAP_WB;
+ }
+
+ vaddr = i915_gem_object_pin_map(hwsp->obj,
+ preferred | I915_MAP_OVERRIDE);
+ if (IS_ERR(vaddr))
+ vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WC);
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h
index deb71a8dbd43..69250de3a814 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
@@ -76,7 +76,7 @@ static inline void intel_timeline_put(struct intel_timeline *timeline)
static inline bool
intel_timeline_has_initial_breadcrumb(const struct intel_timeline *tl)
{
- return tl->has_initial_breadcrumb;
+ return tl->mode == INTEL_TIMELINE_ABSOLUTE;
}
static inline int __intel_timeline_sync_set(struct intel_timeline *tl,
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
index f187c5aac11c..32c51425a0c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
@@ -20,6 +20,12 @@ struct i915_syncmap;
struct intel_gt;
struct intel_timeline_hwsp;
+enum intel_timeline_mode {
+ INTEL_TIMELINE_ABSOLUTE = 0,
+ INTEL_TIMELINE_CONTEXT = BIT(0),
+ INTEL_TIMELINE_GLOBAL = BIT(1),
+};
+
struct intel_timeline {
u64 fence_context;
u32 seqno;
@@ -45,6 +51,8 @@ struct intel_timeline {
atomic_t pin_count;
atomic_t active_count;
+ enum intel_timeline_mode mode;
+
const u32 *hwsp_seqno;
struct i915_vma *hwsp_ggtt;
u32 hwsp_offset;
@@ -52,8 +60,6 @@ struct intel_timeline {
struct intel_timeline_cacheline *hwsp_cacheline;
- bool has_initial_breadcrumb;
-
/**
* List of breadcrumbs associated with GPU requests currently
* outstanding.
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 38+ messages in thread* Re: [Intel-gfx] [PATCH 18/21] drm/i915/gt: Add timeline "mode"
2020-12-10 8:02 ` [Intel-gfx] [PATCH 18/21] drm/i915/gt: Add timeline "mode" Chris Wilson
@ 2020-12-10 19:28 ` Matthew Brost
2020-12-10 21:00 ` Chris Wilson
0 siblings, 1 reply; 38+ messages in thread
From: Matthew Brost @ 2020-12-10 19:28 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Dec 10, 2020 at 08:02:37AM +0000, Chris Wilson wrote:
> Explicitly differentiate between the absolute and relative timelines,
> and the global HWSP and ppHWSP relative offsets. When using a timeline
> that is relative to a known status page, we can replace the absolute
> addressing in the commands with indexed variants.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_timeline.c | 21 ++++++++++++++++---
> drivers/gpu/drm/i915/gt/intel_timeline.h | 2 +-
> .../gpu/drm/i915/gt/intel_timeline_types.h | 10 +++++++--
> 3 files changed, 27 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
> index cb20fcbb326b..da0a9659557a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
> @@ -229,7 +229,6 @@ static int intel_timeline_init(struct intel_timeline *timeline,
>
> timeline->gt = gt;
>
> - timeline->has_initial_breadcrumb = !hwsp;
> timeline->hwsp_cacheline = NULL;
>
> if (!hwsp) {
> @@ -246,13 +245,29 @@ static int intel_timeline_init(struct intel_timeline *timeline,
> return PTR_ERR(cl);
> }
>
> + timeline->mode = INTEL_TIMELINE_ABSOLUTE;
> timeline->hwsp_cacheline = cl;
> timeline->hwsp_offset = cacheline * CACHELINE_BYTES;
>
> vaddr = page_mask_bits(cl->vaddr);
> } else {
> - timeline->hwsp_offset = offset;
> - vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WB);
> + int preferred;
> +
> + if (offset & INTEL_TIMELINE_CONTEXT) {
> + timeline->mode = INTEL_TIMELINE_CONTEXT;
> + timeline->hwsp_offset =
> + offset & ~INTEL_TIMELINE_CONTEXT;
> + preferred = i915_coherent_map_type(gt->i915);
> + } else {
> + timeline->mode = INTEL_TIMELINE_GLOBAL;
> + timeline->hwsp_offset = offset;
> + preferred = I915_MAP_WB;
> + }
> +
> + vaddr = i915_gem_object_pin_map(hwsp->obj,
> + preferred | I915_MAP_OVERRIDE);
> + if (IS_ERR(vaddr))
> + vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WC);
> if (IS_ERR(vaddr))
> return PTR_ERR(vaddr);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h
> index deb71a8dbd43..69250de3a814 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.h
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
> @@ -76,7 +76,7 @@ static inline void intel_timeline_put(struct intel_timeline *timeline)
> static inline bool
> intel_timeline_has_initial_breadcrumb(const struct intel_timeline *tl)
> {
> - return tl->has_initial_breadcrumb;
> + return tl->mode == INTEL_TIMELINE_ABSOLUTE;
> }
>
> static inline int __intel_timeline_sync_set(struct intel_timeline *tl,
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> index f187c5aac11c..32c51425a0c4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> @@ -20,6 +20,12 @@ struct i915_syncmap;
> struct intel_gt;
> struct intel_timeline_hwsp;
>
> +enum intel_timeline_mode {
> + INTEL_TIMELINE_ABSOLUTE = 0,
> + INTEL_TIMELINE_CONTEXT = BIT(0),
> + INTEL_TIMELINE_GLOBAL = BIT(1),
> +};
> +
Not sure I like these names.
How about:
INTEL_TIMELINE_ABSOLUTE_GGTT
INTEL_TIMELINE_RELATIVE_PPGTT
INTEL_TIMELINE_RELATIVE_GGTT
Also not convinced we need the 'RELATIVE' modes. See my comments in 'Use
indices for writing into relative'.
Matt
> struct intel_timeline {
> u64 fence_context;
> u32 seqno;
> @@ -45,6 +51,8 @@ struct intel_timeline {
> atomic_t pin_count;
> atomic_t active_count;
>
> + enum intel_timeline_mode mode;
> +
> const u32 *hwsp_seqno;
> struct i915_vma *hwsp_ggtt;
> u32 hwsp_offset;
> @@ -52,8 +60,6 @@ struct intel_timeline {
>
> struct intel_timeline_cacheline *hwsp_cacheline;
>
> - bool has_initial_breadcrumb;
> -
> /**
> * List of breadcrumbs associated with GPU requests currently
> * outstanding.
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [Intel-gfx] [PATCH 18/21] drm/i915/gt: Add timeline "mode"
2020-12-10 19:28 ` Matthew Brost
@ 2020-12-10 21:00 ` Chris Wilson
2020-12-10 21:18 ` Matthew Brost
0 siblings, 1 reply; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 21:00 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-gfx
Quoting Matthew Brost (2020-12-10 19:28:06)
> On Thu, Dec 10, 2020 at 08:02:37AM +0000, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > index f187c5aac11c..32c51425a0c4 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > @@ -20,6 +20,12 @@ struct i915_syncmap;
> > struct intel_gt;
> > struct intel_timeline_hwsp;
> >
> > +enum intel_timeline_mode {
> > + INTEL_TIMELINE_ABSOLUTE = 0,
> > + INTEL_TIMELINE_CONTEXT = BIT(0),
> > + INTEL_TIMELINE_GLOBAL = BIT(1),
> > +};
> > +
>
> Not sure I like these names.
>
> How about:
> INTEL_TIMELINE_ABSOLUTE_GGTT
> INTEL_TIMELINE_RELATIVE_PPGTT
> INTEL_TIMELINE_RELATIVE_GGTT
They are all in the GGTT, including the ppHWSP.
One is relative to the context, the other relative to the engine.
INTEL_TIMELINE_ABSOLUTE
INTEL_TIMELINE_RELATIVE_CONTEXT
INTEL_TIMELINE_RELATIVE_ENGINE
> Also not convinced we need the 'RELATIVE' modes. See my comments in 'Use
> indices for writing into relative'.
It saves extra allocations for when we don't (e.g. gen8, and other
contexts where we know we will never require disposable slots), and
there's a strong incentive to not use absolute addressing with GVT.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [Intel-gfx] [PATCH 18/21] drm/i915/gt: Add timeline "mode"
2020-12-10 21:00 ` Chris Wilson
@ 2020-12-10 21:18 ` Matthew Brost
0 siblings, 0 replies; 38+ messages in thread
From: Matthew Brost @ 2020-12-10 21:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Dec 10, 2020 at 09:00:53PM +0000, Chris Wilson wrote:
> Quoting Matthew Brost (2020-12-10 19:28:06)
> > On Thu, Dec 10, 2020 at 08:02:37AM +0000, Chris Wilson wrote:
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > > index f187c5aac11c..32c51425a0c4 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > > @@ -20,6 +20,12 @@ struct i915_syncmap;
> > > struct intel_gt;
> > > struct intel_timeline_hwsp;
> > >
> > > +enum intel_timeline_mode {
> > > + INTEL_TIMELINE_ABSOLUTE = 0,
> > > + INTEL_TIMELINE_CONTEXT = BIT(0),
> > > + INTEL_TIMELINE_GLOBAL = BIT(1),
> > > +};
> > > +
> >
> > Not sure I like these names.
> >
> > How about:
> > INTEL_TIMELINE_ABSOLUTE_GGTT
> > INTEL_TIMELINE_RELATIVE_PPGTT
> > INTEL_TIMELINE_RELATIVE_GGTT
>
> They are all in the GGTT, including the ppHWSP.
>
Ah, got it. The 'MI_FLUSH_DW_USE_GTT' in a later patch threw me off. I
see now that it is picking between global status page and per-process
page in that case.
> One is relative to the context, the other relative to the engine.
>
> INTEL_TIMELINE_ABSOLUTE
> INTEL_TIMELINE_RELATIVE_CONTEXT
> INTEL_TIMELINE_RELATIVE_ENGINE
>
I like these names better.
> > Also not convinced we need the 'RELATIVE' modes. See my comments in 'Use
> > indices for writing into relative'.
>
> It saves extra allocations for when we don't (e.g. gen8, and other
> contexts where we know we will never require disposable slots), and
> there's a strong incentive to not use absolute addressing with GVT
Understand using the status page to save on allocations.
I could see relative addressing helping with GVT.
With the name nits:
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 19/21] drm/i915/gt: Use indices for writing into relative timelines
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (16 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 18/21] drm/i915/gt: Add timeline "mode" Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 19:16 ` Matthew Brost
2020-12-10 8:02 ` [Intel-gfx] [PATCH 20/21] drm/i915/selftests: Exercise relative timeline modes Chris Wilson
` (7 subsequent siblings)
25 siblings, 1 reply; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Relative timelines are relative to either the global or per-process
HWSP, and so we can replace the absolute addressing with store-index
variants for position invariance.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 98 +++++++++++++++++-------
drivers/gpu/drm/i915/gt/intel_timeline.h | 12 +++
2 files changed, 82 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index ed88dc4de72c..386da26816d0 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -502,7 +502,19 @@ gen8_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)
static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)
{
- return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);
+ struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
+ unsigned int flags = MI_FLUSH_DW_OP_STOREDW;
+ u32 offset = hwsp_offset(rq);
+
+ if (intel_timeline_is_relative(tl)) {
+ offset = offset_in_page(offset);
+ flags |= MI_FLUSH_DW_STORE_INDEX;
+ }
+ GEM_BUG_ON(offset & 7);
+ if (intel_timeline_is_global(tl))
+ offset |= MI_FLUSH_DW_USE_GTT;
+
+ return __gen8_emit_flush_dw(cs, rq->fence.seqno, offset, flags);
}
u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
@@ -512,6 +524,18 @@ u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{
+ struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
+ unsigned int flags = PIPE_CONTROL_FLUSH_ENABLE | PIPE_CONTROL_CS_STALL;
+ u32 offset = hwsp_offset(rq);
+
+ if (intel_timeline_is_relative(tl)) {
+ offset = offset_in_page(offset);
+ flags |= PIPE_CONTROL_STORE_DATA_INDEX;
+ }
+ GEM_BUG_ON(offset & 7);
+ if (intel_timeline_is_global(tl))
+ flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+
cs = gen8_emit_pipe_control(cs,
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
@@ -519,26 +543,33 @@ u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
0);
/* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
- cs = gen8_emit_ggtt_write_rcs(cs,
- rq->fence.seqno,
- hwsp_offset(rq),
- PIPE_CONTROL_FLUSH_ENABLE |
- PIPE_CONTROL_CS_STALL);
+ cs = __gen8_emit_write_rcs(cs, rq->fence.seqno, offset, 0, flags);
return gen8_emit_fini_breadcrumb_tail(rq, cs);
}
u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{
- cs = gen8_emit_ggtt_write_rcs(cs,
- rq->fence.seqno,
- hwsp_offset(rq),
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_TILE_CACHE_FLUSH |
- PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_DC_FLUSH_ENABLE |
- PIPE_CONTROL_FLUSH_ENABLE);
+ struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
+ u32 offset = hwsp_offset(rq);
+ unsigned int flags;
+
+ flags = (PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_TILE_CACHE_FLUSH |
+ PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ PIPE_CONTROL_DC_FLUSH_ENABLE |
+ PIPE_CONTROL_FLUSH_ENABLE);
+
+ if (intel_timeline_is_relative(tl)) {
+ offset = offset_in_page(offset);
+ flags |= PIPE_CONTROL_STORE_DATA_INDEX;
+ }
+ GEM_BUG_ON(offset & 7);
+ if (intel_timeline_is_global(tl))
+ flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+
+ cs = __gen8_emit_write_rcs(cs, rq->fence.seqno, offset, 0, flags);
return gen8_emit_fini_breadcrumb_tail(rq, cs);
}
@@ -601,19 +632,30 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{
- cs = gen12_emit_ggtt_write_rcs(cs,
- rq->fence.seqno,
- hwsp_offset(rq),
- PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_TILE_CACHE_FLUSH |
- PIPE_CONTROL_FLUSH_L3 |
- PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- /* Wa_1409600907:tgl */
- PIPE_CONTROL_DEPTH_STALL |
- PIPE_CONTROL_DC_FLUSH_ENABLE |
- PIPE_CONTROL_FLUSH_ENABLE);
+ struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
+ u32 offset = hwsp_offset(rq);
+ unsigned int flags;
+
+ flags = (PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_TILE_CACHE_FLUSH |
+ PIPE_CONTROL_FLUSH_L3 |
+ PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ /* Wa_1409600907:tgl */
+ PIPE_CONTROL_DEPTH_STALL |
+ PIPE_CONTROL_DC_FLUSH_ENABLE |
+ PIPE_CONTROL_FLUSH_ENABLE);
+
+ if (intel_timeline_is_relative(tl)) {
+ offset = offset_in_page(offset);
+ flags |= PIPE_CONTROL_STORE_DATA_INDEX;
+ }
+ GEM_BUG_ON(offset & 7);
+ if (intel_timeline_is_global(tl))
+ flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+
+ cs = __gen8_emit_write_rcs(cs, rq->fence.seqno, offset,
+ PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags);
return gen12_emit_fini_breadcrumb_tail(rq, cs);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h
index 69250de3a814..a3bdbff62e96 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
@@ -79,6 +79,18 @@ intel_timeline_has_initial_breadcrumb(const struct intel_timeline *tl)
return tl->mode == INTEL_TIMELINE_ABSOLUTE;
}
+static inline bool
+intel_timeline_is_relative(const struct intel_timeline *tl)
+{
+ return tl->mode != INTEL_TIMELINE_ABSOLUTE;
+}
+
+static inline bool
+intel_timeline_is_global(const struct intel_timeline *tl)
+{
+ return tl->mode != INTEL_TIMELINE_CONTEXT;
+}
+
static inline int __intel_timeline_sync_set(struct intel_timeline *tl,
u64 context, u32 seqno)
{
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 38+ messages in thread* Re: [Intel-gfx] [PATCH 19/21] drm/i915/gt: Use indices for writing into relative timelines
2020-12-10 8:02 ` [Intel-gfx] [PATCH 19/21] drm/i915/gt: Use indices for writing into relative timelines Chris Wilson
@ 2020-12-10 19:16 ` Matthew Brost
2020-12-10 21:05 ` Chris Wilson
0 siblings, 1 reply; 38+ messages in thread
From: Matthew Brost @ 2020-12-10 19:16 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Dec 10, 2020 at 08:02:38AM +0000, Chris Wilson wrote:
> Relative timelines are relative to either the global or per-process
> HWSP, and so we can replace the absolute addressing with store-index
> variants for position invariance.
>
Can you explain the benifit of relative addressing? Why can't we also
use absolute? If we can always use absolute, I don't see the point
complicating the breadcrumb code.
Matt
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 98 +++++++++++++++++-------
> drivers/gpu/drm/i915/gt/intel_timeline.h | 12 +++
> 2 files changed, 82 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index ed88dc4de72c..386da26816d0 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -502,7 +502,19 @@ gen8_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)
>
> static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)
> {
> - return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);
> + struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
> + unsigned int flags = MI_FLUSH_DW_OP_STOREDW;
> + u32 offset = hwsp_offset(rq);
> +
> + if (intel_timeline_is_relative(tl)) {
> + offset = offset_in_page(offset);
> + flags |= MI_FLUSH_DW_STORE_INDEX;
> + }
> + GEM_BUG_ON(offset & 7);
> + if (intel_timeline_is_global(tl))
> + offset |= MI_FLUSH_DW_USE_GTT;
> +
> + return __gen8_emit_flush_dw(cs, rq->fence.seqno, offset, flags);
> }
>
> u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
> @@ -512,6 +524,18 @@ u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
>
> u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> {
> + struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
> + unsigned int flags = PIPE_CONTROL_FLUSH_ENABLE | PIPE_CONTROL_CS_STALL;
> + u32 offset = hwsp_offset(rq);
> +
> + if (intel_timeline_is_relative(tl)) {
> + offset = offset_in_page(offset);
> + flags |= PIPE_CONTROL_STORE_DATA_INDEX;
> + }
> + GEM_BUG_ON(offset & 7);
> + if (intel_timeline_is_global(tl))
> + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> +
> cs = gen8_emit_pipe_control(cs,
> PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
> PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> @@ -519,26 +543,33 @@ u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> 0);
>
> /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
> - cs = gen8_emit_ggtt_write_rcs(cs,
> - rq->fence.seqno,
> - hwsp_offset(rq),
> - PIPE_CONTROL_FLUSH_ENABLE |
> - PIPE_CONTROL_CS_STALL);
> + cs = __gen8_emit_write_rcs(cs, rq->fence.seqno, offset, 0, flags);
>
> return gen8_emit_fini_breadcrumb_tail(rq, cs);
> }
>
> u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> {
> - cs = gen8_emit_ggtt_write_rcs(cs,
> - rq->fence.seqno,
> - hwsp_offset(rq),
> - PIPE_CONTROL_CS_STALL |
> - PIPE_CONTROL_TILE_CACHE_FLUSH |
> - PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
> - PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> - PIPE_CONTROL_DC_FLUSH_ENABLE |
> - PIPE_CONTROL_FLUSH_ENABLE);
> + struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
> + u32 offset = hwsp_offset(rq);
> + unsigned int flags;
> +
> + flags = (PIPE_CONTROL_CS_STALL |
> + PIPE_CONTROL_TILE_CACHE_FLUSH |
> + PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
> + PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> + PIPE_CONTROL_DC_FLUSH_ENABLE |
> + PIPE_CONTROL_FLUSH_ENABLE);
> +
> + if (intel_timeline_is_relative(tl)) {
> + offset = offset_in_page(offset);
> + flags |= PIPE_CONTROL_STORE_DATA_INDEX;
> + }
> + GEM_BUG_ON(offset & 7);
> + if (intel_timeline_is_global(tl))
> + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> +
> + cs = __gen8_emit_write_rcs(cs, rq->fence.seqno, offset, 0, flags);
>
> return gen8_emit_fini_breadcrumb_tail(rq, cs);
> }
> @@ -601,19 +632,30 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
>
> u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> {
> - cs = gen12_emit_ggtt_write_rcs(cs,
> - rq->fence.seqno,
> - hwsp_offset(rq),
> - PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
> - PIPE_CONTROL_CS_STALL |
> - PIPE_CONTROL_TILE_CACHE_FLUSH |
> - PIPE_CONTROL_FLUSH_L3 |
> - PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
> - PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> - /* Wa_1409600907:tgl */
> - PIPE_CONTROL_DEPTH_STALL |
> - PIPE_CONTROL_DC_FLUSH_ENABLE |
> - PIPE_CONTROL_FLUSH_ENABLE);
> + struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
> + u32 offset = hwsp_offset(rq);
> + unsigned int flags;
> +
> + flags = (PIPE_CONTROL_CS_STALL |
> + PIPE_CONTROL_TILE_CACHE_FLUSH |
> + PIPE_CONTROL_FLUSH_L3 |
> + PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
> + PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> + /* Wa_1409600907:tgl */
> + PIPE_CONTROL_DEPTH_STALL |
> + PIPE_CONTROL_DC_FLUSH_ENABLE |
> + PIPE_CONTROL_FLUSH_ENABLE);
> +
> + if (intel_timeline_is_relative(tl)) {
> + offset = offset_in_page(offset);
> + flags |= PIPE_CONTROL_STORE_DATA_INDEX;
> + }
> + GEM_BUG_ON(offset & 7);
> + if (intel_timeline_is_global(tl))
> + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> +
> + cs = __gen8_emit_write_rcs(cs, rq->fence.seqno, offset,
> + PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags);
>
> return gen12_emit_fini_breadcrumb_tail(rq, cs);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h
> index 69250de3a814..a3bdbff62e96 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.h
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
> @@ -79,6 +79,18 @@ intel_timeline_has_initial_breadcrumb(const struct intel_timeline *tl)
> return tl->mode == INTEL_TIMELINE_ABSOLUTE;
> }
>
> +static inline bool
> +intel_timeline_is_relative(const struct intel_timeline *tl)
> +{
> + return tl->mode != INTEL_TIMELINE_ABSOLUTE;
> +}
> +
> +static inline bool
> +intel_timeline_is_global(const struct intel_timeline *tl)
> +{
> + return tl->mode != INTEL_TIMELINE_CONTEXT;
> +}
> +
> static inline int __intel_timeline_sync_set(struct intel_timeline *tl,
> u64 context, u32 seqno)
> {
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [Intel-gfx] [PATCH 19/21] drm/i915/gt: Use indices for writing into relative timelines
2020-12-10 19:16 ` Matthew Brost
@ 2020-12-10 21:05 ` Chris Wilson
2020-12-10 21:51 ` Matthew Brost
0 siblings, 1 reply; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 21:05 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-gfx
Quoting Matthew Brost (2020-12-10 19:16:44)
> On Thu, Dec 10, 2020 at 08:02:38AM +0000, Chris Wilson wrote:
> > Relative timelines are relative to either the global or per-process
> > HWSP, and so we can replace the absolute addressing with store-index
> > variants for position invariance.
> >
>
> Can you explain the benifit of relative addressing? Why can't we also
> use absolute? If we can always use absolute, I don't see the point
> complicating the breadcrumb code.
It basically allows a third party to move the contexts between hosts
with far less patching of global state. They want us to avoid all fixed
GGTT addressing.
The breadcrumbs themselves do not notice at all, it's just the timeline
setup and decision to take advantage of the relative commands. The
breadcrumb patches in this series are some outstanding fixes from ~6
months ago.
-Chris
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 19/21] drm/i915/gt: Use indices for writing into relative timelines
2020-12-10 21:05 ` Chris Wilson
@ 2020-12-10 21:51 ` Matthew Brost
0 siblings, 0 replies; 38+ messages in thread
From: Matthew Brost @ 2020-12-10 21:51 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Dec 10, 2020 at 09:05:44PM +0000, Chris Wilson wrote:
> Quoting Matthew Brost (2020-12-10 19:16:44)
> > On Thu, Dec 10, 2020 at 08:02:38AM +0000, Chris Wilson wrote:
> > > Relative timelines are relative to either the global or per-process
> > > HWSP, and so we can replace the absolute addressing with store-index
> > > variants for position invariance.
> > >
> >
> > Can you explain the benifit of relative addressing? Why can't we also
> > use absolute? If we can always use absolute, I don't see the point
> > complicating the breadcrumb code.
>
> It basically allows a third party to move the contexts between hosts
> with far less patching of global state. They want us to avoid all fixed
> GGTT addressing.
>
> The breadcrumbs themselves do not notice at all, it's just the timeline
> setup and decision to take advantage of the relative commands. The
> breadcrumb patches in this series are some outstanding fixes from ~6
> months ago.
By breadcrumbs, I meant the emit code. Relative addressing for GVT makes
sense.
With that, for this patch:
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> -Chris
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^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 20/21] drm/i915/selftests: Exercise relative timeline modes
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (17 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 19/21] drm/i915/gt: Use indices for writing into relative timelines Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 8:02 ` [Intel-gfx] [PATCH 21/21] drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines Chris Wilson
` (6 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
A quick test to verify that the backend accepts each type of timeline
and can use them to track and control request emission.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 93 +++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index 6f355c8a4f81..4164be36bec9 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -1364,9 +1364,102 @@ static int live_hwsp_recycle(void *arg)
return err;
}
+static int live_hwsp_relative(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ /*
+ * Check backend support for different timeline modes.
+ */
+
+ for_each_engine(engine, gt, id) {
+ enum intel_timeline_mode mode;
+
+ if (!engine->schedule)
+ continue;
+
+ for (mode = INTEL_TIMELINE_ABSOLUTE;
+ mode <= INTEL_TIMELINE_GLOBAL;
+ mode++) {
+ struct intel_timeline *tl;
+ struct i915_request *rq;
+ struct intel_context *ce;
+ const char *msg;
+ int err;
+
+ if (mode == INTEL_TIMELINE_CONTEXT &&
+ INTEL_GEN(gt->i915) < 8)
+ continue;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ err = intel_context_alloc_state(ce);
+ if (err) {
+ intel_context_put(ce);
+ return err;
+ }
+
+ switch (mode) {
+ case INTEL_TIMELINE_ABSOLUTE:
+ tl = intel_timeline_create(gt);
+ msg = "local";
+ break;
+
+ case INTEL_TIMELINE_CONTEXT:
+ tl = __intel_timeline_create(gt,
+ ce->state,
+ 0x400 | INTEL_TIMELINE_CONTEXT);
+ msg = "ppHWSP";
+ break;
+
+ case INTEL_TIMELINE_GLOBAL:
+ tl = __intel_timeline_create(gt,
+ engine->status_page.vma,
+ 0x400);
+ msg = "HWSP";
+ break;
+ }
+ if (IS_ERR(tl)) {
+ intel_context_put(ce);
+ return PTR_ERR(tl);
+ }
+
+ pr_info("Testing %s timeline on %s\n",
+ msg, engine->name);
+
+ intel_timeline_put(ce->timeline);
+ ce->timeline = tl;
+
+ rq = intel_context_create_request(ce);
+ intel_context_put(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ GEM_BUG_ON(rcu_access_pointer(rq->timeline) != tl);
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0) {
+ i915_request_put(rq);
+ return -EIO;
+ }
+
+ i915_request_put(rq);
+ }
+ }
+
+ return 0;
+}
+
int intel_timeline_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
+ SUBTEST(live_hwsp_relative),
SUBTEST(live_hwsp_recycle),
SUBTEST(live_hwsp_engine),
SUBTEST(live_hwsp_alternate),
--
2.20.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 38+ messages in thread* [Intel-gfx] [PATCH 21/21] drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (18 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 20/21] drm/i915/selftests: Exercise relative timeline modes Chris Wilson
@ 2020-12-10 8:02 ` Chris Wilson
2020-12-10 21:28 ` Matthew Brost
2020-12-10 8:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/21] drm/i915/gt: Mark legacy ring context as lost Patchwork
` (5 subsequent siblings)
25 siblings, 1 reply; 38+ messages in thread
From: Chris Wilson @ 2020-12-10 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
When we are not using semaphores with a context/engine, we can simply
reuse the same seqno location across wraps, but we still require each
timeline to have its own address. For LRC submission, each context is
prefixed by a per-process HWSP, which provides us with a unique location
for each context-local timeline. A shared timeline that is common to
multiple contexts will continue to use a separate page.
This enables us to create position invariant contexts should we feel the
need to relocate them.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
.../drm/i915/gt/intel_execlists_submission.c | 37 +++++++++++--------
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 8bff0559a6a9..cc1b3509d808 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -4749,6 +4749,14 @@ static struct intel_timeline *pinned_timeline(struct intel_context *ce)
page_unmask_bits(tl));
}
+static struct intel_timeline *pphwsp_timeline(struct intel_context *ce,
+ struct i915_vma *state)
+{
+ return __intel_timeline_create(ce->engine->gt, state,
+ I915_GEM_HWS_SEQNO_ADDR |
+ INTEL_TIMELINE_CONTEXT);
+}
+
static int __execlists_context_alloc(struct intel_context *ce,
struct intel_engine_cs *engine)
{
@@ -4779,6 +4787,16 @@ static int __execlists_context_alloc(struct intel_context *ce,
goto error_deref_obj;
}
+ ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
+ if (IS_ERR(ring)) {
+ ret = PTR_ERR(ring);
+ goto error_deref_obj;
+ }
+
+ ret = populate_lr_context(ce, ctx_obj, engine, ring);
+ if (ret)
+ goto error_ring_free;
+
if (!page_mask_bits(ce->timeline)) {
struct intel_timeline *tl;
@@ -4788,29 +4806,18 @@ static int __execlists_context_alloc(struct intel_context *ce,
*/
if (unlikely(ce->timeline))
tl = pinned_timeline(ce);
- else
+ else if (intel_engine_has_semaphores(engine))
tl = intel_timeline_create(engine->gt);
+ else
+ tl = pphwsp_timeline(ce, vma);
if (IS_ERR(tl)) {
ret = PTR_ERR(tl);
- goto error_deref_obj;
+ goto error_ring_free;
}
ce->timeline = tl;
}
- ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
- if (IS_ERR(ring)) {
- ret = PTR_ERR(ring);
- goto error_deref_obj;
- }
-
- ret = populate_lr_context(ce, ctx_obj, engine, ring);
- if (ret) {
- drm_dbg(&engine->i915->drm,
- "Failed to populate LRC: %d\n", ret);
- goto error_ring_free;
- }
-
ce->ring = ring;
ce->state = vma;
--
2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 38+ messages in thread* Re: [Intel-gfx] [PATCH 21/21] drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines
2020-12-10 8:02 ` [Intel-gfx] [PATCH 21/21] drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines Chris Wilson
@ 2020-12-10 21:28 ` Matthew Brost
0 siblings, 0 replies; 38+ messages in thread
From: Matthew Brost @ 2020-12-10 21:28 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Dec 10, 2020 at 08:02:40AM +0000, Chris Wilson wrote:
> When we are not using semaphores with a context/engine, we can simply
> reuse the same seqno location across wraps, but we still require each
> timeline to have its own address. For LRC submission, each context is
> prefixed by a per-process HWSP, which provides us with a unique location
> for each context-local timeline. A shared timeline that is common to
> multiple contexts will continue to use a separate page.
>
> This enables us to create position invariant contexts should we feel the
> need to relocate them.
>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 37 +++++++++++--------
> 1 file changed, 22 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 8bff0559a6a9..cc1b3509d808 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -4749,6 +4749,14 @@ static struct intel_timeline *pinned_timeline(struct intel_context *ce)
> page_unmask_bits(tl));
> }
>
> +static struct intel_timeline *pphwsp_timeline(struct intel_context *ce,
> + struct i915_vma *state)
> +{
> + return __intel_timeline_create(ce->engine->gt, state,
> + I915_GEM_HWS_SEQNO_ADDR |
> + INTEL_TIMELINE_CONTEXT);
> +}
> +
> static int __execlists_context_alloc(struct intel_context *ce,
> struct intel_engine_cs *engine)
> {
> @@ -4779,6 +4787,16 @@ static int __execlists_context_alloc(struct intel_context *ce,
> goto error_deref_obj;
> }
>
> + ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
> + if (IS_ERR(ring)) {
> + ret = PTR_ERR(ring);
> + goto error_deref_obj;
> + }
> +
> + ret = populate_lr_context(ce, ctx_obj, engine, ring);
> + if (ret)
> + goto error_ring_free;
> +
> if (!page_mask_bits(ce->timeline)) {
> struct intel_timeline *tl;
>
> @@ -4788,29 +4806,18 @@ static int __execlists_context_alloc(struct intel_context *ce,
> */
> if (unlikely(ce->timeline))
> tl = pinned_timeline(ce);
> - else
> + else if (intel_engine_has_semaphores(engine))
> tl = intel_timeline_create(engine->gt);
> + else
> + tl = pphwsp_timeline(ce, vma);
> if (IS_ERR(tl)) {
> ret = PTR_ERR(tl);
> - goto error_deref_obj;
> + goto error_ring_free;
> }
>
> ce->timeline = tl;
> }
>
> - ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
> - if (IS_ERR(ring)) {
> - ret = PTR_ERR(ring);
> - goto error_deref_obj;
> - }
> -
> - ret = populate_lr_context(ce, ctx_obj, engine, ring);
> - if (ret) {
> - drm_dbg(&engine->i915->drm,
> - "Failed to populate LRC: %d\n", ret);
> - goto error_ring_free;
> - }
> -
> ce->ring = ring;
> ce->state = vma;
>
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/21] drm/i915/gt: Mark legacy ring context as lost
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (19 preceding siblings ...)
2020-12-10 8:02 ` [Intel-gfx] [PATCH 21/21] drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines Chris Wilson
@ 2020-12-10 8:31 ` Patchwork
2020-12-10 8:34 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
` (4 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Patchwork @ 2020-12-10 8:31 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/21] drm/i915/gt: Mark legacy ring context as lost
URL : https://patchwork.freedesktop.org/series/84766/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1326:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1448:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1502:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread* [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [01/21] drm/i915/gt: Mark legacy ring context as lost
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (20 preceding siblings ...)
2020-12-10 8:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/21] drm/i915/gt: Mark legacy ring context as lost Patchwork
@ 2020-12-10 8:34 ` Patchwork
2020-12-10 8:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Patchwork @ 2020-12-10 8:34 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/21] drm/i915/gt: Mark legacy ring context as lost
URL : https://patchwork.freedesktop.org/series/84766/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
Error: Cannot open file ./drivers/gpu/drm/i915/gt/intel_lrc.c
WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -sphinx-version 1.7.9 -function Logical Rings, Logical Ring Contexts and Execlists ./drivers/gpu/drm/i915/gt/intel_lrc.c' failed with return code 1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/21] drm/i915/gt: Mark legacy ring context as lost
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (21 preceding siblings ...)
2020-12-10 8:34 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2020-12-10 8:59 ` Patchwork
2020-12-10 12:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
25 siblings, 0 replies; 38+ messages in thread
From: Patchwork @ 2020-12-10 8:59 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4331 bytes --]
== Series Details ==
Series: series starting with [01/21] drm/i915/gt: Mark legacy ring context as lost
URL : https://patchwork.freedesktop.org/series/84766/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9468 -> Patchwork_19107
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/index.html
Known issues
------------
Here are the changes found in Patchwork_19107 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-7500u: [PASS][1] -> [DMESG-WARN][2] ([i915#2605])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/fi-kbl-7500u/igt@core_hotunplug@unbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/fi-kbl-7500u/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#2411] / [i915#402])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
#### Possible fixes ####
* igt@prime_vgem@basic-fence-flip:
- fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 39)
------------------------------
Missing (4): fi-bdw-gvtdvm fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9468 -> Patchwork_19107
CI-20190529: 20190529
CI_DRM_9468: b7b601789c54389ad15a5a3fd68e6988bb47631e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5887: 7d87d0f1a22544e6a78dc0920b3f54b64144a029 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19107: 23c6eae80d83026d0dbd904a4b6b1fcfb4ffaf06 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
23c6eae80d83 drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines
7f388763b57e drm/i915/selftests: Exercise relative timeline modes
0f7b7ca1901c drm/i915/gt: Use indices for writing into relative timelines
e9a52574e98c drm/i915/gt: Add timeline "mode"
68c8f982084a drm/i915/gt: Track timeline GGTT offset separately from subpage offset
4dfa0ed068f5 drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb
d246335f5c21 drm/i915/gt: Track all timelines created using the HWSP
aa7ba59c3814 drm/i915: Encode fence specific waitqueue behaviour into the wait.flags
57b61c362e5f drm/i915/gt: Track the overall awake/busy time
01de5ce3e0a9 drm/i915/gem: Drop free_work for GEM contexts
c9b01159b322 drm/i915/gt: ce->inflight updates are now serialised
c6a364ebc5a1 drm/i915/gt: Simplify virtual engine handling for execlists_hold()
968bd98266ff drm/i915/gt: Resubmit the virtual engine on schedule-out
f32c95f760b7 drm/i915/gt: Shrink the critical section for irq signaling
3181e34dd98b drm/i915/gt: Remove virtual breadcrumb before transfer
327842c9688f drm/i915/gt: Defer schedule_out until after the next dequeue
d23c7763370b drm/i915/gt: Decouple inflight virtual engines
069752baaacf drm/i915/gt: Use virtual_engine during execlists_dequeue
75b288bb99a5 drm/i915/gt: Replace direct submit with direct call to tasklet
da5c590480af drm/i915/gt: Wean workaround selftests off GEM context
ba60f89ca0d5 drm/i915/gt: Mark legacy ring context as lost
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/index.html
[-- Attachment #1.2: Type: text/html, Size: 5271 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/21] drm/i915/gt: Mark legacy ring context as lost
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (22 preceding siblings ...)
2020-12-10 8:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-12-10 12:18 ` Patchwork
2020-12-10 16:39 ` [Intel-gfx] [PATCH 01/21] " Mika Kuoppala
2020-12-10 17:04 ` Matthew Brost
25 siblings, 0 replies; 38+ messages in thread
From: Patchwork @ 2020-12-10 12:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 20043 bytes --]
== Series Details ==
Series: series starting with [01/21] drm/i915/gt: Mark legacy ring context as lost
URL : https://patchwork.freedesktop.org/series/84766/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9468_full -> Patchwork_19107_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19107_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19107_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19107_full:
### IGT changes ###
#### Possible regressions ####
* igt@perf_pmu@other-init-4:
- shard-apl: [PASS][1] -> [FAIL][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-apl1/igt@perf_pmu@other-init-4.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-apl2/igt@perf_pmu@other-init-4.html
- shard-tglb: [PASS][3] -> [FAIL][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-tglb7/igt@perf_pmu@other-init-4.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-tglb8/igt@perf_pmu@other-init-4.html
- shard-glk: [PASS][5] -> [FAIL][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-glk4/igt@perf_pmu@other-init-4.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-glk6/igt@perf_pmu@other-init-4.html
- shard-skl: [PASS][7] -> [FAIL][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl1/igt@perf_pmu@other-init-4.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl9/igt@perf_pmu@other-init-4.html
- shard-hsw: [PASS][9] -> [FAIL][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-hsw4/igt@perf_pmu@other-init-4.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-hsw4/igt@perf_pmu@other-init-4.html
- shard-kbl: [PASS][11] -> [FAIL][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-kbl7/igt@perf_pmu@other-init-4.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-kbl4/igt@perf_pmu@other-init-4.html
* igt@perf_pmu@other-read-4:
- shard-snb: [PASS][13] -> [FAIL][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-snb6/igt@perf_pmu@other-read-4.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-snb7/igt@perf_pmu@other-read-4.html
- shard-iclb: [PASS][15] -> [FAIL][16] +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-iclb8/igt@perf_pmu@other-read-4.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-iclb6/igt@perf_pmu@other-read-4.html
Known issues
------------
Here are the changes found in Patchwork_19107_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][17] -> [SKIP][18] ([i915#658])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-iclb2/igt@feature_discovery@psr2.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-iclb4/igt@feature_discovery@psr2.html
* igt@gem_exec_endless@dispatch@rcs0:
- shard-kbl: [PASS][19] -> [INCOMPLETE][20] ([i915#2502])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-kbl3/igt@gem_exec_endless@dispatch@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-kbl1/igt@gem_exec_endless@dispatch@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][21] ([i915#2389])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-iclb4/igt@gem_exec_reloc@basic-wide-active@vcs1.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: [PASS][22] -> [FAIL][23] ([i915#454])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl5/igt@i915_pm_dc@dc6-psr.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl6/igt@i915_pm_dc@dc6-psr.html
* igt@kms_chamelium@hdmi-audio:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl3/igt@kms_chamelium@hdmi-audio.html
* igt@kms_color@pipe-c-ctm-0-5:
- shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl5/igt@kms_color@pipe-c-ctm-0-5.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl6/igt@kms_color@pipe-c-ctm-0-5.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-random:
- shard-skl: [PASS][27] -> [FAIL][28] ([i915#54]) +4 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-hsw: NOTRUN -> [INCOMPLETE][31] ([i915#2295])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-hsw4/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#79])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
- shard-hsw: [PASS][34] -> [INCOMPLETE][35] ([i915#2295])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-hsw6/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-hsw2/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
* igt@kms_flip@plain-flip-fb-recreate@a-edp1:
- shard-skl: [PASS][36] -> [FAIL][37] ([i915#2122])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl5/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-skl: NOTRUN -> [SKIP][38] ([fdo#109271]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl3/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-skl: [PASS][39] -> [FAIL][40] ([i915#53])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl5/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][41] -> [FAIL][42] ([fdo#108145] / [i915#265]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109642] / [fdo#111068])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-iclb2/igt@kms_psr2_su@page_flip.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-iclb1/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [PASS][45] -> [SKIP][46] ([fdo#109441]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-skl: [PASS][47] -> [INCOMPLETE][48] ([i915#198] / [i915#2295])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: [PASS][49] -> [INCOMPLETE][50] ([i915#198] / [i915#2405])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl6/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl10/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
#### Possible fixes ####
* igt@gem_eio@in-flight-contexts-10ms:
- shard-hsw: [TIMEOUT][51] ([i915#1037] / [i915#1976]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-hsw4/igt@gem_eio@in-flight-contexts-10ms.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-hsw4/igt@gem_eio@in-flight-contexts-10ms.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-hsw: [WARN][53] ([i915#1519]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-hsw4/igt@i915_pm_rc6_residency@rc6-fence.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-hsw4/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [FAIL][55] ([i915#2521]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl3/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen:
- shard-skl: [FAIL][57] ([i915#54]) -> [PASS][58] +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
* igt@kms_draw_crc@fill-fb:
- shard-iclb: [FAIL][59] ([i915#52]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-iclb6/igt@kms_draw_crc@fill-fb.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-iclb7/igt@kms_draw_crc@fill-fb.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [FAIL][61] ([i915#79]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
- shard-glk: [FAIL][63] ([i915#79]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-glk4/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
- shard-skl: [FAIL][65] ([i915#2122]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf@polling-parameterized:
- shard-glk: [FAIL][69] ([i915#1542]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-glk6/igt@perf@polling-parameterized.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-glk3/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][71] ([i915#658]) -> [SKIP][72] ([i915#588])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][73] ([i915#2681] / [i915#2684]) -> [WARN][74] ([i915#1804] / [i915#2684]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-kbl: [INCOMPLETE][75] ([i915#155]) -> [DMESG-WARN][76] ([i915#1602])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-kbl4/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-kbl7/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
* igt@runner@aborted:
- shard-kbl: [FAIL][77] ([i915#2295] / [i915#2722] / [i915#483]) -> ([FAIL][78], [FAIL][79], [FAIL][80]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#483] / [i915#602])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-kbl2/igt@runner@aborted.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-kbl6/igt@runner@aborted.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-kbl7/igt@runner@aborted.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-kbl7/igt@runner@aborted.html
- shard-iclb: ([FAIL][81], [FAIL][82]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#2724] / [i915#483]) -> ([FAIL][83], [FAIL][84]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#2724])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-iclb8/igt@runner@aborted.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-iclb4/igt@runner@aborted.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-iclb3/igt@runner@aborted.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-iclb4/igt@runner@aborted.html
- shard-glk: ([FAIL][85], [FAIL][86]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#483] / [k.org#202321]) -> ([FAIL][87], [FAIL][88]) ([i915#1814] / [i915#2295] / [i915#2722] / [k.org#202321])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-glk3/igt@runner@aborted.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-glk2/igt@runner@aborted.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-glk1/igt@runner@aborted.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-glk1/igt@runner@aborted.html
- shard-skl: [FAIL][89] ([i915#2295] / [i915#2722]) -> ([FAIL][90], [FAIL][91]) ([i915#2029] / [i915#2295] / [i915#2722] / [i915#483])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-skl1/igt@runner@aborted.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl3/igt@runner@aborted.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/shard-skl9/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
[i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1976]: https://gitlab.freedesktop.org/drm/intel/issues/1976
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9468 -> Patchwork_19107
CI-20190529: 20190529
CI_DRM_9468: b7b601789c54389ad15a5a3fd68e6988bb47631e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5887: 7d87d0f1a22544e6a78dc0920b3f54b64144a029 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19107: 23c6eae80d83026d0dbd904a4b6b1fcfb4ffaf06 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19107/index.html
[-- Attachment #1.2: Type: text/html, Size: 24293 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (23 preceding siblings ...)
2020-12-10 12:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-12-10 16:39 ` Mika Kuoppala
2020-12-10 17:04 ` Matthew Brost
25 siblings, 0 replies; 38+ messages in thread
From: Mika Kuoppala @ 2020-12-10 16:39 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> When we reset the legacy ring context, due to potential corruption over
> suspend/resume, remove the valid bit so that we avoid loading garbage.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index a41b43f445b8..1959e3e5b8e9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -602,6 +602,7 @@ static int ring_context_pin(struct intel_context *ce, void *unused)
> static void ring_context_reset(struct intel_context *ce)
> {
> intel_ring_reset(ce->ring, ce->ring->emit);
> + __clear_bit(CONTEXT_VALID_BIT, &ce->flags);
> }
>
> static const struct intel_context_ops ring_context_ops = {
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost
2020-12-10 8:02 [Intel-gfx] [PATCH 01/21] drm/i915/gt: Mark legacy ring context as lost Chris Wilson
` (24 preceding siblings ...)
2020-12-10 16:39 ` [Intel-gfx] [PATCH 01/21] " Mika Kuoppala
@ 2020-12-10 17:04 ` Matthew Brost
25 siblings, 0 replies; 38+ messages in thread
From: Matthew Brost @ 2020-12-10 17:04 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Dec 10, 2020 at 08:02:20AM +0000, Chris Wilson wrote:
> When we reset the legacy ring context, due to potential corruption over
> suspend/resume, remove the valid bit so that we avoid loading garbage.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index a41b43f445b8..1959e3e5b8e9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -602,6 +602,7 @@ static int ring_context_pin(struct intel_context *ce, void *unused)
> static void ring_context_reset(struct intel_context *ce)
> {
> intel_ring_reset(ce->ring, ce->ring->emit);
> + __clear_bit(CONTEXT_VALID_BIT, &ce->flags);
> }
>
> static const struct intel_context_ops ring_context_ops = {
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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