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From: Keith Packard via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Keith Packard" <keithp@keithp.com>,
	qemu-riscv@nongnu.org,
	"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
	"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
	"Laurent Vivier" <laurent@vivier.eu>,
	qemu-arm@nongnu.org,
	"Alistair Francis" <Alistair.Francis@wdc.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Kito Cheng" <kito.cheng@sifive.com>,
	"Alex Bennée" <alex.bennee@linaro.org>
Subject: [PATCH 6/9] riscv: Add semihosting support for user mode
Date: Mon, 14 Dec 2020 12:07:10 -0800	[thread overview]
Message-ID: <20201214200713.3886611-7-keithp@keithp.com> (raw)
In-Reply-To: <20201214200713.3886611-1-keithp@keithp.com>

From: Kito Cheng <kito.cheng@sifive.com>

This could made testing more easier and ARM/AArch64 has supported on
their linux user mode too, so I think it should be reasonable.

Verified GCC testsuite with newlib/semihosting.

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
---
 linux-user/riscv/cpu_loop.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index aa9e437875..9665dabb09 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -23,6 +23,7 @@
 #include "qemu.h"
 #include "cpu_loop-common.h"
 #include "elf.h"
+#include "hw/semihosting/common-semi.h"
 
 void cpu_loop(CPURISCVState *env)
 {
@@ -91,6 +92,10 @@ void cpu_loop(CPURISCVState *env)
             sigcode = TARGET_SEGV_MAPERR;
             sigaddr = env->badaddr;
             break;
+        case RISCV_EXCP_SEMIHOST:
+            env->gpr[xA0] = do_common_semihosting(cs);
+            env->pc += 4;
+            break;
         case EXCP_DEBUG:
         gdbstep:
             signum = TARGET_SIGTRAP;
-- 
2.29.2



WARNING: multiple messages have this Message-ID (diff)
From: Keith Packard <keithp@keithp.com>
To: qemu-devel@nongnu.org
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
	"Alistair Francis" <Alistair.Francis@wdc.com>,
	"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
	"Laurent Vivier" <laurent@vivier.eu>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, qemu-riscv@nongnu.org,
	"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
	"Kito Cheng" <kito.cheng@sifive.com>,
	"Keith Packard" <keithp@keithp.com>
Subject: [PATCH 6/9] riscv: Add semihosting support for user mode
Date: Mon, 14 Dec 2020 12:07:10 -0800	[thread overview]
Message-ID: <20201214200713.3886611-7-keithp@keithp.com> (raw)
In-Reply-To: <20201214200713.3886611-1-keithp@keithp.com>

From: Kito Cheng <kito.cheng@sifive.com>

This could made testing more easier and ARM/AArch64 has supported on
their linux user mode too, so I think it should be reasonable.

Verified GCC testsuite with newlib/semihosting.

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
---
 linux-user/riscv/cpu_loop.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index aa9e437875..9665dabb09 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -23,6 +23,7 @@
 #include "qemu.h"
 #include "cpu_loop-common.h"
 #include "elf.h"
+#include "hw/semihosting/common-semi.h"
 
 void cpu_loop(CPURISCVState *env)
 {
@@ -91,6 +92,10 @@ void cpu_loop(CPURISCVState *env)
             sigcode = TARGET_SEGV_MAPERR;
             sigaddr = env->badaddr;
             break;
+        case RISCV_EXCP_SEMIHOST:
+            env->gpr[xA0] = do_common_semihosting(cs);
+            env->pc += 4;
+            break;
         case EXCP_DEBUG:
         gdbstep:
             signum = TARGET_SIGTRAP;
-- 
2.29.2



  parent reply	other threads:[~2020-12-14 20:13 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-25 21:36 [PATCH 0/8] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 Keith Packard via
2020-11-25 21:36 ` Keith Packard
2020-11-25 21:36 ` [PATCH 1/8] semihosting: Move ARM semihosting code to shared directories [v3] Keith Packard via
2020-11-25 21:36   ` Keith Packard
2020-11-25 21:36 ` [PATCH 2/8] semihosting: Change common-semi API to be architecture-independent Keith Packard via
2020-11-25 21:36   ` Keith Packard
2020-11-25 21:36 ` [PATCH 3/8] semihosting: Change internal common-semi interfaces to use CPUState * [v2] Keith Packard via
2020-11-25 21:36   ` Keith Packard
2020-11-25 21:36 ` [PATCH 4/8] semihosting: Support SYS_HEAPINFO when env->boot_info is not set Keith Packard via
2020-11-25 21:36   ` Keith Packard
2020-11-25 21:36 ` [PATCH 5/8] riscv: Add semihosting support [v13] Keith Packard via
2020-11-25 21:36   ` Keith Packard
2020-12-09  7:58   ` Kito Cheng
2020-12-09  7:58     ` Kito Cheng
2020-12-09 16:29     ` Keith Packard via
2020-12-09 16:29       ` Keith Packard
2020-12-10  3:39       ` Kito Cheng
2020-12-10  3:39         ` Kito Cheng
2020-12-10  6:21         ` Keith Packard via
2020-12-10  6:21           ` Keith Packard
2020-12-14 11:29         ` Alex Bennée
2020-12-14 11:29           ` Alex Bennée
2020-11-25 21:36 ` [PATCH 6/8] semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ Keith Packard via
2020-11-25 21:36   ` Keith Packard
2020-11-25 21:36 ` [PATCH 7/8] semihosting: Implement SYS_TMPNAM Keith Packard via
2020-11-25 21:36   ` Keith Packard
2020-11-25 21:36 ` [PATCH 8/8] semihosting: Implement SYS_ISERROR Keith Packard via
2020-11-25 21:36   ` Keith Packard
2020-12-14 11:24 ` [PATCH 0/8] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 Alex Bennée
2020-12-14 11:24   ` Alex Bennée
2020-12-14 14:58   ` Alex Bennée
2020-12-14 14:58     ` Alex Bennée
2020-12-14 20:06     ` Keith Packard via
2020-12-14 20:06       ` Keith Packard
2020-12-14 20:07     ` [PATCH 0/9] " Keith Packard via
2020-12-14 20:07       ` Keith Packard
2020-12-14 20:07       ` [PATCH 1/9] semihosting: Move ARM semihosting code to shared directories Keith Packard via
2020-12-14 20:07         ` Keith Packard
2020-12-14 20:07       ` [PATCH 2/9] semihosting: Change common-semi API to be architecture-independent Keith Packard via
2020-12-14 20:07         ` Keith Packard
2020-12-14 20:07       ` [PATCH 3/9] semihosting: Change internal common-semi interfaces to use CPUState * Keith Packard via
2020-12-14 20:07         ` Keith Packard
2020-12-14 20:07       ` [PATCH 4/9] semihosting: Support SYS_HEAPINFO when env->boot_info is not set Keith Packard via
2020-12-14 20:07         ` Keith Packard
2020-12-14 20:07       ` [PATCH 5/9] riscv: Add semihosting support Keith Packard via
2020-12-14 20:07         ` Keith Packard
2020-12-14 20:07       ` Keith Packard via [this message]
2020-12-14 20:07         ` [PATCH 6/9] riscv: Add semihosting support for user mode Keith Packard
2020-12-14 20:07       ` [PATCH 7/9] semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ Keith Packard via
2020-12-14 20:07         ` Keith Packard
2020-12-14 20:07       ` [PATCH 8/9] semihosting: Implement SYS_TMPNAM Keith Packard via
2020-12-14 20:07         ` Keith Packard
2020-12-14 20:07       ` [PATCH 9/9] semihosting: Implement SYS_ISERROR Keith Packard via
2020-12-14 20:07         ` Keith Packard
2021-01-07 17:07 [PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 Keith Packard via
2021-01-07 17:07 ` [PATCH 6/9] riscv: Add semihosting support for user mode Keith Packard via
2021-01-07 17:07   ` Keith Packard

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