* [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Measure timeslice distribution when oversaturated
@ 2020-12-14 20:44 ` Chris Wilson
0 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2020-12-14 20:44 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Chris Wilson
Check that timeslices for an oversaturated system (where there is more
work than can be supported by a single engine) are evenly distributed
between the clients.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
tests/i915/gem_exec_schedule.c | 179 +++++++++++++++++++++++++++++++++
1 file changed, 179 insertions(+)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index f23d63ac3..263f1dd78 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -2516,6 +2516,154 @@ static void measure_semaphore_power(int i915)
rapl_close(&pkg);
}
+static int read_timestamp_frequency(int i915)
+{
+ int value = 0;
+ drm_i915_getparam_t gp = {
+ .value = &value,
+ .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
+ };
+ ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp);
+ return value;
+}
+
+static uint64_t div64_u64_round_up(uint64_t x, uint64_t y)
+{
+ return (x + y - 1) / y;
+}
+
+static uint64_t ticks_to_ns(int i915, uint64_t ticks)
+{
+ return div64_u64_round_up(ticks * NSEC_PER_SEC,
+ read_timestamp_frequency(i915));
+}
+
+static int cmp_u32(const void *A, const void *B)
+{
+ const uint32_t *a = A, *b = B;
+
+ if (*a < *b)
+ return -1;
+ else if (*a > *b)
+ return 1;
+ else
+ return 0;
+}
+
+static uint32_t read_ctx_timestamp(int i915,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e)
+{
+ const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
+ const uint32_t base = gem_engine_mmio_base(i915, e->name);
+ struct drm_i915_gem_relocation_entry reloc;
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = gem_create(i915, 4096),
+ .offset = 32 << 20,
+ .relocs_ptr = to_user_pointer(&reloc),
+ .relocation_count = 1,
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&obj),
+ .buffer_count = 1,
+ .flags = e->flags,
+ .rsvd1 = ctx,
+ };
+#define RUNTIME (base + 0x3a8)
+ uint32_t *map, *cs;
+ uint32_t ts;
+
+ igt_require(base);
+
+ cs = map = gem_mmap__device_coherent(i915, obj.handle,
+ 0, 4096, PROT_WRITE);
+
+ *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
+ *cs++ = RUNTIME;
+ memset(&reloc, 0, sizeof(reloc));
+ reloc.target_handle = obj.handle;
+ reloc.presumed_offset = obj.offset;
+ reloc.offset = offset_in_page(cs);
+ reloc.delta = 4000;
+ *cs++ = obj.offset + 4000;
+ *cs++ = obj.offset >> 32;
+
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ gem_execbuf(i915, &execbuf);
+ gem_sync(i915, obj.handle);
+ gem_close(i915, obj.handle);
+
+ ts = map[1000];
+ munmap(map, 4096);
+
+ return ts;
+}
+
+static void fairslice(int i915,
+ const struct intel_execution_engine2 *e,
+ unsigned long flags,
+ int duration)
+{
+ const double timeslice_duration_ns = 1e6;
+ igt_spin_t *spin = NULL;
+ double threshold;
+ uint32_t ctx[3];
+ uint32_t ts[3];
+
+ for (int i = 0; i < ARRAY_SIZE(ctx); i++) {
+ ctx[i] = gem_context_clone_with_engines(i915, 0);
+ if (spin == NULL) {
+ spin = __igt_spin_new(i915,
+ .ctx = ctx[i],
+ .engine = e->flags,
+ .flags = flags);
+ } else {
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = 1,
+ .buffers_ptr = to_user_pointer(&spin->obj[IGT_SPIN_BATCH]),
+ .flags = e->flags,
+ .rsvd1 = ctx[i],
+ };
+ gem_execbuf(i915, &eb);
+ }
+ }
+
+ sleep(duration); /* over the course of many timeslices */
+
+ igt_assert(gem_bo_busy(i915, spin->handle));
+ igt_spin_end(spin);
+ for (int i = 0; i < ARRAY_SIZE(ctx); i++)
+ ts[i] = read_ctx_timestamp(i915, ctx[i], e);
+
+ for (int i = 0; i < ARRAY_SIZE(ctx); i++)
+ gem_context_destroy(i915, ctx[i]);
+ igt_spin_free(i915, spin);
+
+ /*
+ * If we imagine that the timeslices are randomly distributed to
+ * the virtual engines, we would expect the variation to be modelled
+ * by a drunken walk; ergo sqrt(num_timeslices).
+ */
+ threshold = sqrt(1e9 * duration / timeslice_duration_ns);
+ threshold *= timeslice_duration_ns;
+ threshold *= 2; /* CI safety factor before crying wolf */
+
+ qsort(ts, 3, sizeof(*ts), cmp_u32);
+ igt_info("%s: [%.1f, %.1f, %.1f] ms, expect %1.f +- %.1fms\n", e->name,
+ 1e-6 * ticks_to_ns(i915, ts[0]),
+ 1e-6 * ticks_to_ns(i915, ts[1]),
+ 1e-6 * ticks_to_ns(i915, ts[2]),
+ 1e3 * duration / 3,
+ 1e-6 * threshold);
+
+ igt_assert_f(ts[2], "CTX_TIMESTAMP not reported!\n");
+ igt_assert_f(ticks_to_ns(i915, ts[2] - ts[0]) < 2 * threshold,
+ "Range of timeslices greater than tolerable: %.2fms > %.2fms; unfair!\n",
+ 1e-6 * ticks_to_ns(i915, ts[2] - ts[0]),
+ 1e-6 * threshold * 2);
+}
+
#define test_each_engine(T, i915, e) \
igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
igt_dynamic_f("%s", e->name)
@@ -2582,6 +2730,37 @@ igt_main
test_each_engine("lateslice", fd, e)
lateslice(fd, e->flags);
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(gem_scheduler_has_semaphores(fd));
+ igt_require(gem_scheduler_has_preemption(fd));
+ igt_require(intel_gen(intel_get_drm_devid(fd)) >= 8);
+ }
+
+ test_each_engine("fairslice", fd, e)
+ fairslice(fd, e, 0, 2);
+
+ test_each_engine("u-fairslice", fd, e)
+ fairslice(fd, e, IGT_SPIN_USERPTR, 2);
+
+ igt_subtest("fairslice-all") {
+ __for_each_physical_engine(fd, e) {
+ igt_fork(child, 1)
+ fairslice(fd, e, 0, 2);
+ }
+ igt_waitchildren();
+ }
+ igt_subtest("u-fairslice-all") {
+ __for_each_physical_engine(fd, e) {
+ igt_fork(child, 1)
+ fairslice(fd, e,
+ IGT_SPIN_USERPTR,
+ 2);
+ }
+ igt_waitchildren();
+ }
+ }
+
test_each_engine("submit-early-slice", fd, e)
submit_slice(fd, e, EARLY_SUBMIT);
test_each_engine("submit-golden-slice", fd, e)
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Measure timeslice distribution when oversaturated
@ 2020-12-14 20:44 ` Chris Wilson
0 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2020-12-14 20:44 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Tvrtko Ursulin, Chris Wilson
Check that timeslices for an oversaturated system (where there is more
work than can be supported by a single engine) are evenly distributed
between the clients.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
tests/i915/gem_exec_schedule.c | 179 +++++++++++++++++++++++++++++++++
1 file changed, 179 insertions(+)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index f23d63ac3..263f1dd78 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -2516,6 +2516,154 @@ static void measure_semaphore_power(int i915)
rapl_close(&pkg);
}
+static int read_timestamp_frequency(int i915)
+{
+ int value = 0;
+ drm_i915_getparam_t gp = {
+ .value = &value,
+ .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
+ };
+ ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp);
+ return value;
+}
+
+static uint64_t div64_u64_round_up(uint64_t x, uint64_t y)
+{
+ return (x + y - 1) / y;
+}
+
+static uint64_t ticks_to_ns(int i915, uint64_t ticks)
+{
+ return div64_u64_round_up(ticks * NSEC_PER_SEC,
+ read_timestamp_frequency(i915));
+}
+
+static int cmp_u32(const void *A, const void *B)
+{
+ const uint32_t *a = A, *b = B;
+
+ if (*a < *b)
+ return -1;
+ else if (*a > *b)
+ return 1;
+ else
+ return 0;
+}
+
+static uint32_t read_ctx_timestamp(int i915,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e)
+{
+ const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
+ const uint32_t base = gem_engine_mmio_base(i915, e->name);
+ struct drm_i915_gem_relocation_entry reloc;
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = gem_create(i915, 4096),
+ .offset = 32 << 20,
+ .relocs_ptr = to_user_pointer(&reloc),
+ .relocation_count = 1,
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&obj),
+ .buffer_count = 1,
+ .flags = e->flags,
+ .rsvd1 = ctx,
+ };
+#define RUNTIME (base + 0x3a8)
+ uint32_t *map, *cs;
+ uint32_t ts;
+
+ igt_require(base);
+
+ cs = map = gem_mmap__device_coherent(i915, obj.handle,
+ 0, 4096, PROT_WRITE);
+
+ *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
+ *cs++ = RUNTIME;
+ memset(&reloc, 0, sizeof(reloc));
+ reloc.target_handle = obj.handle;
+ reloc.presumed_offset = obj.offset;
+ reloc.offset = offset_in_page(cs);
+ reloc.delta = 4000;
+ *cs++ = obj.offset + 4000;
+ *cs++ = obj.offset >> 32;
+
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ gem_execbuf(i915, &execbuf);
+ gem_sync(i915, obj.handle);
+ gem_close(i915, obj.handle);
+
+ ts = map[1000];
+ munmap(map, 4096);
+
+ return ts;
+}
+
+static void fairslice(int i915,
+ const struct intel_execution_engine2 *e,
+ unsigned long flags,
+ int duration)
+{
+ const double timeslice_duration_ns = 1e6;
+ igt_spin_t *spin = NULL;
+ double threshold;
+ uint32_t ctx[3];
+ uint32_t ts[3];
+
+ for (int i = 0; i < ARRAY_SIZE(ctx); i++) {
+ ctx[i] = gem_context_clone_with_engines(i915, 0);
+ if (spin == NULL) {
+ spin = __igt_spin_new(i915,
+ .ctx = ctx[i],
+ .engine = e->flags,
+ .flags = flags);
+ } else {
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = 1,
+ .buffers_ptr = to_user_pointer(&spin->obj[IGT_SPIN_BATCH]),
+ .flags = e->flags,
+ .rsvd1 = ctx[i],
+ };
+ gem_execbuf(i915, &eb);
+ }
+ }
+
+ sleep(duration); /* over the course of many timeslices */
+
+ igt_assert(gem_bo_busy(i915, spin->handle));
+ igt_spin_end(spin);
+ for (int i = 0; i < ARRAY_SIZE(ctx); i++)
+ ts[i] = read_ctx_timestamp(i915, ctx[i], e);
+
+ for (int i = 0; i < ARRAY_SIZE(ctx); i++)
+ gem_context_destroy(i915, ctx[i]);
+ igt_spin_free(i915, spin);
+
+ /*
+ * If we imagine that the timeslices are randomly distributed to
+ * the virtual engines, we would expect the variation to be modelled
+ * by a drunken walk; ergo sqrt(num_timeslices).
+ */
+ threshold = sqrt(1e9 * duration / timeslice_duration_ns);
+ threshold *= timeslice_duration_ns;
+ threshold *= 2; /* CI safety factor before crying wolf */
+
+ qsort(ts, 3, sizeof(*ts), cmp_u32);
+ igt_info("%s: [%.1f, %.1f, %.1f] ms, expect %1.f +- %.1fms\n", e->name,
+ 1e-6 * ticks_to_ns(i915, ts[0]),
+ 1e-6 * ticks_to_ns(i915, ts[1]),
+ 1e-6 * ticks_to_ns(i915, ts[2]),
+ 1e3 * duration / 3,
+ 1e-6 * threshold);
+
+ igt_assert_f(ts[2], "CTX_TIMESTAMP not reported!\n");
+ igt_assert_f(ticks_to_ns(i915, ts[2] - ts[0]) < 2 * threshold,
+ "Range of timeslices greater than tolerable: %.2fms > %.2fms; unfair!\n",
+ 1e-6 * ticks_to_ns(i915, ts[2] - ts[0]),
+ 1e-6 * threshold * 2);
+}
+
#define test_each_engine(T, i915, e) \
igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
igt_dynamic_f("%s", e->name)
@@ -2582,6 +2730,37 @@ igt_main
test_each_engine("lateslice", fd, e)
lateslice(fd, e->flags);
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(gem_scheduler_has_semaphores(fd));
+ igt_require(gem_scheduler_has_preemption(fd));
+ igt_require(intel_gen(intel_get_drm_devid(fd)) >= 8);
+ }
+
+ test_each_engine("fairslice", fd, e)
+ fairslice(fd, e, 0, 2);
+
+ test_each_engine("u-fairslice", fd, e)
+ fairslice(fd, e, IGT_SPIN_USERPTR, 2);
+
+ igt_subtest("fairslice-all") {
+ __for_each_physical_engine(fd, e) {
+ igt_fork(child, 1)
+ fairslice(fd, e, 0, 2);
+ }
+ igt_waitchildren();
+ }
+ igt_subtest("u-fairslice-all") {
+ __for_each_physical_engine(fd, e) {
+ igt_fork(child, 1)
+ fairslice(fd, e,
+ IGT_SPIN_USERPTR,
+ 2);
+ }
+ igt_waitchildren();
+ }
+ }
+
test_each_engine("submit-early-slice", fd, e)
submit_slice(fd, e, EARLY_SUBMIT);
test_each_engine("submit-golden-slice", fd, e)
--
2.29.2
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_exec_schedule: Measure timeslice distribution when oversaturated
2020-12-14 20:44 ` [igt-dev] " Chris Wilson
(?)
@ 2020-12-14 21:20 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-12-14 21:20 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 3989 bytes --]
== Series Details ==
Series: i915/gem_exec_schedule: Measure timeslice distribution when oversaturated
URL : https://patchwork.freedesktop.org/series/84917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9482 -> IGTPW_5288
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/index.html
Known issues
------------
Here are the changes found in IGTPW_5288 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s0:
- fi-snb-2600: [PASS][3] -> [DMESG-WARN][4] ([i915#2772])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/fi-snb-2600/igt@gem_exec_suspend@basic-s0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/fi-snb-2600/igt@gem_exec_suspend@basic-s0.html
* igt@i915_selftest@live@execlists:
- fi-icl-y: [PASS][5] -> [INCOMPLETE][6] ([i915#1037] / [i915#2089] / [i915#2276])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/fi-icl-y/igt@i915_selftest@live@execlists.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/fi-icl-y/igt@i915_selftest@live@execlists.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-bdw-5557u: NOTRUN -> [SKIP][7] ([fdo#109271]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/fi-bdw-5557u/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html
* igt@runner@aborted:
- fi-snb-2600: NOTRUN -> [FAIL][9] ([i915#698])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/fi-snb-2600/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_flink_basic@bad-flink:
- fi-tgl-y: [DMESG-WARN][10] ([i915#402]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/fi-tgl-y/igt@gem_flink_basic@bad-flink.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/fi-tgl-y/igt@gem_flink_basic@bad-flink.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
[i915#2089]: https://gitlab.freedesktop.org/drm/intel/issues/2089
[i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276
[i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#698]: https://gitlab.freedesktop.org/drm/intel/issues/698
Participating hosts (43 -> 37)
------------------------------
Missing (6): fi-hsw-4200u fi-byt-j1900 fi-bsw-cyan fi-ctg-p8600 fi-dg1-1 fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5894 -> IGTPW_5288
CI-20190529: 20190529
CI_DRM_9482: 279e4ca8a7117e617c498833deaa287b797e7d09 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5288: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/index.html
IGT_5894: a668d5c148ec3c1d3958f660a146a88676aac25d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@gem_exec_schedule@fairslice
+igt@gem_exec_schedule@fairslice-all
+igt@gem_exec_schedule@u-fairslice
+igt@gem_exec_schedule@u-fairslice-all
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/index.html
[-- Attachment #1.2: Type: text/html, Size: 4899 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for i915/gem_exec_schedule: Measure timeslice distribution when oversaturated
2020-12-14 20:44 ` [igt-dev] " Chris Wilson
(?)
(?)
@ 2020-12-14 22:50 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-12-14 22:50 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 30288 bytes --]
== Series Details ==
Series: i915/gem_exec_schedule: Measure timeslice distribution when oversaturated
URL : https://patchwork.freedesktop.org/series/84917/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9482_full -> IGTPW_5288_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_5288_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_5288_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_5288_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_request_retire@retire-vma-not-inactive:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-iclb8/igt@gem_request_retire@retire-vma-not-inactive.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb6/igt@gem_request_retire@retire-vma-not-inactive.html
New tests
---------
New tests have been introduced between CI_DRM_9482_full and IGTPW_5288_full:
### New IGT tests (14) ###
* igt@gem_exec_schedule@fairslice:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fairslice-all:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 2.12] s
* igt@gem_exec_schedule@fairslice@bcs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.04] s
* igt@gem_exec_schedule@fairslice@rcs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.03] s
* igt@gem_exec_schedule@fairslice@vcs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.03] s
* igt@gem_exec_schedule@fairslice@vcs1:
- Statuses : 3 pass(s)
- Exec time: [2.01, 2.02] s
* igt@gem_exec_schedule@fairslice@vecs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.03] s
* igt@gem_exec_schedule@u-fairslice:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-fairslice-all:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 2.10] s
* igt@gem_exec_schedule@u-fairslice@bcs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.03] s
* igt@gem_exec_schedule@u-fairslice@rcs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.02] s
* igt@gem_exec_schedule@u-fairslice@vcs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.03] s
* igt@gem_exec_schedule@u-fairslice@vcs1:
- Statuses : 3 pass(s)
- Exec time: [2.01] s
* igt@gem_exec_schedule@u-fairslice@vecs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.03] s
Known issues
------------
Here are the changes found in IGTPW_5288_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@hostile:
- shard-hsw: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-hsw7/igt@gem_ctx_persistence@hostile.html
* igt@gem_ctx_sseu@invalid-args:
- shard-apl: NOTRUN -> [SKIP][4] ([fdo#109271]) +38 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-apl3/igt@gem_ctx_sseu@invalid-args.html
- shard-tglb: NOTRUN -> [SKIP][5] ([i915#280])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb1/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_exec_params@secure-non-root:
- shard-tglb: NOTRUN -> [SKIP][6] ([fdo#112283])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb5/igt@gem_exec_params@secure-non-root.html
- shard-iclb: NOTRUN -> [SKIP][7] ([fdo#112283])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb7/igt@gem_exec_params@secure-non-root.html
* {igt@gem_exec_schedule@u-fairslice-all} (NEW):
- shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-snb7/igt@gem_exec_schedule@u-fairslice-all.html
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118] / [i915#95]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-glk3/igt@gem_exec_whisper@basic-queues-forked-all.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-glk1/igt@gem_exec_whisper@basic-queues-forked-all.html
* igt@gem_pwrite@basic-exhaustion:
- shard-iclb: NOTRUN -> [WARN][11] ([i915#2658])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb8/igt@gem_pwrite@basic-exhaustion.html
- shard-kbl: NOTRUN -> [WARN][12] ([i915#2658])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-kbl6/igt@gem_pwrite@basic-exhaustion.html
- shard-apl: NOTRUN -> [WARN][13] ([i915#2658])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-apl3/igt@gem_pwrite@basic-exhaustion.html
- shard-tglb: NOTRUN -> [WARN][14] ([i915#2658])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb8/igt@gem_pwrite@basic-exhaustion.html
- shard-glk: NOTRUN -> [WARN][15] ([i915#2658])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-glk4/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@mmap-offset-invalidate-idle@gtt:
- shard-tglb: NOTRUN -> [SKIP][16] ([i915#1317]) +3 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb5/igt@gem_userptr_blits@mmap-offset-invalidate-idle@gtt.html
* igt@gem_userptr_blits@mmap-offset-invalidate-idle@uc:
- shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271]) +37 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-kbl6/igt@gem_userptr_blits@mmap-offset-invalidate-idle@uc.html
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#1317]) +3 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb7/igt@gem_userptr_blits@mmap-offset-invalidate-idle@uc.html
* igt@gem_userptr_blits@mmap-offset-invalidate-idle@wb:
- shard-glk: NOTRUN -> [SKIP][19] ([fdo#109271]) +31 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-glk2/igt@gem_userptr_blits@mmap-offset-invalidate-idle@wb.html
* igt@gem_workarounds@suspend-resume:
- shard-glk: [PASS][20] -> [DMESG-WARN][21] ([i915#1602] / [i915#2635])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-glk6/igt@gem_workarounds@suspend-resume.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-glk2/igt@gem_workarounds@suspend-resume.html
- shard-iclb: [PASS][22] -> [DMESG-WARN][23] ([i915#1602])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-iclb3/igt@gem_workarounds@suspend-resume.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb7/igt@gem_workarounds@suspend-resume.html
- shard-apl: [PASS][24] -> [DMESG-WARN][25] ([i915#1602] / [i915#2635])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-apl6/igt@gem_workarounds@suspend-resume.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-apl4/igt@gem_workarounds@suspend-resume.html
- shard-kbl: [PASS][26] -> [INCOMPLETE][27] ([i915#155])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-kbl2/igt@gem_workarounds@suspend-resume.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-kbl6/igt@gem_workarounds@suspend-resume.html
- shard-hsw: [PASS][28] -> [DMESG-WARN][29] ([i915#2637])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-hsw7/igt@gem_workarounds@suspend-resume.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-hsw4/igt@gem_workarounds@suspend-resume.html
* igt@gen9_exec_parse@bb-start-param:
- shard-tglb: NOTRUN -> [SKIP][30] ([fdo#112306])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb5/igt@gen9_exec_parse@bb-start-param.html
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#112306])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb2/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: NOTRUN -> [WARN][32] ([i915#2681])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb8/igt@i915_pm_rc6_residency@rc6-fence.html
- shard-iclb: NOTRUN -> [WARN][33] ([i915#1804] / [i915#2684])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb3/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rpm@fences-dpms:
- shard-kbl: [PASS][34] -> [SKIP][35] ([fdo#109271])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-kbl7/igt@i915_pm_rpm@fences-dpms.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-kbl6/igt@i915_pm_rpm@fences-dpms.html
- shard-hsw: [PASS][36] -> [SKIP][37] ([fdo#109271])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-hsw7/igt@i915_pm_rpm@fences-dpms.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-hsw4/igt@i915_pm_rpm@fences-dpms.html
- shard-glk: [PASS][38] -> [SKIP][39] ([fdo#109271])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-glk7/igt@i915_pm_rpm@fences-dpms.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-glk2/igt@i915_pm_rpm@fences-dpms.html
- shard-apl: [PASS][40] -> [SKIP][41] ([fdo#109271])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-apl2/igt@i915_pm_rpm@fences-dpms.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-apl4/igt@i915_pm_rpm@fences-dpms.html
- shard-iclb: [PASS][42] -> [SKIP][43] ([i915#579])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-iclb5/igt@i915_pm_rpm@fences-dpms.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb7/igt@i915_pm_rpm@fences-dpms.html
* igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing:
- shard-tglb: NOTRUN -> [SKIP][44] ([fdo#112016] / [fdo#112025])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb7/igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
- shard-tglb: NOTRUN -> [SKIP][45] ([fdo#111615]) +4 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb7/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#110723]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb2/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-hsw: NOTRUN -> [SKIP][47] ([fdo#109271]) +75 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-hsw4/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-glk: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-glk3/igt@kms_chamelium@dp-hpd-storm-disable.html
- shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-apl3/igt@kms_chamelium@dp-hpd-storm-disable.html
* igt@kms_chamelium@hdmi-hpd-with-enabled-mode:
- shard-kbl: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +3 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-kbl6/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html
* igt@kms_color_chamelium@pipe-c-ctm-0-5:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109284] / [fdo#111827]) +4 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb4/igt@kms_color_chamelium@pipe-c-ctm-0-5.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-tglb: NOTRUN -> [SKIP][52] ([fdo#109284] / [fdo#111827]) +5 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb2/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
- shard-iclb: NOTRUN -> [SKIP][53] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb8/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_color_chamelium@pipe-d-ctm-0-75:
- shard-hsw: NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +4 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-hsw4/igt@kms_color_chamelium@pipe-d-ctm-0-75.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-random:
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#109279])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-512x512-random.html
- shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109278] / [fdo#109279])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-512x512-random.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-tglb: [PASS][57] -> [INCOMPLETE][58] ([i915#1436] / [i915#1982])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109274] / [fdo#109278]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109274])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1:
- shard-tglb: [PASS][61] -> [FAIL][62] ([i915#2122])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-tglb8/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb7/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [PASS][63] -> [DMESG-WARN][64] ([i915#180]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-kbl2/igt@kms_flip@flip-vs-suspend@c-dp1.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-kbl6/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-iclb: NOTRUN -> [SKIP][65] ([fdo#109285])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb5/igt@kms_force_connector_basic@force-load-detect.html
- shard-tglb: NOTRUN -> [SKIP][66] ([fdo#109285])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][67] ([fdo#109280]) +6 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move:
- shard-tglb: NOTRUN -> [SKIP][68] ([fdo#111825]) +11 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move.html
* igt@kms_hdr@static-toggle-suspend:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#1187])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb7/igt@kms_hdr@static-toggle-suspend.html
- shard-iclb: NOTRUN -> [SKIP][70] ([i915#1187])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb6/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-glk: NOTRUN -> [FAIL][71] ([i915#265])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-glk6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
- shard-apl: NOTRUN -> [FAIL][72] ([i915#265])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
- shard-kbl: NOTRUN -> [FAIL][73] ([i915#265])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-d-tiling-none:
- shard-iclb: NOTRUN -> [SKIP][74] ([fdo#109278]) +3 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb1/igt@kms_plane_lowres@pipe-d-tiling-none.html
* igt@kms_psr2_su@frontbuffer:
- shard-tglb: NOTRUN -> [FAIL][75] ([i915#2596])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb6/igt@kms_psr2_su@frontbuffer.html
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109642] / [fdo#111068])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb7/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][77] -> [SKIP][78] ([fdo#109441]) +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html
* igt@prime_nv_test@nv_write_i915_cpu_mmap_read:
- shard-tglb: NOTRUN -> [SKIP][79] ([fdo#109291])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb8/igt@prime_nv_test@nv_write_i915_cpu_mmap_read.html
- shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109291]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb1/igt@prime_nv_test@nv_write_i915_cpu_mmap_read.html
* igt@prime_vgem@fence-write-hang:
- shard-iclb: NOTRUN -> [SKIP][81] ([fdo#109295])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb7/igt@prime_vgem@fence-write-hang.html
- shard-tglb: NOTRUN -> [SKIP][82] ([fdo#109295])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb6/igt@prime_vgem@fence-write-hang.html
#### Possible fixes ####
* igt@gem_exec_whisper@basic-fds-forked-all:
- shard-glk: [DMESG-WARN][83] ([i915#118] / [i915#95]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-glk7/igt@gem_exec_whisper@basic-fds-forked-all.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-glk4/igt@gem_exec_whisper@basic-fds-forked-all.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][85] ([i915#454]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@fences:
- shard-tglb: [SKIP][87] ([i915#579]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-tglb8/igt@i915_pm_rpm@fences.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb6/igt@i915_pm_rpm@fences.html
- shard-kbl: [SKIP][89] ([fdo#109271]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-kbl3/igt@i915_pm_rpm@fences.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-kbl1/igt@i915_pm_rpm@fences.html
- shard-iclb: [SKIP][91] ([i915#579]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-iclb3/igt@i915_pm_rpm@fences.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb7/igt@i915_pm_rpm@fences.html
- shard-hsw: [SKIP][93] ([fdo#109271]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-hsw6/igt@i915_pm_rpm@fences.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-hsw7/igt@i915_pm_rpm@fences.html
- shard-glk: [SKIP][95] ([fdo#109271]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-glk4/igt@i915_pm_rpm@fences.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-glk5/igt@i915_pm_rpm@fences.html
- shard-apl: [SKIP][97] ([fdo#109271]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-apl1/igt@i915_pm_rpm@fences.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-apl1/igt@i915_pm_rpm@fences.html
* igt@i915_suspend@debugfs-reader:
- shard-glk: [DMESG-WARN][99] ([i915#1602] / [i915#2635]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-glk4/igt@i915_suspend@debugfs-reader.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-glk1/igt@i915_suspend@debugfs-reader.html
- shard-apl: [DMESG-WARN][101] ([i915#1602] / [i915#2635]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-apl1/igt@i915_suspend@debugfs-reader.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-apl4/igt@i915_suspend@debugfs-reader.html
- shard-kbl: [INCOMPLETE][103] ([i915#155]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-kbl3/igt@i915_suspend@debugfs-reader.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-kbl2/igt@i915_suspend@debugfs-reader.html
- shard-hsw: [DMESG-WARN][105] ([i915#2637]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-hsw6/igt@i915_suspend@debugfs-reader.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-hsw6/igt@i915_suspend@debugfs-reader.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1:
- shard-apl: [FAIL][107] ([i915#79]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-apl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-apl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-tglb: [FAIL][109] ([i915#2598]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
- shard-hsw: [INCOMPLETE][111] ([i915#2055]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-hsw7/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-hsw2/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-tglb: [DMESG-WARN][113] ([i915#1436] / [i915#1602] / [i915#1887] / [i915#2411]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
- shard-iclb: [DMESG-WARN][115] -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][117] ([fdo#109441]) -> [PASS][118] +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-iclb6/igt@kms_psr@psr2_cursor_blt.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [FAIL][119] ([i915#2680]) -> [WARN][120] ([i915#2681] / [i915#2684])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@runner@aborted:
- shard-hsw: [FAIL][121] ([i915#2295]) -> [FAIL][122] ([fdo#109271] / [i915#2295])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-hsw6/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-hsw4/igt@runner@aborted.html
- shard-iclb: ([FAIL][123], [FAIL][124]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#2724] / [i915#483]) -> ([FAIL][125], [FAIL][126]) ([i915#2295] / [i915#2722] / [i915#2724] / [i915#483])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-iclb3/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-iclb5/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb4/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-iclb7/igt@runner@aborted.html
- shard-apl: ([FAIL][127], [FAIL][128]) ([i915#2295] / [i915#2722]) -> ([FAIL][129], [FAIL][130]) ([fdo#109271] / [i915#2295] / [i915#2722])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-apl1/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-apl8/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-apl3/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-apl4/igt@runner@aborted.html
- shard-tglb: ([FAIL][131], [FAIL][132]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#456]) -> ([FAIL][133], [FAIL][134]) ([i915#1602] / [i915#2295] / [i915#2722])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-tglb3/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9482/shard-tglb8/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb1/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/shard-tglb5/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112016]: https://bugs.freedesktop.org/show_bug.cgi?id=112016
[fdo#112025]: https://bugs.freedesktop.org/show_bug.cgi?id=112025
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[fdo#112306]: https://bugs.freedesktop.org/show_bug.cgi?id=112306
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1187]: https://gitlab.freedesktop.org/drm/intel/issues/1187
[i915#1317]: https://gitlab.freedesktop.org/drm/intel/issues/1317
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2596]: https://gitlab.freedesktop.org/drm/intel/issues/2596
[i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598
[i915#2635]: https://gitlab.freedesktop.org/drm/intel/issues/2635
[i915#2637]: https://gitlab.freedesktop.org/drm/intel/issues/2637
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5288/index.html
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_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Measure timeslice distribution when oversaturated
2020-12-14 20:44 ` [igt-dev] " Chris Wilson
@ 2020-12-15 9:41 ` Tvrtko Ursulin
-1 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2020-12-15 9:41 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev
On 14/12/2020 20:44, Chris Wilson wrote:
> Check that timeslices for an oversaturated system (where there is more
> work than can be supported by a single engine) are evenly distributed
> between the clients.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> tests/i915/gem_exec_schedule.c | 179 +++++++++++++++++++++++++++++++++
> 1 file changed, 179 insertions(+)
>
> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> index f23d63ac3..263f1dd78 100644
> --- a/tests/i915/gem_exec_schedule.c
> +++ b/tests/i915/gem_exec_schedule.c
> @@ -2516,6 +2516,154 @@ static void measure_semaphore_power(int i915)
> rapl_close(&pkg);
> }
>
> +static int read_timestamp_frequency(int i915)
> +{
> + int value = 0;
> + drm_i915_getparam_t gp = {
> + .value = &value,
> + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
> + };
> + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp);
> + return value;
> +}
> +
> +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y)
> +{
> + return (x + y - 1) / y;
> +}
> +
> +static uint64_t ticks_to_ns(int i915, uint64_t ticks)
> +{
> + return div64_u64_round_up(ticks * NSEC_PER_SEC,
> + read_timestamp_frequency(i915));
> +}
> +
> +static int cmp_u32(const void *A, const void *B)
> +{
> + const uint32_t *a = A, *b = B;
> +
> + if (*a < *b)
> + return -1;
> + else if (*a > *b)
> + return 1;
> + else
> + return 0;
> +}
> +
> +static uint32_t read_ctx_timestamp(int i915,
> + uint32_t ctx,
> + const struct intel_execution_engine2 *e)
> +{
> + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
> + const uint32_t base = gem_engine_mmio_base(i915, e->name);
> + struct drm_i915_gem_relocation_entry reloc;
> + struct drm_i915_gem_exec_object2 obj = {
> + .handle = gem_create(i915, 4096),
> + .offset = 32 << 20,
> + .relocs_ptr = to_user_pointer(&reloc),
> + .relocation_count = 1,
> + };
> + struct drm_i915_gem_execbuffer2 execbuf = {
> + .buffers_ptr = to_user_pointer(&obj),
> + .buffer_count = 1,
> + .flags = e->flags,
> + .rsvd1 = ctx,
> + };
> +#define RUNTIME (base + 0x3a8)
> + uint32_t *map, *cs;
> + uint32_t ts;
> +
> + igt_require(base);
> +
> + cs = map = gem_mmap__device_coherent(i915, obj.handle,
> + 0, 4096, PROT_WRITE);
> +
> + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
> + *cs++ = RUNTIME;
> + memset(&reloc, 0, sizeof(reloc));
> + reloc.target_handle = obj.handle;
> + reloc.presumed_offset = obj.offset;
> + reloc.offset = offset_in_page(cs);
> + reloc.delta = 4000;
> + *cs++ = obj.offset + 4000;
> + *cs++ = obj.offset >> 32;
> +
> + *cs++ = MI_BATCH_BUFFER_END;
> +
> + gem_execbuf(i915, &execbuf);
> + gem_sync(i915, obj.handle);
> + gem_close(i915, obj.handle);
> +
> + ts = map[1000];
> + munmap(map, 4096);
> +
> + return ts;
> +}
> +
> +static void fairslice(int i915,
> + const struct intel_execution_engine2 *e,
> + unsigned long flags,
> + int duration)
> +{
> + const double timeslice_duration_ns = 1e6;
> + igt_spin_t *spin = NULL;
> + double threshold;
> + uint32_t ctx[3];
> + uint32_t ts[3];
> +
> + for (int i = 0; i < ARRAY_SIZE(ctx); i++) {
> + ctx[i] = gem_context_clone_with_engines(i915, 0);
> + if (spin == NULL) {
> + spin = __igt_spin_new(i915,
> + .ctx = ctx[i],
> + .engine = e->flags,
> + .flags = flags);
> + } else {
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffer_count = 1,
> + .buffers_ptr = to_user_pointer(&spin->obj[IGT_SPIN_BATCH]),
> + .flags = e->flags,
> + .rsvd1 = ctx[i],
> + };
> + gem_execbuf(i915, &eb);
> + }
> + }
> +
> + sleep(duration); /* over the course of many timeslices */
> +
> + igt_assert(gem_bo_busy(i915, spin->handle));
> + igt_spin_end(spin);
> + for (int i = 0; i < ARRAY_SIZE(ctx); i++)
> + ts[i] = read_ctx_timestamp(i915, ctx[i], e);
> +
> + for (int i = 0; i < ARRAY_SIZE(ctx); i++)
> + gem_context_destroy(i915, ctx[i]);
> + igt_spin_free(i915, spin);
> +
> + /*
> + * If we imagine that the timeslices are randomly distributed to
> + * the virtual engines, we would expect the variation to be modelled
> + * by a drunken walk; ergo sqrt(num_timeslices).
> + */
> + threshold = sqrt(1e9 * duration / timeslice_duration_ns);
> + threshold *= timeslice_duration_ns;
> + threshold *= 2; /* CI safety factor before crying wolf */
> +
> + qsort(ts, 3, sizeof(*ts), cmp_u32);
> + igt_info("%s: [%.1f, %.1f, %.1f] ms, expect %1.f +- %.1fms\n", e->name,
> + 1e-6 * ticks_to_ns(i915, ts[0]),
> + 1e-6 * ticks_to_ns(i915, ts[1]),
> + 1e-6 * ticks_to_ns(i915, ts[2]),
> + 1e3 * duration / 3,
> + 1e-6 * threshold);
> +
> + igt_assert_f(ts[2], "CTX_TIMESTAMP not reported!\n");
> + igt_assert_f(ticks_to_ns(i915, ts[2] - ts[0]) < 2 * threshold,
Is this second threshold x2 by accident?
> + "Range of timeslices greater than tolerable: %.2fms > %.2fms; unfair!\n",
> + 1e-6 * ticks_to_ns(i915, ts[2] - ts[0]),
> + 1e-6 * threshold * 2);
* 2 as well.
> +}
> +
> #define test_each_engine(T, i915, e) \
> igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
> igt_dynamic_f("%s", e->name)
> @@ -2582,6 +2730,37 @@ igt_main
> test_each_engine("lateslice", fd, e)
> lateslice(fd, e->flags);
>
> + igt_subtest_group {
> + igt_fixture {
> + igt_require(gem_scheduler_has_semaphores(fd));
> + igt_require(gem_scheduler_has_preemption(fd));
> + igt_require(intel_gen(intel_get_drm_devid(fd)) >= 8);
> + }
> +
> + test_each_engine("fairslice", fd, e)
> + fairslice(fd, e, 0, 2);
> +
> + test_each_engine("u-fairslice", fd, e)
> + fairslice(fd, e, IGT_SPIN_USERPTR, 2);
> +
> + igt_subtest("fairslice-all") {
> + __for_each_physical_engine(fd, e) {
> + igt_fork(child, 1)
> + fairslice(fd, e, 0, 2);
> + }
> + igt_waitchildren();
> + }
> + igt_subtest("u-fairslice-all") {
> + __for_each_physical_engine(fd, e) {
> + igt_fork(child, 1)
> + fairslice(fd, e,
> + IGT_SPIN_USERPTR,
> + 2);
> + }
> + igt_waitchildren();
> + }
> + }
> +
> test_each_engine("submit-early-slice", fd, e)
> submit_slice(fd, e, EARLY_SUBMIT);
> test_each_engine("submit-golden-slice", fd, e)
>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Measure timeslice distribution when oversaturated
@ 2020-12-15 9:41 ` Tvrtko Ursulin
0 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2020-12-15 9:41 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
On 14/12/2020 20:44, Chris Wilson wrote:
> Check that timeslices for an oversaturated system (where there is more
> work than can be supported by a single engine) are evenly distributed
> between the clients.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> tests/i915/gem_exec_schedule.c | 179 +++++++++++++++++++++++++++++++++
> 1 file changed, 179 insertions(+)
>
> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> index f23d63ac3..263f1dd78 100644
> --- a/tests/i915/gem_exec_schedule.c
> +++ b/tests/i915/gem_exec_schedule.c
> @@ -2516,6 +2516,154 @@ static void measure_semaphore_power(int i915)
> rapl_close(&pkg);
> }
>
> +static int read_timestamp_frequency(int i915)
> +{
> + int value = 0;
> + drm_i915_getparam_t gp = {
> + .value = &value,
> + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
> + };
> + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp);
> + return value;
> +}
> +
> +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y)
> +{
> + return (x + y - 1) / y;
> +}
> +
> +static uint64_t ticks_to_ns(int i915, uint64_t ticks)
> +{
> + return div64_u64_round_up(ticks * NSEC_PER_SEC,
> + read_timestamp_frequency(i915));
> +}
> +
> +static int cmp_u32(const void *A, const void *B)
> +{
> + const uint32_t *a = A, *b = B;
> +
> + if (*a < *b)
> + return -1;
> + else if (*a > *b)
> + return 1;
> + else
> + return 0;
> +}
> +
> +static uint32_t read_ctx_timestamp(int i915,
> + uint32_t ctx,
> + const struct intel_execution_engine2 *e)
> +{
> + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
> + const uint32_t base = gem_engine_mmio_base(i915, e->name);
> + struct drm_i915_gem_relocation_entry reloc;
> + struct drm_i915_gem_exec_object2 obj = {
> + .handle = gem_create(i915, 4096),
> + .offset = 32 << 20,
> + .relocs_ptr = to_user_pointer(&reloc),
> + .relocation_count = 1,
> + };
> + struct drm_i915_gem_execbuffer2 execbuf = {
> + .buffers_ptr = to_user_pointer(&obj),
> + .buffer_count = 1,
> + .flags = e->flags,
> + .rsvd1 = ctx,
> + };
> +#define RUNTIME (base + 0x3a8)
> + uint32_t *map, *cs;
> + uint32_t ts;
> +
> + igt_require(base);
> +
> + cs = map = gem_mmap__device_coherent(i915, obj.handle,
> + 0, 4096, PROT_WRITE);
> +
> + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
> + *cs++ = RUNTIME;
> + memset(&reloc, 0, sizeof(reloc));
> + reloc.target_handle = obj.handle;
> + reloc.presumed_offset = obj.offset;
> + reloc.offset = offset_in_page(cs);
> + reloc.delta = 4000;
> + *cs++ = obj.offset + 4000;
> + *cs++ = obj.offset >> 32;
> +
> + *cs++ = MI_BATCH_BUFFER_END;
> +
> + gem_execbuf(i915, &execbuf);
> + gem_sync(i915, obj.handle);
> + gem_close(i915, obj.handle);
> +
> + ts = map[1000];
> + munmap(map, 4096);
> +
> + return ts;
> +}
> +
> +static void fairslice(int i915,
> + const struct intel_execution_engine2 *e,
> + unsigned long flags,
> + int duration)
> +{
> + const double timeslice_duration_ns = 1e6;
> + igt_spin_t *spin = NULL;
> + double threshold;
> + uint32_t ctx[3];
> + uint32_t ts[3];
> +
> + for (int i = 0; i < ARRAY_SIZE(ctx); i++) {
> + ctx[i] = gem_context_clone_with_engines(i915, 0);
> + if (spin == NULL) {
> + spin = __igt_spin_new(i915,
> + .ctx = ctx[i],
> + .engine = e->flags,
> + .flags = flags);
> + } else {
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffer_count = 1,
> + .buffers_ptr = to_user_pointer(&spin->obj[IGT_SPIN_BATCH]),
> + .flags = e->flags,
> + .rsvd1 = ctx[i],
> + };
> + gem_execbuf(i915, &eb);
> + }
> + }
> +
> + sleep(duration); /* over the course of many timeslices */
> +
> + igt_assert(gem_bo_busy(i915, spin->handle));
> + igt_spin_end(spin);
> + for (int i = 0; i < ARRAY_SIZE(ctx); i++)
> + ts[i] = read_ctx_timestamp(i915, ctx[i], e);
> +
> + for (int i = 0; i < ARRAY_SIZE(ctx); i++)
> + gem_context_destroy(i915, ctx[i]);
> + igt_spin_free(i915, spin);
> +
> + /*
> + * If we imagine that the timeslices are randomly distributed to
> + * the virtual engines, we would expect the variation to be modelled
> + * by a drunken walk; ergo sqrt(num_timeslices).
> + */
> + threshold = sqrt(1e9 * duration / timeslice_duration_ns);
> + threshold *= timeslice_duration_ns;
> + threshold *= 2; /* CI safety factor before crying wolf */
> +
> + qsort(ts, 3, sizeof(*ts), cmp_u32);
> + igt_info("%s: [%.1f, %.1f, %.1f] ms, expect %1.f +- %.1fms\n", e->name,
> + 1e-6 * ticks_to_ns(i915, ts[0]),
> + 1e-6 * ticks_to_ns(i915, ts[1]),
> + 1e-6 * ticks_to_ns(i915, ts[2]),
> + 1e3 * duration / 3,
> + 1e-6 * threshold);
> +
> + igt_assert_f(ts[2], "CTX_TIMESTAMP not reported!\n");
> + igt_assert_f(ticks_to_ns(i915, ts[2] - ts[0]) < 2 * threshold,
Is this second threshold x2 by accident?
> + "Range of timeslices greater than tolerable: %.2fms > %.2fms; unfair!\n",
> + 1e-6 * ticks_to_ns(i915, ts[2] - ts[0]),
> + 1e-6 * threshold * 2);
* 2 as well.
> +}
> +
> #define test_each_engine(T, i915, e) \
> igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
> igt_dynamic_f("%s", e->name)
> @@ -2582,6 +2730,37 @@ igt_main
> test_each_engine("lateslice", fd, e)
> lateslice(fd, e->flags);
>
> + igt_subtest_group {
> + igt_fixture {
> + igt_require(gem_scheduler_has_semaphores(fd));
> + igt_require(gem_scheduler_has_preemption(fd));
> + igt_require(intel_gen(intel_get_drm_devid(fd)) >= 8);
> + }
> +
> + test_each_engine("fairslice", fd, e)
> + fairslice(fd, e, 0, 2);
> +
> + test_each_engine("u-fairslice", fd, e)
> + fairslice(fd, e, IGT_SPIN_USERPTR, 2);
> +
> + igt_subtest("fairslice-all") {
> + __for_each_physical_engine(fd, e) {
> + igt_fork(child, 1)
> + fairslice(fd, e, 0, 2);
> + }
> + igt_waitchildren();
> + }
> + igt_subtest("u-fairslice-all") {
> + __for_each_physical_engine(fd, e) {
> + igt_fork(child, 1)
> + fairslice(fd, e,
> + IGT_SPIN_USERPTR,
> + 2);
> + }
> + igt_waitchildren();
> + }
> + }
> +
> test_each_engine("submit-early-slice", fd, e)
> submit_slice(fd, e, EARLY_SUBMIT);
> test_each_engine("submit-golden-slice", fd, e)
>
Regards,
Tvrtko
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Measure timeslice distribution when oversaturated
2020-12-15 9:41 ` Tvrtko Ursulin
@ 2020-12-15 9:47 ` Chris Wilson
-1 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2020-12-15 9:47 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: igt-dev
Quoting Tvrtko Ursulin (2020-12-15 09:41:09)
>
> On 14/12/2020 20:44, Chris Wilson wrote:
> > Check that timeslices for an oversaturated system (where there is more
> > work than can be supported by a single engine) are evenly distributed
> > between the clients.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> > tests/i915/gem_exec_schedule.c | 179 +++++++++++++++++++++++++++++++++
> > 1 file changed, 179 insertions(+)
> >
> > diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> > index f23d63ac3..263f1dd78 100644
> > --- a/tests/i915/gem_exec_schedule.c
> > +++ b/tests/i915/gem_exec_schedule.c
> > @@ -2516,6 +2516,154 @@ static void measure_semaphore_power(int i915)
> > rapl_close(&pkg);
> > }
> >
> > +static int read_timestamp_frequency(int i915)
> > +{
> > + int value = 0;
> > + drm_i915_getparam_t gp = {
> > + .value = &value,
> > + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
> > + };
> > + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp);
> > + return value;
> > +}
> > +
> > +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y)
> > +{
> > + return (x + y - 1) / y;
> > +}
> > +
> > +static uint64_t ticks_to_ns(int i915, uint64_t ticks)
> > +{
> > + return div64_u64_round_up(ticks * NSEC_PER_SEC,
> > + read_timestamp_frequency(i915));
> > +}
> > +
> > +static int cmp_u32(const void *A, const void *B)
> > +{
> > + const uint32_t *a = A, *b = B;
> > +
> > + if (*a < *b)
> > + return -1;
> > + else if (*a > *b)
> > + return 1;
> > + else
> > + return 0;
> > +}
> > +
> > +static uint32_t read_ctx_timestamp(int i915,
> > + uint32_t ctx,
> > + const struct intel_execution_engine2 *e)
> > +{
> > + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
> > + const uint32_t base = gem_engine_mmio_base(i915, e->name);
> > + struct drm_i915_gem_relocation_entry reloc;
> > + struct drm_i915_gem_exec_object2 obj = {
> > + .handle = gem_create(i915, 4096),
> > + .offset = 32 << 20,
> > + .relocs_ptr = to_user_pointer(&reloc),
> > + .relocation_count = 1,
> > + };
> > + struct drm_i915_gem_execbuffer2 execbuf = {
> > + .buffers_ptr = to_user_pointer(&obj),
> > + .buffer_count = 1,
> > + .flags = e->flags,
> > + .rsvd1 = ctx,
> > + };
> > +#define RUNTIME (base + 0x3a8)
> > + uint32_t *map, *cs;
> > + uint32_t ts;
> > +
> > + igt_require(base);
> > +
> > + cs = map = gem_mmap__device_coherent(i915, obj.handle,
> > + 0, 4096, PROT_WRITE);
> > +
> > + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
> > + *cs++ = RUNTIME;
> > + memset(&reloc, 0, sizeof(reloc));
> > + reloc.target_handle = obj.handle;
> > + reloc.presumed_offset = obj.offset;
> > + reloc.offset = offset_in_page(cs);
> > + reloc.delta = 4000;
> > + *cs++ = obj.offset + 4000;
> > + *cs++ = obj.offset >> 32;
> > +
> > + *cs++ = MI_BATCH_BUFFER_END;
> > +
> > + gem_execbuf(i915, &execbuf);
> > + gem_sync(i915, obj.handle);
> > + gem_close(i915, obj.handle);
> > +
> > + ts = map[1000];
> > + munmap(map, 4096);
> > +
> > + return ts;
> > +}
> > +
> > +static void fairslice(int i915,
> > + const struct intel_execution_engine2 *e,
> > + unsigned long flags,
> > + int duration)
> > +{
> > + const double timeslice_duration_ns = 1e6;
> > + igt_spin_t *spin = NULL;
> > + double threshold;
> > + uint32_t ctx[3];
> > + uint32_t ts[3];
> > +
> > + for (int i = 0; i < ARRAY_SIZE(ctx); i++) {
> > + ctx[i] = gem_context_clone_with_engines(i915, 0);
> > + if (spin == NULL) {
> > + spin = __igt_spin_new(i915,
> > + .ctx = ctx[i],
> > + .engine = e->flags,
> > + .flags = flags);
> > + } else {
> > + struct drm_i915_gem_execbuffer2 eb = {
> > + .buffer_count = 1,
> > + .buffers_ptr = to_user_pointer(&spin->obj[IGT_SPIN_BATCH]),
> > + .flags = e->flags,
> > + .rsvd1 = ctx[i],
> > + };
> > + gem_execbuf(i915, &eb);
> > + }
> > + }
> > +
> > + sleep(duration); /* over the course of many timeslices */
> > +
> > + igt_assert(gem_bo_busy(i915, spin->handle));
> > + igt_spin_end(spin);
> > + for (int i = 0; i < ARRAY_SIZE(ctx); i++)
> > + ts[i] = read_ctx_timestamp(i915, ctx[i], e);
> > +
> > + for (int i = 0; i < ARRAY_SIZE(ctx); i++)
> > + gem_context_destroy(i915, ctx[i]);
> > + igt_spin_free(i915, spin);
> > +
> > + /*
> > + * If we imagine that the timeslices are randomly distributed to
> > + * the virtual engines, we would expect the variation to be modelled
> > + * by a drunken walk; ergo sqrt(num_timeslices).
> > + */
> > + threshold = sqrt(1e9 * duration / timeslice_duration_ns);
> > + threshold *= timeslice_duration_ns;
> > + threshold *= 2; /* CI safety factor before crying wolf */
> > +
> > + qsort(ts, 3, sizeof(*ts), cmp_u32);
> > + igt_info("%s: [%.1f, %.1f, %.1f] ms, expect %1.f +- %.1fms\n", e->name,
> > + 1e-6 * ticks_to_ns(i915, ts[0]),
> > + 1e-6 * ticks_to_ns(i915, ts[1]),
> > + 1e-6 * ticks_to_ns(i915, ts[2]),
> > + 1e3 * duration / 3,
> > + 1e-6 * threshold);
> > +
> > + igt_assert_f(ts[2], "CTX_TIMESTAMP not reported!\n");
> > + igt_assert_f(ticks_to_ns(i915, ts[2] - ts[0]) < 2 * threshold,
>
> Is this second threshold x2 by accident?
The drunken walk model's variance is evenly distributed about the mean
(one-sided). We are comparing max-min, so a two-sided range test.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Measure timeslice distribution when oversaturated
@ 2020-12-15 9:47 ` Chris Wilson
0 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2020-12-15 9:47 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2020-12-15 09:41:09)
>
> On 14/12/2020 20:44, Chris Wilson wrote:
> > Check that timeslices for an oversaturated system (where there is more
> > work than can be supported by a single engine) are evenly distributed
> > between the clients.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> > tests/i915/gem_exec_schedule.c | 179 +++++++++++++++++++++++++++++++++
> > 1 file changed, 179 insertions(+)
> >
> > diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> > index f23d63ac3..263f1dd78 100644
> > --- a/tests/i915/gem_exec_schedule.c
> > +++ b/tests/i915/gem_exec_schedule.c
> > @@ -2516,6 +2516,154 @@ static void measure_semaphore_power(int i915)
> > rapl_close(&pkg);
> > }
> >
> > +static int read_timestamp_frequency(int i915)
> > +{
> > + int value = 0;
> > + drm_i915_getparam_t gp = {
> > + .value = &value,
> > + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
> > + };
> > + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp);
> > + return value;
> > +}
> > +
> > +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y)
> > +{
> > + return (x + y - 1) / y;
> > +}
> > +
> > +static uint64_t ticks_to_ns(int i915, uint64_t ticks)
> > +{
> > + return div64_u64_round_up(ticks * NSEC_PER_SEC,
> > + read_timestamp_frequency(i915));
> > +}
> > +
> > +static int cmp_u32(const void *A, const void *B)
> > +{
> > + const uint32_t *a = A, *b = B;
> > +
> > + if (*a < *b)
> > + return -1;
> > + else if (*a > *b)
> > + return 1;
> > + else
> > + return 0;
> > +}
> > +
> > +static uint32_t read_ctx_timestamp(int i915,
> > + uint32_t ctx,
> > + const struct intel_execution_engine2 *e)
> > +{
> > + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
> > + const uint32_t base = gem_engine_mmio_base(i915, e->name);
> > + struct drm_i915_gem_relocation_entry reloc;
> > + struct drm_i915_gem_exec_object2 obj = {
> > + .handle = gem_create(i915, 4096),
> > + .offset = 32 << 20,
> > + .relocs_ptr = to_user_pointer(&reloc),
> > + .relocation_count = 1,
> > + };
> > + struct drm_i915_gem_execbuffer2 execbuf = {
> > + .buffers_ptr = to_user_pointer(&obj),
> > + .buffer_count = 1,
> > + .flags = e->flags,
> > + .rsvd1 = ctx,
> > + };
> > +#define RUNTIME (base + 0x3a8)
> > + uint32_t *map, *cs;
> > + uint32_t ts;
> > +
> > + igt_require(base);
> > +
> > + cs = map = gem_mmap__device_coherent(i915, obj.handle,
> > + 0, 4096, PROT_WRITE);
> > +
> > + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
> > + *cs++ = RUNTIME;
> > + memset(&reloc, 0, sizeof(reloc));
> > + reloc.target_handle = obj.handle;
> > + reloc.presumed_offset = obj.offset;
> > + reloc.offset = offset_in_page(cs);
> > + reloc.delta = 4000;
> > + *cs++ = obj.offset + 4000;
> > + *cs++ = obj.offset >> 32;
> > +
> > + *cs++ = MI_BATCH_BUFFER_END;
> > +
> > + gem_execbuf(i915, &execbuf);
> > + gem_sync(i915, obj.handle);
> > + gem_close(i915, obj.handle);
> > +
> > + ts = map[1000];
> > + munmap(map, 4096);
> > +
> > + return ts;
> > +}
> > +
> > +static void fairslice(int i915,
> > + const struct intel_execution_engine2 *e,
> > + unsigned long flags,
> > + int duration)
> > +{
> > + const double timeslice_duration_ns = 1e6;
> > + igt_spin_t *spin = NULL;
> > + double threshold;
> > + uint32_t ctx[3];
> > + uint32_t ts[3];
> > +
> > + for (int i = 0; i < ARRAY_SIZE(ctx); i++) {
> > + ctx[i] = gem_context_clone_with_engines(i915, 0);
> > + if (spin == NULL) {
> > + spin = __igt_spin_new(i915,
> > + .ctx = ctx[i],
> > + .engine = e->flags,
> > + .flags = flags);
> > + } else {
> > + struct drm_i915_gem_execbuffer2 eb = {
> > + .buffer_count = 1,
> > + .buffers_ptr = to_user_pointer(&spin->obj[IGT_SPIN_BATCH]),
> > + .flags = e->flags,
> > + .rsvd1 = ctx[i],
> > + };
> > + gem_execbuf(i915, &eb);
> > + }
> > + }
> > +
> > + sleep(duration); /* over the course of many timeslices */
> > +
> > + igt_assert(gem_bo_busy(i915, spin->handle));
> > + igt_spin_end(spin);
> > + for (int i = 0; i < ARRAY_SIZE(ctx); i++)
> > + ts[i] = read_ctx_timestamp(i915, ctx[i], e);
> > +
> > + for (int i = 0; i < ARRAY_SIZE(ctx); i++)
> > + gem_context_destroy(i915, ctx[i]);
> > + igt_spin_free(i915, spin);
> > +
> > + /*
> > + * If we imagine that the timeslices are randomly distributed to
> > + * the virtual engines, we would expect the variation to be modelled
> > + * by a drunken walk; ergo sqrt(num_timeslices).
> > + */
> > + threshold = sqrt(1e9 * duration / timeslice_duration_ns);
> > + threshold *= timeslice_duration_ns;
> > + threshold *= 2; /* CI safety factor before crying wolf */
> > +
> > + qsort(ts, 3, sizeof(*ts), cmp_u32);
> > + igt_info("%s: [%.1f, %.1f, %.1f] ms, expect %1.f +- %.1fms\n", e->name,
> > + 1e-6 * ticks_to_ns(i915, ts[0]),
> > + 1e-6 * ticks_to_ns(i915, ts[1]),
> > + 1e-6 * ticks_to_ns(i915, ts[2]),
> > + 1e3 * duration / 3,
> > + 1e-6 * threshold);
> > +
> > + igt_assert_f(ts[2], "CTX_TIMESTAMP not reported!\n");
> > + igt_assert_f(ticks_to_ns(i915, ts[2] - ts[0]) < 2 * threshold,
>
> Is this second threshold x2 by accident?
The drunken walk model's variance is evenly distributed about the mean
(one-sided). We are comparing max-min, so a two-sided range test.
-Chris
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Measure timeslice distribution when oversaturated
2020-12-15 9:47 ` Chris Wilson
(?)
@ 2020-12-15 9:51 ` Tvrtko Ursulin
-1 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2020-12-15 9:51 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev
On 15/12/2020 09:47, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2020-12-15 09:41:09)
>>
>> On 14/12/2020 20:44, Chris Wilson wrote:
>>> Check that timeslices for an oversaturated system (where there is more
>>> work than can be supported by a single engine) are evenly distributed
>>> between the clients.
>>>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> ---
>>> tests/i915/gem_exec_schedule.c | 179 +++++++++++++++++++++++++++++++++
>>> 1 file changed, 179 insertions(+)
>>>
>>> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
>>> index f23d63ac3..263f1dd78 100644
>>> --- a/tests/i915/gem_exec_schedule.c
>>> +++ b/tests/i915/gem_exec_schedule.c
>>> @@ -2516,6 +2516,154 @@ static void measure_semaphore_power(int i915)
>>> rapl_close(&pkg);
>>> }
>>>
>>> +static int read_timestamp_frequency(int i915)
>>> +{
>>> + int value = 0;
>>> + drm_i915_getparam_t gp = {
>>> + .value = &value,
>>> + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
>>> + };
>>> + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp);
>>> + return value;
>>> +}
>>> +
>>> +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y)
>>> +{
>>> + return (x + y - 1) / y;
>>> +}
>>> +
>>> +static uint64_t ticks_to_ns(int i915, uint64_t ticks)
>>> +{
>>> + return div64_u64_round_up(ticks * NSEC_PER_SEC,
>>> + read_timestamp_frequency(i915));
>>> +}
>>> +
>>> +static int cmp_u32(const void *A, const void *B)
>>> +{
>>> + const uint32_t *a = A, *b = B;
>>> +
>>> + if (*a < *b)
>>> + return -1;
>>> + else if (*a > *b)
>>> + return 1;
>>> + else
>>> + return 0;
>>> +}
>>> +
>>> +static uint32_t read_ctx_timestamp(int i915,
>>> + uint32_t ctx,
>>> + const struct intel_execution_engine2 *e)
>>> +{
>>> + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
>>> + const uint32_t base = gem_engine_mmio_base(i915, e->name);
>>> + struct drm_i915_gem_relocation_entry reloc;
>>> + struct drm_i915_gem_exec_object2 obj = {
>>> + .handle = gem_create(i915, 4096),
>>> + .offset = 32 << 20,
>>> + .relocs_ptr = to_user_pointer(&reloc),
>>> + .relocation_count = 1,
>>> + };
>>> + struct drm_i915_gem_execbuffer2 execbuf = {
>>> + .buffers_ptr = to_user_pointer(&obj),
>>> + .buffer_count = 1,
>>> + .flags = e->flags,
>>> + .rsvd1 = ctx,
>>> + };
>>> +#define RUNTIME (base + 0x3a8)
>>> + uint32_t *map, *cs;
>>> + uint32_t ts;
>>> +
>>> + igt_require(base);
>>> +
>>> + cs = map = gem_mmap__device_coherent(i915, obj.handle,
>>> + 0, 4096, PROT_WRITE);
>>> +
>>> + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
>>> + *cs++ = RUNTIME;
>>> + memset(&reloc, 0, sizeof(reloc));
>>> + reloc.target_handle = obj.handle;
>>> + reloc.presumed_offset = obj.offset;
>>> + reloc.offset = offset_in_page(cs);
>>> + reloc.delta = 4000;
>>> + *cs++ = obj.offset + 4000;
>>> + *cs++ = obj.offset >> 32;
>>> +
>>> + *cs++ = MI_BATCH_BUFFER_END;
>>> +
>>> + gem_execbuf(i915, &execbuf);
>>> + gem_sync(i915, obj.handle);
>>> + gem_close(i915, obj.handle);
>>> +
>>> + ts = map[1000];
>>> + munmap(map, 4096);
>>> +
>>> + return ts;
>>> +}
>>> +
>>> +static void fairslice(int i915,
>>> + const struct intel_execution_engine2 *e,
>>> + unsigned long flags,
>>> + int duration)
>>> +{
>>> + const double timeslice_duration_ns = 1e6;
>>> + igt_spin_t *spin = NULL;
>>> + double threshold;
>>> + uint32_t ctx[3];
>>> + uint32_t ts[3];
>>> +
>>> + for (int i = 0; i < ARRAY_SIZE(ctx); i++) {
>>> + ctx[i] = gem_context_clone_with_engines(i915, 0);
>>> + if (spin == NULL) {
>>> + spin = __igt_spin_new(i915,
>>> + .ctx = ctx[i],
>>> + .engine = e->flags,
>>> + .flags = flags);
>>> + } else {
>>> + struct drm_i915_gem_execbuffer2 eb = {
>>> + .buffer_count = 1,
>>> + .buffers_ptr = to_user_pointer(&spin->obj[IGT_SPIN_BATCH]),
>>> + .flags = e->flags,
>>> + .rsvd1 = ctx[i],
>>> + };
>>> + gem_execbuf(i915, &eb);
>>> + }
>>> + }
>>> +
>>> + sleep(duration); /* over the course of many timeslices */
>>> +
>>> + igt_assert(gem_bo_busy(i915, spin->handle));
>>> + igt_spin_end(spin);
>>> + for (int i = 0; i < ARRAY_SIZE(ctx); i++)
>>> + ts[i] = read_ctx_timestamp(i915, ctx[i], e);
>>> +
>>> + for (int i = 0; i < ARRAY_SIZE(ctx); i++)
>>> + gem_context_destroy(i915, ctx[i]);
>>> + igt_spin_free(i915, spin);
>>> +
>>> + /*
>>> + * If we imagine that the timeslices are randomly distributed to
>>> + * the virtual engines, we would expect the variation to be modelled
>>> + * by a drunken walk; ergo sqrt(num_timeslices).
>>> + */
>>> + threshold = sqrt(1e9 * duration / timeslice_duration_ns);
>>> + threshold *= timeslice_duration_ns;
>>> + threshold *= 2; /* CI safety factor before crying wolf */
>>> +
>>> + qsort(ts, 3, sizeof(*ts), cmp_u32);
>>> + igt_info("%s: [%.1f, %.1f, %.1f] ms, expect %1.f +- %.1fms\n", e->name,
>>> + 1e-6 * ticks_to_ns(i915, ts[0]),
>>> + 1e-6 * ticks_to_ns(i915, ts[1]),
>>> + 1e-6 * ticks_to_ns(i915, ts[2]),
>>> + 1e3 * duration / 3,
>>> + 1e-6 * threshold);
>>> +
>>> + igt_assert_f(ts[2], "CTX_TIMESTAMP not reported!\n");
>>> + igt_assert_f(ticks_to_ns(i915, ts[2] - ts[0]) < 2 * threshold,
>>
>> Is this second threshold x2 by accident?
>
> The drunken walk model's variance is evenly distributed about the mean
> (one-sided). We are comparing max-min, so a two-sided range test.
Ah okay.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-12-15 9:51 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-14 20:44 [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Measure timeslice distribution when oversaturated Chris Wilson
2020-12-14 20:44 ` [igt-dev] " Chris Wilson
2020-12-14 21:20 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2020-12-14 22:50 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2020-12-15 9:41 ` [Intel-gfx] [igt-dev] [PATCH i-g-t] " Tvrtko Ursulin
2020-12-15 9:41 ` Tvrtko Ursulin
2020-12-15 9:47 ` [Intel-gfx] " Chris Wilson
2020-12-15 9:47 ` Chris Wilson
2020-12-15 9:51 ` [Intel-gfx] " Tvrtko Ursulin
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