* [PATCH v2 1/4] Documentation/bindings: phy: update references to cp11x
2020-12-17 7:55 [PATCH v2 0/4] DTS updates for Marvell Armada CN913x platforms kostap
@ 2020-12-17 7:55 ` kostap
2020-12-17 7:55 ` [PATCH v2 2/4] arch/arm64/boot/dts/marvell: fix NAND partitioning scheme kostap
` (2 subsequent siblings)
3 siblings, 0 replies; 13+ messages in thread
From: kostap @ 2020-12-17 7:55 UTC (permalink / raw)
To: linux-arm-kernel
Cc: tmn505, andrew, jaz, gregory.clement, nadavh, robh+dt,
Konstantin Porotchkin, stefanc, mw, bpeled,
sebastian.hesselbarth
From: Grzegorz Jaszczyk <jaz@semihalf.com>
The cp11x references in dts has changed, reflect it in comphy
documentation.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
index 8c60e6985950..5ffd0f55d010 100644
--- a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
@@ -42,22 +42,22 @@ Required properties (child nodes):
Examples:
- cpm_comphy: phy@120000 {
+ CP11X_LABEL(comphy): phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
- marvell,system-controller = <&cpm_syscon0>;
- clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
- <&CP110_LABEL(clk) 1 18>;
+ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+ clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
+ <&CP11X_LABEL(clk) 1 18>;
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
- cpm_comphy0: phy@0 {
+ CP11X_LABEL(comphy0): phy@0 {
reg = <0>;
#phy-cells = <1>;
};
- cpm_comphy1: phy@1 {
+ CP11X_LABEL(comphy1): phy@1 {
reg = <1>;
#phy-cells = <1>;
};
--
2.17.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v2 2/4] arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
2020-12-17 7:55 [PATCH v2 0/4] DTS updates for Marvell Armada CN913x platforms kostap
2020-12-17 7:55 ` [PATCH v2 1/4] Documentation/bindings: phy: update references to cp11x kostap
@ 2020-12-17 7:55 ` kostap
2020-12-17 15:36 ` Andrew Lunn
2020-12-17 7:55 ` [PATCH v2 3/4] arm64: dts: cn913x: add device trees for topology B boards kostap
2020-12-17 7:55 ` [PATCH v2 4/4] arm64: dts: add support for Marvell cn9130-crb platform kostap
3 siblings, 1 reply; 13+ messages in thread
From: kostap @ 2020-12-17 7:55 UTC (permalink / raw)
To: linux-arm-kernel
Cc: tmn505, andrew, jaz, gregory.clement, nadavh, robh+dt,
Konstantin Porotchkin, stefanc, mw, bpeled,
sebastian.hesselbarth
From: Konstantin Porotchkin <kostap@marvell.com>
Eliminate 1MB gap between Linux and filesystem partitions.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/cn9130-db.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dts
index ce49a70d88a0..d24294888400 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -258,7 +258,7 @@
};
partition@200000 {
label = "Linux";
- reg = <0x200000 0xd00000>;
+ reg = <0x200000 0xe00000>;
};
partition@1000000 {
label = "Filesystem";
--
2.17.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 2/4] arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
2020-12-17 7:55 ` [PATCH v2 2/4] arch/arm64/boot/dts/marvell: fix NAND partitioning scheme kostap
@ 2020-12-17 15:36 ` Andrew Lunn
0 siblings, 0 replies; 13+ messages in thread
From: Andrew Lunn @ 2020-12-17 15:36 UTC (permalink / raw)
To: kostap
Cc: tmn505, jaz, gregory.clement, nadavh, robh+dt, stefanc, mw,
bpeled, linux-arm-kernel, sebastian.hesselbarth
On Thu, Dec 17, 2020 at 09:55:40AM +0200, kostap@marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
>
> Eliminate 1MB gap between Linux and filesystem partitions.
>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 3/4] arm64: dts: cn913x: add device trees for topology B boards
2020-12-17 7:55 [PATCH v2 0/4] DTS updates for Marvell Armada CN913x platforms kostap
2020-12-17 7:55 ` [PATCH v2 1/4] Documentation/bindings: phy: update references to cp11x kostap
2020-12-17 7:55 ` [PATCH v2 2/4] arch/arm64/boot/dts/marvell: fix NAND partitioning scheme kostap
@ 2020-12-17 7:55 ` kostap
2020-12-17 15:41 ` Andrew Lunn
2020-12-17 7:55 ` [PATCH v2 4/4] arm64: dts: add support for Marvell cn9130-crb platform kostap
3 siblings, 1 reply; 13+ messages in thread
From: kostap @ 2020-12-17 7:55 UTC (permalink / raw)
To: linux-arm-kernel
Cc: tmn505, andrew, jaz, gregory.clement, nadavh, robh+dt,
Konstantin Porotchkin, stefanc, mw, bpeled,
sebastian.hesselbarth
From: Konstantin Porotchkin <kostap@marvell.com>
The CN913x DB with topology B is similar to a regular setup (A)
boards, but uses NAND flash as a boot device, while topology A
boards are booting from SPI flash.
Since NAND and SPI on CN913x DB boards share some wires, they
cannot be activated simultaneously.
The DTS files for setup "B" are based on setup "A", in which the
CP0 NAND controller enabled and CP0 SPI1 disabled.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/Makefile | 9 +++++---
arch/arm64/boot/dts/marvell/cn9130-db-A.dts | 22 ++++++++++++++++++++
arch/arm64/boot/dts/marvell/cn9130-db-B.dts | 22 ++++++++++++++++++++
arch/arm64/boot/dts/marvell/{cn9130-db.dts => cn9130-db.dtsi} | 5 ++---
arch/arm64/boot/dts/marvell/cn9131-db-A.dts | 22 ++++++++++++++++++++
arch/arm64/boot/dts/marvell/cn9131-db-B.dts | 22 ++++++++++++++++++++
arch/arm64/boot/dts/marvell/{cn9131-db.dts => cn9131-db.dtsi} | 5 ++---
arch/arm64/boot/dts/marvell/cn9132-db-A.dts | 22 ++++++++++++++++++++
arch/arm64/boot/dts/marvell/cn9132-db-B.dts | 22 ++++++++++++++++++++
arch/arm64/boot/dts/marvell/{cn9132-db.dts => cn9132-db.dtsi} | 5 ++---
10 files changed, 144 insertions(+), 12 deletions(-)
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-A.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-B.dts
rename arch/arm64/boot/dts/marvell/{cn9130-db.dts => cn9130-db.dtsi} (99%)
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-A.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-B.dts
rename arch/arm64/boot/dts/marvell/{cn9131-db.dts => cn9131-db.dtsi} (97%)
create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db-A.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db-B.dts
rename arch/arm64/boot/dts/marvell/{cn9132-db.dts => cn9132-db.dtsi} (97%)
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index 3e5f2e7a040c..d9b924a63d89 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -13,6 +13,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
-dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
-dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
-dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-A.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-B.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-A.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-A.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-A.dts b/arch/arm64/boot/dts/marvell/cn9130-db-A.dts
new file mode 100644
index 000000000000..adb3a67a20b1
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-db-A.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB board.
+ */
+
+#include "cn9131-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-DB setup A";
+};
+
+/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When SPI controller is enabled, NAND should be disabled.
+ */
+
+&cp0_spi1 {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-B.dts b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts
new file mode 100644
index 000000000000..57e41cacd483
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB board (setup "B").
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-DB setup B";
+};
+
+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
+ */
+
+&cp0_nand_controller {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
similarity index 99%
rename from arch/arm64/boot/dts/marvell/cn9130-db.dts
rename to arch/arm64/boot/dts/marvell/cn9130-db.dtsi
index d24294888400..8de3a552b806 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
@@ -10,8 +10,6 @@
#include <dt-bindings/gpio/gpio.h>
/ {
- model = "Marvell Armada CN9130-DB";
-
chosen {
stdout-path = "serial0:115200n8";
};
@@ -235,6 +233,7 @@
/* U54 */
&cp0_nand_controller {
+ status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&nand_pins &nand_rb>;
@@ -306,7 +305,7 @@
/* U55 */
&cp0_spi1 {
- status = "okay";
+ status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
reg = <0x700680 0x50>;
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-A.dts b/arch/arm64/boot/dts/marvell/cn9131-db-A.dts
new file mode 100644
index 000000000000..a60fdee79bf8
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9131-db-A.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB board.
+ */
+
+#include "cn9131-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9131-DB setup A";
+};
+
+/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When SPI controller is enabled, NAND should be disabled.
+ */
+
+&cp0_spi1 {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-B.dts b/arch/arm64/boot/dts/marvell/cn9131-db-B.dts
new file mode 100644
index 000000000000..94e01192aed1
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9131-db-B.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB board (setup "B").
+ */
+
+#include "cn9131-db-A.dts"
+
+/ {
+ model = "Marvell Armada CN9131-DB setup B";
+};
+
+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
+ */
+
+&cp0_nand_controller {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dts b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
similarity index 97%
rename from arch/arm64/boot/dts/marvell/cn9131-db.dts
rename to arch/arm64/boot/dts/marvell/cn9131-db.dtsi
index 3c975f98b2a3..82471a83ad6d 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
@@ -1,14 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2019 Marvell International Ltd.
+ * Copyright (C) 2020 Marvell International Ltd.
*
* Device tree for the CN9131-DB board.
*/
-#include "cn9130-db.dts"
+#include "cn9130-db.dtsi"
/ {
- model = "Marvell Armada CN9131-DB";
compatible = "marvell,cn9131", "marvell,cn9130",
"marvell,armada-ap807-quad", "marvell,armada-ap807";
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db-A.dts b/arch/arm64/boot/dts/marvell/cn9132-db-A.dts
new file mode 100644
index 000000000000..1f2e6377afc3
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9132-db-A.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9132-DB board.
+ */
+
+#include "cn9132-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9132-DB setup A";
+};
+
+/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When SPI controller is enabled, NAND should be disabled.
+ */
+
+&cp0_spi1 {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db-B.dts b/arch/arm64/boot/dts/marvell/cn9132-db-B.dts
new file mode 100644
index 000000000000..7137a6f22d0f
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9132-db-B.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9132-DB board.
+ */
+
+#include "cn9132-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9132-DB setup B";
+};
+
+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
+ */
+
+&cp0_nand_controller {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dts b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
similarity index 97%
rename from arch/arm64/boot/dts/marvell/cn9132-db.dts
rename to arch/arm64/boot/dts/marvell/cn9132-db.dtsi
index 4ef0df3097ca..0c2d9f57318b 100644
--- a/arch/arm64/boot/dts/marvell/cn9132-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
@@ -1,14 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2019 Marvell International Ltd.
+ * Copyright (C) 2020 Marvell International Ltd.
*
* Device tree for the CN9132-DB board.
*/
-#include "cn9131-db.dts"
+#include "cn9131-db.dtsi"
/ {
- model = "Marvell Armada CN9132-DB";
compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
"marvell,armada-ap807-quad", "marvell,armada-ap807";
--
2.17.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 3/4] arm64: dts: cn913x: add device trees for topology B boards
2020-12-17 7:55 ` [PATCH v2 3/4] arm64: dts: cn913x: add device trees for topology B boards kostap
@ 2020-12-17 15:41 ` Andrew Lunn
2020-12-20 7:32 ` [EXT] " Kostya Porotchkin
0 siblings, 1 reply; 13+ messages in thread
From: Andrew Lunn @ 2020-12-17 15:41 UTC (permalink / raw)
To: kostap
Cc: tmn505, jaz, gregory.clement, nadavh, robh+dt, stefanc, mw,
bpeled, linux-arm-kernel, sebastian.hesselbarth
> diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
> index 3e5f2e7a040c..d9b924a63d89 100644
> --- a/arch/arm64/boot/dts/marvell/Makefile
> +++ b/arch/arm64/boot/dts/marvell/Makefile
> @@ -13,6 +13,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
> -dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
> -dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
> -dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
> +dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-A.dtb
> +dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-B.dtb
> +dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-A.dtb
> +dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb
> +dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-A.dtb
> +dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
Are the filenames consider ABI? I wonder if cn9130-db A should
continue to be called cn9130-db.dtb? Are bootloaders and image
installers going to break because the filename changed?
The rest of the changes look fine.
Andrew
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^ permalink raw reply [flat|nested] 13+ messages in thread* RE: [EXT] Re: [PATCH v2 3/4] arm64: dts: cn913x: add device trees for topology B boards
2020-12-17 15:41 ` Andrew Lunn
@ 2020-12-20 7:32 ` Kostya Porotchkin
2020-12-20 16:34 ` Andrew Lunn
0 siblings, 1 reply; 13+ messages in thread
From: Kostya Porotchkin @ 2020-12-20 7:32 UTC (permalink / raw)
To: Andrew Lunn
Cc: tmn505, jaz, gregory.clement, Nadav Haklai, robh+dt,
Stefan Chulski, mw, Ben Peled, linux-arm-kernel,
sebastian.hesselbarth
Hello, Andrew,
Thank you for review!
> -----Original Message-----
> From: Andrew Lunn <andrew@lunn.ch>
> Sent: Thursday, December 17, 2020 17:41
> To: Kostya Porotchkin <kostap@marvell.com>
> Cc: linux-arm-kernel@lists.infradead.org; tmn505@gmail.com;
> jaz@semihalf.com; gregory.clement@bootlin.com; Nadav Haklai
> <nadavh@marvell.com>; robh+dt@kernel.org; Stefan Chulski
> <stefanc@marvell.com>; mw@semihalf.com; Ben Peled
> <bpeled@marvell.com>; sebastian.hesselbarth@gmail.com
> Subject: [EXT] Re: [PATCH v2 3/4] arm64: dts: cn913x: add device trees for
> topology B boards
>
> External Email
>
> ----------------------------------------------------------------------
> > diff --git a/arch/arm64/boot/dts/marvell/Makefile
> > b/arch/arm64/boot/dts/marvell/Makefile
> > index 3e5f2e7a040c..d9b924a63d89 100644
> > --- a/arch/arm64/boot/dts/marvell/Makefile
> > +++ b/arch/arm64/boot/dts/marvell/Makefile
> > @@ -13,6 +13,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-
> db.dtb
> > dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
> > dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
> > dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
> > -dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
> > -dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
> > -dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
> > +dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-A.dtb
> > +dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-B.dtb
> > +dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-A.dtb
> > +dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb
> > +dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-A.dtb
> > +dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
>
> Are the filenames consider ABI? I wonder if cn9130-db A should continue to
> be called cn9130-db.dtb? Are bootloaders and image installers going to break
> because the filename changed?
[KP] I wanted to
1) make the DTS naming match the current SDK code
2) avoid similarity between DTS and DTSI names
I do not expect wide usage of DB platforms at this time, I expect the CRB to be more popular due to its size and price.
Do you think it may cause a problem?
Kosta
>
> The rest of the changes look fine.
>
> Andrew
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [EXT] Re: [PATCH v2 3/4] arm64: dts: cn913x: add device trees for topology B boards
2020-12-20 7:32 ` [EXT] " Kostya Porotchkin
@ 2020-12-20 16:34 ` Andrew Lunn
2020-12-21 6:57 ` Kostya Porotchkin
0 siblings, 1 reply; 13+ messages in thread
From: Andrew Lunn @ 2020-12-20 16:34 UTC (permalink / raw)
To: Kostya Porotchkin
Cc: tmn505, jaz, gregory.clement, Nadav Haklai, robh+dt,
Stefan Chulski, mw, Ben Peled, linux-arm-kernel,
sebastian.hesselbarth
> 1) make the DTS naming match the current SDK code
Where do i found the SDK?
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread* RE: [EXT] Re: [PATCH v2 3/4] arm64: dts: cn913x: add device trees for topology B boards
2020-12-20 16:34 ` Andrew Lunn
@ 2020-12-21 6:57 ` Kostya Porotchkin
2020-12-21 13:58 ` Andrew Lunn
0 siblings, 1 reply; 13+ messages in thread
From: Kostya Porotchkin @ 2020-12-21 6:57 UTC (permalink / raw)
To: Andrew Lunn
Cc: tmn505, jaz, gregory.clement, Nadav Haklai, robh+dt,
Stefan Chulski, mw, Ben Peled, linux-arm-kernel,
sebastian.hesselbarth
> -----Original Message-----
> From: Andrew Lunn <andrew@lunn.ch>
> Sent: Sunday, December 20, 2020 18:35
> To: Kostya Porotchkin <kostap@marvell.com>
> Cc: linux-arm-kernel@lists.infradead.org; tmn505@gmail.com;
> jaz@semihalf.com; gregory.clement@bootlin.com; Nadav Haklai
> <nadavh@marvell.com>; robh+dt@kernel.org; Stefan Chulski
> <stefanc@marvell.com>; mw@semihalf.com; Ben Peled
> <bpeled@marvell.com>; sebastian.hesselbarth@gmail.com
> Subject: Re: [EXT] Re: [PATCH v2 3/4] arm64: dts: cn913x: add device trees for
> topology B boards
>
> > 1) make the DTS naming match the current SDK code
>
> Where do i found the SDK?
[KP] Unfortunately the last Github published release is 2 years old.
The new SDK is available only after registration (and accepting the NDA terms) on marvell.com site.
Kosta
>
> Andrew
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [EXT] Re: [PATCH v2 3/4] arm64: dts: cn913x: add device trees for topology B boards
2020-12-21 6:57 ` Kostya Porotchkin
@ 2020-12-21 13:58 ` Andrew Lunn
2020-12-21 15:55 ` Kostya Porotchkin
0 siblings, 1 reply; 13+ messages in thread
From: Andrew Lunn @ 2020-12-21 13:58 UTC (permalink / raw)
To: Kostya Porotchkin
Cc: tmn505, jaz, gregory.clement, Nadav Haklai, robh+dt,
Stefan Chulski, mw, Ben Peled, linux-arm-kernel,
sebastian.hesselbarth
On Mon, Dec 21, 2020 at 06:57:46AM +0000, Kostya Porotchkin wrote:
>
>
> > -----Original Message-----
> > From: Andrew Lunn <andrew@lunn.ch>
> > Sent: Sunday, December 20, 2020 18:35
> > To: Kostya Porotchkin <kostap@marvell.com>
> > Cc: linux-arm-kernel@lists.infradead.org; tmn505@gmail.com;
> > jaz@semihalf.com; gregory.clement@bootlin.com; Nadav Haklai
> > <nadavh@marvell.com>; robh+dt@kernel.org; Stefan Chulski
> > <stefanc@marvell.com>; mw@semihalf.com; Ben Peled
> > <bpeled@marvell.com>; sebastian.hesselbarth@gmail.com
> > Subject: Re: [EXT] Re: [PATCH v2 3/4] arm64: dts: cn913x: add device trees for
> > topology B boards
> >
> > > 1) make the DTS naming match the current SDK code
> >
> > Where do i found the SDK?
> [KP] Unfortunately the last Github published release is 2 years old.
> The new SDK is available only after registration (and accepting the NDA terms) on marvell.com site.
Which leads to the question, why should the mainline kernel be changed
to be compatible with a closed source SDK?
What mainline should not do is break compatibility with
mainline. Which is why i think the existing DTB file needs to keep its
name, and B gets a new file name.
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [EXT] Re: [PATCH v2 3/4] arm64: dts: cn913x: add device trees for topology B boards
2020-12-21 13:58 ` Andrew Lunn
@ 2020-12-21 15:55 ` Kostya Porotchkin
0 siblings, 0 replies; 13+ messages in thread
From: Kostya Porotchkin @ 2020-12-21 15:55 UTC (permalink / raw)
To: Andrew Lunn
Cc: tmn505, jaz, gregory.clement, Nadav Haklai, robh+dt,
Stefan Chulski, mw, Ben Peled, linux-arm-kernel,
sebastian.hesselbarth
> -----Original Message-----
> From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org> On
> Behalf Of Andrew Lunn
> Sent: Monday, December 21, 2020 15:58
> To: Kostya Porotchkin <kostap@marvell.com>
> Cc: tmn505@gmail.com; jaz@semihalf.com; gregory.clement@bootlin.com;
> Nadav Haklai <nadavh@marvell.com>; robh+dt@kernel.org; Stefan Chulski
> <stefanc@marvell.com>; mw@semihalf.com; Ben Peled
> <bpeled@marvell.com>; linux-arm-kernel@lists.infradead.org;
> sebastian.hesselbarth@gmail.com
> Subject: Re: [EXT] Re: [PATCH v2 3/4] arm64: dts: cn913x: add device trees for
> topology B boards
>
> On Mon, Dec 21, 2020 at 06:57:46AM +0000, Kostya Porotchkin wrote:
> >
> >
> > > -----Original Message-----
> > > From: Andrew Lunn <andrew@lunn.ch>
> > > Sent: Sunday, December 20, 2020 18:35
> > > To: Kostya Porotchkin <kostap@marvell.com>
> > > Cc: linux-arm-kernel@lists.infradead.org; tmn505@gmail.com;
> > > jaz@semihalf.com; gregory.clement@bootlin.com; Nadav Haklai
> > > <nadavh@marvell.com>; robh+dt@kernel.org; Stefan Chulski
> > > <stefanc@marvell.com>; mw@semihalf.com; Ben Peled
> > > <bpeled@marvell.com>; sebastian.hesselbarth@gmail.com
> > > Subject: Re: [EXT] Re: [PATCH v2 3/4] arm64: dts: cn913x: add device
> > > trees for topology B boards
> > >
> > > > 1) make the DTS naming match the current SDK code
> > >
> > > Where do i found the SDK?
> > [KP] Unfortunately the last Github published release is 2 years old.
> > The new SDK is available only after registration (and accepting the NDA
> terms) on marvell.com site.
>
> Which leads to the question, why should the mainline kernel be changed to
> be compatible with a closed source SDK?
>
> What mainline should not do is break compatibility with mainline. Which is
> why i think the existing DTB file needs to keep its name, and B gets a new file
> name.
[KP] OK, I am issuing v3 with the required fix
Kosta
>
> Andrew
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> https://urldefense.proofpoint.com/v2/url?u=http-
> 3A__lists.infradead.org_mailman_listinfo_linux-2Darm-
> 2Dkernel&d=DwICAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=-
> N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=BL9A0Gh-
> Ms3OYS-W9ZPlfwCDLSqls8VBMlXnWVVyt_A&s=f0fzA_9FLRapsAeWB5-
> afYMajDMq_tDuXtvXSVWgr-U&e=
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 4/4] arm64: dts: add support for Marvell cn9130-crb platform
2020-12-17 7:55 [PATCH v2 0/4] DTS updates for Marvell Armada CN913x platforms kostap
` (2 preceding siblings ...)
2020-12-17 7:55 ` [PATCH v2 3/4] arm64: dts: cn913x: add device trees for topology B boards kostap
@ 2020-12-17 7:55 ` kostap
2020-12-17 15:43 ` Andrew Lunn
3 siblings, 1 reply; 13+ messages in thread
From: kostap @ 2020-12-17 7:55 UTC (permalink / raw)
To: linux-arm-kernel
Cc: tmn505, andrew, jaz, gregory.clement, nadavh, robh+dt,
Konstantin Porotchkin, stefanc, mw, bpeled,
sebastian.hesselbarth
From: Konstantin Porotchkin <kostap@marvell.com>
The Marvell reference platform CN9130-CRB is a small form factor
board in a metal case. The platform is based on CN9130 SoC with
addition of 8 Gigabit ports SOHO Ethernet switch.
The reference platform features the following:
* Up to 4 CPU cores ARMv8 Cortex-A72 CPU
* CPU core operating speed of up to 2.2GHz
* DDR4 DIMM – 8GB 64bit+ECC @ 2400Mhz.
* 1x eMMC 8GB device
* 1x uSD card 4 bits port on CP
* 1x 128MB SPI NOR flash memory
* 1x USB 3.0 Host port (Type A)
* 1x SATA Gen3 via M.2
* 1x USB 3.0 via M.2
* 1x SIM card slot
* 1x 1G Ethernet port via RGMII
* 1x 10G switch port over SFP+ connector
* 8x 1G ports through 88E6393X switch via XFI
* 1x 2.5G/1G/100M/10M port via HS_SGMII
* 1x PCI Express (PCIe)x1 Gen 3.0
* 1x PCI Express (PCIe)x4 Gen 3.0 via NVMe M.2
* JTAG port
The plaform supports two HW configurations - "A" and "B"
CN9130-CRB-A
* AP-MPP configuration: SDIO, UART
* CP0 Serdes configuration:
* Lane0-3: NVMe (PCIe x4)
* Lane4: XFI
* Lane5: HS_SGMII
2. CN9130-CRB-B
* AP-MPP configuration: SDIO, UART
* CP0-MPP configuration: RGMII, SDIO, I2C0, I2C1, SMI, XSMI
* CP0 Serdes configuration:
* Lane0: PCIe x1
* Lane1: USB3_0 x1
* Lane2: SATA x1
* Lane3: USB3_1 x1
* Lane4: XFI
* Lane5: HS_SGMII
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/Makefile | 2 +
arch/arm64/boot/dts/marvell/cn9130-crb-A.dts | 38 ++++
arch/arm64/boot/dts/marvell/cn9130-crb-B.dts | 46 ++++
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 222 ++++++++++++++++++++
4 files changed, 308 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index d9b924a63d89..04161e27272a 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -19,3 +19,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-A.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-A.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts b/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
new file mode 100644
index 000000000000..a7b6dfba8af5
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include "cn9130-crb.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-CRB-A";
+};
+
+&cp0_pcie0 {
+ status = "okay";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy0 0
+ &cp0_comphy1 0
+ &cp0_comphy2 0
+ &cp0_comphy3 0>;
+ iommu-map =
+ <0x0 &smmu 0x480 0x20>,
+ <0x100 &smmu 0x4a0 0x20>,
+ <0x200 &smmu 0x4c0 0x20>;
+ iommu-map-mask = <0x031f>;
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts b/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
new file mode 100644
index 000000000000..0904cb0309ae
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include "cn9130-crb.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-CRB-B";
+};
+
+&cp0_pcie0 {
+ status = "okay";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy0 0>;
+ iommu-map =
+ <0x0 &smmu 0x480 0x20>,
+ <0x100 &smmu 0x4a0 0x20>,
+ <0x200 &smmu 0x4c0 0x20>;
+ iommu-map-mask = <0x031f>;
+};
+
+&cp0_sata0 {
+ status = "okay";
+ sata-port@0 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy2 0>;
+ };
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+ phys = <&cp0_comphy1 0>;
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+ phys = <&cp0_comphy3 1>;
+};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
new file mode 100644
index 000000000000..1da19a5d3d4f
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include "cn9130.dtsi" /* include SoC device tree */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cp0_i2c0;
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp0_eth1;
+ ethernet2 = &cp0_eth2;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ap0_reg_mmc_vccq: ap0_mmc_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "ap0_mmc_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+
+ cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_usb3_0_phy0: cp0_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ };
+
+ cp0_usb3_0_phy1: cp0_usb3_phy1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_vbus1>;
+ };
+
+ cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+
+ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0_sd_vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* on-board eMMC U6 */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ bus-width = <8>;
+ status = "okay";
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ vqmmc-supply = <&ap0_reg_mmc_vccq>;
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+ cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
+ marvell,pins = "mpp55";
+ marvell,function = "gpio";
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ };
+};
+
+&cp0_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+ expander0: mcp23x17@20 {
+ compatible = "microchip,mcp23017";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ status = "okay";
+ };
+};
+
+&cp0_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c1_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+
+&cp0_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins
+ &cp0_sdhci_cd_pins_crb>;
+ bus-width = <4>;
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+ status = "okay";
+};
+
+&cp0_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi0_pins>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>; /* CS0 */
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+&cp0_mdio {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&cp0_xmdio {
+ status = "okay";
+ nbaset_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+&cp0_eth0 {
+ /* This port is connected to 88E6393X switch */
+ status = "okay";
+ phy-mode = "10gbase-kr";
+ managed = "in-band-status";
+ phys = <&cp0_comphy4 0>;
+};
+
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_eth2 {
+ /* This port uses "2500base-t" phy-mode */
+ status = "disabled";
+ phy = <&nbaset_phy0>;
+ phys = <&cp0_comphy5 2>;
+};
+
--
2.17.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 4/4] arm64: dts: add support for Marvell cn9130-crb platform
2020-12-17 7:55 ` [PATCH v2 4/4] arm64: dts: add support for Marvell cn9130-crb platform kostap
@ 2020-12-17 15:43 ` Andrew Lunn
0 siblings, 0 replies; 13+ messages in thread
From: Andrew Lunn @ 2020-12-17 15:43 UTC (permalink / raw)
To: kostap
Cc: tmn505, jaz, gregory.clement, nadavh, robh+dt, stefanc, mw,
bpeled, linux-arm-kernel, sebastian.hesselbarth
On Thu, Dec 17, 2020 at 09:55:42AM +0200, kostap@marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
>
> The Marvell reference platform CN9130-CRB is a small form factor
> board in a metal case. The platform is based on CN9130 SoC with
> addition of 8 Gigabit ports SOHO Ethernet switch.
> The reference platform features the following:
> * Up to 4 CPU cores ARMv8 Cortex-A72 CPU
> * CPU core operating speed of up to 2.2GHz
> * DDR4 DIMM – 8GB 64bit+ECC @ 2400Mhz.
> * 1x eMMC 8GB device
> * 1x uSD card 4 bits port on CP
> * 1x 128MB SPI NOR flash memory
> * 1x USB 3.0 Host port (Type A)
> * 1x SATA Gen3 via M.2
> * 1x USB 3.0 via M.2
> * 1x SIM card slot
> * 1x 1G Ethernet port via RGMII
> * 1x 10G switch port over SFP+ connector
> * 8x 1G ports through 88E6393X switch via XFI
> * 1x 2.5G/1G/100M/10M port via HS_SGMII
> * 1x PCI Express (PCIe)x1 Gen 3.0
> * 1x PCI Express (PCIe)x4 Gen 3.0 via NVMe M.2
> * JTAG port
>
> The plaform supports two HW configurations - "A" and "B"
> CN9130-CRB-A
> * AP-MPP configuration: SDIO, UART
> * CP0 Serdes configuration:
> * Lane0-3: NVMe (PCIe x4)
> * Lane4: XFI
> * Lane5: HS_SGMII
>
> 2. CN9130-CRB-B
> * AP-MPP configuration: SDIO, UART
> * CP0-MPP configuration: RGMII, SDIO, I2C0, I2C1, SMI, XSMI
> * CP0 Serdes configuration:
> * Lane0: PCIe x1
> * Lane1: USB3_0 x1
> * Lane2: SATA x1
> * Lane3: USB3_1 x1
> * Lane4: XFI
> * Lane5: HS_SGMII
>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
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^ permalink raw reply [flat|nested] 13+ messages in thread