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From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Mark Brown <broonie@kernel.org>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Peter Geis <pgwipeout@gmail.com>,
	Nicolas Chauvet <kwizart@gmail.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Kevin Hilman <khilman@kernel.org>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Viresh Kumar <vireshk@kernel.org>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>
Cc: devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-media@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-clk@vger.kernel.org
Subject: [PATCH v2 24/48] soc/tegra: pmc: Ensure that clock rates aren't too high
Date: Thu, 17 Dec 2020 21:06:14 +0300	[thread overview]
Message-ID: <20201217180638.22748-25-digetx@gmail.com> (raw)
In-Reply-To: <20201217180638.22748-1-digetx@gmail.com>

Switch all clocks of a power domain to a safe rate which is suitable
for all possible voltages in order to ensure that hardware constraints
aren't violated when power domain state toggles.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/soc/tegra/pmc.c | 92 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 90 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 985373ce52b1..8edcd5b319f6 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -237,6 +237,7 @@ struct tegra_powergate {
 	unsigned int id;
 	struct clk **clks;
 	unsigned int num_clks;
+	unsigned long *clk_rates;
 	struct reset_control *reset;
 };
 
@@ -586,6 +587,57 @@ static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
 	return 0;
 }
 
+static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
+{
+	unsigned long safe_rate = 100 * 1000 * 1000;
+	unsigned int i;
+	int err;
+
+	for (i = 0; i < pg->num_clks; i++) {
+		pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
+
+		if (!pg->clk_rates[i]) {
+			err = -EINVAL;
+			goto out;
+		}
+
+		if (pg->clk_rates[i] <= safe_rate)
+			continue;
+
+		/*
+		 * We don't know whether voltage state is okay for the
+		 * current clock rate, hence it's better to temporally
+		 * switch clock to a safe rate which is suitable for
+		 * all voltages, before enabling the clock.
+		 */
+		err = clk_set_rate(pg->clks[i], safe_rate);
+		if (err)
+			goto out;
+	}
+
+	return 0;
+
+out:
+	while (i--)
+		clk_set_rate(pg->clks[i], pg->clk_rates[i]);
+
+	return err;
+}
+
+static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
+{
+	unsigned int i;
+	int err;
+
+	for (i = 0; i < pg->num_clks; i++) {
+		err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
+		if (err)
+			return err;
+	}
+
+	return 0;
+}
+
 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
 {
 	unsigned int i;
@@ -636,10 +688,14 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,
 
 	usleep_range(10, 20);
 
-	err = tegra_powergate_enable_clocks(pg);
+	err = tegra_powergate_prepare_clocks(pg);
 	if (err)
 		goto powergate_off;
 
+	err = tegra_powergate_enable_clocks(pg);
+	if (err)
+		goto unprepare_clks;
+
 	usleep_range(10, 20);
 
 	err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
@@ -670,12 +726,19 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,
 	if (disable_clocks)
 		tegra_powergate_disable_clocks(pg);
 
+	err = tegra_powergate_unprepare_clocks(pg);
+	if (err)
+		return err;
+
 	return 0;
 
 disable_clks:
 	tegra_powergate_disable_clocks(pg);
 	usleep_range(10, 20);
 
+unprepare_clks:
+	tegra_powergate_unprepare_clocks(pg);
+
 powergate_off:
 	tegra_powergate_set(pg->pmc, pg->id, false);
 
@@ -686,10 +749,14 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg)
 {
 	int err;
 
-	err = tegra_powergate_enable_clocks(pg);
+	err = tegra_powergate_prepare_clocks(pg);
 	if (err)
 		return err;
 
+	err = tegra_powergate_enable_clocks(pg);
+	if (err)
+		goto unprepare_clks;
+
 	usleep_range(10, 20);
 
 	err = reset_control_assert(pg->reset);
@@ -706,6 +773,10 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg)
 	if (err)
 		goto assert_resets;
 
+	err = tegra_powergate_unprepare_clocks(pg);
+	if (err)
+		return err;
+
 	return 0;
 
 assert_resets:
@@ -717,6 +788,9 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg)
 disable_clks:
 	tegra_powergate_disable_clocks(pg);
 
+unprepare_clks:
+	tegra_powergate_unprepare_clocks(pg);
+
 	return err;
 }
 
@@ -834,6 +908,12 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
 	if (!pg)
 		return -ENOMEM;
 
+	pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
+	if (!pg->clk_rates) {
+		kfree(pg->clks);
+		return -ENOMEM;
+	}
+
 	pg->id = id;
 	pg->clks = &clk;
 	pg->num_clks = 1;
@@ -845,6 +925,7 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
 		dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
 			err);
 
+	kfree(pg->clk_rates);
 	kfree(pg);
 
 	return err;
@@ -995,6 +1076,12 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
 	if (!pg->clks)
 		return -ENOMEM;
 
+	pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
+	if (!pg->clk_rates) {
+		kfree(pg->clks);
+		return -ENOMEM;
+	}
+
 	for (i = 0; i < count; i++) {
 		pg->clks[i] = of_clk_get(np, i);
 		if (IS_ERR(pg->clks[i])) {
@@ -1011,6 +1098,7 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
 	while (i--)
 		clk_put(pg->clks[i]);
 
+	kfree(pg->clk_rates);
 	kfree(pg->clks);
 
 	return err;
-- 
2.29.2


WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Mark Brown <broonie@kernel.org>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Peter Geis <pgwipeout@gmail.com>,
	Nicolas Chauvet <kwizart@gmail.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Kevin Hilman <khilman@kernel.org>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Viresh Kumar <vireshk@kernel.org>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>
Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-media@vger.kernel.org
Subject: [PATCH v2 24/48] soc/tegra: pmc: Ensure that clock rates aren't too high
Date: Thu, 17 Dec 2020 21:06:14 +0300	[thread overview]
Message-ID: <20201217180638.22748-25-digetx@gmail.com> (raw)
In-Reply-To: <20201217180638.22748-1-digetx@gmail.com>

Switch all clocks of a power domain to a safe rate which is suitable
for all possible voltages in order to ensure that hardware constraints
aren't violated when power domain state toggles.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/soc/tegra/pmc.c | 92 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 90 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 985373ce52b1..8edcd5b319f6 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -237,6 +237,7 @@ struct tegra_powergate {
 	unsigned int id;
 	struct clk **clks;
 	unsigned int num_clks;
+	unsigned long *clk_rates;
 	struct reset_control *reset;
 };
 
@@ -586,6 +587,57 @@ static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
 	return 0;
 }
 
+static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
+{
+	unsigned long safe_rate = 100 * 1000 * 1000;
+	unsigned int i;
+	int err;
+
+	for (i = 0; i < pg->num_clks; i++) {
+		pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
+
+		if (!pg->clk_rates[i]) {
+			err = -EINVAL;
+			goto out;
+		}
+
+		if (pg->clk_rates[i] <= safe_rate)
+			continue;
+
+		/*
+		 * We don't know whether voltage state is okay for the
+		 * current clock rate, hence it's better to temporally
+		 * switch clock to a safe rate which is suitable for
+		 * all voltages, before enabling the clock.
+		 */
+		err = clk_set_rate(pg->clks[i], safe_rate);
+		if (err)
+			goto out;
+	}
+
+	return 0;
+
+out:
+	while (i--)
+		clk_set_rate(pg->clks[i], pg->clk_rates[i]);
+
+	return err;
+}
+
+static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
+{
+	unsigned int i;
+	int err;
+
+	for (i = 0; i < pg->num_clks; i++) {
+		err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
+		if (err)
+			return err;
+	}
+
+	return 0;
+}
+
 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
 {
 	unsigned int i;
@@ -636,10 +688,14 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,
 
 	usleep_range(10, 20);
 
-	err = tegra_powergate_enable_clocks(pg);
+	err = tegra_powergate_prepare_clocks(pg);
 	if (err)
 		goto powergate_off;
 
+	err = tegra_powergate_enable_clocks(pg);
+	if (err)
+		goto unprepare_clks;
+
 	usleep_range(10, 20);
 
 	err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
@@ -670,12 +726,19 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,
 	if (disable_clocks)
 		tegra_powergate_disable_clocks(pg);
 
+	err = tegra_powergate_unprepare_clocks(pg);
+	if (err)
+		return err;
+
 	return 0;
 
 disable_clks:
 	tegra_powergate_disable_clocks(pg);
 	usleep_range(10, 20);
 
+unprepare_clks:
+	tegra_powergate_unprepare_clocks(pg);
+
 powergate_off:
 	tegra_powergate_set(pg->pmc, pg->id, false);
 
@@ -686,10 +749,14 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg)
 {
 	int err;
 
-	err = tegra_powergate_enable_clocks(pg);
+	err = tegra_powergate_prepare_clocks(pg);
 	if (err)
 		return err;
 
+	err = tegra_powergate_enable_clocks(pg);
+	if (err)
+		goto unprepare_clks;
+
 	usleep_range(10, 20);
 
 	err = reset_control_assert(pg->reset);
@@ -706,6 +773,10 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg)
 	if (err)
 		goto assert_resets;
 
+	err = tegra_powergate_unprepare_clocks(pg);
+	if (err)
+		return err;
+
 	return 0;
 
 assert_resets:
@@ -717,6 +788,9 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg)
 disable_clks:
 	tegra_powergate_disable_clocks(pg);
 
+unprepare_clks:
+	tegra_powergate_unprepare_clocks(pg);
+
 	return err;
 }
 
@@ -834,6 +908,12 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
 	if (!pg)
 		return -ENOMEM;
 
+	pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
+	if (!pg->clk_rates) {
+		kfree(pg->clks);
+		return -ENOMEM;
+	}
+
 	pg->id = id;
 	pg->clks = &clk;
 	pg->num_clks = 1;
@@ -845,6 +925,7 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
 		dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
 			err);
 
+	kfree(pg->clk_rates);
 	kfree(pg);
 
 	return err;
@@ -995,6 +1076,12 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
 	if (!pg->clks)
 		return -ENOMEM;
 
+	pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
+	if (!pg->clk_rates) {
+		kfree(pg->clks);
+		return -ENOMEM;
+	}
+
 	for (i = 0; i < count; i++) {
 		pg->clks[i] = of_clk_get(np, i);
 		if (IS_ERR(pg->clks[i])) {
@@ -1011,6 +1098,7 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
 	while (i--)
 		clk_put(pg->clks[i]);
 
+	kfree(pg->clk_rates);
 	kfree(pg->clks);
 
 	return err;
-- 
2.29.2

_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel

WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Mark Brown <broonie@kernel.org>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Peter Geis <pgwipeout@gmail.com>,
	Nicolas Chauvet <kwizart@gmail.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Kevin Hilman <khilman@kernel.org>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Viresh Kumar <vireshk@kernel.org>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>
Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-media@vger.kernel.org
Subject: [PATCH v2 24/48] soc/tegra: pmc: Ensure that clock rates aren't too high
Date: Thu, 17 Dec 2020 21:06:14 +0300	[thread overview]
Message-ID: <20201217180638.22748-25-digetx@gmail.com> (raw)
In-Reply-To: <20201217180638.22748-1-digetx@gmail.com>

Switch all clocks of a power domain to a safe rate which is suitable
for all possible voltages in order to ensure that hardware constraints
aren't violated when power domain state toggles.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/soc/tegra/pmc.c | 92 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 90 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 985373ce52b1..8edcd5b319f6 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -237,6 +237,7 @@ struct tegra_powergate {
 	unsigned int id;
 	struct clk **clks;
 	unsigned int num_clks;
+	unsigned long *clk_rates;
 	struct reset_control *reset;
 };
 
@@ -586,6 +587,57 @@ static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
 	return 0;
 }
 
+static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
+{
+	unsigned long safe_rate = 100 * 1000 * 1000;
+	unsigned int i;
+	int err;
+
+	for (i = 0; i < pg->num_clks; i++) {
+		pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
+
+		if (!pg->clk_rates[i]) {
+			err = -EINVAL;
+			goto out;
+		}
+
+		if (pg->clk_rates[i] <= safe_rate)
+			continue;
+
+		/*
+		 * We don't know whether voltage state is okay for the
+		 * current clock rate, hence it's better to temporally
+		 * switch clock to a safe rate which is suitable for
+		 * all voltages, before enabling the clock.
+		 */
+		err = clk_set_rate(pg->clks[i], safe_rate);
+		if (err)
+			goto out;
+	}
+
+	return 0;
+
+out:
+	while (i--)
+		clk_set_rate(pg->clks[i], pg->clk_rates[i]);
+
+	return err;
+}
+
+static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
+{
+	unsigned int i;
+	int err;
+
+	for (i = 0; i < pg->num_clks; i++) {
+		err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
+		if (err)
+			return err;
+	}
+
+	return 0;
+}
+
 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
 {
 	unsigned int i;
@@ -636,10 +688,14 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,
 
 	usleep_range(10, 20);
 
-	err = tegra_powergate_enable_clocks(pg);
+	err = tegra_powergate_prepare_clocks(pg);
 	if (err)
 		goto powergate_off;
 
+	err = tegra_powergate_enable_clocks(pg);
+	if (err)
+		goto unprepare_clks;
+
 	usleep_range(10, 20);
 
 	err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
@@ -670,12 +726,19 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,
 	if (disable_clocks)
 		tegra_powergate_disable_clocks(pg);
 
+	err = tegra_powergate_unprepare_clocks(pg);
+	if (err)
+		return err;
+
 	return 0;
 
 disable_clks:
 	tegra_powergate_disable_clocks(pg);
 	usleep_range(10, 20);
 
+unprepare_clks:
+	tegra_powergate_unprepare_clocks(pg);
+
 powergate_off:
 	tegra_powergate_set(pg->pmc, pg->id, false);
 
@@ -686,10 +749,14 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg)
 {
 	int err;
 
-	err = tegra_powergate_enable_clocks(pg);
+	err = tegra_powergate_prepare_clocks(pg);
 	if (err)
 		return err;
 
+	err = tegra_powergate_enable_clocks(pg);
+	if (err)
+		goto unprepare_clks;
+
 	usleep_range(10, 20);
 
 	err = reset_control_assert(pg->reset);
@@ -706,6 +773,10 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg)
 	if (err)
 		goto assert_resets;
 
+	err = tegra_powergate_unprepare_clocks(pg);
+	if (err)
+		return err;
+
 	return 0;
 
 assert_resets:
@@ -717,6 +788,9 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg)
 disable_clks:
 	tegra_powergate_disable_clocks(pg);
 
+unprepare_clks:
+	tegra_powergate_unprepare_clocks(pg);
+
 	return err;
 }
 
@@ -834,6 +908,12 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
 	if (!pg)
 		return -ENOMEM;
 
+	pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
+	if (!pg->clk_rates) {
+		kfree(pg->clks);
+		return -ENOMEM;
+	}
+
 	pg->id = id;
 	pg->clks = &clk;
 	pg->num_clks = 1;
@@ -845,6 +925,7 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
 		dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
 			err);
 
+	kfree(pg->clk_rates);
 	kfree(pg);
 
 	return err;
@@ -995,6 +1076,12 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
 	if (!pg->clks)
 		return -ENOMEM;
 
+	pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
+	if (!pg->clk_rates) {
+		kfree(pg->clks);
+		return -ENOMEM;
+	}
+
 	for (i = 0; i < count; i++) {
 		pg->clks[i] = of_clk_get(np, i);
 		if (IS_ERR(pg->clks[i])) {
@@ -1011,6 +1098,7 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
 	while (i--)
 		clk_put(pg->clks[i]);
 
+	kfree(pg->clk_rates);
 	kfree(pg->clks);
 
 	return err;
-- 
2.29.2

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https://lists.freedesktop.org/mailman/listinfo/dri-devel

  parent reply	other threads:[~2020-12-17 18:13 UTC|newest]

Thread overview: 369+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-17 18:05 [PATCH v2 00/48] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs Dmitry Osipenko
2020-12-17 18:05 ` Dmitry Osipenko
2020-12-17 18:05 ` Dmitry Osipenko
2020-12-17 18:05 ` [PATCH v2 01/48] dt-bindings: memory: tegra20: emc: Replace core regulator with power domain Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-21 22:53   ` Rob Herring
2020-12-21 22:53     ` Rob Herring
2020-12-21 22:53     ` Rob Herring
2020-12-17 18:05 ` [PATCH v2 02/48] dt-bindings: memory: tegra30: " Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-21 22:54   ` Rob Herring
2020-12-21 22:54     ` Rob Herring
2020-12-21 22:54     ` Rob Herring
2020-12-22 19:16     ` Dmitry Osipenko
2020-12-22 19:16       ` Dmitry Osipenko
2020-12-22 19:16       ` Dmitry Osipenko
2020-12-17 18:05 ` [PATCH v2 03/48] dt-bindings: memory: tegra124: " Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-17 18:05 ` [PATCH v2 04/48] dt-bindings: host1x: Document OPP and power domain properties Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-22  0:09   ` Rob Herring
2020-12-22  0:09     ` Rob Herring
2020-12-22  0:09     ` Rob Herring
2020-12-17 18:05 ` [PATCH v2 05/48] media: dt: bindings: tegra-vde: " Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-22  0:09   ` Rob Herring
2020-12-22  0:09     ` Rob Herring
2020-12-22  0:09     ` Rob Herring
2020-12-17 18:05 ` [PATCH v2 06/48] dt-bindings: clock: tegra: Document clocks sub-node Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-22  0:14   ` Rob Herring
2020-12-22  0:14     ` Rob Herring
2020-12-22  0:14     ` Rob Herring
2020-12-22 19:16     ` Dmitry Osipenko
2020-12-22 19:16       ` Dmitry Osipenko
2020-12-22 19:16       ` Dmitry Osipenko
2020-12-17 18:05 ` [PATCH v2 07/48] dt-bindings: arm: tegra: Add binding for core power domain Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-19 10:57   ` Krzysztof Kozlowski
2020-12-19 10:57     ` Krzysztof Kozlowski
2020-12-19 10:57     ` Krzysztof Kozlowski
2020-12-20 18:26     ` Dmitry Osipenko
2020-12-20 18:26       ` Dmitry Osipenko
2020-12-20 18:26       ` Dmitry Osipenko
2020-12-17 18:05 ` [PATCH v2 08/48] regulator: Make regulator_sync_voltage() usable by coupled regulators Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-17 18:05 ` [PATCH v2 09/48] opp: Add dev_pm_opp_sync_regulators() Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-17 18:05   ` Dmitry Osipenko
2020-12-22  6:41   ` Viresh Kumar
2020-12-22  6:41     ` Viresh Kumar
2020-12-22  6:41     ` Viresh Kumar
2020-12-17 18:06 ` [PATCH v2 10/48] opp: Add dev_pm_opp_set_voltage() Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-22  6:41   ` Viresh Kumar
2020-12-22  6:41     ` Viresh Kumar
2020-12-22  6:41     ` Viresh Kumar
2020-12-17 18:06 ` [PATCH v2 11/48] opp: Add dev_pm_opp_find_level_ceil() Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-22  6:42   ` Viresh Kumar
2020-12-22  6:42     ` Viresh Kumar
2020-12-22  6:42     ` Viresh Kumar
2020-12-22 19:15     ` Dmitry Osipenko
2020-12-22 19:15       ` Dmitry Osipenko
2020-12-22 19:15       ` Dmitry Osipenko
2020-12-23  4:19       ` Viresh Kumar
2020-12-23  4:19         ` Viresh Kumar
2020-12-23  4:19         ` Viresh Kumar
2020-12-23 20:37         ` Dmitry Osipenko
2020-12-23 20:37           ` Dmitry Osipenko
2020-12-23 20:37           ` Dmitry Osipenko
2020-12-24  6:43           ` Viresh Kumar
2020-12-24  6:43             ` Viresh Kumar
2020-12-24  6:43             ` Viresh Kumar
2020-12-24 13:00             ` Dmitry Osipenko
2020-12-24 13:00               ` Dmitry Osipenko
2020-12-24 13:00               ` Dmitry Osipenko
2020-12-28  6:22               ` Viresh Kumar
2020-12-28  6:22                 ` Viresh Kumar
2020-12-28  6:22                 ` Viresh Kumar
2020-12-28 14:03                 ` Dmitry Osipenko
2020-12-28 14:03                   ` Dmitry Osipenko
2020-12-28 14:03                   ` Dmitry Osipenko
2020-12-30  4:46                   ` Viresh Kumar
2020-12-30  4:46                     ` Viresh Kumar
2020-12-30  4:46                     ` Viresh Kumar
2020-12-30 14:02                     ` Dmitry Osipenko
2020-12-30 14:02                       ` Dmitry Osipenko
2020-12-30 14:02                       ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 12/48] opp: Add dev_pm_opp_get_required_pstate() Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 13/48] opp: Add resource-managed versions of OPP API functions Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-22  8:55   ` Viresh Kumar
2020-12-22  8:55     ` Viresh Kumar
2020-12-22  8:55     ` Viresh Kumar
2020-12-22 19:14     ` Dmitry Osipenko
2020-12-22 19:14       ` Dmitry Osipenko
2020-12-22 19:14       ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 14/48] opp: Filter out OPPs based on availability of a required-OPP Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-22  8:59   ` Viresh Kumar
2020-12-22  8:59     ` Viresh Kumar
2020-12-22  8:59     ` Viresh Kumar
2020-12-22 19:17     ` Dmitry Osipenko
2020-12-22 19:17       ` Dmitry Osipenko
2020-12-22 19:17       ` Dmitry Osipenko
2020-12-23  4:22       ` Viresh Kumar
2020-12-23  4:22         ` Viresh Kumar
2020-12-23  4:22         ` Viresh Kumar
2020-12-23 20:48         ` Dmitry Osipenko
2020-12-23 20:48           ` Dmitry Osipenko
2020-12-23 20:48           ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 15/48] opp: Support set_opp() customization without requiring to use regulators Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-22  9:01   ` Viresh Kumar
2020-12-22  9:01     ` Viresh Kumar
2020-12-22  9:01     ` Viresh Kumar
2020-12-22 19:18     ` Dmitry Osipenko
2020-12-22 19:18       ` Dmitry Osipenko
2020-12-22 19:18       ` Dmitry Osipenko
2020-12-23  6:01   ` Viresh Kumar
2020-12-23  6:01     ` Viresh Kumar
2020-12-23  6:01     ` Viresh Kumar
2020-12-23 20:38     ` Dmitry Osipenko
2020-12-23 20:38       ` Dmitry Osipenko
2020-12-23 20:38       ` Dmitry Osipenko
2020-12-24  4:10       ` Viresh Kumar
2020-12-24  4:10         ` Viresh Kumar
2020-12-24  4:10         ` Viresh Kumar
2020-12-24 12:16         ` Dmitry Osipenko
2020-12-24 12:16           ` Dmitry Osipenko
2020-12-24 12:16           ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 16/48] opp: Handle missing OPP table in dev_pm_opp_xlate_performance_state() Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 17/48] opp: Correct debug message in _opp_add_static_v2() Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 18/48] opp: Print OPP level in debug message of _opp_add_static_v2() Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 19/48] opp: Fix adding OPP entries in a wrong order if rate is unavailable Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-22  9:12   ` Viresh Kumar
2020-12-22  9:12     ` Viresh Kumar
2020-12-22  9:12     ` Viresh Kumar
2020-12-22 19:19     ` Dmitry Osipenko
2020-12-22 19:19       ` Dmitry Osipenko
2020-12-22 19:19       ` Dmitry Osipenko
2020-12-23  4:34       ` Viresh Kumar
2020-12-23  4:34         ` Viresh Kumar
2020-12-23  4:34         ` Viresh Kumar
2020-12-23 20:36         ` Dmitry Osipenko
2020-12-23 20:36           ` Dmitry Osipenko
2020-12-23 20:36           ` Dmitry Osipenko
2020-12-24  6:28           ` Viresh Kumar
2020-12-24  6:28             ` Viresh Kumar
2020-12-24  6:28             ` Viresh Kumar
2020-12-24 12:14             ` Dmitry Osipenko
2020-12-24 12:14               ` Dmitry Osipenko
2020-12-24 12:14               ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 20/48] PM: domains: Make set_performance_state() callback optional Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2021-01-11  9:10   ` Ulf Hansson
2020-12-17 18:06 ` [PATCH v2 21/48] PM: domains: Add "performance" column to debug summary Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2021-01-11  9:13   ` Ulf Hansson
2021-01-11 11:28     ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 22/48] soc/tegra: pmc: Fix imbalanced clock disabling in error code path Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 23/48] soc/tegra: pmc: Pulse resets after removing power clamp Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-30 14:56   ` Dmitry Osipenko
2020-12-30 14:56     ` Dmitry Osipenko
2020-12-30 14:56     ` Dmitry Osipenko
2020-12-17 18:06 ` Dmitry Osipenko [this message]
2020-12-17 18:06   ` [PATCH v2 24/48] soc/tegra: pmc: Ensure that clock rates aren't too high Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 25/48] soc/tegra: pmc: Print out domain name when reset fails to acquire Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 26/48] soc/tegra: Add devm_tegra_core_dev_init_opp_table() Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 27/48] soc/tegra: Add CONFIG_SOC_TEGRA_COMMON and select PM_OPP by default Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 28/48] soc/tegra: Introduce core power domain driver Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-22  6:40   ` Viresh Kumar
2020-12-22  6:40     ` Viresh Kumar
2020-12-22  6:40     ` Viresh Kumar
2020-12-22 19:21     ` Dmitry Osipenko
2020-12-22 19:21       ` Dmitry Osipenko
2020-12-22 19:21       ` Dmitry Osipenko
2020-12-22 19:39       ` Dmitry Osipenko
2020-12-22 19:39         ` Dmitry Osipenko
2020-12-22 19:39         ` Dmitry Osipenko
2020-12-23  5:57         ` Viresh Kumar
2020-12-23  5:57           ` Viresh Kumar
2020-12-23  5:57           ` Viresh Kumar
2020-12-23 20:37           ` Dmitry Osipenko
2020-12-23 20:37             ` Dmitry Osipenko
2020-12-23 20:37             ` Dmitry Osipenko
2020-12-23 20:59             ` Dmitry Osipenko
2020-12-23 20:59               ` Dmitry Osipenko
2020-12-23 20:59               ` Dmitry Osipenko
2020-12-24  6:51             ` Viresh Kumar
2020-12-24  6:51               ` Viresh Kumar
2020-12-24  6:51               ` Viresh Kumar
2020-12-24 12:14               ` Dmitry Osipenko
2020-12-24 12:14                 ` Dmitry Osipenko
2020-12-24 12:14                 ` Dmitry Osipenko
2021-01-12 13:57   ` Ulf Hansson
2021-01-12 13:57     ` Ulf Hansson
2021-01-12 13:57     ` Ulf Hansson
2020-12-17 18:06 ` [PATCH v2 29/48] soc/tegra: pmc: Link domains to the parent Core domain Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2021-01-12 13:30   ` Ulf Hansson
2021-01-12 16:22     ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 30/48] soc/tegra: regulators: Fix locking up when voltage-spread is out of range Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 31/48] soc/tegra: regulators: Support Core domain state syncing Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2021-01-12 13:57   ` Ulf Hansson
2021-01-12 13:57     ` Ulf Hansson
2021-01-12 13:57     ` Ulf Hansson
2020-12-17 18:06 ` [PATCH v2 32/48] clk: tegra: Support runtime PM, power domain and OPP Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 33/48] gpu: host1x: Add host1x_channel_stop() Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 34/48] gpu: host1x: Support power management Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:21   ` Mikko Perttunen
2020-12-17 18:21     ` Mikko Perttunen
2020-12-17 18:21     ` Mikko Perttunen
2020-12-17 18:45     ` Dmitry Osipenko
2020-12-17 18:45       ` Dmitry Osipenko
2020-12-17 18:45       ` Dmitry Osipenko
2020-12-17 20:58       ` Dmitry Osipenko
2020-12-17 20:58         ` Dmitry Osipenko
2020-12-17 20:58         ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 35/48] drm/tegra: dc: Support OPP and SoC core voltage scaling Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2021-01-12 14:16   ` Ulf Hansson
2020-12-17 18:06 ` [PATCH v2 36/48] drm/tegra: gr2d: Correct swapped device-tree compatibles Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 37/48] drm/tegra: gr2d: Support OPP and power management Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 38/48] drm/tegra: g3d: " Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 39/48] drm/tegra: vic: Stop channel before suspending Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 40/48] media: staging: tegra-vde: Support OPP and generic power domain Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 41/48] memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table() Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-19 11:02   ` Krzysztof Kozlowski
2020-12-19 11:02     ` Krzysztof Kozlowski
2020-12-19 11:02     ` Krzysztof Kozlowski
2020-12-20 18:34     ` Dmitry Osipenko
2020-12-20 18:34       ` Dmitry Osipenko
2020-12-20 18:34       ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 42/48] memory: tegra30-emc: " Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 43/48] ARM: tegra: Add OPP tables and power domains to Tegra20 device-tree Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-22  5:47   ` Viresh Kumar
2020-12-22  5:47     ` Viresh Kumar
2020-12-22  5:47     ` Viresh Kumar
2020-12-22 19:24     ` Dmitry Osipenko
2020-12-22 19:24       ` Dmitry Osipenko
2020-12-22 19:24       ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 44/48] ARM: tegra: Add OPP tables and power domains to Tegra30 device-tree Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-22  9:14   ` Viresh Kumar
2020-12-22  9:14     ` Viresh Kumar
2020-12-22  9:14     ` Viresh Kumar
2020-12-22 19:25     ` Dmitry Osipenko
2020-12-22 19:25       ` Dmitry Osipenko
2020-12-22 19:25       ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 45/48] ARM: tegra: acer-a500: Enable core voltage scaling Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 46/48] ARM: tegra: ventana: " Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 47/48] ARM: tegra: ventana: Support CPU voltage scaling and thermal throttling Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:28   ` Daniel Lezcano
2020-12-17 18:28     ` Daniel Lezcano
2020-12-17 18:28     ` Daniel Lezcano
2020-12-17 19:01     ` Dmitry Osipenko
2020-12-17 19:01       ` Dmitry Osipenko
2020-12-17 19:01       ` Dmitry Osipenko
2020-12-17 19:36       ` Daniel Lezcano
2020-12-17 19:36         ` Daniel Lezcano
2020-12-17 19:36         ` Daniel Lezcano
2020-12-17 20:28         ` Dmitry Osipenko
2020-12-17 20:28           ` Dmitry Osipenko
2020-12-17 20:28           ` Dmitry Osipenko
2020-12-17 21:19           ` Daniel Lezcano
2020-12-17 21:19             ` Daniel Lezcano
2020-12-17 21:19             ` Daniel Lezcano
2020-12-17 21:56             ` Dmitry Osipenko
2020-12-17 21:56               ` Dmitry Osipenko
2020-12-17 21:56               ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 48/48] ARM: tegra: cardhu: " Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:06   ` Dmitry Osipenko
2020-12-17 18:28   ` Daniel Lezcano
2020-12-17 18:28     ` Daniel Lezcano
2020-12-17 18:28     ` Daniel Lezcano
2020-12-18  7:14 ` [PATCH v2 00/48] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs Viresh Kumar
2020-12-18  7:14   ` Viresh Kumar
2020-12-18  7:14   ` Viresh Kumar
2020-12-18 13:51   ` Dmitry Osipenko
2020-12-18 13:51     ` Dmitry Osipenko
2020-12-18 13:51     ` Dmitry Osipenko
2020-12-22  9:15     ` Viresh Kumar
2020-12-22  9:15       ` Viresh Kumar
2020-12-22  9:15       ` Viresh Kumar
2020-12-22 19:14       ` Dmitry Osipenko
2020-12-22 19:14         ` Dmitry Osipenko
2020-12-22 19:14         ` Dmitry Osipenko
2021-01-05 17:11 ` Krzysztof Kozlowski
2021-01-05 17:11   ` Krzysztof Kozlowski
2021-01-05 17:11   ` Krzysztof Kozlowski
2021-01-07 19:39   ` Dmitry Osipenko
2021-01-07 19:39     ` Dmitry Osipenko
2021-01-07 19:39     ` Dmitry Osipenko

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