[v4 00/17] Enable ARM Trusted Firmware for U-Boot

[v4 00/17] Enable ARM Trusted Firmware for U-Boot

[Siew Chin Lim]

This is the 4th version of patchset to enable ARM Trusted Firmware
for U-Boot for Intel Stratix10 and Agilex platform.

New U-boot flow with ARM Trusted Firmware (ATF) support:
SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)

SPL loads the u-boot.itb which consist of:
1) u-boot-nodtb.bin (U-Boot Proper image)
2) u-boot.dtb (U-Boot Proper DTB)
3) bl31.bin (ATF-BL31 image)


Patch status:
Have changes: Patch 7, 8, 9, 16
Other patches unchanged.

Detail changelog can find in commit message.

v3->v4:
--------
Patch 7:
-  Add secure register access helper functions for SoC 64bits
   These secure register access functions allow U-Boot proper running
   at EL2 (non-secure) to access System Manager's secure registers
   by calling the ATF's PSCI runtime services (EL3/secure).

Patch 8:
-  Call secure register access helper function to set
   SDMMC's DRVSEL and SMPLSEL.

Patch 9:
-  Call secure register access helper function to setup
   the PHY interface.

patch 16:
-  Adjust BINMAN sequence in code, sorted by alphabetical order.
   No change on functionality.


History:
--------
[v1]: https://patchwork.ozlabs.org/project/uboot/cover/20200817043431.28718-1-chee.hong.ang at intel.com/
[v2]: https://patchwork.ozlabs.org/project/uboot/cover/20201001091614.184612-1-elly.siew.chin.lim at intel.com/
[v3]: https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259-1-elly.siew.chin.lim at intel.com/


These patchsets have dependency on:
arm: socfpga: soc64: Add timeout waiting for NOC idle ACK
https://lists.denx.de/pipermail/u-boot/2020-August/423029.html

Rename Stratix10 FPGA driver and support Agilex
https://lists.denx.de/pipermail/u-boot/2020-August/422798.html

SoCFPGA mailbox driver fixes and enhancements
https://lists.denx.de/pipermail/u-boot/2020-August/423140.html

arm: socfpga: soc64: Initialize timer in SPL only
https://lists.denx.de/pipermail/u-boot/2020-July/419692.html

arm: socfpga: soc64: Remove PHY interface setup from misc arch init
https://lists.denx.de/pipermail/u-boot/2020-July/419690.html

Enable sysreset support for SoCFPGA SoC64 platforms
https://lists.denx.de/pipermail/u-boot/2020-August/422509.html

arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
https://lists.denx.de/pipermail/u-boot/2020-August/423373.html


Chee Hong Ang (14):
  arm: socfpga: Add function for checking description from FIT image
  arm: socfpga: soc64: Load FIT image with ATF support
  arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
  arm: socfpga: Disable "spin-table" method for booting Linux
  arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA
    (64bits)
  arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP
    services
  mmc: dwmmc: socfpga: Add ATF support for MMC driver
  net: designware: socfpga: Add ATF support for MAC driver
  arm: socfpga: soc64: Add ATF support for Reset Manager driver
  arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
  arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
    mbox_reset_cold()
  arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
  arm: socfpga: soc64: Skip handoff data access in SSBL
  configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
    support

Siew Chin Lim (3):
  arm: socfpga: Add secure register access helper functions for SoC
    64bits
  arm: socfpga: dts: soc64: Add binman node of FIT image with ATF
    support
  arm: socfpga: soc64: Enable FIT image generation using binman

 Makefile                                           |   7 +
 arch/arm/dts/socfpga_agilex-u-boot.dtsi            |   4 +-
 arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi         | 120 +++++
 arch/arm/dts/socfpga_stratix10-u-boot.dtsi         |   8 +
 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi   |   4 +-
 arch/arm/mach-socfpga/Kconfig                      |   4 +-
 arch/arm/mach-socfpga/Makefile                     |   5 +
 arch/arm/mach-socfpga/board.c                      |  12 +-
 .../mach-socfpga/include/mach/secure_reg_helper.h  |  19 +
 arch/arm/mach-socfpga/include/mach/smc_api.h       |  13 +
 arch/arm/mach-socfpga/lowlevel_init_soc64.S        |  76 +++
 arch/arm/mach-socfpga/mailbox_s10.c                |   5 +
 arch/arm/mach-socfpga/reset_manager_s10.c          |  13 +
 arch/arm/mach-socfpga/secure_reg_helper.c          |  73 +++
 arch/arm/mach-socfpga/smc_api.c                    |  56 ++
 arch/arm/mach-socfpga/wrap_pll_config_s10.c        |   3 +-
 configs/socfpga_agilex_atf_defconfig               |  72 +++
 configs/socfpga_stratix10_atf_defconfig            |  74 +++
 drivers/fpga/intel_sdm_mb.c                        | 139 +++++
 drivers/mmc/socfpga_dw_mmc.c                       |   8 +
 drivers/net/dwmac_socfpga.c                        |  34 +-
 include/configs/socfpga_soc64_common.h             |  24 +-
 include/linux/intel-smc.h                          | 573 +++++++++++++++++++++
 23 files changed, 1333 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_stratix10-u-boot.dtsi
 create mode 100644 arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
 create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S
 create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c
 create mode 100644 arch/arm/mach-socfpga/smc_api.c
 create mode 100644 configs/socfpga_agilex_atf_defconfig
 create mode 100644 configs/socfpga_stratix10_atf_defconfig
 create mode 100644 include/linux/intel-smc.h

-- 
2.13.0

[v4 01/17] arm: socfpga: Add function for checking description from FIT image

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 arch/arm/mach-socfpga/board.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 340abf9305..7993c27646 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -13,7 +13,7 @@
 #include <asm/arch/clock_manager.h>
 #include <asm/arch/misc.h>
 #include <asm/io.h>
-
+#include <log.h>
 #include <usb.h>
 #include <usb/dwc2_udc.h>
 
@@ -87,3 +87,13 @@ int g_dnl_board_usb_cable_connected(void)
 	return 1;
 }
 #endif
+
+#ifdef CONFIG_SPL_BUILD
+__weak int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
-- 
2.13.0

[v4 02/17] arm: socfpga: soc64: Load FIT image with ATF support

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.

For OS, u-boot now loads FIT images (kernel.itb) which
includes Linux Image and Linux's DTB.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 include/configs/socfpga_soc64_common.h | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index fb5e2e8aaf..990f879b07 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -78,12 +78,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * CONFIG_BOOTARGS goes into the environment value "bootargs".
  * Do note the value will override also the chosen node in FDT blob.
  */
+
+#ifdef CONFIG_FIT
+#define CONFIG_BOOTFILE "kernel.itb"
+#define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run linux_qspi_enable;" \
+			   "run mmcfitboot"
+#else
+#define CONFIG_BOOTFILE "Image"
 #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
 			   "run mmcboot"
+#endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"bootfile=Image\0" \
+	"bootfile=" CONFIG_BOOTFILE "\0" \
 	"fdt_addr=8000000\0" \
 	"fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
 	"mmcroot=/dev/mmcblk0p2\0" \
@@ -93,6 +101,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 	"mmcload=mmc rescan;" \
 		"load mmc 0:1 ${loadaddr} ${bootfile};" \
 		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"bootm ${loadaddr}\0" \
+	"mmcfitload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootfile}\0" \
 	"linux_qspi_enable=if sf probe; then " \
 		"echo Enabling QSPI at Linux DTB...;" \
 		"fdt addr ${fdt_addr}; fdt resize;" \
@@ -193,6 +206,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
 					- CONFIG_SYS_SPL_MALLOC_SIZE)
 
 /* SPL SDMMC boot support */
+#ifdef CONFIG_SPL_LOAD_FIT
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.itb"
+#else
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#endif
 
 #endif	/* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */
-- 
2.13.0

[v4 03/17] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

Override 'lowlevel_init' to make sure secondary CPUs trapped
in ATF instead of SPL. After ATF is initialized, it will signal
the secondary CPUs to jump from SPL to ATF waiting to be 'activated'
by Linux OS via PSCI call.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 arch/arm/mach-socfpga/Makefile                     |  2 ++
 .../arm/mach-socfpga/lowlevel_init_soc64.S         | 41 ++++++++--------------
 2 files changed, 17 insertions(+), 26 deletions(-)
 copy board/cortina/presidio-asic/lowlevel_init.S => arch/arm/mach-socfpga/lowlevel_init_soc64.S (66%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 418f543b20..c63162a5c6 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -29,6 +29,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
+obj-y	+= lowlevel_init_soc64.o
 obj-y	+= mailbox_s10.o
 obj-y	+= misc_s10.o
 obj-y	+= mmu-arm64_s10.o
@@ -41,6 +42,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 obj-y	+= clock_manager_agilex.o
+obj-y	+= lowlevel_init_soc64.o
 obj-y	+= mailbox_s10.o
 obj-y	+= misc_s10.o
 obj-y	+= mmu-arm64_s10.o
diff --git a/board/cortina/presidio-asic/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S
similarity index 66%
copy from board/cortina/presidio-asic/lowlevel_init.S
copy to arch/arm/mach-socfpga/lowlevel_init_soc64.S
index 4450a5df79..612ea8a037 100644
--- a/board/cortina/presidio-asic/lowlevel_init.S
+++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S
@@ -1,43 +1,31 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2020 Cortina-Access
+ * Copyright (C) 2020 Intel Corporation. All rights reserved
  *
+ * SPDX-License-Identifier:    GPL-2.0
  */
 
-
 #include <asm-offsets.h>
 #include <config.h>
 #include <linux/linkage.h>
 #include <asm/macro.h>
-#include <asm/armv8/mmu.h>
 
-	.globl lowlevel_init
-lowlevel_init:
+ENTRY(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
-#if defined(CONFIG_SOC_CA7774)
-	/* Enable SMPEN in CPUECTLR */
-	mrs     x0, s3_1_c15_c2_1
-	tst     x0, #0x40
-        b.ne    skip_smp_setup
-	orr     x0, x0, #0x40
-	msr     s3_1_c15_c2_1, x0
-skip_smp_setup:
-#endif
-
-#if defined(CONFIG_SOC_CA8277B)
-	/* Enable CPU Timer */
-	ldr x0, =CONFIG_SYS_TIMER_BASE
-	mov x1, #1
-	str w1, [x0]
-#endif
-
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+wait_for_atf:
+	ldr	x4, =CPU_RELEASE_ADDR
+	ldr	x5, [x4]
+	cbz	x5, slave_wait_atf
+	br	x5
+slave_wait_atf:
+	branch_if_slave x0, wait_for_atf
+#else
 	branch_if_slave x0, 1f
-#ifndef CONFIG_TARGET_VENUS
+#endif
 	ldr	x0, =GICD_BASE
 	bl	gic_init_secure
-#endif
 1:
 #if defined(CONFIG_GICV3)
 	ldr	x0, =GICR_BASE
@@ -54,7 +42,7 @@ skip_smp_setup:
 
 	/*
 	 * Slave should wait for master clearing spin table.
-	 * This sync prevent salves observing incorrect
+	 * This sync prevent slaves observing incorrect
 	 * value of spin table and jumping to wrong place.
 	 */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
@@ -85,3 +73,4 @@ lowlevel_in_el1:
 2:
 	mov	lr, x29			/* Restore LR */
 	ret
+ENDPROC(lowlevel_init)
-- 
2.13.0

[v4 04/17] arm: socfpga: Disable "spin-table" method for booting Linux

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable SMP
booting in Linux on SoC 64bits platform.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 arch/arm/mach-socfpga/Kconfig | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 26f2cf8e47..01f5a1fc41 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -33,7 +33,6 @@ config TARGET_SOCFPGA_AGILEX
 	bool
 	select ARMV8_MULTIENTRY
 	select ARMV8_SET_SMPEN
-	select ARMV8_SPIN_TABLE
 	select CLK
 	select FPGA_INTEL_SDM_MAILBOX
 	select NCORE_CACHE
@@ -79,7 +78,6 @@ config TARGET_SOCFPGA_STRATIX10
 	bool
 	select ARMV8_MULTIENTRY
 	select ARMV8_SET_SMPEN
-	select ARMV8_SPIN_TABLE
 	select FPGA_INTEL_SDM_MAILBOX
 
 choice
-- 
2.13.0

[v4 05/17] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.

smc_send_mailbox() is a send mailbox command helper function which invokes
the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD)
to send mailbox messages to Secure Device Manager (SDM).

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 arch/arm/mach-socfpga/Makefile               |  2 +
 arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +++++++
 arch/arm/mach-socfpga/smc_api.c              | 56 ++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
 create mode 100644 arch/arm/mach-socfpga/smc_api.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index c63162a5c6..0b05283a7a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -72,6 +72,8 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 obj-y	+= firewall.o
 obj-y	+= spl_agilex.o
 endif
+else
+obj-$(CONFIG_SPL_ATF) += smc_api.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/smc_api.h b/arch/arm/mach-socfpga/include/mach/smc_api.h
new file mode 100644
index 0000000000..bbefdd8dd9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/smc_api.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#ifndef _SMC_API_H_
+#define _SMC_API_H_
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+		     u32 *resp_buf);
+
+#endif /* _SMC_API_H_ */
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
new file mode 100644
index 0000000000..085daba162
--- /dev/null
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <linux/intel-smc.h>
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len)
+{
+	struct pt_regs regs;
+
+	memset(&regs, 0, sizeof(regs));
+	regs.regs[0] = func_id;
+
+	if (args)
+		memcpy(&regs.regs[1], args, arg_len * sizeof(*args));
+
+	smc_call(&regs);
+
+	if (ret_arg)
+		memcpy(ret_arg, &regs.regs[1], ret_len * sizeof(*ret_arg));
+
+	return regs.regs[0];
+}
+
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+		     u32 *resp_buf)
+{
+	int ret;
+	u64 args[6];
+	u64 resp[3];
+
+	args[0] = cmd;
+	args[1] = (u64)arg;
+	args[2] = len;
+	args[3] = urgent;
+	args[4] = (u64)resp_buf;
+	if (resp_buf_len)
+		args[5] = *resp_buf_len;
+	else
+		args[5] = 0;
+
+	ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
+			 resp, ARRAY_SIZE(resp));
+
+	if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) {
+		if (!resp[0])
+			*resp_buf_len = resp[1];
+	}
+
+	return (int)resp[0];
+}
-- 
2.13.0

[v4 06/17] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

This header file defines the Secure Monitor Call (SMC) message
protocol for ATF (BL31) PSCI runtime services. It includes all
the PSCI SiP function identifiers for the secure runtime services
provided by ATF. The secure runtime services include System Manager's
registers access, 2nd phase bitstream FPGA reconfiguration, Remote
System Update (RSU) and etc.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 include/linux/intel-smc.h | 573 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 573 insertions(+)
 create mode 100644 include/linux/intel-smc.h

diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h
new file mode 100644
index 0000000000..cacb410691
--- /dev/null
+++ b/include/linux/intel-smc.h
@@ -0,0 +1,573 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017-2018, Intel Corporation
+ */
+
+#ifndef __INTEL_SMC_H
+#define __INTEL_SMC_H
+
+#include <linux/arm-smccc.h>
+#include <linux/bitops.h>
+
+/*
+ * This file defines the Secure Monitor Call (SMC) message protocol used for
+ * service layer driver in normal world (EL1) to communicate with secure
+ * monitor software in Secure Monitor Exception Level 3 (EL3).
+ *
+ * This file is shared with secure firmware (FW) which is out of u-boot tree.
+ *
+ * An ARM SMC instruction takes a function identifier and up to 6 64-bit
+ * register values as arguments, and can return up to 4 64-bit register
+ * values. The operation of the secure monitor is determined by the parameter
+ * values passed in through registers.
+
+ * EL1 and EL3 communicates pointer as physical address rather than the
+ * virtual address.
+ */
+
+/*
+ * Functions specified by ARM SMC Calling convention:
+ *
+ * FAST call executes atomic operations, returns when the requested operation
+ * has completed.
+ * STD call starts a operation which can be preempted by a non-secure
+ * interrupt. The call can return before the requested operation has
+ * completed.
+ *
+ * a0..a7 is used as register names in the descriptions below, on arm32
+ * that translates to r0..r7 and on arm64 to w0..w7.
+ */
+
+#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
+	ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
+	ARM_SMCCC_OWNER_SIP, (func_num))
+
+#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
+	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
+	ARM_SMCCC_OWNER_SIP, (func_num))
+
+/*
+ * Return values in INTEL_SIP_SMC_* call
+ *
+ * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION:
+ * Secure monitor software doesn't recognize the request.
+ *
+ * INTEL_SIP_SMC_STATUS_OK:
+ * SMC call completed successfully,
+ * In case of FPGA configuration write operation, it means secure monitor
+ * software can accept the next chunk of FPGA configuration data.
+ *
+ * INTEL_SIP_SMC_STATUS_BUSY:
+ * In case of FPGA configuration write operation, it means secure monitor
+ * software is still processing previous data & can't accept the next chunk
+ * of data. Service driver needs to issue
+ * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the
+ * completed block(s).
+ *
+ * INTEL_SIP_SMC_STATUS_ERROR:
+ * There is error during the SMC call process.
+ *
+ * INTEL_SIP_SMC_REG_ERROR:
+ * There is error during a read or write operation of the protected
+ * registers.
+ */
+#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION		0xFFFFFFFF
+#define INTEL_SIP_SMC_STATUS_OK				0x0
+#define INTEL_SIP_SMC_STATUS_BUSY			0x1
+#define INTEL_SIP_SMC_STATUS_REJECTED			0x2
+#define INTEL_SIP_SMC_STATUS_ERROR			0x4
+#define INTEL_SIP_SMC_REG_ERROR				0x5
+#define INTEL_SIP_SMC_RSU_ERROR				0x7
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_START
+ *
+ * Sync call used by service driver at EL1 to request the FPGA in EL3 to
+ * be prepare to receive a new configuration.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_START.
+ * a1: flag for full or partial configuration
+ *    0 full reconfiguration.
+ *    1 partial reconfiguration.
+ * a2-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1
+#define INTEL_SIP_SMC_FPGA_CONFIG_START \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE
+ *
+ * Async call used by service driver at EL1 to provide FPGA configuration data
+ * to secure world.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE.
+ * a1: 64bit physical address of the configuration data memory block
+ * a2: Size of configuration data block.
+ * a3-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY,
+ * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1: 64bit physical address of 1st completed memory block if any completed
+ * block, otherwise zero value.
+ * a2: 64bit physical address of 2nd completed memory block if any completed
+ * block, otherwise zero value.
+ * a3: 64bit physical address of 3rd completed memory block if any completed
+ * block, otherwise zero value.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2
+#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \
+	INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE
+ *
+ * Sync call used by service driver at EL1 to track the completed write
+ * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE
+ * call returns INTEL_SIP_SMC_STATUS_BUSY.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
+ * INTEL_SIP_SMC_STATUS_ERROR.
+ * a1: 64bit physical address of 1st completed memory block.
+ * a2: 64bit physical address of 2nd completed memory block if
+ * any completed block, otherwise zero value.
+ * a3: 64bit physical address of 3rd completed memory block if
+ * any completed block, otherwise zero value.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3
+#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \
+INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE
+ *
+ * Sync call used by service driver at EL1 to inform secure world that all
+ * data are sent, to check whether or not the secure world had completed
+ * the FPGA configuration process.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
+ * INTEL_SIP_SMC_STATUS_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4
+#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM
+ *
+ * Sync call used by service driver at EL1 to query the physical address of
+ * memory block reserved by secure monitor software.
+ *
+ * Call register usage:
+ * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1: start of physical address of reserved memory block.
+ * a2: size of reserved memory block.
+ * a3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5
+#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK
+ *
+ * For SMC loop-back mode only, used for internal integration, debugging
+ * or troubleshooting.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6
+#define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK)
+
+/*
+ * Request INTEL_SIP_SMC_REG_READ
+ *
+ * Read a protected register using SMCCC
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_READ.
+ * a1: register address.
+ * a2-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+ * a1: Value in the register
+ * a2-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_READ 7
+#define INTEL_SIP_SMC_REG_READ \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
+
+/*
+ * Request INTEL_SIP_SMC_REG_WRITE
+ *
+ * Write a protected register using SMCCC
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_WRITE.
+ * a1: register address
+ * a2: value to program into register.
+ * a3-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
+#define INTEL_SIP_SMC_REG_WRITE \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
+
+/*
+ * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE
+ *
+ * Update one or more bits in a protected register using a
+ * read-modify-write operation.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_UPDATE.
+ * a1: register address
+ * a2: Write Mask.
+ * a3: Value to write.
+ * a4-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+ * a1-3: Not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9
+#define INTEL_SIP_SMC_REG_UPDATE \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE)
+
+/*
+* Request INTEL_SIP_SMC_RSU_STATUS
+*
+* Sync call used by service driver at EL1 to query the RSU status
+*
+* Call register usage:
+* a0 INTEL_SIP_SMC_RSU_STATUS
+* a1-7 not used
+*
+* Return status
+* a0: Current Image
+* a1: Last Failing Image
+* a2: Version [width 32 bit] | State [width 32 bit]
+* a3: Error details [width 32 bit] | Error location [width 32 bit]
+*
+* Or
+*
+* a0: INTEL_SIP_SMC_RSU_ERROR
+*/
+#define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11
+#define INTEL_SIP_SMC_RSU_STATUS \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS)
+
+/*
+* Request INTEL_SIP_SMC_RSU_UPDATE
+*
+* Sync call used by service driver at EL1 to tell you next reboot is RSU_UPDATE
+*
+* Call register usage:
+* a0 INTEL_SIP_SMC_RSU_UPDATE
+* a1 64bit physical address of the configuration data memory in flash
+* a2-7 not used
+*
+* Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+*/
+#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12
+#define INTEL_SIP_SMC_RSU_UPDATE \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE)
+
+/*
+ * Request INTEL_SIP_SMC_ECC_DBE
+ *
+ * Sync call used by service driver at EL1 alert EL3 that a Double Bit
+ * ECC error has occurred.
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_ECC_DBE
+ * a1 SysManager Double Bit Error value
+ * a2-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_ECC_DBE 13
+#define INTEL_SIP_SMC_ECC_DBE \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE)
+
+/*
+* Request INTEL_SIP_SMC_RSU_NOTIFY
+*
+* Sync call used by service driver at EL1 to report HPS software execution stage
+*
+* Call register usage:
+* a0 INTEL_SIP_SMC_RSU_NOTIFY
+* a1 32bit HPS software execution stage
+* a2-7 not used
+*
+* Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+*/
+#define INTEL_SIP_SMC_FUNCID_RSU_NOTIFY 14
+#define INTEL_SIP_SMC_RSU_NOTIFY \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_NOTIFY)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_RETRY_COUNTER
+ *
+ * Sync call used by service driver at EL1 to query the RSU retry counter
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_RETRY_COUNTER
+ * a1-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_RSU_ERROR.
+ * a1 retry counter
+*/
+#define INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER 15
+#define INTEL_SIP_SMC_RSU_RETRY_COUNTER \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_DCMF_VERSION
+ *
+ * Sync call used by service driver at EL1 to query DCMF version
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_DCMF_VERSION
+ * a1-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ * a1 dcmf1 version | dcmf0 version
+ * a2 dcmf3 version | dcmf2 version
+ *
+ * Or
+ *
+ * a0 INTEL_SIP_SMC_RSU_ERROR
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION 16
+#define INTEL_SIP_SMC_RSU_DCMF_VERSION \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION
+ *
+ * Sync call used by SSBL (EL2) to copy DCMF version to ATF memory
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION
+ * a1 dcmf1 version | dcmf0 version
+ * a2 dcmf3 version | dcmf2 version
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION 17
+#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_MAX_RETRY
+ *
+ * Sync call used by service driver at EL1 to query max_retry parameter
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_MAX_RETRY
+ * a1-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ * a1 max_retry
+ *
+ * Or
+ *
+ * a0 INTEL_SIP_SMC_RSU_ERROR
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY 18
+#define INTEL_SIP_SMC_RSU_MAX_RETRY \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_COPY_MAX_RETRY
+ *
+ * Sync call used by SSBL (EL2) to copy RSU 'max retry' to ATF memory
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_COPY_MAX_RETRY
+ * a1 max retry
+ * a2-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY 19
+#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_DCMF_STATUS
+ *
+ * Sync call used by service driver at EL1 to query DCMF status
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_DCMF_STATUS
+ * a1-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ * a1 dcmf3 status | dcmf2 status | dcmf1 status | dcmf0 status
+ *
+ * Or
+ *
+ * a0 INTEL_SIP_SMC_RSU_ERROR
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS 20
+#define INTEL_SIP_SMC_RSU_DCMF_STATUS \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS
+ *
+ * Sync call used by SSBL (EL2) to copy RSU 'dcmf status' to ATF memory
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS
+ * a1 dcmf status
+ * a2-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS 21
+#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS)
+
+/*
+ * Request INTEL_SIP_SMC_HPS_SET_BRIDGES
+ *
+ * Enable/disable the SoC FPGA bridges
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES
+ * a1 Set bridges status:
+ *      0 - Disable
+ *      1 - Enable
+ * a2-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES	50
+#define INTEL_SIP_SMC_HPS_SET_BRIDGES \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES)
+
+/*
+ * Request INTEL_SIP_SMC_MBOX_SEND_CMD
+ *
+ * Send mailbox command to SDM
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_MBOX_SEND_CMD
+ * a1 Mailbox command
+ * a2 64bit physical address pointer to command's arguments
+ * a3 Length of the argument
+ * a4 Urgent command:
+ *      0 - Disable
+ *      1 - Enable
+ * a5 64bit physical address pointer to a buffer for receiving responses
+ * a6 Length of the buffer
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR
+ * a1 Status of mailbox response
+ * a2 Received length in the buffer
+ */
+#define INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD	60
+#define INTEL_SIP_SMC_MBOX_SEND_CMD \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD)
+
+/*
+ * Request INTEL_SIP_SMC_HPS_SET_PHYINTF
+ *
+ * Select EMACx PHY interface
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_HPS_SET_PHYINTF
+ * a1 EMAC number:
+ *      0 - EMAC0
+ *      1 - EMAC1
+ *      2 - EMAC2
+ * a2 Type of PHY interface:
+ *      0 - GMII_MII
+ *      1 - RGMII
+ *      2 - RMII
+ *      3 - RESET
+ * a3-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR
+ */
+#define INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF	61
+#define INTEL_SIP_SMC_HPS_SET_PHYINTF \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF)
+
+/*
+ * Request INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
+ *
+ * Select which phase shift of the clocks (drvsel & smplsel) for SDMMC
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
+ * a1 Select which phase shift of the clock for cclk_in_drv (drvsel):
+ *      0 - 0 degree
+ *      1 - 45 degrees
+ *      2 - 90 degrees
+ *      3 - 135 degrees
+ *      4 - 180 degrees
+ *      5 - 225 degrees
+ *      6 - 270 degrees
+ *      7 - 315 degrees
+ * a2 Select which phase shift of the clock for cclk_in_sample (smplsel):
+ *      (Same as above)
+ * a3-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK	62
+#define INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK \
+	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK)
+
+#endif
-- 
2.13.0

[v4 07/17] arm: socfpga: Add secure register access helper functions for SoC 64bits

[Siew Chin Lim]

These secure register access functions allow U-Boot proper running
at EL2 (non-secure) to access System Manager's secure registers
by calling the ATF's PSCI runtime services (EL3/secure).

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 arch/arm/mach-socfpga/Makefile                     |  1 +
 .../mach-socfpga/include/mach/secure_reg_helper.h  | 19 ++++++
 arch/arm/mach-socfpga/secure_reg_helper.c          | 73 ++++++++++++++++++++++
 3 files changed, 93 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
 create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 0b05283a7a..82b681d870 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -73,6 +73,7 @@ obj-y	+= firewall.o
 obj-y	+= spl_agilex.o
 endif
 else
+obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
 obj-$(CONFIG_SPL_ATF) += smc_api.o
 endif
 
diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
new file mode 100644
index 0000000000..f959e6f802
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef	_SECURE_REG_HELPER_H_
+#define	_SECURE_REG_HELPER_H_
+
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2 4
+
+u32 socfpga_secure_reg_read32(u32 id);
+void socfpga_secure_reg_write32(u32 val, u32 id);
+void socfpga_secure_reg_update32(u32 id, u32 mask, u32 val);
+
+#endif /* _SECURE_REG_HELPER_H_ */
diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c b/arch/arm/mach-socfpga/secure_reg_helper.c
new file mode 100644
index 0000000000..286f597617
--- /dev/null
+++ b/arch/arm/mach-socfpga/secure_reg_helper.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/secure_reg_helper.h>
+#include <asm/arch/smc_api.h>
+#include <asm/arch/system_manager.h>
+#include <linux/intel-smc.h>
+
+phys_addr_t socfpga_secure_convert_reg_id_to_addr(u32 id)
+{
+	switch (id) {
+	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC:
+		return socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC;
+	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0:
+		return socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0;
+	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1:
+		return socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1;
+	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2:
+		return socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2;
+	default:
+		hang();
+	}
+}
+
+u32 socfpga_secure_reg_read32(u32 id)
+{
+	int ret;
+	u64 ret_arg;
+	u64 args[1];
+	phys_addr_t reg_addr = socfpga_secure_convert_reg_id_to_addr(id);
+
+	args[0] = (u64)reg_addr;
+	ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
+	if (ret)
+		hang();
+
+	return ret_arg;
+}
+
+void socfpga_secure_reg_write32(u32 val, u32 id)
+{
+	int ret;
+	u64 args[2];
+	phys_addr_t reg_addr = socfpga_secure_convert_reg_id_to_addr(id);
+
+	args[0] = (u64)reg_addr;
+	args[1] = val;
+	ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
+	if (ret)
+		hang();
+}
+
+void socfpga_secure_reg_update32(u32 id, u32 mask, u32 val)
+{
+	int ret;
+	u64 args[3];
+	phys_addr_t reg_addr = socfpga_secure_convert_reg_id_to_addr(id);
+
+	args[0] = (u64)reg_addr;
+	args[1] = mask;
+	args[2] = val;
+	ret = invoke_smc(INTEL_SIP_SMC_REG_UPDATE, args, 3, NULL, 0);
+	if (ret)
+		hang();
+}
-- 
2.13.0

[v4 08/17] mmc: dwmmc: socfpga: Add ATF support for MMC driver

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>

---
v2
---
Call secure register access helper function to write the secure register
---
 drivers/mmc/socfpga_dw_mmc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 0022f943bd..04f67754f5 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -6,6 +6,7 @@
 #include <common.h>
 #include <log.h>
 #include <asm/arch/clock_manager.h>
+#include <asm/arch/secure_reg_helper.h>
 #include <asm/arch/system_manager.h>
 #include <clk.h>
 #include <dm.h>
@@ -13,6 +14,7 @@
 #include <errno.h>
 #include <fdtdec.h>
 #include <dm/device_compat.h>
+#include <linux/intel-smc.h>
 #include <linux/libfdt.h>
 #include <linux/err.h>
 #include <malloc.h>
@@ -58,10 +60,16 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
 
 	debug("%s: drvsel %d smplsel %d\n", __func__,
 	      priv->drvsel, priv->smplsel);
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+	socfpga_secure_reg_write32(sdmmc_mask,
+				   SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC);
+#else
 	writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
 
 	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
 		readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+#endif
 
 	/* Enable SDMMC clock */
 	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
-- 
2.13.0

[v4 09/17] net: designware: socfpga: Add ATF support for MAC driver

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>

---
v2
---
Call secure register access helper function to write the secure register
---
 drivers/net/dwmac_socfpga.c | 34 ++++++++++++++++++++++++++++------
 1 file changed, 28 insertions(+), 6 deletions(-)

diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561dffa..8a09902c99 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -6,6 +6,8 @@
  */
 
 #include <common.h>
+#include <asm/arch/secure_reg_helper.h>
+#include <asm/arch/system_manager.h>
 #include <asm/io.h>
 #include <dm.h>
 #include <clk.h>
@@ -17,8 +19,6 @@
 #include <dm/device_compat.h>
 #include <linux/err.h>
 
-#include <asm/arch/system_manager.h>
-
 struct dwmac_socfpga_platdata {
 	struct dw_eth_pdata	dw_eth_pdata;
 	void			*phy_intf;
@@ -64,6 +64,29 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
 	return designware_eth_ofdata_to_platdata(dev);
 }
 
+static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg)
+{
+	struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
+	u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+	u32 val = (readl(pdata->phy_intf) & ~modemask) |
+		  (modereg << pdata->reg_shift);
+
+	u32 index = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() -
+		     SYSMGR_SOC64_EMAC0) >> 2;
+
+	socfpga_secure_reg_write32(val,
+				   SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 +
+				   index);
+#else
+	clrsetbits_le32(pdata->phy_intf, modemask,
+			modereg << pdata->reg_shift);
+#endif
+
+	return 0;
+}
+
 static int dwmac_socfpga_probe(struct udevice *dev)
 {
 	struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
@@ -71,7 +94,6 @@ static int dwmac_socfpga_probe(struct udevice *dev)
 	struct reset_ctl_bulk reset_bulk;
 	int ret;
 	u32 modereg;
-	u32 modemask;
 
 	switch (edata->phy_interface) {
 	case PHY_INTERFACE_MODE_MII:
@@ -97,9 +119,9 @@ static int dwmac_socfpga_probe(struct udevice *dev)
 
 	reset_assert_bulk(&reset_bulk);
 
-	modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
-	clrsetbits_le32(pdata->phy_intf, modemask,
-			modereg << pdata->reg_shift);
+	ret = dwmac_socfpga_do_setphy(dev, modereg);
+	if (ret)
+		return ret;
 
 	reset_release_bulk(&reset_bulk);
 
-- 
2.13.0

[v4 10/17] arm: socfpga: soc64: Add ATF support for Reset Manager driver

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 arch/arm/mach-socfpga/reset_manager_s10.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 3746e6a60c..af8f2c0873 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,11 +5,14 @@
  */
 
 #include <common.h>
+#include <hang.h>
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
+#include <asm/arch/smc_api.h>
 #include <asm/arch/system_manager.h>
 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
 #include <linux/iopoll.h>
+#include <linux/intel-smc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -55,6 +58,15 @@ void socfpga_per_reset_all(void)
 
 void socfpga_bridges_reset(int enable)
 {
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+	u64 arg = enable;
+
+	int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
+	if (ret) {
+		printf("SMC call failed with error %d in %s.\n", ret, __func__);
+		return;
+	}
+#else
 	u32 reg;
 
 	if (enable) {
@@ -101,6 +113,7 @@ void socfpga_bridges_reset(int enable)
 		/* Disable NOC timeout */
 		writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
 	}
+#endif
 }
 
 /*
-- 
2.13.0

[v4 11/17] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 drivers/fpga/intel_sdm_mb.c | 139 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 139 insertions(+)

diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index 9a1dc2c0c8..f5fd9a14c2 100644
--- a/drivers/fpga/intel_sdm_mb.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -8,11 +8,149 @@
 #include <log.h>
 #include <watchdog.h>
 #include <asm/arch/mailbox_s10.h>
+#include <asm/arch/smc_api.h>
 #include <linux/delay.h>
+#include <linux/intel-smc.h>
 
 #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS		60000
 #define RECONFIG_STATUS_INTERVAL_DELAY_US		1000000
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#define BITSTREAM_CHUNK_SIZE				0xFFFF0
+#define RECONFIG_STATUS_POLL_RETRY_MAX			100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+	int ret;
+	unsigned long start = get_timer(0);
+
+	while (1) {
+		ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+				 NULL, 0);
+
+		if (!ret)
+			return 0;	/* configuration success */
+
+		if (ret != INTEL_SIP_SMC_STATUS_BUSY)
+			return ret;
+
+		if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+			return -ETIMEDOUT;	/* time out */
+
+		puts(".");
+		udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+		WATCHDOG_RESET();
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int send_bitstream(const void *rbf_data, size_t rbf_size)
+{
+	int i;
+	u64 res_buf[3];
+	u64 args[2];
+	u32 xfer_count = 0;
+	int ret, wr_ret = 0, retry = 0;
+	size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+				BITSTREAM_CHUNK_SIZE : rbf_size;
+
+	while (rbf_size || xfer_count) {
+		if (!wr_ret && rbf_size) {
+			args[0] = (u64)rbf_data;
+			args[1] = buf_size;
+			wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+					    args, 2, NULL, 0);
+
+			debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+			      wr_ret, rbf_data, buf_size);
+
+			if (wr_ret)
+				continue;
+
+			rbf_size -= buf_size;
+			rbf_data += buf_size;
+
+			if (buf_size >= rbf_size)
+				buf_size = rbf_size;
+
+			xfer_count++;
+			puts(".");
+		} else {
+			ret = invoke_smc(
+				INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+				NULL, 0, res_buf, ARRAY_SIZE(res_buf));
+			if (!ret) {
+				for (i = 0; i < ARRAY_SIZE(res_buf); i++) {
+					if (!res_buf[i])
+						break;
+					xfer_count--;
+					wr_ret = 0;
+					retry = 0;
+				}
+			} else if (ret !=
+				   INTEL_SIP_SMC_STATUS_BUSY)
+				return ret;
+			else if (!xfer_count)
+				return INTEL_SIP_SMC_STATUS_ERROR;
+
+			if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+				return -ETIMEDOUT;
+
+			udelay(20000);
+		}
+		WATCHDOG_RESET();
+	}
+
+	return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+	int ret;
+	u64 arg = 1;
+
+	debug("Invoking FPGA_CONFIG_START...\n");
+
+	ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
+
+	if (ret) {
+		puts("Failure in RECONFIG mailbox command!\n");
+		return ret;
+	}
+
+	ret = send_bitstream(rbf_data, rbf_size);
+	if (ret) {
+		puts("Error sending bitstream!\n");
+		return ret;
+	}
+
+	/* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+	udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+	debug("Polling with MBOX_RECONFIG_STATUS...\n");
+	ret = reconfig_status_polling_resp();
+	if (ret) {
+		puts("FPGA reconfiguration failed!");
+		return ret;
+	}
+
+	puts("FPGA reconfiguration OK!\n");
+
+	return ret;
+}
+
+#else
+
 static const struct mbox_cfgstat_state {
 	int			err_no;
 	const char		*error_name;
@@ -286,3 +424,4 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 
 	return ret;
 }
+#endif
-- 
2.13.0

[v4 12/17] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 arch/arm/mach-socfpga/mailbox_s10.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index 18d44924e6..429444f069 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -11,6 +11,7 @@
 #include <asm/arch/mailbox_s10.h>
 #include <asm/arch/system_manager.h>
 #include <asm/secure.h>
+#include <asm/system.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -398,6 +399,9 @@ error:
 
 int mbox_reset_cold(void)
 {
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+	psci_system_reset();
+#else
 	int ret;
 
 	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
@@ -406,6 +410,7 @@ int mbox_reset_cold(void)
 		/* mailbox sent failure, wait for watchdog to kick in */
 		hang();
 	}
+#endif
 	return 0;
 }
 
-- 
2.13.0

[v4 13/17] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

Since SSBL is running in DRAM, it shall setup the stack in DRAM
instead of OCRAM which is occupied by SPL and handoff data.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 include/configs/socfpga_soc64_common.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 990f879b07..fdcd7d3e9a 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -40,9 +40,14 @@
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
 #define CONFIG_SYS_INIT_RAM_SIZE	0x40000
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR  \
 					+ CONFIG_SYS_INIT_RAM_SIZE \
 					- S10_HANDOFF_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE \
+					+ 0x100000)
+#endif
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_SP_ADDR)
 #define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
 
-- 
2.13.0

[v4 14/17] arm: socfpga: soc64: Skip handoff data access in SSBL

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index 3da85791a1..049c5711a8 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -12,6 +12,7 @@
 
 const struct cm_config * const cm_get_default_config(void)
 {
+#ifdef CONFIG_SPL_BUILD
 	struct cm_config *cm_handoff_cfg = (struct cm_config *)
 		(S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
 	u32 *conversion = (u32 *)cm_handoff_cfg;
@@ -26,7 +27,7 @@ const struct cm_config * const cm_get_default_config(void)
 	} else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
 		return cm_handoff_cfg;
 	}
-
+#endif
 	return NULL;
 }
 
-- 
2.13.0

[v4 15/17] arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support

[Siew Chin Lim]

Add binman node to device tree to generate the FIT image for u-boot
(u-boot.itb) and OS kernel (kernel.itb).

u-boot.itb contains arm trusted firmware (ATF), u-boot proper and
u-boot device tree for ATF u-boot flow.

kernel.itb contains Linux Image and Linux device tree.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 arch/arm/dts/socfpga_agilex-u-boot.dtsi          |   4 +-
 arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi       | 120 +++++++++++++++++++++++
 arch/arm/dts/socfpga_stratix10-u-boot.dtsi       |   8 ++
 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi |   4 +-
 4 files changed, 134 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_stratix10-u-boot.dtsi

diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
index f0528a9ad9..08f7cf7f7a 100644
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
@@ -2,9 +2,11 @@
 /*
  * U-Boot additions
  *
- * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
  */
 
+#include "socfpga_soc64_fit-u-boot.dtsi"
+
 /{
 	memory {
 		#address-cells = <2>;
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
new file mode 100644
index 0000000000..2d4d56a6df
--- /dev/null
+++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ */
+
+#if defined(CONFIG_FIT)
+
+/ {
+	binman: binman {
+		multiple-images;
+	};
+};
+
+&binman {
+	u-boot {
+		filename = "u-boot.itb";
+		fit {
+			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+			description = "FIT with firmware and bootloader";
+			#address-cells = <1>;
+
+			images {
+				uboot {
+					description = "U-Boot SoC64";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "arm64";
+					compression = "none";
+					load = <0x00200000>;
+
+					uboot_blob: blob {
+						filename = "u-boot-nodtb.bin";
+					};
+				};
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					os = "arm-trusted-firmware";
+					arch = "arm64";
+					compression = "none";
+					load = <0x00001000>;
+					entry = <0x00001000>;
+
+					atf_blob: blob {
+						filename = "bl31.bin";
+					};
+				};
+
+				fdt {
+					description = "U-Boot SoC64 flat device-tree";
+					type = "flat_dt";
+					compression = "none";
+
+					uboot_fdt_blob: blob {
+						filename = "u-boot.dtb";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf";
+				conf {
+					description = "Intel SoC64 FPGA";
+					firmware = "atf";
+					loadables = "uboot";
+					fdt = "fdt";
+				};
+			};
+		};
+	};
+
+	kernel {
+		filename = "kernel.itb";
+		fit {
+			description = "FIT with Linux kernel image and FDT blob";
+			#address-cells = <1>;
+
+			images {
+				kernel {
+					description = "Linux Kernel";
+					type = "kernel";
+					arch = "arm64";
+					os = "linux";
+					compression = "none";
+					load = <0x4080000>;
+					entry = <0x4080000>;
+
+					kernel_blob: blob {
+						filename = "Image";
+					};
+				};
+
+				fdt {
+					description = "Linux DTB";
+					type = "flat_dt";
+					arch = "arm64";
+					compression = "none";
+
+					kernel_fdt_blob: blob {
+						filename = "linux.dtb";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf";
+				conf {
+					description = "Intel SoC64 FPGA";
+					kernel = "kernel";
+					fdt = "fdt";
+				};
+			};
+		};
+	};
+};
+
+#endif
diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
new file mode 100644
index 0000000000..3e3a378046
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ */
+
+#include "socfpga_soc64_fit-u-boot.dtsi"
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
index 2669abb383..61df425f14 100755
--- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -2,9 +2,11 @@
 /*
  * U-Boot additions
  *
- * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
  */
 
+#include "socfpga_stratix10-u-boot.dtsi"
+
 /{
 	aliases {
 		spi0 = &qspi;
-- 
2.13.0

[v4 16/17] arm: socfpga: soc64: Enable FIT image generation using binman

[Siew Chin Lim]

Add new build target "fit-itb" for FIT image generation.

In preparation to support Vendor Authorized Boot (VAB) for Intel
SOC64 device in near future. With VAB, u-boot proper, dtb and
arm trusted firmware need to be signed before FIT image generation.

To align user experience for ATF boot with and without VAB
feature, we skip binman for ARCH_SOCFPGA in default Makefile
flow. User always use 'make fit-itb' to generate FIT image
after successfully compile u-boot.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>

---
v2
---
Adjust BINMAN sequence in code, sorted by alphabetical order.
---
 Makefile                      | 7 +++++++
 arch/arm/mach-socfpga/Kconfig | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/Makefile b/Makefile
index 41446d80cb..d3032cb9b7 100644
--- a/Makefile
+++ b/Makefile
@@ -1021,8 +1021,10 @@ inputs: $(INPUTS-y)
 
 all: .binman_stamp inputs
 ifeq ($(CONFIG_BINMAN),y)
+ifneq ($(CONFIG_ARCH_SOCFPGA),y)
 	$(call if_changed,binman)
 endif
+endif
 
 # Timestamp file to make sure that binman always runs
 .binman_stamp: FORCE
@@ -1608,6 +1610,11 @@ cmd_socnandboot = cat	u-boot-spl-padx4.sfp u-boot.img > $@ || rm -f $@
 u-boot-with-nand-spl.sfp: u-boot-spl-padx4.sfp u-boot.img FORCE
 	$(call if_changed,socnandboot)
 
+ifeq ($(CONFIG_FIT),y)
+fit-itb:
+	$(call if_changed,binman)
+endif
+
 endif
 
 ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 01f5a1fc41..4d4ff16337 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -33,6 +33,7 @@ config TARGET_SOCFPGA_AGILEX
 	bool
 	select ARMV8_MULTIENTRY
 	select ARMV8_SET_SMPEN
+	select BINMAN if SPL_ATF
 	select CLK
 	select FPGA_INTEL_SDM_MAILBOX
 	select NCORE_CACHE
@@ -78,6 +79,7 @@ config TARGET_SOCFPGA_STRATIX10
 	bool
 	select ARMV8_MULTIENTRY
 	select ARMV8_SET_SMPEN
+	select BINMAN if SPL_ATF
 	select FPGA_INTEL_SDM_MAILBOX
 
 choice
-- 
2.13.0

[v4 17/17] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support

[Siew Chin Lim]

From: Chee Hong Ang <chee.hong.ang@intel.com>

Booting Agilex and Stratix 10 with ATF support.

SPL now loads ATF (BL31), U-Boot proper and DTB from FIT
image. The new boot flow with ATF support is as follow:

SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)

U-Boot proper now starts at 0x200000 (CONFIG_SYS_TEXT_BASE).
ATF will occupy the address range starting from 0x1000.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 ...ilex_defconfig => socfpga_agilex_atf_defconfig} | 22 ++++++++++++--------
 ...0_defconfig => socfpga_stratix10_atf_defconfig} | 24 +++++++++++++---------
 2 files changed, 28 insertions(+), 18 deletions(-)
 copy configs/{socfpga_agilex_defconfig => socfpga_agilex_atf_defconfig} (80%)
 copy configs/{socfpga_stratix10_defconfig => socfpga_stratix10_atf_defconfig} (80%)

diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_atf_defconfig
similarity index 80%
copy from configs/socfpga_agilex_defconfig
copy to configs/socfpga_agilex_atf_defconfig
index 230d3c2ce5..ad87a8098f 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -1,25 +1,29 @@
 CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_TEXT_BASE=0x200000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SYS_MEMTEST_START=0x00000000
-CONFIG_SYS_MEMTEST_END=0x3fe00000
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
 CONFIG_DM_GPIO=y
-CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
 CONFIG_IDENT_STRING="socfpga_agilex"
 CONFIG_SPL_FS_FAT=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_BOOTDELAY=5
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="earlycon"
 CONFIG_SPL_CACHE=y
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
 CONFIG_CMD_MEMTEST=y
@@ -35,6 +39,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
@@ -44,6 +49,7 @@ CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
+CONFIG_MTD=y
 CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_atf_defconfig
similarity index 80%
copy from configs/socfpga_stratix10_defconfig
copy to configs/socfpga_stratix10_atf_defconfig
index 3df44bb88d..1005ba979e 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -1,26 +1,28 @@
 CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_TEXT_BASE=0x200000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SYS_MEMTEST_START=0x00000000
-CONFIG_SYS_MEMTEST_END=0x3fe00000
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000
 CONFIG_DM_GPIO=y
-CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
 CONFIG_IDENT_STRING="socfpga_stratix10"
 CONFIG_SPL_FS_FAT=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
-CONFIG_OPTIMIZE_INLINING=y
-CONFIG_SPL_OPTIMIZE_INLINING=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_BOOTDELAY=5
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="earlycon"
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
 CONFIG_CMD_MEMTEST=y
@@ -37,11 +39,13 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_FPGA_INTEL_PR=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_DW=y
-- 
2.13.0

[v4 16/17] arm: socfpga: soc64: Enable FIT image generation using binman

[Simon Glass]

Hi Siew,

On Thu, 17 Dec 2020 at 20:29, Siew Chin Lim
<elly.siew.chin.lim@intel.com> wrote:
>
> Add new build target "fit-itb" for FIT image generation.
>
> In preparation to support Vendor Authorized Boot (VAB) for Intel
> SOC64 device in near future. With VAB, u-boot proper, dtb and
> arm trusted firmware need to be signed before FIT image generation.
>
> To align user experience for ATF boot with and without VAB
> feature, we skip binman for ARCH_SOCFPGA in default Makefile
> flow. User always use 'make fit-itb' to generate FIT image
> after successfully compile u-boot.
>
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
>
> ---
> v2
> ---
> Adjust BINMAN sequence in code, sorted by alphabetical order.
> ---
>  Makefile                      | 7 +++++++
>  arch/arm/mach-socfpga/Kconfig | 2 ++
>  2 files changed, 9 insertions(+)

Can't we make binman do this?

Regards,
Simon

[v4 16/17] arm: socfpga: soc64: Enable FIT image generation using binman

[Lim, Elly Siew Chin]

Hi Simon,

We call binman to generate itb file in "make fit-itb".

We didn't put it in default binman flow is because it require Arm-trusted-firmware (bl31.bin) and Linux Image and dtb to build the itb file. These files are not part of u-boot. The user will hit compilation error if these files are not prepared before they build u-boot. Besides, we are in progressing enabling Vendor Authorized Boot (VAB) for Intel SoC FPGA, which requires u-boot prope, dtb, bl31.bin and Linux Image, dtb to be signed before generate the itb. The signing process involves another signing tool. 

We prefer not to add new dependency into default u-boot compilation process. As a result, we build itb files with "make fit-itb".

Thanks,
Siew Chin


> -----Original Message-----
> From: Simon Glass <sjg@chromium.org>
> Sent: Saturday, December 19, 2020 10:29 AM
> To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Marek Vasut
> <marex@denx.de>; Tan, Ley Foon <ley.foon.tan@intel.com>; See, Chin Liang
> <chin.liang.see@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>; Westergreen, Dalon
> <dalon.westergreen@intel.com>; Gan, Yau Wai <yau.wai.gan@intel.com>
> Subject: Re: [v4 16/17] arm: socfpga: soc64: Enable FIT image generation using
> binman
> 
> Hi Siew,
> 
> On Thu, 17 Dec 2020 at 20:29, Siew Chin Lim <elly.siew.chin.lim@intel.com>
> wrote:
> >
> > Add new build target "fit-itb" for FIT image generation.
> >
> > In preparation to support Vendor Authorized Boot (VAB) for Intel
> > SOC64 device in near future. With VAB, u-boot proper, dtb and arm
> > trusted firmware need to be signed before FIT image generation.
> >
> > To align user experience for ATF boot with and without VAB feature, we
> > skip binman for ARCH_SOCFPGA in default Makefile flow. User always use
> > 'make fit-itb' to generate FIT image after successfully compile
> > u-boot.
> >
> > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> >
> > ---
> > v2
> > ---
> > Adjust BINMAN sequence in code, sorted by alphabetical order.
> > ---
> >  Makefile                      | 7 +++++++
> >  arch/arm/mach-socfpga/Kconfig | 2 ++
> >  2 files changed, 9 insertions(+)
> 
> Can't we make binman do this?
> 
> Regards,
> Simon

[v4 16/17] arm: socfpga: soc64: Enable FIT image generation using binman

[Simon Glass]

Hi Siew,

On Sun, 20 Dec 2020 at 02:06, Lim, Elly Siew Chin
<elly.siew.chin.lim@intel.com> wrote:
>
> Hi Simon,
>
> We call binman to generate itb file in "make fit-itb".
>
> We didn't put it in default binman flow is because it require Arm-trusted-firmware (bl31.bin) and Linux Image and dtb to build the itb file. These files are not part of u-boot. The user will hit compilation error if these files are not prepared before they build u-boot. Besides, we are in progressing enabling Vendor Authorized Boot (VAB) for Intel SoC FPGA, which requires u-boot prope, dtb, bl31.bin and Linux Image, dtb to be signed before generate the itb. The signing process involves another signing tool.
>
> We prefer not to add new dependency into default u-boot compilation process. As a result, we build itb files with "make fit-itb".

The ATF stuff is not new. On various we use the 'external' flag (or
blob-ext entry type) to handle this. See atf_bl31.py for example. If
the file is not available, a warning is printing but the build
succeeds.

Binman should be able to generate all the images. The split of
responsibilities should be:

- Makefile - builds the binaries
- Other projects - build their binaries
- binman - put it all together into images

Regards,
Simon


>
> Thanks,
> Siew Chin
>
>
> > -----Original Message-----
> > From: Simon Glass <sjg@chromium.org>
> > Sent: Saturday, December 19, 2020 10:29 AM
> > To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Marek Vasut
> > <marex@denx.de>; Tan, Ley Foon <ley.foon.tan@intel.com>; See, Chin Liang
> > <chin.liang.see@intel.com>; Simon Goldschmidt
> > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> > <tien.fong.chee@intel.com>; Westergreen, Dalon
> > <dalon.westergreen@intel.com>; Gan, Yau Wai <yau.wai.gan@intel.com>
> > Subject: Re: [v4 16/17] arm: socfpga: soc64: Enable FIT image generation using
> > binman
> >
> > Hi Siew,
> >
> > On Thu, 17 Dec 2020 at 20:29, Siew Chin Lim <elly.siew.chin.lim@intel.com>
> > wrote:
> > >
> > > Add new build target "fit-itb" for FIT image generation.
> > >
> > > In preparation to support Vendor Authorized Boot (VAB) for Intel
> > > SOC64 device in near future. With VAB, u-boot proper, dtb and arm
> > > trusted firmware need to be signed before FIT image generation.
> > >
> > > To align user experience for ATF boot with and without VAB feature, we
> > > skip binman for ARCH_SOCFPGA in default Makefile flow. User always use
> > > 'make fit-itb' to generate FIT image after successfully compile
> > > u-boot.
> > >
> > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> > >
> > > ---
> > > v2
> > > ---
> > > Adjust BINMAN sequence in code, sorted by alphabetical order.
> > > ---
> > >  Makefile                      | 7 +++++++
> > >  arch/arm/mach-socfpga/Kconfig | 2 ++
> > >  2 files changed, 9 insertions(+)
> >
> > Can't we make binman do this?
> >
> > Regards,
> > Simon

[v4 16/17] arm: socfpga: soc64: Enable FIT image generation using binman

[Lim, Elly Siew Chin]

> -----Original Message-----
> From: Simon Glass <sjg@chromium.org>
> Sent: Sunday, December 20, 2020 11:58 PM
> To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Marek Vasut
> <marex@denx.de>; Tan, Ley Foon <ley.foon.tan@intel.com>; See, Chin Liang
> <chin.liang.see@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>; Westergreen, Dalon
> <dalon.westergreen@intel.com>; Gan, Yau Wai <yau.wai.gan@intel.com>
> Subject: Re: [v4 16/17] arm: socfpga: soc64: Enable FIT image generation using
> binman
> 
> Hi Siew,
> 
> On Sun, 20 Dec 2020 at 02:06, Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> wrote:
> >
> > Hi Simon,
> >
> > We call binman to generate itb file in "make fit-itb".
> >
> > We didn't put it in default binman flow is because it require Arm-trusted-
> firmware (bl31.bin) and Linux Image and dtb to build the itb file. These files are
> not part of u-boot. The user will hit compilation error if these files are not
> prepared before they build u-boot. Besides, we are in progressing enabling
> Vendor Authorized Boot (VAB) for Intel SoC FPGA, which requires u-boot prope,
> dtb, bl31.bin and Linux Image, dtb to be signed before generate the itb. The
> signing process involves another signing tool.
> >
> > We prefer not to add new dependency into default u-boot compilation
> process. As a result, we build itb files with "make fit-itb".
> 
> The ATF stuff is not new. On various we use the 'external' flag (or blob-ext entry
> type) to handle this. See atf_bl31.py for example. If the file is not available, a
> warning is printing but the build succeeds.
> 
> Binman should be able to generate all the images. The split of responsibilities
> should be:
> 
> - Makefile - builds the binaries
> - Other projects - build their binaries
> - binman - put it all together into images
> 
> Regards,
> Simon
> 

Hi Simon,

I get what you mean, Simon. I will do the following changes:

(1) I will change blob to blob-ext entry in binman dts node for all input files. 
-					uboot_blob: blob {
+					uboot_blob: blob-ext {

(2) I will revert all changes in Makefile to allow binman to run by default. And, I will remove "make fit-itb". Yes, I saw that it will report warning instead of error.

> - Makefile - builds the binaries
BINMAN  all
Image 'main-section' is missing external blobs and is non-functional: blob-ext

Some images are invalid

(3) We will directly use binman command to generate the fit image. Binman will report error if the input file doesn't exist.
> - binman - put it all together into images

bash-4.1$ ./tools/binman/binman build -u -d u-boot.dtb -O . -i u-boot
bash-4.1$ ./tools/binman/binman build -u -d u-boot.dtb -O . -i kernel
binman: [Errno 2] No such file or directory: 'Image'


Thanks,
Siew Chin

> 
> >
> > Thanks,
> > Siew Chin
> >
> >
> > > -----Original Message-----
> > > From: Simon Glass <sjg@chromium.org>
> > > Sent: Saturday, December 19, 2020 10:29 AM
> > > To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> > > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Marek Vasut
> > > <marex@denx.de>; Tan, Ley Foon <ley.foon.tan@intel.com>; See, Chin
> > > Liang <chin.liang.see@intel.com>; Simon Goldschmidt
> > > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> > > <tien.fong.chee@intel.com>; Westergreen, Dalon
> > > <dalon.westergreen@intel.com>; Gan, Yau Wai <yau.wai.gan@intel.com>
> > > Subject: Re: [v4 16/17] arm: socfpga: soc64: Enable FIT image
> > > generation using binman
> > >
> > > Hi Siew,
> > >
> > > On Thu, 17 Dec 2020 at 20:29, Siew Chin Lim
> > > <elly.siew.chin.lim@intel.com>
> > > wrote:
> > > >
> > > > Add new build target "fit-itb" for FIT image generation.
> > > >
> > > > In preparation to support Vendor Authorized Boot (VAB) for Intel
> > > > SOC64 device in near future. With VAB, u-boot proper, dtb and arm
> > > > trusted firmware need to be signed before FIT image generation.
> > > >
> > > > To align user experience for ATF boot with and without VAB
> > > > feature, we skip binman for ARCH_SOCFPGA in default Makefile flow.
> > > > User always use 'make fit-itb' to generate FIT image after
> > > > successfully compile u-boot.
> > > >
> > > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> > > >
> > > > ---
> > > > v2
> > > > ---
> > > > Adjust BINMAN sequence in code, sorted by alphabetical order.
> > > > ---
> > > >  Makefile                      | 7 +++++++
> > > >  arch/arm/mach-socfpga/Kconfig | 2 ++
> > > >  2 files changed, 9 insertions(+)
> > >
> > > Can't we make binman do this?
> > >
> > > Regards,
> > > Simon

[v4 16/17] arm: socfpga: soc64: Enable FIT image generation using binman

[Simon Glass]

Hi Siew Chin,

On Sun, 20 Dec 2020 at 19:12, Lim, Elly Siew Chin
<elly.siew.chin.lim@intel.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Simon Glass <sjg@chromium.org>
> > Sent: Sunday, December 20, 2020 11:58 PM
> > To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Marek Vasut
> > <marex@denx.de>; Tan, Ley Foon <ley.foon.tan@intel.com>; See, Chin Liang
> > <chin.liang.see@intel.com>; Simon Goldschmidt
> > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> > <tien.fong.chee@intel.com>; Westergreen, Dalon
> > <dalon.westergreen@intel.com>; Gan, Yau Wai <yau.wai.gan@intel.com>
> > Subject: Re: [v4 16/17] arm: socfpga: soc64: Enable FIT image generation using
> > binman
> >
> > Hi Siew,
> >
> > On Sun, 20 Dec 2020 at 02:06, Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> > wrote:
> > >
> > > Hi Simon,
> > >
> > > We call binman to generate itb file in "make fit-itb".
> > >
> > > We didn't put it in default binman flow is because it require Arm-trusted-
> > firmware (bl31.bin) and Linux Image and dtb to build the itb file. These files are
> > not part of u-boot. The user will hit compilation error if these files are not
> > prepared before they build u-boot. Besides, we are in progressing enabling
> > Vendor Authorized Boot (VAB) for Intel SoC FPGA, which requires u-boot prope,
> > dtb, bl31.bin and Linux Image, dtb to be signed before generate the itb. The
> > signing process involves another signing tool.
> > >
> > > We prefer not to add new dependency into default u-boot compilation
> > process. As a result, we build itb files with "make fit-itb".
> >
> > The ATF stuff is not new. On various we use the 'external' flag (or blob-ext entry
> > type) to handle this. See atf_bl31.py for example. If the file is not available, a
> > warning is printing but the build succeeds.
> >
> > Binman should be able to generate all the images. The split of responsibilities
> > should be:
> >
> > - Makefile - builds the binaries
> > - Other projects - build their binaries
> > - binman - put it all together into images
> >
> > Regards,
> > Simon
> >
>
> Hi Simon,
>
> I get what you mean, Simon. I will do the following changes:
>
> (1) I will change blob to blob-ext entry in binman dts node for all input files.
> -                                       uboot_blob: blob {
> +                                       uboot_blob: blob-ext {
>

OK, also you can create your own entry type that sets external to True
if you like.

> (2) I will revert all changes in Makefile to allow binman to run by default. And, I will remove "make fit-itb". Yes, I saw that it will report warning instead of error.
>
> > - Makefile - builds the binaries
> BINMAN  all
> Image 'main-section' is missing external blobs and is non-functional: blob-ext
>
> Some images are invalid
>

OK ta

> (3) We will directly use binman command to generate the fit image. Binman will report error if the input file doesn't exist.
> > - binman - put it all together into images
>
> bash-4.1$ ./tools/binman/binman build -u -d u-boot.dtb -O . -i u-boot
> bash-4.1$ ./tools/binman/binman build -u -d u-boot.dtb -O . -i kernel
> binman: [Errno 2] No such file or directory: 'Image'

Do you need -i or can you just get it to build everything in one go?

Try -D to get debug info. I don't know what is going on there.

Regards,
Simon

>
>
> Thanks,
> Siew Chin
>
> >
> > >
> > > Thanks,
> > > Siew Chin
> > >
> > >
> > > > -----Original Message-----
> > > > From: Simon Glass <sjg@chromium.org>
> > > > Sent: Saturday, December 19, 2020 10:29 AM
> > > > To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> > > > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Marek Vasut
> > > > <marex@denx.de>; Tan, Ley Foon <ley.foon.tan@intel.com>; See, Chin
> > > > Liang <chin.liang.see@intel.com>; Simon Goldschmidt
> > > > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> > > > <tien.fong.chee@intel.com>; Westergreen, Dalon
> > > > <dalon.westergreen@intel.com>; Gan, Yau Wai <yau.wai.gan@intel.com>
> > > > Subject: Re: [v4 16/17] arm: socfpga: soc64: Enable FIT image
> > > > generation using binman
> > > >
> > > > Hi Siew,
> > > >
> > > > On Thu, 17 Dec 2020 at 20:29, Siew Chin Lim
> > > > <elly.siew.chin.lim@intel.com>
> > > > wrote:
> > > > >
> > > > > Add new build target "fit-itb" for FIT image generation.
> > > > >
> > > > > In preparation to support Vendor Authorized Boot (VAB) for Intel
> > > > > SOC64 device in near future. With VAB, u-boot proper, dtb and arm
> > > > > trusted firmware need to be signed before FIT image generation.
> > > > >
> > > > > To align user experience for ATF boot with and without VAB
> > > > > feature, we skip binman for ARCH_SOCFPGA in default Makefile flow.
> > > > > User always use 'make fit-itb' to generate FIT image after
> > > > > successfully compile u-boot.
> > > > >
> > > > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> > > > >
> > > > > ---
> > > > > v2
> > > > > ---
> > > > > Adjust BINMAN sequence in code, sorted by alphabetical order.
> > > > > ---
> > > > >  Makefile                      | 7 +++++++
> > > > >  arch/arm/mach-socfpga/Kconfig | 2 ++
> > > > >  2 files changed, 9 insertions(+)
> > > >
> > > > Can't we make binman do this?
> > > >
> > > > Regards,
> > > > Simon

[v4 16/17] arm: socfpga: soc64: Enable FIT image generation using binman

[Lim, Elly Siew Chin]

Hi Simon,

> -----Original Message-----
> From: Simon Glass <sjg@chromium.org>
> Sent: Monday, December 21, 2020 10:17 AM
> To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Marek Vasut
> <marex@denx.de>; Tan, Ley Foon <ley.foon.tan@intel.com>; See, Chin Liang
> <chin.liang.see@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>; Westergreen, Dalon
> <dalon.westergreen@intel.com>; Gan, Yau Wai <yau.wai.gan@intel.com>
> Subject: Re: [v4 16/17] arm: socfpga: soc64: Enable FIT image generation using
> binman
> 
> Hi Siew Chin,
> 
> On Sun, 20 Dec 2020 at 19:12, Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Simon Glass <sjg@chromium.org>
> > > Sent: Sunday, December 20, 2020 11:58 PM
> > > To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> > > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Marek Vasut
> > > <marex@denx.de>; Tan, Ley Foon <ley.foon.tan@intel.com>; See, Chin
> > > Liang <chin.liang.see@intel.com>; Simon Goldschmidt
> > > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> > > <tien.fong.chee@intel.com>; Westergreen, Dalon
> > > <dalon.westergreen@intel.com>; Gan, Yau Wai <yau.wai.gan@intel.com>
> > > Subject: Re: [v4 16/17] arm: socfpga: soc64: Enable FIT image
> > > generation using binman
> > >
> > > Hi Siew,
> > >
> > > On Sun, 20 Dec 2020 at 02:06, Lim, Elly Siew Chin
> > > <elly.siew.chin.lim@intel.com>
> > > wrote:
> > > >
> > > > Hi Simon,
> > > >
> > > > We call binman to generate itb file in "make fit-itb".
> > > >
> > > > We didn't put it in default binman flow is because it require
> > > > Arm-trusted-
> > > firmware (bl31.bin) and Linux Image and dtb to build the itb file.
> > > These files are not part of u-boot. The user will hit compilation
> > > error if these files are not prepared before they build u-boot.
> > > Besides, we are in progressing enabling Vendor Authorized Boot (VAB)
> > > for Intel SoC FPGA, which requires u-boot prope, dtb, bl31.bin and
> > > Linux Image, dtb to be signed before generate the itb. The signing process
> involves another signing tool.
> > > >
> > > > We prefer not to add new dependency into default u-boot
> > > > compilation
> > > process. As a result, we build itb files with "make fit-itb".
> > >
> > > The ATF stuff is not new. On various we use the 'external' flag (or
> > > blob-ext entry
> > > type) to handle this. See atf_bl31.py for example. If the file is
> > > not available, a warning is printing but the build succeeds.
> > >
> > > Binman should be able to generate all the images. The split of
> > > responsibilities should be:
> > >
> > > - Makefile - builds the binaries
> > > - Other projects - build their binaries
> > > - binman - put it all together into images
> > >
> > > Regards,
> > > Simon
> > >
> >
> > Hi Simon,
> >
> > I get what you mean, Simon. I will do the following changes:
> >
> > (1) I will change blob to blob-ext entry in binman dts node for all input files.
> > -                                       uboot_blob: blob {
> > +                                       uboot_blob: blob-ext {
> >
> 
> OK, also you can create your own entry type that sets external to True if you like.
> 
> > (2) I will revert all changes in Makefile to allow binman to run by default. And,
> I will remove "make fit-itb". Yes, I saw that it will report warning instead of error.
> >
> > > - Makefile - builds the binaries
> > BINMAN  all
> > Image 'main-section' is missing external blobs and is non-functional:
> > blob-ext
> >
> > Some images are invalid
> >
> 
> OK ta
> 
> > (3) We will directly use binman command to generate the fit image. Binman
> will report error if the input file doesn't exist.
> > > - binman - put it all together into images
> >
> > bash-4.1$ ./tools/binman/binman build -u -d u-boot.dtb -O . -i u-boot
> > bash-4.1$ ./tools/binman/binman build -u -d u-boot.dtb -O . -i kernel
> > binman: [Errno 2] No such file or directory: 'Image'
> 
> Do you need -i or can you just get it to build everything in one go?
> 
> Try -D to get debug info. I don't know what is going on there.

User may use both. For first time, user can build everything in one go with -i. After that, if they only need to update Linux images, they can use -i to only build kernel itb.

I have tested using binman without -i, it will build all itb defined in dts.
bash-4.1$ ./tools/binman/binman build -u -d u-boot.dtb -O .
binman: [Errno 2] No such file or directory: 'Image'

> 
> Regards,
> Simon
> 
> >
> >
> > Thanks,
> > Siew Chin
> >
> > >
> > > >
> > > > Thanks,
> > > > Siew Chin
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Simon Glass <sjg@chromium.org>
> > > > > Sent: Saturday, December 19, 2020 10:29 AM
> > > > > To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> > > > > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Marek Vasut
> > > > > <marex@denx.de>; Tan, Ley Foon <ley.foon.tan@intel.com>; See,
> > > > > Chin Liang <chin.liang.see@intel.com>; Simon Goldschmidt
> > > > > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> > > > > <tien.fong.chee@intel.com>; Westergreen, Dalon
> > > > > <dalon.westergreen@intel.com>; Gan, Yau Wai
> > > > > <yau.wai.gan@intel.com>
> > > > > Subject: Re: [v4 16/17] arm: socfpga: soc64: Enable FIT image
> > > > > generation using binman
> > > > >
> > > > > Hi Siew,
> > > > >
> > > > > On Thu, 17 Dec 2020 at 20:29, Siew Chin Lim
> > > > > <elly.siew.chin.lim@intel.com>
> > > > > wrote:
> > > > > >
> > > > > > Add new build target "fit-itb" for FIT image generation.
> > > > > >
> > > > > > In preparation to support Vendor Authorized Boot (VAB) for
> > > > > > Intel
> > > > > > SOC64 device in near future. With VAB, u-boot proper, dtb and
> > > > > > arm trusted firmware need to be signed before FIT image generation.
> > > > > >
> > > > > > To align user experience for ATF boot with and without VAB
> > > > > > feature, we skip binman for ARCH_SOCFPGA in default Makefile flow.
> > > > > > User always use 'make fit-itb' to generate FIT image after
> > > > > > successfully compile u-boot.
> > > > > >
> > > > > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> > > > > >
> > > > > > ---
> > > > > > v2
> > > > > > ---
> > > > > > Adjust BINMAN sequence in code, sorted by alphabetical order.
> > > > > > ---
> > > > > >  Makefile                      | 7 +++++++
> > > > > >  arch/arm/mach-socfpga/Kconfig | 2 ++
> > > > > >  2 files changed, 9 insertions(+)
> > > > >
> > > > > Can't we make binman do this?
> > > > >
> > > > > Regards,
> > > > > Simon

[v4 16/17] arm: socfpga: soc64: Enable FIT image generation using binman

[Simon Glass]

Hi Siew Chin,

On Sun, 20 Dec 2020 at 19:28, Lim, Elly Siew Chin
<elly.siew.chin.lim@intel.com> wrote:
>
> Hi Simon,
>
> > -----Original Message-----
> > From: Simon Glass <sjg@chromium.org>
> > Sent: Monday, December 21, 2020 10:17 AM
> > To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Marek Vasut
> > <marex@denx.de>; Tan, Ley Foon <ley.foon.tan@intel.com>; See, Chin Liang
> > <chin.liang.see@intel.com>; Simon Goldschmidt
> > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> > <tien.fong.chee@intel.com>; Westergreen, Dalon
> > <dalon.westergreen@intel.com>; Gan, Yau Wai <yau.wai.gan@intel.com>
> > Subject: Re: [v4 16/17] arm: socfpga: soc64: Enable FIT image generation using
> > binman
> >
> > Hi Siew Chin,
> >
> > On Sun, 20 Dec 2020 at 19:12, Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> > wrote:
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Simon Glass <sjg@chromium.org>
> > > > Sent: Sunday, December 20, 2020 11:58 PM
> > > > To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> > > > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Marek Vasut
> > > > <marex@denx.de>; Tan, Ley Foon <ley.foon.tan@intel.com>; See, Chin
> > > > Liang <chin.liang.see@intel.com>; Simon Goldschmidt
> > > > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> > > > <tien.fong.chee@intel.com>; Westergreen, Dalon
> > > > <dalon.westergreen@intel.com>; Gan, Yau Wai <yau.wai.gan@intel.com>
> > > > Subject: Re: [v4 16/17] arm: socfpga: soc64: Enable FIT image
> > > > generation using binman
> > > >
> > > > Hi Siew,
> > > >
> > > > On Sun, 20 Dec 2020 at 02:06, Lim, Elly Siew Chin
> > > > <elly.siew.chin.lim@intel.com>
> > > > wrote:
> > > > >
> > > > > Hi Simon,
> > > > >
> > > > > We call binman to generate itb file in "make fit-itb".
> > > > >
> > > > > We didn't put it in default binman flow is because it require
> > > > > Arm-trusted-
> > > > firmware (bl31.bin) and Linux Image and dtb to build the itb file.
> > > > These files are not part of u-boot. The user will hit compilation
> > > > error if these files are not prepared before they build u-boot.
> > > > Besides, we are in progressing enabling Vendor Authorized Boot (VAB)
> > > > for Intel SoC FPGA, which requires u-boot prope, dtb, bl31.bin and
> > > > Linux Image, dtb to be signed before generate the itb. The signing process
> > involves another signing tool.
> > > > >
> > > > > We prefer not to add new dependency into default u-boot
> > > > > compilation
> > > > process. As a result, we build itb files with "make fit-itb".
> > > >
> > > > The ATF stuff is not new. On various we use the 'external' flag (or
> > > > blob-ext entry
> > > > type) to handle this. See atf_bl31.py for example. If the file is
> > > > not available, a warning is printing but the build succeeds.
> > > >
> > > > Binman should be able to generate all the images. The split of
> > > > responsibilities should be:
> > > >
> > > > - Makefile - builds the binaries
> > > > - Other projects - build their binaries
> > > > - binman - put it all together into images
> > > >
> > > > Regards,
> > > > Simon
> > > >
> > >
> > > Hi Simon,
> > >
> > > I get what you mean, Simon. I will do the following changes:
> > >
> > > (1) I will change blob to blob-ext entry in binman dts node for all input files.
> > > -                                       uboot_blob: blob {
> > > +                                       uboot_blob: blob-ext {
> > >
> >
> > OK, also you can create your own entry type that sets external to True if you like.
> >
> > > (2) I will revert all changes in Makefile to allow binman to run by default. And,
> > I will remove "make fit-itb". Yes, I saw that it will report warning instead of error.
> > >
> > > > - Makefile - builds the binaries
> > > BINMAN  all
> > > Image 'main-section' is missing external blobs and is non-functional:
> > > blob-ext
> > >
> > > Some images are invalid
> > >
> >
> > OK ta
> >
> > > (3) We will directly use binman command to generate the fit image. Binman
> > will report error if the input file doesn't exist.
> > > > - binman - put it all together into images
> > >
> > > bash-4.1$ ./tools/binman/binman build -u -d u-boot.dtb -O . -i u-boot
> > > bash-4.1$ ./tools/binman/binman build -u -d u-boot.dtb -O . -i kernel
> > > binman: [Errno 2] No such file or directory: 'Image'
> >
> > Do you need -i or can you just get it to build everything in one go?
> >
> > Try -D to get debug info. I don't know what is going on there.
>
> User may use both. For first time, user can build everything in one go with -i. After that, if they only need to update Linux images, they can use -i to only build kernel itb.
>
> I have tested using binman without -i, it will build all itb defined in dts.
> bash-4.1$ ./tools/binman/binman build -u -d u-boot.dtb -O .
> binman: [Errno 2] No such file or directory: 'Image'

OK I'm not sure what is going on here. But binman should be fairly
quick, so perhaps just rebuild everything? We don't currently bother
to select which images to build.

Perhaps we should add that feature to the build system. But it is
complicated, because the Makefile does not (in general) know what
files are being generated by binman.

Regards,
Simon
> > > > > > -----Original Message-----
> > > > > > From: Simon Glass <sjg@chromium.org>
> > > > > > Sent: Saturday, December 19, 2020 10:29 AM
> > > > > > To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> > > > > > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Marek Vasut
> > > > > > <marex@denx.de>; Tan, Ley Foon <ley.foon.tan@intel.com>; See,
> > > > > > Chin Liang <chin.liang.see@intel.com>; Simon Goldschmidt
> > > > > > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> > > > > > <tien.fong.chee@intel.com>; Westergreen, Dalon
> > > > > > <dalon.westergreen@intel.com>; Gan, Yau Wai
> > > > > > <yau.wai.gan@intel.com>
> > > > > > Subject: Re: [v4 16/17] arm: socfpga: soc64: Enable FIT image
> > > > > > generation using binman
> > > > > >
> > > > > > Hi Siew,
> > > > > >
> > > > > > On Thu, 17 Dec 2020 at 20:29, Siew Chin Lim
> > > > > > <elly.siew.chin.lim@intel.com>
> > > > > > wrote:
> > > > > > >
> > > > > > > Add new build target "fit-itb" for FIT image generation.
> > > > > > >
> > > > > > > In preparation to support Vendor Authorized Boot (VAB) for
> > > > > > > Intel
> > > > > > > SOC64 device in near future. With VAB, u-boot proper, dtb and
> > > > > > > arm trusted firmware need to be signed before FIT image generation.
> > > > > > >
> > > > > > > To align user experience for ATF boot with and without VAB
> > > > > > > feature, we skip binman for ARCH_SOCFPGA in default Makefile flow.
> > > > > > > User always use 'make fit-itb' to generate FIT image after
> > > > > > > successfully compile u-boot.
> > > > > > >
> > > > > > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> > > > > > >
> > > > > > > ---
> > > > > > > v2
> > > > > > > ---
> > > > > > > Adjust BINMAN sequence in code, sorted by alphabetical order.
> > > > > > > ---
> > > > > > >  Makefile                      | 7 +++++++
> > > > > > >  arch/arm/mach-socfpga/Kconfig | 2 ++
> > > > > > >  2 files changed, 9 insertions(+)
> > > > > >
> > > > > > Can't we make binman do this?
> > > > > >
> > > > > > Regards,
> > > > > > Simon

[v4 07/17] arm: socfpga: Add secure register access helper functions for SoC 64bits

[Tan, Ley Foon]

> -----Original Message-----
> From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Sent: Friday, December 18, 2020 11:29 AM
> To: u-boot at lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon
> <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>;
> Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>; Westergreen, Dalon
> <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan,
> Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: [v4 07/17] arm: socfpga: Add secure register access helper functions
> for SoC 64bits
> 
> These secure register access functions allow U-Boot proper running at EL2
> (non-secure) to access System Manager's secure registers by calling the ATF's
> PSCI runtime services (EL3/secure).
> 
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile                     |  1 +
>  .../mach-socfpga/include/mach/secure_reg_helper.h  | 19 ++++++
>  arch/arm/mach-socfpga/secure_reg_helper.c          | 73
> ++++++++++++++++++++++
>  3 files changed, 93 insertions(+)
>  create mode 100644 arch/arm/mach-
> socfpga/include/mach/secure_reg_helper.h
>  create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> socfpga/Makefile index 0b05283a7a..82b681d870 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -73,6 +73,7 @@ obj-y	+= firewall.o
>  obj-y	+= spl_agilex.o
>  endif
>  else
> +obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
>  obj-$(CONFIG_SPL_ATF) += smc_api.o
>  endif
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
> b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
> new file mode 100644
> index 0000000000..f959e6f802
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2020 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#ifndef	_SECURE_REG_HELPER_H_
> +#define	_SECURE_REG_HELPER_H_
> +
> +#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1 #define
> +SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2 #define
> +SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3 #define
> +SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2 4
> +
> +u32 socfpga_secure_reg_read32(u32 id);
> +void socfpga_secure_reg_write32(u32 val, u32 id); void
> +socfpga_secure_reg_update32(u32 id, u32 mask, u32 val);
> +
> +#endif /* _SECURE_REG_HELPER_H_ */
> diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c b/arch/arm/mach-
> socfpga/secure_reg_helper.c
> new file mode 100644
> index 0000000000..286f597617
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/secure_reg_helper.c
> @@ -0,0 +1,73 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#include <common.h>
> +#include <hang.h>
> +#include <asm/io.h>
> +#include <asm/system.h>
> +#include <asm/arch/misc.h>
> +#include <asm/arch/secure_reg_helper.h> #include <asm/arch/smc_api.h>
> +#include <asm/arch/system_manager.h> #include <linux/intel-smc.h>
> +
> +phys_addr_t socfpga_secure_convert_reg_id_to_addr(u32 id) {
> +	switch (id) {
> +	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC:
> +		return socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_SDMMC;
> +	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0:
> +		return socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_EMAC0;
> +	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1:
> +		return socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_EMAC1;
> +	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2:
> +		return socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_EMAC2;
> +	default:
> +		hang();
Don't hang the system when error. Same for functions below.


> +	}
> +}
> +
> +u32 socfpga_secure_reg_read32(u32 id)
> +{
> +	int ret;
> +	u64 ret_arg;
> +	u64 args[1];
> +	phys_addr_t reg_addr = socfpga_secure_convert_reg_id_to_addr(id);
> +
> +	args[0] = (u64)reg_addr;
> +	ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
> +	if (ret)
> +		hang();
> +
> +	return ret_arg;
> +}
> +
> +void socfpga_secure_reg_write32(u32 val, u32 id) {
> +	int ret;
> +	u64 args[2];
> +	phys_addr_t reg_addr = socfpga_secure_convert_reg_id_to_addr(id);
> +
> +	args[0] = (u64)reg_addr;
> +	args[1] = val;
> +	ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
> +	if (ret)
> +		hang();
> +}
> +
> +void socfpga_secure_reg_update32(u32 id, u32 mask, u32 val) {
> +	int ret;
> +	u64 args[3];
> +	phys_addr_t reg_addr = socfpga_secure_convert_reg_id_to_addr(id);
> +
> +	args[0] = (u64)reg_addr;
> +	args[1] = mask;
> +	args[2] = val;
> +	ret = invoke_smc(INTEL_SIP_SMC_REG_UPDATE, args, 3, NULL, 0);
> +	if (ret)
> +		hang();
> +}
> --
> 2.13.0

Regards
Ley Foon