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From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
To: u-boot@lists.denx.de
Subject: [v5 07/18] arm: socfpga: Add secure register access helper functions for SoC 64bits
Date: Tue, 22 Dec 2020 00:49:31 +0800	[thread overview]
Message-ID: <20201221164942.11640-8-elly.siew.chin.lim@intel.com> (raw)
In-Reply-To: <20201221164942.11640-1-elly.siew.chin.lim@intel.com>

These secure register access functions allow U-Boot proper running
at EL2 (non-secure) to access System Manager's secure registers
by calling the ATF's PSCI runtime services (EL3/secure).

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>

---
v5
---
Return error code instead of hang the system if fail to access
the secure register.
---
 arch/arm/mach-socfpga/Makefile                     |  1 +
 .../mach-socfpga/include/mach/secure_reg_helper.h  | 19 +++++
 arch/arm/mach-socfpga/secure_reg_helper.c          | 97 ++++++++++++++++++++++
 3 files changed, 117 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
 create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 0b05283a7a..82b681d870 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -73,6 +73,7 @@ obj-y	+= firewall.o
 obj-y	+= spl_agilex.o
 endif
 else
+obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
 obj-$(CONFIG_SPL_ATF) += smc_api.o
 endif
 
diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
new file mode 100644
index 0000000000..d5a11122c7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef	_SECURE_REG_HELPER_H_
+#define	_SECURE_REG_HELPER_H_
+
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2 4
+
+int socfpga_secure_reg_read32(u32 id, u32 *val);
+int socfpga_secure_reg_write32(u32 id, u32 val);
+int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val);
+
+#endif /* _SECURE_REG_HELPER_H_ */
diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c b/arch/arm/mach-socfpga/secure_reg_helper.c
new file mode 100644
index 0000000000..d9be45cc97
--- /dev/null
+++ b/arch/arm/mach-socfpga/secure_reg_helper.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/secure_reg_helper.h>
+#include <asm/arch/smc_api.h>
+#include <asm/arch/system_manager.h>
+#include <linux/errno.h>
+#include <linux/intel-smc.h>
+
+int socfpga_secure_convert_reg_id_to_addr(u32 id, phys_addr_t *reg_addr)
+{
+	switch (id) {
+	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC:
+		*reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC;
+		break;
+	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0:
+		*reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0;
+		break;
+	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1:
+		*reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1;
+		break;
+	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2:
+		*reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2;
+		break;
+	default:
+		return -EADDRNOTAVAIL;
+	}
+	return 0;
+}
+
+int socfpga_secure_reg_read32(u32 id, u32 *val)
+{
+	int ret;
+	u64 ret_arg;
+	u64 args[1];
+
+	phys_addr_t reg_addr;
+	ret = socfpga_secure_convert_reg_id_to_addr(id, &reg_addr);
+	if (ret)
+		return ret;
+
+	args[0] = (u64)reg_addr;
+	ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
+	if (ret)
+		return ret;
+
+	*val = (u32)ret_arg;
+
+	return 0;
+}
+
+int socfpga_secure_reg_write32(u32 id, u32 val)
+{
+	int ret;
+	u64 args[2];
+
+	phys_addr_t reg_addr;
+	ret = socfpga_secure_convert_reg_id_to_addr(id, &reg_addr);
+	if (ret)
+		return ret;
+
+	args[0] = (u64)reg_addr;
+	args[1] = val;
+	ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val)
+{
+	int ret;
+	u64 args[3];
+
+	phys_addr_t reg_addr;
+	ret = socfpga_secure_convert_reg_id_to_addr(id, &reg_addr);
+	if (ret)
+		return ret;
+
+	args[0] = (u64)reg_addr;
+	args[1] = mask;
+	args[2] = val;
+	ret = invoke_smc(INTEL_SIP_SMC_REG_UPDATE, args, 3, NULL, 0);
+	if (ret)
+		return ret;
+
+	return 0;
+}
-- 
2.13.0

  parent reply	other threads:[~2020-12-21 16:49 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-21 16:49 [v5 00/18] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
2020-12-21 16:49 ` [v5 01/18] arm: socfpga: Add function for checking description from FIT image Siew Chin Lim
2020-12-21 16:49 ` [v5 02/18] arm: socfpga: soc64: Load FIT image with ATF support Siew Chin Lim
2020-12-21 16:49 ` [v5 03/18] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF Siew Chin Lim
2020-12-21 16:49 ` [v5 04/18] arm: socfpga: Disable "spin-table" method for booting Linux Siew Chin Lim
2020-12-21 16:49 ` [v5 05/18] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) Siew Chin Lim
2020-12-21 16:49 ` [v5 06/18] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services Siew Chin Lim
2020-12-21 16:49 ` Siew Chin Lim [this message]
2020-12-23  3:28   ` [v5 07/18] arm: socfpga: Add secure register access helper functions for SoC 64bits Tan, Ley Foon
2020-12-21 16:49 ` [v5 08/18] mmc: dwmmc: Change designware MMC 'clksel' callback function to return status Siew Chin Lim
2020-12-22 23:49   ` Jaehoon Chung
2020-12-23  3:31   ` Tan, Ley Foon
2020-12-21 16:49 ` [v5 09/18] mmc: dwmmc: socfpga: Add ATF support for MMC driver Siew Chin Lim
2020-12-22 23:50   ` Jaehoon Chung
2020-12-23  3:33   ` Tan, Ley Foon
2020-12-21 16:49 ` [v5 10/18] net: designware: socfpga: Add ATF support for MAC driver Siew Chin Lim
2020-12-23  3:42   ` Tan, Ley Foon
2020-12-21 16:49 ` [v5 11/18] arm: socfpga: soc64: Add ATF support for Reset Manager driver Siew Chin Lim
2020-12-21 16:49 ` [v5 12/18] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver Siew Chin Lim
2020-12-21 16:49 ` [v5 13/18] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() Siew Chin Lim
2020-12-21 16:49 ` [v5 14/18] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM Siew Chin Lim
2020-12-21 16:49 ` [v5 15/18] arm: socfpga: soc64: Skip handoff data access in SSBL Siew Chin Lim
2020-12-21 16:49 ` [v5 16/18] arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support Siew Chin Lim
2020-12-23  3:45   ` Tan, Ley Foon
2020-12-29  3:31   ` Simon Glass
2020-12-21 16:49 ` [v5 17/18] arm: socfpga: soc64: Enable FIT image generation using binman Siew Chin Lim
2020-12-23  3:48   ` Tan, Ley Foon
2020-12-29  3:31   ` Simon Glass
2020-12-21 16:49 ` [v5 18/18] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support Siew Chin Lim

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