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From: Jaehoon Chung <jh80.chung@samsung.com>
To: u-boot@lists.denx.de
Subject: [v5 08/18] mmc: dwmmc: Change designware MMC 'clksel' callback function to return status
Date: Wed, 23 Dec 2020 08:49:43 +0900	[thread overview]
Message-ID: <163928b0-58b5-4408-98e9-c2041b8c29df@samsung.com> (raw)
In-Reply-To: <20201221164942.11640-9-elly.siew.chin.lim@intel.com>

On 12/22/20 1:49 AM, Siew Chin Lim wrote:
> Change 'clksel' callback function to allow the code to return a
> status.
> 
> This patch is a preparation for enabling Arm-Trusted-Firmware (ATF)
> in Intel SoC FPGA. This patch does not change functionality.
> 
> When using Arm-Trusted-Firmware (ATF) in Intel SoC FPGA, the MMC clock
> related register is secure register which is required to be written
> via SMC/PCSI call. It is possible that U-Boot fail to write the
> register if there is unexpected error between U-Boot and ATF.
> As a result, there maybe signal integrity on MMC connection due to
> clock. So, the code should reports error to user when 'clksel' fail.
> 
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>

Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>

Best Regards,
Jaehoon Chung

> ---
>  drivers/mmc/ca_dw_mmc.c      | 4 +++-
>  drivers/mmc/dw_mmc.c         | 9 +++++++--
>  drivers/mmc/exynos_dw_mmc.c  | 4 +++-
>  drivers/mmc/nexell_dw_mmc.c  | 4 +++-
>  drivers/mmc/socfpga_dw_mmc.c | 4 +++-
>  include/dwmmc.h              | 2 +-
>  6 files changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c
> index 198c41f451..d0cf1b7248 100644
> --- a/drivers/mmc/ca_dw_mmc.c
> +++ b/drivers/mmc/ca_dw_mmc.c
> @@ -40,7 +40,7 @@ struct ca_dwmmc_priv_data {
>  	u8 ds;
>  };
>  
> -static void ca_dwmci_clksel(struct dwmci_host *host)
> +static int ca_dwmci_clksel(struct dwmci_host *host)
>  {
>  	struct ca_dwmmc_priv_data *priv = host->priv;
>  	u32 val = readl(priv->sd_dll_reg);
> @@ -52,6 +52,8 @@ static void ca_dwmci_clksel(struct dwmci_host *host)
>  		val |= SD_CLK_SEL_100MHZ;
>  
>  	writel(val, priv->sd_dll_reg);
> +
> +	return 0;
>  }
>  
>  static void ca_dwmci_board_init(struct dwmci_host *host)
> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
> index 7702f4be3f..7c8a312fa7 100644
> --- a/drivers/mmc/dw_mmc.c
> +++ b/drivers/mmc/dw_mmc.c
> @@ -496,8 +496,13 @@ static int dwmci_set_ios(struct mmc *mmc)
>  
>  	dwmci_writel(host, DWMCI_UHS_REG, regs);
>  
> -	if (host->clksel)
> -		host->clksel(host);
> +	if (host->clksel) {
> +		int ret;
> +
> +		ret = host->clksel(host);
> +		if (ret)
> +			return ret;
> +	}
>  
>  #if CONFIG_IS_ENABLED(DM_REGULATOR)
>  	if (mmc->vqmmc_supply) {
> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
> index 435ccac594..7a25dac841 100644
> --- a/drivers/mmc/exynos_dw_mmc.c
> +++ b/drivers/mmc/exynos_dw_mmc.c
> @@ -44,7 +44,7 @@ struct dwmci_exynos_priv_data {
>   * Function used as callback function to initialise the
>   * CLKSEL register for every mmc channel.
>   */
> -static void exynos_dwmci_clksel(struct dwmci_host *host)
> +static int exynos_dwmci_clksel(struct dwmci_host *host)
>  {
>  #ifdef CONFIG_DM_MMC
>  	struct dwmci_exynos_priv_data *priv =
> @@ -53,6 +53,8 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
>  	struct dwmci_exynos_priv_data *priv = host->priv;
>  #endif
>  	dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
> +
> +	return 0;
>  }
>  
>  unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
> diff --git a/drivers/mmc/nexell_dw_mmc.c b/drivers/mmc/nexell_dw_mmc.c
> index 0462759444..fe00189fe1 100644
> --- a/drivers/mmc/nexell_dw_mmc.c
> +++ b/drivers/mmc/nexell_dw_mmc.c
> @@ -51,7 +51,7 @@ struct nexell_dwmmc_priv {
>  
>  struct clk *clk_get(const char *id);
>  
> -static void nx_dw_mmc_clksel(struct dwmci_host *host)
> +static int nx_dw_mmc_clksel(struct dwmci_host *host)
>  {
>  	/* host->priv is pointer to "struct udevice" */
>  	struct nexell_dwmmc_priv *priv = dev_get_priv(host->priv);
> @@ -65,6 +65,8 @@ static void nx_dw_mmc_clksel(struct dwmci_host *host)
>  		      DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(3);
>  
>  	dwmci_writel(host, DWMCI_CLKSEL, val);
> +
> +	return 0;
>  }
>  
>  static void nx_dw_mmc_reset(int ch)
> diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
> index 0022f943bd..0a2845bcc2 100644
> --- a/drivers/mmc/socfpga_dw_mmc.c
> +++ b/drivers/mmc/socfpga_dw_mmc.c
> @@ -46,7 +46,7 @@ static void socfpga_dwmci_reset(struct udevice *dev)
>  	reset_deassert_bulk(&reset_bulk);
>  }
>  
> -static void socfpga_dwmci_clksel(struct dwmci_host *host)
> +static int socfpga_dwmci_clksel(struct dwmci_host *host)
>  {
>  	struct dwmci_socfpga_priv_data *priv = host->priv;
>  	u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
> @@ -66,6 +66,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
>  	/* Enable SDMMC clock */
>  	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
>  		     CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
> +
> +	return 0;
>  }
>  
>  static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
> diff --git a/include/dwmmc.h b/include/dwmmc.h
> index d8a8355a0a..f8aeda7697 100644
> --- a/include/dwmmc.h
> +++ b/include/dwmmc.h
> @@ -174,7 +174,7 @@ struct dwmci_host {
>  	struct mmc *mmc;
>  	void *priv;
>  
> -	void (*clksel)(struct dwmci_host *host);
> +	int (*clksel)(struct dwmci_host *host);
>  	void (*board_init)(struct dwmci_host *host);
>  
>  	/**
> 

  reply	other threads:[~2020-12-22 23:49 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-21 16:49 [v5 00/18] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
2020-12-21 16:49 ` [v5 01/18] arm: socfpga: Add function for checking description from FIT image Siew Chin Lim
2020-12-21 16:49 ` [v5 02/18] arm: socfpga: soc64: Load FIT image with ATF support Siew Chin Lim
2020-12-21 16:49 ` [v5 03/18] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF Siew Chin Lim
2020-12-21 16:49 ` [v5 04/18] arm: socfpga: Disable "spin-table" method for booting Linux Siew Chin Lim
2020-12-21 16:49 ` [v5 05/18] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) Siew Chin Lim
2020-12-21 16:49 ` [v5 06/18] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services Siew Chin Lim
2020-12-21 16:49 ` [v5 07/18] arm: socfpga: Add secure register access helper functions for SoC 64bits Siew Chin Lim
2020-12-23  3:28   ` Tan, Ley Foon
2020-12-21 16:49 ` [v5 08/18] mmc: dwmmc: Change designware MMC 'clksel' callback function to return status Siew Chin Lim
2020-12-22 23:49   ` Jaehoon Chung [this message]
2020-12-23  3:31   ` Tan, Ley Foon
2020-12-21 16:49 ` [v5 09/18] mmc: dwmmc: socfpga: Add ATF support for MMC driver Siew Chin Lim
2020-12-22 23:50   ` Jaehoon Chung
2020-12-23  3:33   ` Tan, Ley Foon
2020-12-21 16:49 ` [v5 10/18] net: designware: socfpga: Add ATF support for MAC driver Siew Chin Lim
2020-12-23  3:42   ` Tan, Ley Foon
2020-12-21 16:49 ` [v5 11/18] arm: socfpga: soc64: Add ATF support for Reset Manager driver Siew Chin Lim
2020-12-21 16:49 ` [v5 12/18] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver Siew Chin Lim
2020-12-21 16:49 ` [v5 13/18] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() Siew Chin Lim
2020-12-21 16:49 ` [v5 14/18] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM Siew Chin Lim
2020-12-21 16:49 ` [v5 15/18] arm: socfpga: soc64: Skip handoff data access in SSBL Siew Chin Lim
2020-12-21 16:49 ` [v5 16/18] arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support Siew Chin Lim
2020-12-23  3:45   ` Tan, Ley Foon
2020-12-29  3:31   ` Simon Glass
2020-12-21 16:49 ` [v5 17/18] arm: socfpga: soc64: Enable FIT image generation using binman Siew Chin Lim
2020-12-23  3:48   ` Tan, Ley Foon
2020-12-29  3:31   ` Simon Glass
2020-12-21 16:49 ` [v5 18/18] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support Siew Chin Lim

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