* [PATCH 00/22] tcg: backend constraints cleanup
@ 2020-12-23 6:01 Richard Henderson
2020-12-23 6:01 ` [PATCH 01/22] tcg/tci: Drop L and S constraints Richard Henderson
` (22 more replies)
0 siblings, 23 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
This pulls out constraints to a couple of headers, which
reduces the boilerplate just a little.
I have a longer term goal, which this aids, in which I
move some of the startup-time debug-only validation into
build/compile-time validation. But not yet.
r~
Richard Henderson (22):
tcg/tci: Drop L and S constraints
tcg/i386: Move constraint type check to tcg_target_const_match
tcg: Split out target constraints to tcg-target-constr.h
tcg/arm: Convert to tcg-target-constr.h
tcg/aarch64: Convert to tcg-target-constr.h
tcg/ppc: Convert to tcg-target-constr.h
tcg/tci: Convert to tcg-target-constr.h
tcg/mips: Convert to tcg-target-constr.h
tcg/riscv: Convert to tcg-target-constr.h
tcg/s390: Convert to tcg-target-constr.h
tcg/sparc: Convert to tcg-target-constr.h
tcg: Remove TCG_TARGET_CONSTR_H
tcg: Split out constraint sets to tcg-target-conset.h
tcg/aarch64: Convert to tcg-target-conset.h
tcg/arm: Convert to tcg-target-conset.h
tcg/mips: Convert to tcg-target-conset.h
tcg/ppc: Convert to tcg-target-conset.h
tcg/riscv: Convert to tcg-target-conset.h
tcg/s390: Convert to tcg-target-conset.h
tcg/sparc: Convert to tcg-target-conset.h
tcg/tci: Convert to tcg-target-conset.h
tcg: Remove TCG_TARGET_CONSET_H
tcg/aarch64/tcg-target-conset.h | 31 +++
tcg/aarch64/tcg-target-constr.h | 27 +++
tcg/arm/tcg-target-conset.h | 30 +++
tcg/arm/tcg-target-constr.h | 31 +++
tcg/i386/tcg-target-conset.h | 44 ++++
tcg/i386/tcg-target-constr.h | 26 +++
tcg/mips/tcg-target-conset.h | 31 +++
tcg/mips/tcg-target-constr.h | 31 +++
tcg/ppc/tcg-target-conset.h | 37 ++++
tcg/ppc/tcg-target-constr.h | 37 ++++
tcg/riscv/tcg-target-conset.h | 25 +++
tcg/riscv/tcg-target-constr.h | 24 +++
tcg/s390/tcg-target-conset.h | 24 +++
tcg/s390/tcg-target-constr.h | 15 ++
tcg/sparc/tcg-target-conset.h | 27 +++
tcg/sparc/tcg-target-constr.h | 16 ++
tcg/tci/tcg-target-conset.h | 20 ++
tcg/tci/tcg-target-constr.h | 9 +
tcg/tcg.c | 140 ++++++++++++-
tcg/aarch64/tcg-target.c.inc | 132 +++---------
tcg/arm/tcg-target.c.inc | 154 +++-----------
tcg/i386/tcg-target.c.inc | 281 ++++++++-----------------
tcg/mips/tcg-target.c.inc | 152 +++-----------
tcg/ppc/tcg-target.c.inc | 194 +++++------------
tcg/riscv/tcg-target.c.inc | 122 ++---------
tcg/s390/tcg-target.c.inc | 161 +++++---------
tcg/sparc/tcg-target.c.inc | 114 ++--------
tcg/tci/tcg-target.c.inc | 359 +++++++++++---------------------
28 files changed, 1064 insertions(+), 1230 deletions(-)
create mode 100644 tcg/aarch64/tcg-target-conset.h
create mode 100644 tcg/aarch64/tcg-target-constr.h
create mode 100644 tcg/arm/tcg-target-conset.h
create mode 100644 tcg/arm/tcg-target-constr.h
create mode 100644 tcg/i386/tcg-target-conset.h
create mode 100644 tcg/i386/tcg-target-constr.h
create mode 100644 tcg/mips/tcg-target-conset.h
create mode 100644 tcg/mips/tcg-target-constr.h
create mode 100644 tcg/ppc/tcg-target-conset.h
create mode 100644 tcg/ppc/tcg-target-constr.h
create mode 100644 tcg/riscv/tcg-target-conset.h
create mode 100644 tcg/riscv/tcg-target-constr.h
create mode 100644 tcg/s390/tcg-target-conset.h
create mode 100644 tcg/s390/tcg-target-constr.h
create mode 100644 tcg/sparc/tcg-target-conset.h
create mode 100644 tcg/sparc/tcg-target-constr.h
create mode 100644 tcg/tci/tcg-target-conset.h
create mode 100644 tcg/tci/tcg-target-constr.h
--
2.25.1
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 01/22] tcg/tci: Drop L and S constraints
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2020-12-23 6:01 ` [PATCH 02/22] tcg/i386: Move constraint type check to tcg_target_const_match Richard Henderson
` (21 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
These are identical to the 'r' constraint.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 231b9b1775..50a08bef03 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -46,11 +46,11 @@
# define R64 "r"
#endif
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-# define L "L", "L"
-# define S "S", "S"
+# define L "r", "r"
+# define S "r", "r"
#else
-# define L "L"
-# define S "S"
+# define L "r"
+# define S "r"
#endif
/* TODO: documentation. */
@@ -390,8 +390,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch (*ct_str++) {
case 'r':
- case 'L': /* qemu_ld constraint */
- case 'S': /* qemu_st constraint */
ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
break;
default:
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 02/22] tcg/i386: Move constraint type check to tcg_target_const_match
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
2020-12-23 6:01 ` [PATCH 01/22] tcg/tci: Drop L and S constraints Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2020-12-23 6:01 ` [PATCH 03/22] tcg: Split out target constraints to tcg-target-constr.h Richard Henderson
` (20 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
Rather than check the type when filling in the constraint,
check it when matching the constant. This removes the only
use of the type argument to target_parse_constraint.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 28 +++++++++++++++++-----------
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index d8797ed398..b73873f715 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -254,13 +254,13 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
break;
case 'e':
- ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32);
+ ct->ct |= TCG_CT_CONST_S32;
break;
case 'Z':
- ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_U32);
+ ct->ct |= TCG_CT_CONST_U32;
break;
case 'I':
- ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_I32);
+ ct->ct |= TCG_CT_CONST_I32;
break;
default:
@@ -277,14 +277,20 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
if (ct & TCG_CT_CONST) {
return 1;
}
- if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
- return 1;
- }
- if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
- return 1;
- }
- if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
- return 1;
+ if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
+ if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_I32)) {
+ return 1;
+ }
+ } else {
+ if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
+ return 1;
+ }
}
if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
return 1;
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 03/22] tcg: Split out target constraints to tcg-target-constr.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
2020-12-23 6:01 ` [PATCH 01/22] tcg/tci: Drop L and S constraints Richard Henderson
2020-12-23 6:01 ` [PATCH 02/22] tcg/i386: Move constraint type check to tcg_target_const_match Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2021-01-12 11:57 ` Peter Maydell
2020-12-23 6:01 ` [PATCH 04/22] tcg/arm: Convert " Richard Henderson
` (19 subsequent siblings)
22 siblings, 1 reply; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
This eliminates the target-specific function target_parse_constraint
and folds it into the single caller, process_op_defs. Since this is
done directly into the switch statement, duplicates are compilation
errors rather than silently ignored at runtime.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target-constr.h | 26 ++++++++++++++
tcg/i386/tcg-target.h | 1 +
tcg/tcg.c | 33 ++++++++++++++---
tcg/i386/tcg-target.c.inc | 70 ++----------------------------------
4 files changed, 58 insertions(+), 72 deletions(-)
create mode 100644 tcg/i386/tcg-target-constr.h
diff --git a/tcg/i386/tcg-target-constr.h b/tcg/i386/tcg-target-constr.h
new file mode 100644
index 0000000000..e4a4886b6c
--- /dev/null
+++ b/tcg/i386/tcg-target-constr.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * i386 target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+REGS('a', 1u << TCG_REG_EAX)
+REGS('b', 1u << TCG_REG_EBX)
+REGS('c', 1u << TCG_REG_ECX)
+REGS('d', 1u << TCG_REG_EDX)
+REGS('S', 1u << TCG_REG_ESI)
+REGS('D', 1u << TCG_REG_EDI)
+
+REGS('r', ALL_GENERAL_REGS)
+REGS('x', ALL_VECTOR_REGS)
+/* A register that can be used as a byte operand. */
+REGS('q', ALL_BYTEL_REGS)
+/* A register with an addressable second byte (e.g. %ah). */
+REGS('Q', ALL_BYTEH_REGS)
+/* qemu_ld/st address constraint */
+REGS('L', ALL_GENERAL_REGS & ~((1 << TCG_REG_L0) | (1 << TCG_REG_L1)))
+
+CONST('e', TCG_CT_CONST_S32)
+CONST('I', TCG_CT_CONST_I32)
+CONST('W', TCG_CT_CONST_WSZ)
+CONST('Z', TCG_CT_CONST_U32)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index abd4ac7fc0..7c405e166d 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -235,5 +235,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 43c6cf8f52..f5b53d739e 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -102,8 +102,10 @@ static void tcg_register_jit_int(void *buf, size_t size,
__attribute__((unused));
/* Forward declarations for functions declared and used in tcg-target.c.inc. */
+#ifndef TCG_TARGET_CONSTR_H
static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type);
+#endif
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
intptr_t arg2);
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
@@ -2239,7 +2241,6 @@ static void process_op_defs(TCGContext *s)
for (op = 0; op < NB_OPS; op++) {
TCGOpDef *def = &tcg_op_defs[op];
const TCGTargetOpDef *tdefs;
- TCGType type;
int i, nb_args;
if (def->flags & TCG_OPF_NOT_PRESENT) {
@@ -2255,7 +2256,6 @@ static void process_op_defs(TCGContext *s)
/* Missing TCGTargetOpDef entry. */
tcg_debug_assert(tdefs != NULL);
- type = (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32);
for (i = 0; i < nb_args; i++) {
const char *ct_str = tdefs->args_ct_str[i];
/* Incomplete TCGTargetOpDef entry. */
@@ -2287,11 +2287,34 @@ static void process_op_defs(TCGContext *s)
def->args_ct[i].ct |= TCG_CT_CONST;
ct_str++;
break;
+
+#ifdef TCG_TARGET_CONSTR_H
+ /* Include all of the target-specific constraints. */
+
+#undef CONST
+#define CONST(CASE, MASK) \
+ case CASE: def->args_ct[i].ct |= MASK; ct_str++; break;
+#define REGS(CASE, MASK) \
+ case CASE: def->args_ct[i].regs |= MASK; ct_str++; break;
+
+#include "tcg-target-constr.h"
+
+#undef REGS
+#undef CONST
default:
- ct_str = target_parse_constraint(&def->args_ct[i],
- ct_str, type);
/* Typo in TCGTargetOpDef constraint. */
- tcg_debug_assert(ct_str != NULL);
+ g_assert_not_reached();
+#else
+ default:
+ {
+ TCGType type = (def->flags & TCG_OPF_64BIT
+ ? TCG_TYPE_I64 : TCG_TYPE_I32);
+ ct_str = target_parse_constraint(&def->args_ct[i],
+ ct_str, type);
+ /* Typo in TCGTargetOpDef constraint. */
+ tcg_debug_assert(ct_str != NULL);
+ }
+#endif
}
}
}
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index b73873f715..981dd9aca4 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -194,81 +194,17 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
return true;
}
+#define ALL_BYTEH_REGS 0x0000000fu
#if TCG_TARGET_REG_BITS == 64
#define ALL_GENERAL_REGS 0x0000ffffu
#define ALL_VECTOR_REGS 0xffff0000u
+#define ALL_BYTEL_REGS ALL_GENERAL_REGS
#else
#define ALL_GENERAL_REGS 0x000000ffu
#define ALL_VECTOR_REGS 0x00ff0000u
+#define ALL_BYTEL_REGS ALL_BYTEH_REGS
#endif
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch(*ct_str++) {
- case 'a':
- tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
- break;
- case 'b':
- tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
- break;
- case 'c':
- tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
- break;
- case 'd':
- tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
- break;
- case 'S':
- tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
- break;
- case 'D':
- tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
- break;
- case 'q':
- /* A register that can be used as a byte operand. */
- ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
- break;
- case 'Q':
- /* A register with an addressable second byte (e.g. %ah). */
- ct->regs = 0xf;
- break;
- case 'r':
- /* A general register. */
- ct->regs |= ALL_GENERAL_REGS;
- break;
- case 'W':
- /* With TZCNT/LZCNT, we can have operand-size as an input. */
- ct->ct |= TCG_CT_CONST_WSZ;
- break;
- case 'x':
- /* A vector register. */
- ct->regs |= ALL_VECTOR_REGS;
- break;
-
- /* qemu_ld/st address constraint */
- case 'L':
- ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
- tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
- tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
- break;
-
- case 'e':
- ct->ct |= TCG_CT_CONST_S32;
- break;
- case 'Z':
- ct->ct |= TCG_CT_CONST_U32;
- break;
- case 'I':
- ct->ct |= TCG_CT_CONST_I32;
- break;
-
- default:
- return NULL;
- }
- return ct_str;
-}
-
/* test if a constant matches the constraint */
static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 04/22] tcg/arm: Convert to tcg-target-constr.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (2 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 03/22] tcg: Split out target constraints to tcg-target-constr.h Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2020-12-23 6:01 ` [PATCH 05/22] tcg/aarch64: " Richard Henderson
` (18 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target-constr.h | 31 +++++++++++++++++++
tcg/arm/tcg-target.h | 1 +
tcg/arm/tcg-target.c.inc | 60 -------------------------------------
3 files changed, 32 insertions(+), 60 deletions(-)
create mode 100644 tcg/arm/tcg-target-constr.h
diff --git a/tcg/arm/tcg-target-constr.h b/tcg/arm/tcg-target-constr.h
new file mode 100644
index 0000000000..15c5e53406
--- /dev/null
+++ b/tcg/arm/tcg-target-constr.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Arm target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+#define ALL_GENERAL_REGS 0xffffu
+
+#ifdef CONFIG_SOFTMMU
+#define ALL_QLOAD_REGS \
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
+ (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \
+ (1 << TCG_REG_R14)))
+#define ALL_QSTORE_REGS \
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
+ (1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \
+ ((TARGET_LONG_BITS == 64) << TCG_REG_R3)))
+#else
+#define ALL_QLOAD_REGS ALL_GENERAL_REGS
+#define ALL_QSTORE_REGS \
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1)))
+#endif
+
+REGS('r', ALL_GENERAL_REGS)
+REGS('l', ALL_QLOAD_REGS)
+REGS('s', ALL_QSTORE_REGS)
+
+CONST('I', TCG_CT_CONST_ARM)
+CONST('K', TCG_CT_CONST_INV)
+CONST('N', TCG_CT_CONST_NEG)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 17e771374d..6f058d6d9b 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -146,5 +146,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 62c37a954b..ab1b295293 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -234,66 +234,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
#define TCG_CT_CONST_NEG 0x400
#define TCG_CT_CONST_ZERO 0x800
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'I':
- ct->ct |= TCG_CT_CONST_ARM;
- break;
- case 'K':
- ct->ct |= TCG_CT_CONST_INV;
- break;
- case 'N': /* The gcc constraint letter is L, already used here. */
- ct->ct |= TCG_CT_CONST_NEG;
- break;
- case 'Z':
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
-
- case 'r':
- ct->regs = 0xffff;
- break;
-
- /* qemu_ld address */
- case 'l':
- ct->regs = 0xffff;
-#ifdef CONFIG_SOFTMMU
- /* r0-r2,lr will be overwritten when reading the tlb entry,
- so don't use these. */
- tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
- tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
- tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
- tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
-#endif
- break;
-
- /* qemu_st address & data */
- case 's':
- ct->regs = 0xffff;
- /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
- and r0-r1 doing the byte swapping, so don't use these. */
- tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
- tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
-#if defined(CONFIG_SOFTMMU)
- /* Avoid clashes with registers being used for helper args */
- tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
-#if TARGET_LONG_BITS == 64
- /* Avoid clashes with registers being used for helper args */
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-#endif
- tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
-#endif
- break;
-
- default:
- return NULL;
- }
- return ct_str;
-}
-
static inline uint32_t rotl(uint32_t val, int n)
{
return (val << n) | (val >> (32 - n));
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 05/22] tcg/aarch64: Convert to tcg-target-constr.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (3 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 04/22] tcg/arm: Convert " Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2020-12-23 6:01 ` [PATCH 06/22] tcg/ppc: " Richard Henderson
` (17 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target-constr.h | 27 +++++++++++++++++++
tcg/aarch64/tcg-target.h | 1 +
tcg/aarch64/tcg-target.c.inc | 46 ---------------------------------
3 files changed, 28 insertions(+), 46 deletions(-)
create mode 100644 tcg/aarch64/tcg-target-constr.h
diff --git a/tcg/aarch64/tcg-target-constr.h b/tcg/aarch64/tcg-target-constr.h
new file mode 100644
index 0000000000..28f7aa6f03
--- /dev/null
+++ b/tcg/aarch64/tcg-target-constr.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * AArch64 target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+#define ALL_GENERAL_REGS 0xffffffffu
+#define ALL_VECTOR_REGS 0xffffffff00000000ull
+
+#ifdef CONFIG_SOFTMMU
+#define ALL_QLDST_REGS \
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_X0) | (1 << TCG_REG_X1) | \
+ (1 << TCG_REG_X2) | (1 << TCG_REG_X3)))
+#else
+#define ALL_QLDST_REGS ALL_GENERAL_REGS
+#endif
+
+REGS('r', ALL_GENERAL_REGS)
+REGS('l', ALL_QLDST_REGS)
+REGS('w', ALL_VECTOR_REGS)
+
+CONST('A', TCG_CT_CONST_AIMM)
+CONST('L', TCG_CT_CONST_LIMM)
+CONST('M', TCG_CT_CONST_MONE)
+CONST('O', TCG_CT_CONST_ORRI)
+CONST('N', TCG_CT_CONST_ANDI)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 663dd0b95e..ca7af5a589 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -159,5 +159,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CONSTR_H
#endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 26f71cb599..310bc972e3 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -122,52 +122,6 @@ static inline bool patch_reloc(tcg_insn_unit *code_ptr, int type,
#define TCG_CT_CONST_ORRI 0x1000
#define TCG_CT_CONST_ANDI 0x2000
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'r': /* general registers */
- ct->regs |= 0xffffffffu;
- break;
- case 'w': /* advsimd registers */
- ct->regs |= 0xffffffff00000000ull;
- break;
- case 'l': /* qemu_ld / qemu_st address, data_reg */
- ct->regs = 0xffffffffu;
-#ifdef CONFIG_SOFTMMU
- /* x0 and x1 will be overwritten when reading the tlb entry,
- and x2, and x3 for helper args, better to avoid using them. */
- tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
- tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
- tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
- tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
-#endif
- break;
- case 'A': /* Valid for arithmetic immediate (positive or negative). */
- ct->ct |= TCG_CT_CONST_AIMM;
- break;
- case 'L': /* Valid for logical immediate. */
- ct->ct |= TCG_CT_CONST_LIMM;
- break;
- case 'M': /* minus one */
- ct->ct |= TCG_CT_CONST_MONE;
- break;
- case 'O': /* vector orr/bic immediate */
- ct->ct |= TCG_CT_CONST_ORRI;
- break;
- case 'N': /* vector orr/bic immediate, inverted */
- ct->ct |= TCG_CT_CONST_ANDI;
- break;
- case 'Z': /* zero */
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
/* Match a constant valid for addition (12-bit, optionally shifted). */
static inline bool is_aimm(uint64_t val)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 06/22] tcg/ppc: Convert to tcg-target-constr.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (4 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 05/22] tcg/aarch64: " Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2020-12-23 6:01 ` [PATCH 07/22] tcg/tci: " Richard Henderson
` (16 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target-constr.h | 37 +++++++++++++++++++++++
tcg/ppc/tcg-target.h | 1 +
tcg/ppc/tcg-target.c.inc | 58 -------------------------------------
3 files changed, 38 insertions(+), 58 deletions(-)
create mode 100644 tcg/ppc/tcg-target-constr.h
diff --git a/tcg/ppc/tcg-target-constr.h b/tcg/ppc/tcg-target-constr.h
new file mode 100644
index 0000000000..b4937f37f7
--- /dev/null
+++ b/tcg/ppc/tcg-target-constr.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * PowerPC target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+#define ALL_GENERAL_REGS 0xffffffffu
+#define ALL_VECTOR_REGS 0xffffffff00000000ull
+
+#ifdef CONFIG_SOFTMMU
+#define ALL_QLOAD_REGS \
+ (ALL_GENERAL_REGS & \
+ ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5)))
+#define ALL_QSTORE_REGS \
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \
+ (1 << TCG_REG_R5) | (1 << TCG_REG_R6)))
+#else
+#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3))
+#define ALL_QSTORE_REGS ALL_QLOAD_REGS
+#endif
+
+REGS('r', ALL_GENERAL_REGS)
+REGS('v', ALL_VECTOR_REGS)
+REGS('A', 1u << TCG_REG_R3)
+REGS('B', 1u << TCG_REG_R4)
+REGS('C', 1u << TCG_REG_R5)
+REGS('D', 1u << TCG_REG_R6)
+REGS('L', ALL_QLOAD_REGS)
+REGS('S', ALL_QSTORE_REGS)
+
+CONST('I', TCG_CT_CONST_S16)
+CONST('J', TCG_CT_CONST_U16)
+CONST('M', TCG_CT_CONST_MONE)
+CONST('T', TCG_CT_CONST_S32)
+CONST('U', TCG_CT_CONST_U32)
+CONST('W', TCG_CT_CONST_WSZ)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index be10363956..78d3470f3c 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -185,5 +185,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 18ee989f95..c97f95f3cf 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -218,64 +218,6 @@ static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
return false;
}
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'A': case 'B': case 'C': case 'D':
- tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
- break;
- case 'r':
- ct->regs = 0xffffffff;
- break;
- case 'v':
- ct->regs = 0xffffffff00000000ull;
- break;
- case 'L': /* qemu_ld constraint */
- ct->regs = 0xffffffff;
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-#ifdef CONFIG_SOFTMMU
- tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
- tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
-#endif
- break;
- case 'S': /* qemu_st constraint */
- ct->regs = 0xffffffff;
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-#ifdef CONFIG_SOFTMMU
- tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
- tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
- tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
-#endif
- break;
- case 'I':
- ct->ct |= TCG_CT_CONST_S16;
- break;
- case 'J':
- ct->ct |= TCG_CT_CONST_U16;
- break;
- case 'M':
- ct->ct |= TCG_CT_CONST_MONE;
- break;
- case 'T':
- ct->ct |= TCG_CT_CONST_S32;
- break;
- case 'U':
- ct->ct |= TCG_CT_CONST_U32;
- break;
- case 'W':
- ct->ct |= TCG_CT_CONST_WSZ;
- break;
- case 'Z':
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
/* test if a constant matches the constraint */
static int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 07/22] tcg/tci: Convert to tcg-target-constr.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (5 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 06/22] tcg/ppc: " Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2020-12-23 6:01 ` [PATCH 08/22] tcg/mips: " Richard Henderson
` (15 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target-constr.h | 9 +++++++++
tcg/tci/tcg-target.h | 2 ++
tcg/tci/tcg-target.c.inc | 14 --------------
3 files changed, 11 insertions(+), 14 deletions(-)
create mode 100644 tcg/tci/tcg-target-constr.h
diff --git a/tcg/tci/tcg-target-constr.h b/tcg/tci/tcg-target-constr.h
new file mode 100644
index 0000000000..ddf57ca9d0
--- /dev/null
+++ b/tcg/tci/tcg-target-constr.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * TCI target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
+REGS('L', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
+REGS('S', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 8c1c1d265d..cd3dee51bb 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -210,4 +210,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
/* no need to flush icache explicitly */
}
+#define TCG_TARGET_CONSTR_H
+
#endif /* TCG_TARGET_H */
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 50a08bef03..9ac6da2e21 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -384,20 +384,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
return true;
}
-/* Parse target specific constraints. */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'r':
- ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
/* Show current bytecode. Used by tcg interpreter. */
void tci_disas(uint8_t opc)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 08/22] tcg/mips: Convert to tcg-target-constr.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (6 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 07/22] tcg/tci: " Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2020-12-23 6:01 ` [PATCH 09/22] tcg/riscv: " Richard Henderson
` (14 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target-constr.h | 31 ++++++++++++++++++++
tcg/mips/tcg-target.h | 1 +
tcg/mips/tcg-target.c.inc | 56 ------------------------------------
3 files changed, 32 insertions(+), 56 deletions(-)
create mode 100644 tcg/mips/tcg-target-constr.h
diff --git a/tcg/mips/tcg-target-constr.h b/tcg/mips/tcg-target-constr.h
new file mode 100644
index 0000000000..22f6df0806
--- /dev/null
+++ b/tcg/mips/tcg-target-constr.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * MIPS target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+#define ALL_GENERAL_REGS 0xffffffffu
+#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0))
+
+#ifdef CONFIG_SOFTMMU
+#define ALL_QLOAD_REGS \
+ (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2))
+#define ALL_QSTORE_REGS \
+ (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \
+ ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \
+ : (1 << TCG_REG_A1)))
+#else
+#define ALL_QLOAD_REGS NOA0_REGS
+#define ALL_QSTORE_REGS NOA0_REGS
+#endif
+
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_QLOAD_REGS)
+REGS('S', ALL_QSTORE_REGS)
+
+CONST('I', TCG_CT_CONST_U16)
+CONST('J', TCG_CT_CONST_S16)
+CONST('K', TCG_CT_CONST_P2M1)
+CONST('N', TCG_CT_CONST_N16)
+CONST('W', TCG_CT_CONST_WSZ)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index c6b091d849..f4a79bcad1 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -217,5 +217,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#ifdef CONFIG_SOFTMMU
#define TCG_TARGET_NEED_LDST_LABELS
#endif
+#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 41be574e89..d0b674582a 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -189,62 +189,6 @@ static inline bool is_p2m1(tcg_target_long val)
return val && ((val + 1) & val) == 0;
}
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch(*ct_str++) {
- case 'r':
- ct->regs = 0xffffffff;
- break;
- case 'L': /* qemu_ld input arg constraint */
- ct->regs = 0xffffffff;
- tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
-#if defined(CONFIG_SOFTMMU)
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
- }
-#endif
- break;
- case 'S': /* qemu_st constraint */
- ct->regs = 0xffffffff;
- tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
-#if defined(CONFIG_SOFTMMU)
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
- tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
- } else {
- tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
- }
-#endif
- break;
- case 'I':
- ct->ct |= TCG_CT_CONST_U16;
- break;
- case 'J':
- ct->ct |= TCG_CT_CONST_S16;
- break;
- case 'K':
- ct->ct |= TCG_CT_CONST_P2M1;
- break;
- case 'N':
- ct->ct |= TCG_CT_CONST_N16;
- break;
- case 'W':
- ct->ct |= TCG_CT_CONST_WSZ;
- break;
- case 'Z':
- /* We are cheating a bit here, using the fact that the register
- ZERO is also the register number 0. Hence there is no need
- to check for const_args in each instruction. */
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
/* test if a constant matches the constraint */
static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 09/22] tcg/riscv: Convert to tcg-target-constr.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (7 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 08/22] tcg/mips: " Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2021-01-07 17:26 ` Alistair Francis
2020-12-23 6:01 ` [PATCH 10/22] tcg/s390: " Richard Henderson
` (13 subsequent siblings)
22 siblings, 1 reply; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target-constr.h | 24 +++++++++++++++++++++
tcg/riscv/tcg-target.h | 1 +
tcg/riscv/tcg-target.c.inc | 39 -----------------------------------
3 files changed, 25 insertions(+), 39 deletions(-)
create mode 100644 tcg/riscv/tcg-target-constr.h
diff --git a/tcg/riscv/tcg-target-constr.h b/tcg/riscv/tcg-target-constr.h
new file mode 100644
index 0000000000..5daf2e6a5b
--- /dev/null
+++ b/tcg/riscv/tcg-target-constr.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * RISC-V target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+#define ALL_GENERAL_REGS 0xffffffffu
+
+#ifdef CONFIG_SOFTMMU
+#define ALL_QLDST_REGS \
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_A0) | (1 << TCG_REG_A1) | \
+ (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | \
+ (1 << TCG_REG_A5)))
+#else
+#define ALL_QLDST_REGS ALL_GENERAL_REGS
+#endif
+
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_QLDST_REGS)
+
+CONST('I', TCG_CT_CONST_S12)
+CONST('N', TCG_CT_CONST_N12)
+CONST('M', TCG_CT_CONST_M12)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 032439d806..ff8ff43a46 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -175,5 +175,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_POOL_LABELS
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
+#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index d536f3ccc1..33047c1951 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -131,45 +131,6 @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
}
}
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'r':
- ct->regs = 0xffffffff;
- break;
- case 'L':
- /* qemu_ld/qemu_st constraint */
- ct->regs = 0xffffffff;
- /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
-#if defined(CONFIG_SOFTMMU)
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
-#endif
- break;
- case 'I':
- ct->ct |= TCG_CT_CONST_S12;
- break;
- case 'N':
- ct->ct |= TCG_CT_CONST_N12;
- break;
- case 'M':
- ct->ct |= TCG_CT_CONST_M12;
- break;
- case 'Z':
- /* we can use a zero immediate as a zero register argument. */
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
/* test if a constant matches the constraint */
static int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 10/22] tcg/s390: Convert to tcg-target-constr.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (8 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 09/22] tcg/riscv: " Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2020-12-23 6:01 ` [PATCH 11/22] tcg/sparc: " Richard Henderson
` (12 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390/tcg-target-constr.h | 15 ++++++++++++++
tcg/s390/tcg-target.h | 1 +
tcg/s390/tcg-target.c.inc | 40 ------------------------------------
3 files changed, 16 insertions(+), 40 deletions(-)
create mode 100644 tcg/s390/tcg-target-constr.h
diff --git a/tcg/s390/tcg-target-constr.h b/tcg/s390/tcg-target-constr.h
new file mode 100644
index 0000000000..885e91e19b
--- /dev/null
+++ b/tcg/s390/tcg-target-constr.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * S390 target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+REGS('r', 0xffff)
+REGS('L', 0xffff & ~((1 << TCG_REG_R2) | (1 << TCG_REG_R3) | (1 << TCG_REG_R4)))
+REGS('a', 1u << TCG_REG_R2)
+REGS('b', 1u << TCG_REG_R3)
+
+CONST('A', TCG_CT_CONST_S33)
+CONST('I', TCG_CT_CONST_S16)
+CONST('J', TCG_CT_CONST_S32)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 63c8797bd3..3aff3cc572 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -162,5 +162,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index c5e096449b..d00d78f0b9 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -402,46 +402,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
return false;
}
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'r': /* all registers */
- ct->regs = 0xffff;
- break;
- case 'L': /* qemu_ld/st constraint */
- ct->regs = 0xffff;
- tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
- tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
- break;
- case 'a': /* force R2 for division */
- ct->regs = 0;
- tcg_regset_set_reg(ct->regs, TCG_REG_R2);
- break;
- case 'b': /* force R3 for division */
- ct->regs = 0;
- tcg_regset_set_reg(ct->regs, TCG_REG_R3);
- break;
- case 'A':
- ct->ct |= TCG_CT_CONST_S33;
- break;
- case 'I':
- ct->ct |= TCG_CT_CONST_S16;
- break;
- case 'J':
- ct->ct |= TCG_CT_CONST_S32;
- break;
- case 'Z':
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
/* Test if a constant matches the constraint. */
static int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 11/22] tcg/sparc: Convert to tcg-target-constr.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (9 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 10/22] tcg/s390: " Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2020-12-23 6:01 ` [PATCH 12/22] tcg: Remove TCG_TARGET_CONSTR_H Richard Henderson
` (11 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/sparc/tcg-target-constr.h | 16 ++++++++++++++
tcg/sparc/tcg-target.h | 1 +
tcg/sparc/tcg-target.c.inc | 39 -----------------------------------
3 files changed, 17 insertions(+), 39 deletions(-)
create mode 100644 tcg/sparc/tcg-target-constr.h
diff --git a/tcg/sparc/tcg-target-constr.h b/tcg/sparc/tcg-target-constr.h
new file mode 100644
index 0000000000..379eb83ca4
--- /dev/null
+++ b/tcg/sparc/tcg-target-constr.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Sparc target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+#define RESERVE_QLDST (7u << TCG_REG_O0) /* O0, O1, O2 */
+
+REGS('r', 0xffffffff)
+REGS('R', ALL_64)
+REGS('s', 0xffffffff & ~RESERVE_QLDST)
+REGS('S', ALL_64 & ~RESERVE_QLDST)
+
+CONST('I', TCG_CT_CONST_S11)
+CONST('J', TCG_CT_CONST_S13)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 633841ebf2..bfee6191b3 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -179,5 +179,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index 6775bd30fc..c92742aaec 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -319,45 +319,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
return true;
}
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'r':
- ct->regs = 0xffffffff;
- break;
- case 'R':
- ct->regs = ALL_64;
- break;
- case 'A': /* qemu_ld/st address constraint */
- ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
- reserve_helpers:
- tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
- tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
- tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
- break;
- case 's': /* qemu_st data 32-bit constraint */
- ct->regs = 0xffffffff;
- goto reserve_helpers;
- case 'S': /* qemu_st data 64-bit constraint */
- ct->regs = ALL_64;
- goto reserve_helpers;
- case 'I':
- ct->ct |= TCG_CT_CONST_S11;
- break;
- case 'J':
- ct->ct |= TCG_CT_CONST_S13;
- break;
- case 'Z':
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
/* test if a constant matches the constraint */
static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 12/22] tcg: Remove TCG_TARGET_CONSTR_H
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (10 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 11/22] tcg/sparc: " Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2021-01-07 17:27 ` Alistair Francis
2020-12-23 6:01 ` [PATCH 13/22] tcg: Split out constraint sets to tcg-target-conset.h Richard Henderson
` (10 subsequent siblings)
22 siblings, 1 reply; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
All backends have now been converted to tcg-target-constr.h,
so we can remove the fallback code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/tcg-target.h | 1 -
tcg/i386/tcg-target.h | 1 -
tcg/mips/tcg-target.h | 1 -
tcg/ppc/tcg-target.h | 1 -
tcg/riscv/tcg-target.h | 1 -
tcg/s390/tcg-target.h | 1 -
tcg/sparc/tcg-target.h | 1 -
tcg/tci/tcg-target.h | 2 --
tcg/tcg.c | 16 ----------------
10 files changed, 26 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index ca7af5a589..663dd0b95e 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -159,6 +159,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CONSTR_H
#endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 6f058d6d9b..17e771374d 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -146,6 +146,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 7c405e166d..abd4ac7fc0 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -235,6 +235,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index f4a79bcad1..c6b091d849 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -217,6 +217,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#ifdef CONFIG_SOFTMMU
#define TCG_TARGET_NEED_LDST_LABELS
#endif
-#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 78d3470f3c..be10363956 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -185,6 +185,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index ff8ff43a46..032439d806 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -175,6 +175,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_POOL_LABELS
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
-#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 3aff3cc572..63c8797bd3 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -162,6 +162,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index bfee6191b3..633841ebf2 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -179,6 +179,5 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CONSTR_H
#endif
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index cd3dee51bb..8c1c1d265d 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -210,6 +210,4 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
/* no need to flush icache explicitly */
}
-#define TCG_TARGET_CONSTR_H
-
#endif /* TCG_TARGET_H */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index f5b53d739e..2bde926315 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -102,10 +102,6 @@ static void tcg_register_jit_int(void *buf, size_t size,
__attribute__((unused));
/* Forward declarations for functions declared and used in tcg-target.c.inc. */
-#ifndef TCG_TARGET_CONSTR_H
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type);
-#endif
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
intptr_t arg2);
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
@@ -2288,7 +2284,6 @@ static void process_op_defs(TCGContext *s)
ct_str++;
break;
-#ifdef TCG_TARGET_CONSTR_H
/* Include all of the target-specific constraints. */
#undef CONST
@@ -2304,17 +2299,6 @@ static void process_op_defs(TCGContext *s)
default:
/* Typo in TCGTargetOpDef constraint. */
g_assert_not_reached();
-#else
- default:
- {
- TCGType type = (def->flags & TCG_OPF_64BIT
- ? TCG_TYPE_I64 : TCG_TYPE_I32);
- ct_str = target_parse_constraint(&def->args_ct[i],
- ct_str, type);
- /* Typo in TCGTargetOpDef constraint. */
- tcg_debug_assert(ct_str != NULL);
- }
-#endif
}
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 13/22] tcg: Split out constraint sets to tcg-target-conset.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (11 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 12/22] tcg: Remove TCG_TARGET_CONSTR_H Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2021-01-12 11:55 ` Peter Maydell
2020-12-23 6:01 ` [PATCH 14/22] tcg/aarch64: Convert " Richard Henderson
` (9 subsequent siblings)
22 siblings, 1 reply; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
This exports the constraint sets from tcg_target_op_def to
a place we will be able to manipulate more in future.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target-conset.h | 44 ++++++++
tcg/i386/tcg-target.h | 1 +
tcg/tcg.c | 126 +++++++++++++++++++++++
tcg/i386/tcg-target.c.inc | 189 ++++++++++++-----------------------
4 files changed, 236 insertions(+), 124 deletions(-)
create mode 100644 tcg/i386/tcg-target-conset.h
diff --git a/tcg/i386/tcg-target-conset.h b/tcg/i386/tcg-target-conset.h
new file mode 100644
index 0000000000..5a4f991d78
--- /dev/null
+++ b/tcg/i386/tcg-target-conset.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * i386 target-specific constaint sets.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(L, L)
+C_O0_I2(qi, r)
+C_O0_I2(re, r)
+C_O0_I2(ri, r)
+C_O0_I2(r, re)
+C_O0_I2(x, r)
+C_O0_I3(L, L, L)
+C_O0_I4(L, L, L, L)
+C_O0_I4(r, r, ri, ri)
+C_O1_I1(r, 0)
+C_O1_I1(r, L)
+C_O1_I1(r, q)
+C_O1_I1(r, r)
+C_O1_I1(x, r)
+C_O1_I1(x, x)
+C_O1_I2(Q, 0, Q)
+C_O1_I2(q, r, re)
+C_O1_I2(r, 0, ci)
+C_O1_I2(r, 0, r)
+C_O1_I2(r, 0, re)
+C_O1_I2(r, 0, reZ)
+C_O1_I2(r, 0, ri)
+C_O1_I2(r, 0, rI)
+C_O1_I2(r, L, L)
+C_O1_I2(r, r, re)
+C_O1_I2(r, r, ri)
+C_O1_I2(x, x, x)
+C_N1_I2(r, r, r)
+C_N1_I2(r, r, rW)
+C_O1_I3(x, x, x, x)
+C_O1_I4(r, r, re, r, 0)
+C_O1_I4(r, r, r, ri, ri)
+C_O2_I1(r, r, L)
+C_O2_I2(a, d, a, r)
+C_O2_I2(r, r, L, L)
+C_O2_I3(a, d, 0, 1, r)
+C_O2_I4(r, r, 0, 1, re, re)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index abd4ac7fc0..74a2566900 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -235,5 +235,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 2bde926315..c58d728ca5 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -68,7 +68,11 @@
/* Forward declarations for functions declared in tcg-target.c.inc and
used here. */
static void tcg_target_init(TCGContext *s);
+#ifdef TCG_TARGET_CONSET_H
+static int tcg_target_op_def(TCGOpcode);
+#else
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
+#endif
static void tcg_target_qemu_prologue(TCGContext *s);
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend);
@@ -340,6 +344,121 @@ static void set_jmp_reset_offset(TCGContext *s, int which)
s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
}
+#ifdef TCG_TARGET_CONSET_H
+#define C_PFX1(P, A) P##A
+#define C_PFX2(P, A, B) P##A##_##B
+#define C_PFX3(P, A, B, C) P##A##_##B##_##C
+#define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D
+#define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E
+#define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F
+
+/* Define an enumeration for the various combinations. */
+
+#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1),
+#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2),
+#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3),
+#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4),
+
+#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1),
+#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2),
+#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3),
+#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
+
+#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2),
+
+#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1),
+#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2),
+#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3),
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) \
+ C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4),
+
+typedef enum {
+#include "tcg-target-conset.h"
+} TCGConstraintSetIndex;
+
+
+#undef C_O0_I1
+#undef C_O0_I2
+#undef C_O0_I3
+#undef C_O0_I4
+#undef C_O1_I1
+#undef C_O1_I2
+#undef C_O1_I3
+#undef C_O1_I4
+#undef C_N1_I2
+#undef C_O2_I1
+#undef C_O2_I2
+#undef C_O2_I3
+#undef C_O2_I4
+
+/* Put all of the constraint sets into an array, indexed by the enum. */
+
+#define C_O0_I1(I1) { .args_ct_str = { #I1 } },
+#define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } },
+#define C_O0_I3(I1, I2, I3) { .args_ct_str = { #I1, #I2, #I3 } },
+#define C_O0_I4(I1, I2, I3, I4) \
+ { .args_ct_str = { #I1, #I2, #I3, #I4 } },
+
+#define C_O1_I1(O1, I1) { .args_ct_str = { #O1, #I1 } },
+#define C_O1_I2(O1, I1, I2) { .args_ct_str = { #O1, #I1, #I2 } },
+#define C_O1_I3(O1, I1, I2, I3) \
+ { .args_ct_str = { #O1, #I1, #I2, #I3 } },
+#define C_O1_I4(O1, I1, I2, I3, I4) \
+ { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
+
+#define C_N1_I2(O1, I1, I2) \
+ { .args_ct_str = { "&" #O1, #I1, #I2 } },
+
+#define C_O2_I1(O1, O2, I1) \
+ { .args_ct_str = { #O1, #O2, #I1 } },
+#define C_O2_I2(O1, O2, I1, I2) \
+ { .args_ct_str = { #O1, #O2, #I1, #I2 } },
+#define C_O2_I3(O1, O2, I1, I2, I3) \
+ { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } },
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) \
+ { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } },
+
+static const TCGTargetOpDef constraint_sets[] = {
+#include "tcg-target-conset.h"
+};
+
+
+#undef C_O0_I1
+#undef C_O0_I2
+#undef C_O0_I3
+#undef C_O0_I4
+#undef C_O1_I1
+#undef C_O1_I2
+#undef C_O1_I3
+#undef C_O1_I4
+#undef C_N1_I2
+#undef C_O2_I1
+#undef C_O2_I2
+#undef C_O2_I3
+#undef C_O2_I4
+
+/* Expand the enumerator to be returned from tcg_target_op_def(). */
+
+#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1)
+#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2)
+#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3)
+#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4)
+
+#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1)
+#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2)
+#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3)
+#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
+
+#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2)
+
+#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1)
+#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2)
+#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) \
+ C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
+
+#endif /* TCG_TARGET_CONSET_H */
+
#include "tcg-target.c.inc"
/* compare a pointer @ptr and a tb_tc @s */
@@ -2248,9 +2367,16 @@ static void process_op_defs(TCGContext *s)
continue;
}
+#ifdef TCG_TARGET_CONSET_H
+ i = tcg_target_op_def(op);
+ /* Missing TCGTargetOpDef entry. */
+ tcg_debug_assert(i >= 0 && i < ARRAY_SIZE(constraint_sets));
+ tdefs = &constraint_sets[i];
+#else
tdefs = tcg_target_op_def(op);
/* Missing TCGTargetOpDef entry. */
tcg_debug_assert(tdefs != NULL);
+#endif
for (i = 0; i < nb_args; i++) {
const char *ct_str = tdefs->args_ct_str[i];
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 981dd9aca4..708d465cbb 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -2903,39 +2903,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
}
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static int tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef ri_r = { .args_ct_str = { "ri", "r" } };
- static const TCGTargetOpDef re_r = { .args_ct_str = { "re", "r" } };
- static const TCGTargetOpDef qi_r = { .args_ct_str = { "qi", "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_q = { .args_ct_str = { "r", "q" } };
- static const TCGTargetOpDef r_re = { .args_ct_str = { "r", "re" } };
- static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
- static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
- static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
- static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
- static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
- static const TCGTargetOpDef r_r_L_L
- = { .args_ct_str = { "r", "r", "L", "L" } };
- static const TCGTargetOpDef L_L_L_L
- = { .args_ct_str = { "L", "L", "L", "L" } };
- static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } };
- static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } };
- static const TCGTargetOpDef x_x_x_x
- = { .args_ct_str = { "x", "x", "x", "x" } };
- static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
@@ -2949,22 +2921,25 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64:
- return &r_r;
+ return C_O1_I1(r, r);
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
- return &qi_r;
+ return C_O0_I2(qi, r);
+
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
- return &ri_r;
+ return C_O0_I2(ri, r);
+
case INDEX_op_st_i64:
- return &re_r;
+ return C_O0_I2(re, r);
case INDEX_op_add_i32:
case INDEX_op_add_i64:
- return &r_r_re;
+ return C_O1_I2(r, r, re);
+
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
case INDEX_op_mul_i32:
@@ -2973,24 +2948,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_or_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
- return &r_0_re;
+ return C_O1_I2(r, 0, re);
case INDEX_op_and_i32:
case INDEX_op_and_i64:
- {
- static const TCGTargetOpDef and
- = { .args_ct_str = { "r", "0", "reZ" } };
- return ∧
- }
- break;
+ return C_O1_I2(r, 0, reZ);
+
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
- {
- static const TCGTargetOpDef andc
- = { .args_ct_str = { "r", "r", "rI" } };
- return &andc;
- }
- break;
+ return C_O1_I2(r, 0, rI);
case INDEX_op_shl_i32:
case INDEX_op_shl_i64:
@@ -2998,16 +2964,17 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_shr_i64:
case INDEX_op_sar_i32:
case INDEX_op_sar_i64:
- return have_bmi2 ? &r_r_ri : &r_0_ci;
+ return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci);
+
case INDEX_op_rotl_i32:
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
case INDEX_op_rotr_i64:
- return &r_0_ci;
+ return C_O1_I2(r, 0, ci);
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &r_re;
+ return C_O0_I2(r, re);
case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64:
@@ -3019,13 +2986,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_extrh_i64_i32:
- return &r_0;
+ return C_O1_I1(r, 0);
case INDEX_op_ext8s_i32:
case INDEX_op_ext8s_i64:
case INDEX_op_ext8u_i32:
case INDEX_op_ext8u_i64:
- return &r_q;
+ return C_O1_I1(r, q);
+
case INDEX_op_ext16s_i32:
case INDEX_op_ext16s_i64:
case INDEX_op_ext16u_i32:
@@ -3040,108 +3008,80 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_sextract_i32:
case INDEX_op_ctpop_i32:
case INDEX_op_ctpop_i64:
- return &r_r;
+ return C_O1_I1(r, r);
+
case INDEX_op_extract2_i32:
case INDEX_op_extract2_i64:
- return &r_0_r;
+ return C_O1_I2(r, 0, r);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- {
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "Q", "0", "Q" } };
- return &dep;
- }
+ return C_O1_I2(Q, 0, Q);
+
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
- {
- static const TCGTargetOpDef setc
- = { .args_ct_str = { "q", "r", "re" } };
- return &setc;
- }
+ return C_O1_I2(q, r, re);
+
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
- {
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "re", "r", "0" } };
- return &movc;
- }
+ return C_O1_I4(r, r, re, r, 0);
+
case INDEX_op_div2_i32:
case INDEX_op_div2_i64:
case INDEX_op_divu2_i32:
case INDEX_op_divu2_i64:
- {
- static const TCGTargetOpDef div2
- = { .args_ct_str = { "a", "d", "0", "1", "r" } };
- return &div2;
- }
+ return C_O2_I3(a, d, 0, 1, r);
+
case INDEX_op_mulu2_i32:
case INDEX_op_mulu2_i64:
case INDEX_op_muls2_i32:
case INDEX_op_muls2_i64:
- {
- static const TCGTargetOpDef mul2
- = { .args_ct_str = { "a", "d", "a", "r" } };
- return &mul2;
- }
+ return C_O2_I2(a, d, a, r);
+
case INDEX_op_add2_i32:
case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
case INDEX_op_sub2_i64:
- {
- static const TCGTargetOpDef arith2
- = { .args_ct_str = { "r", "r", "0", "1", "re", "re" } };
- return &arith2;
- }
+ return C_O2_I4(r, r, 0, 1, re, re);
+
case INDEX_op_ctz_i32:
case INDEX_op_ctz_i64:
- {
- static const TCGTargetOpDef ctz[2] = {
- { .args_ct_str = { "&r", "r", "r" } },
- { .args_ct_str = { "&r", "r", "rW" } },
- };
- return &ctz[have_bmi1];
- }
+ return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
+
case INDEX_op_clz_i32:
case INDEX_op_clz_i64:
- {
- static const TCGTargetOpDef clz[2] = {
- { .args_ct_str = { "&r", "r", "r" } },
- { .args_ct_str = { "&r", "r", "rW" } },
- };
- return &clz[have_lzcnt];
- }
+ return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
case INDEX_op_qemu_ld_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
+
case INDEX_op_qemu_st_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L;
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O0_I2(L, L) : C_O0_I3(L, L, L));
+
case INDEX_op_qemu_ld_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
- : &r_r_L_L);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
+ : C_O2_I2(r, r, L, L));
+
case INDEX_op_qemu_st_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &L_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L
- : &L_L_L_L);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(L, L, L)
+ : C_O0_I4(L, L, L, L));
case INDEX_op_brcond2_i32:
- {
- static const TCGTargetOpDef b2
- = { .args_ct_str = { "r", "r", "ri", "ri" } };
- return &b2;
- }
+ return C_O0_I4(r, r, ri, ri);
+
case INDEX_op_setcond2_i32:
- {
- static const TCGTargetOpDef s2
- = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
- return &s2;
- }
+ return C_O1_I4(r, r, r, ri, ri);
case INDEX_op_ld_vec:
- case INDEX_op_st_vec:
case INDEX_op_dupm_vec:
- return &x_r;
+ return C_O1_I1(x, r);
+
+ case INDEX_op_st_vec:
+ return C_O0_I2(x, r);
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
@@ -3176,21 +3116,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_dup2_vec:
#endif
- return &x_x_x;
+ return C_O1_I2(x, x, x);
+
case INDEX_op_abs_vec:
case INDEX_op_dup_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
case INDEX_op_x86_psrldq_vec:
- return &x_x;
+ return C_O1_I1(x, x);
+
case INDEX_op_x86_vpblendvb_vec:
- return &x_x_x_x;
+ return C_O1_I3(x, x, x, x);
default:
- break;
+ g_assert_not_reached();
}
- return NULL;
}
int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 14/22] tcg/aarch64: Convert to tcg-target-conset.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (12 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 13/22] tcg: Split out constraint sets to tcg-target-conset.h Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2020-12-23 6:01 ` [PATCH 15/22] tcg/arm: " Richard Henderson
` (8 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target-conset.h | 31 ++++++++++++
tcg/aarch64/tcg-target.h | 1 +
tcg/aarch64/tcg-target.c.inc | 86 +++++++++++----------------------
3 files changed, 60 insertions(+), 58 deletions(-)
create mode 100644 tcg/aarch64/tcg-target-conset.h
diff --git a/tcg/aarch64/tcg-target-conset.h b/tcg/aarch64/tcg-target-conset.h
new file mode 100644
index 0000000000..2df8157b15
--- /dev/null
+++ b/tcg/aarch64/tcg-target-conset.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * AArch64 target-specific constaint sets.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(lZ, l)
+C_O0_I2(r, rA)
+C_O0_I2(rZ, r)
+C_O0_I2(w, r)
+C_O1_I1(r, l)
+C_O1_I1(r, r)
+C_O1_I1(w, r)
+C_O1_I1(w, w)
+C_O1_I1(w, wr)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, rA)
+C_O1_I2(r, r, rAL)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rL)
+C_O1_I2(r, rZ, rZ)
+C_O1_I2(w, 0, w)
+C_O1_I2(w, w, w)
+C_O1_I2(w, w, wN)
+C_O1_I2(w, w, wO)
+C_O1_I2(w, w, wZ)
+C_O1_I3(w, w, w, w)
+C_O1_I4(r, r, rA, rZ, rZ)
+C_O2_I4(r, r, rZ, rZ, rA, rMZ)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 663dd0b95e..a81f6dadf9 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -159,5 +159,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CONSET_H
#endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 310bc972e3..aaf8918a4b 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2541,42 +2541,11 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
va_end(va);
}
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static int tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } };
- static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } };
- static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } };
- static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
- static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } };
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
- static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };
- static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } };
- static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } };
- static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } };
- static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } };
- static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } };
- static const TCGTargetOpDef r_r_rAL
- = { .args_ct_str = { "r", "r", "rAL" } };
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "0", "rZ" } };
- static const TCGTargetOpDef ext2
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
- static const TCGTargetOpDef add2
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } };
- static const TCGTargetOpDef w_w_w_w
- = { .args_ct_str = { "w", "w", "w", "w" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
@@ -2615,7 +2584,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
- return &r_r;
+ return C_O1_I1(r, r);
case INDEX_op_st8_i32:
case INDEX_op_st16_i32:
@@ -2624,7 +2593,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
- return &rZ_r;
+ return C_O0_I2(rZ, r);
case INDEX_op_add_i32:
case INDEX_op_add_i64:
@@ -2632,7 +2601,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_sub_i64:
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
- return &r_r_rA;
+ return C_O1_I2(r, r, rA);
case INDEX_op_mul_i32:
case INDEX_op_mul_i64:
@@ -2646,7 +2615,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_remu_i64:
case INDEX_op_muluh_i64:
case INDEX_op_mulsh_i64:
- return &r_r_r;
+ return C_O1_I2(r, r, r);
case INDEX_op_and_i32:
case INDEX_op_and_i64:
@@ -2660,7 +2629,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_orc_i64:
case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64:
- return &r_r_rL;
+ return C_O1_I2(r, r, rL);
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
@@ -2672,42 +2641,42 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_sar_i64:
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i64:
- return &r_r_ri;
+ return C_O1_I2(r, r, ri);
case INDEX_op_clz_i32:
case INDEX_op_ctz_i32:
case INDEX_op_clz_i64:
case INDEX_op_ctz_i64:
- return &r_r_rAL;
+ return C_O1_I2(r, r, rAL);
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &r_rA;
+ return C_O0_I2(r, rA);
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
- return &movc;
+ return C_O1_I4(r, r, rA, rZ, rZ);
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
- return &r_l;
+ return C_O1_I1(r, l);
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
- return &lZ_l;
+ return C_O0_I2(lZ, l);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- return &dep;
+ return C_O1_I2(r, 0, rZ);
case INDEX_op_extract2_i32:
case INDEX_op_extract2_i64:
- return &ext2;
+ return C_O1_I2(r, rZ, rZ);
case INDEX_op_add2_i32:
case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
case INDEX_op_sub2_i64:
- return &add2;
+ return C_O2_I4(r, r, rZ, rZ, rA, rMZ);
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
@@ -2725,35 +2694,36 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
case INDEX_op_aa64_sshl_vec:
- return &w_w_w;
+ return C_O1_I2(w, w, w);
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
case INDEX_op_abs_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
- return &w_w;
+ return C_O1_I1(w, w);
case INDEX_op_ld_vec:
- case INDEX_op_st_vec:
case INDEX_op_dupm_vec:
- return &w_r;
+ return C_O1_I1(w, r);
+ case INDEX_op_st_vec:
+ return C_O0_I2(w, r);
case INDEX_op_dup_vec:
- return &w_wr;
+ return C_O1_I1(w, wr);
case INDEX_op_or_vec:
case INDEX_op_andc_vec:
- return &w_w_wO;
+ return C_O1_I2(w, w, wO);
case INDEX_op_and_vec:
case INDEX_op_orc_vec:
- return &w_w_wN;
+ return C_O1_I2(w, w, wN);
case INDEX_op_cmp_vec:
- return &w_w_wZ;
+ return C_O1_I2(w, w, wZ);
case INDEX_op_bitsel_vec:
- return &w_w_w_w;
+ return C_O1_I3(w, w, w, w);
case INDEX_op_aa64_sli_vec:
- return &w_0_w;
+ return C_O1_I2(w, 0, w);
default:
- return NULL;
+ g_assert_not_reached();
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 15/22] tcg/arm: Convert to tcg-target-conset.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (13 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 14/22] tcg/aarch64: Convert " Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2020-12-23 6:01 ` [PATCH 16/22] tcg/mips: " Richard Henderson
` (7 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target-conset.h | 30 ++++++++++++
tcg/arm/tcg-target.h | 1 +
tcg/arm/tcg-target.c.inc | 94 +++++++++++++------------------------
3 files changed, 63 insertions(+), 62 deletions(-)
create mode 100644 tcg/arm/tcg-target-conset.h
diff --git a/tcg/arm/tcg-target-conset.h b/tcg/arm/tcg-target-conset.h
new file mode 100644
index 0000000000..7e972e70e0
--- /dev/null
+++ b/tcg/arm/tcg-target-conset.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Arm target-specific constaint sets.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(r, r)
+C_O0_I2(r, rIN)
+C_O0_I2(s, s)
+C_O0_I3(s, s, s)
+C_O0_I4(r, r, rI, rI)
+C_O0_I4(s, s, s, s)
+C_O1_I1(r, l)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, l, l)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, r, rIK)
+C_O1_I2(r, r, rIN)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, r, r, rI, rI)
+C_O1_I4(r, r, rIN, rIK, 0)
+C_O2_I1(r, r, l)
+C_O2_I2(r, r, l, l)
+C_O2_I2(r, r, r, r)
+C_O2_I4(r, r, r, r, rIN, rIK)
+C_O2_I4(r, r, rI, rI, rIN, rIK)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 17e771374d..918f09239a 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -146,5 +146,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index ab1b295293..029d58e4b7 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -2012,57 +2012,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static int tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } };
- static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
- static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } };
- static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } };
- static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_r_rIN
- = { .args_ct_str = { "r", "r", "rIN" } };
- static const TCGTargetOpDef r_r_rIK
- = { .args_ct_str = { "r", "r", "rIK" } };
- static const TCGTargetOpDef r_r_r_r
- = { .args_ct_str = { "r", "r", "r", "r" } };
- static const TCGTargetOpDef r_r_l_l
- = { .args_ct_str = { "r", "r", "l", "l" } };
- static const TCGTargetOpDef s_s_s_s
- = { .args_ct_str = { "s", "s", "s", "s" } };
- static const TCGTargetOpDef br
- = { .args_ct_str = { "r", "rIN" } };
- static const TCGTargetOpDef ext2
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "0", "rZ" } };
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } };
- static const TCGTargetOpDef add2
- = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } };
- static const TCGTargetOpDef sub2
- = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } };
- static const TCGTargetOpDef br2
- = { .args_ct_str = { "r", "r", "rI", "rI" } };
- static const TCGTargetOpDef setc2
- = { .args_ct_str = { "r", "r", "r", "rI", "rI" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
case INDEX_op_neg_i32:
case INDEX_op_not_i32:
case INDEX_op_bswap16_i32:
@@ -2072,62 +2032,72 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ext16u_i32:
case INDEX_op_extract_i32:
case INDEX_op_sextract_i32:
- return &r_r;
+ return C_O1_I1(r, r);
+
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ return C_O0_I2(r, r);
case INDEX_op_add_i32:
case INDEX_op_sub_i32:
case INDEX_op_setcond_i32:
- return &r_r_rIN;
+ return C_O1_I2(r, r, rIN);
+
case INDEX_op_and_i32:
case INDEX_op_andc_i32:
case INDEX_op_clz_i32:
case INDEX_op_ctz_i32:
- return &r_r_rIK;
+ return C_O1_I2(r, r, rIK);
+
case INDEX_op_mul_i32:
case INDEX_op_div_i32:
case INDEX_op_divu_i32:
- return &r_r_r;
+ return C_O1_I2(r, r, r);
+
case INDEX_op_mulu2_i32:
case INDEX_op_muls2_i32:
- return &r_r_r_r;
+ return C_O2_I2(r, r, r, r);
+
case INDEX_op_or_i32:
case INDEX_op_xor_i32:
- return &r_r_rI;
+ return C_O1_I2(r, r, rI);
+
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
case INDEX_op_rotl_i32:
case INDEX_op_rotr_i32:
- return &r_r_ri;
+ return C_O1_I2(r, r, ri);
case INDEX_op_brcond_i32:
- return &br;
+ return C_O0_I2(r, rIN);
case INDEX_op_deposit_i32:
- return &dep;
+ return C_O1_I2(r, 0, rZ);
case INDEX_op_extract2_i32:
- return &ext2;
+ return C_O1_I2(r, rZ, rZ);
case INDEX_op_movcond_i32:
- return &movc;
+ return C_O1_I4(r, r, rIN, rIK, 0);
case INDEX_op_add2_i32:
- return &add2;
+ return C_O2_I4(r, r, r, r, rIN, rIK);
case INDEX_op_sub2_i32:
- return &sub2;
+ return C_O2_I4(r, r, rI, rI, rIN, rIK);
case INDEX_op_brcond2_i32:
- return &br2;
+ return C_O0_I4(r, r, rI, rI);
case INDEX_op_setcond2_i32:
- return &setc2;
+ return C_O1_I4(r, r, r, rI, rI);
case INDEX_op_qemu_ld_i32:
- return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l;
+ return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l);
case INDEX_op_qemu_ld_i64:
- return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l;
+ return TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, r, l, l);
case INDEX_op_qemu_st_i32:
- return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s;
+ return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s);
case INDEX_op_qemu_st_i64:
- return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s;
+ return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
default:
- return NULL;
+ g_assert_not_reached();
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 16/22] tcg/mips: Convert to tcg-target-conset.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (14 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 15/22] tcg/arm: " Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2020-12-23 6:01 ` [PATCH 17/22] tcg/ppc: " Richard Henderson
` (6 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target-conset.h | 31 ++++++++++++
tcg/mips/tcg-target.h | 1 +
tcg/mips/tcg-target.c.inc | 96 +++++++++++-------------------------
3 files changed, 61 insertions(+), 67 deletions(-)
create mode 100644 tcg/mips/tcg-target-conset.h
diff --git a/tcg/mips/tcg-target-conset.h b/tcg/mips/tcg-target-conset.h
new file mode 100644
index 0000000000..94f8f5f683
--- /dev/null
+++ b/tcg/mips/tcg-target-conset.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * MIPS target-specific constaint sets.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(rZ, r)
+C_O0_I2(rZ, rZ)
+C_O0_I2(SZ, S)
+C_O0_I3(SZ, S, S)
+C_O0_I3(SZ, SZ, S)
+C_O0_I4(rZ, rZ, rZ, rZ)
+C_O0_I4(SZ, SZ, S, S)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, L, L)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, r, rIK)
+C_O1_I2(r, r, rJ)
+C_O1_I2(r, r, rWZ)
+C_O1_I2(r, rZ, rN)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, rZ, rZ, rZ, 0)
+C_O1_I4(r, rZ, rZ, rZ, rZ)
+C_O2_I1(r, r, L)
+C_O2_I2(r, r, L, L)
+C_O2_I2(r, r, r, r)
+C_O2_I4(r, r, rZ, rZ, rN, rN)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index c6b091d849..688d691cda 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -217,5 +217,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#ifdef CONFIG_SOFTMMU
#define TCG_TARGET_NEED_LDST_LABELS
#endif
+#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index d0b674582a..2ec1d6ac05 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -2104,52 +2104,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static int tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
- static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
- static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
- static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
- static const TCGTargetOpDef SZ_SZ_S
- = { .args_ct_str = { "SZ", "SZ", "S" } };
- static const TCGTargetOpDef SZ_SZ_S_S
- = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
- static const TCGTargetOpDef r_rZ_rN
- = { .args_ct_str = { "r", "rZ", "rN" } };
- static const TCGTargetOpDef r_rZ_rZ
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef r_r_rIK
- = { .args_ct_str = { "r", "r", "rIK" } };
- static const TCGTargetOpDef r_r_rWZ
- = { .args_ct_str = { "r", "r", "rWZ" } };
- static const TCGTargetOpDef r_r_r_r
- = { .args_ct_str = { "r", "r", "r", "r" } };
- static const TCGTargetOpDef r_r_L_L
- = { .args_ct_str = { "r", "r", "L", "L" } };
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "0", "rZ" } };
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
- static const TCGTargetOpDef movc_r6
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef add2
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
- static const TCGTargetOpDef br2
- = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef setc2
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
@@ -2182,7 +2141,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_extract_i64:
- return &r_r;
+ return C_O1_I1(r, r);
case INDEX_op_st8_i32:
case INDEX_op_st16_i32:
@@ -2191,14 +2150,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
- return &rZ_r;
+ return C_O0_I2(rZ, r);
case INDEX_op_add_i32:
case INDEX_op_add_i64:
- return &r_r_rJ;
+ return C_O1_I2(r, r, rJ);
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
- return &r_rZ_rN;
+ return C_O1_I2(r, rZ, rN);
case INDEX_op_mul_i32:
case INDEX_op_mulsh_i32:
case INDEX_op_muluh_i32:
@@ -2217,20 +2176,20 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_remu_i64:
case INDEX_op_nor_i64:
case INDEX_op_setcond_i64:
- return &r_rZ_rZ;
+ return C_O1_I2(r, rZ, rZ);
case INDEX_op_muls2_i32:
case INDEX_op_mulu2_i32:
case INDEX_op_muls2_i64:
case INDEX_op_mulu2_i64:
- return &r_r_r_r;
+ return C_O2_I2(r, r, r, r);
case INDEX_op_and_i32:
case INDEX_op_and_i64:
- return &r_r_rIK;
+ return C_O1_I2(r, r, rIK);
case INDEX_op_or_i32:
case INDEX_op_xor_i32:
case INDEX_op_or_i64:
case INDEX_op_xor_i64:
- return &r_r_rI;
+ return C_O1_I2(r, r, rI);
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
@@ -2241,44 +2200,47 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_sar_i64:
case INDEX_op_rotr_i64:
case INDEX_op_rotl_i64:
- return &r_r_ri;
+ return C_O1_I2(r, r, ri);
case INDEX_op_clz_i32:
case INDEX_op_clz_i64:
- return &r_r_rWZ;
+ return C_O1_I2(r, r, rWZ);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- return &dep;
+ return C_O1_I2(r, 0, rZ);
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &rZ_rZ;
+ return C_O0_I2(rZ, rZ);
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
- return use_mips32r6_instructions ? &movc_r6 : &movc;
-
+ return (use_mips32r6_instructions
+ ? C_O1_I4(r, rZ, rZ, rZ, rZ)
+ : C_O1_I4(r, rZ, rZ, rZ, 0));
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
- return &add2;
+ return C_O2_I4(r, r, rZ, rZ, rN, rN);
case INDEX_op_setcond2_i32:
- return &setc2;
+ return C_O1_I4(r, rZ, rZ, rZ, rZ);
case INDEX_op_brcond2_i32:
- return &br2;
+ return C_O0_I4(rZ, rZ, rZ, rZ);
case INDEX_op_qemu_ld_i32:
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &r_L : &r_L_L);
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
case INDEX_op_qemu_st_i32:
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &SZ_S : &SZ_S_S);
+ ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S));
case INDEX_op_qemu_ld_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+ : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L)
+ : C_O2_I2(r, r, L, L));
case INDEX_op_qemu_st_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
- : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S)
+ : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S)
+ : C_O0_I4(SZ, SZ, S, S));
default:
- return NULL;
+ g_assert_not_reached();
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 17/22] tcg/ppc: Convert to tcg-target-conset.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (15 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 16/22] tcg/mips: " Richard Henderson
@ 2020-12-23 6:01 ` Richard Henderson
2020-12-23 6:02 ` [PATCH 18/22] tcg/riscv: " Richard Henderson
` (5 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:01 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target-conset.h | 37 ++++++++++
tcg/ppc/tcg-target.h | 1 +
tcg/ppc/tcg-target.c.inc | 136 +++++++++++++++---------------------
3 files changed, 94 insertions(+), 80 deletions(-)
create mode 100644 tcg/ppc/tcg-target-conset.h
diff --git a/tcg/ppc/tcg-target-conset.h b/tcg/ppc/tcg-target-conset.h
new file mode 100644
index 0000000000..448ac6d155
--- /dev/null
+++ b/tcg/ppc/tcg-target-conset.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * PowerPC target-specific constaint sets.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O0_I2(S, S)
+C_O0_I2(v, r)
+C_O0_I3(S, S, S)
+C_O0_I4(r, r, ri, ri)
+C_O0_I4(S, S, S, S)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I1(v, r)
+C_O1_I1(v, v)
+C_O1_I1(v, vr)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, L, L)
+C_O1_I2(r, rI, ri)
+C_O1_I2(r, rI, rT)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, r, rT)
+C_O1_I2(r, r, rU)
+C_O1_I2(r, r, rZW)
+C_O1_I2(v, v, v)
+C_O1_I3(v, v, v, v)
+C_O1_I4(r, r, ri, rZ, rZ)
+C_O1_I4(r, r, r, ri, ri)
+C_O2_I1(L, L, L)
+C_O2_I2(L, L, L, L)
+C_O2_I4(r, r, rI, rZM, r, r)
+C_O2_I4(r, r, r, r, rI, rZM)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index be10363956..c958faffb7 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -185,5 +185,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index c97f95f3cf..eb8a626ad4 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -3425,62 +3425,17 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
va_end(va);
}
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static int tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
- static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
- static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
- static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
- static const TCGTargetOpDef r_rI_ri
- = { .args_ct_str = { "r", "rI", "ri" } };
- static const TCGTargetOpDef r_rI_rT
- = { .args_ct_str = { "r", "rI", "rT" } };
- static const TCGTargetOpDef r_r_rZW
- = { .args_ct_str = { "r", "r", "rZW" } };
- static const TCGTargetOpDef L_L_L_L
- = { .args_ct_str = { "L", "L", "L", "L" } };
- static const TCGTargetOpDef S_S_S_S
- = { .args_ct_str = { "S", "S", "S", "S" } };
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "0", "rZ" } };
- static const TCGTargetOpDef br2
- = { .args_ct_str = { "r", "r", "ri", "ri" } };
- static const TCGTargetOpDef setc2
- = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
- static const TCGTargetOpDef add2
- = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
- static const TCGTargetOpDef sub2
- = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
- static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
- static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } };
- static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
- static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
- static const TCGTargetOpDef v_v_v_v
- = { .args_ct_str = { "v", "v", "v", "v" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
case INDEX_op_ctpop_i32:
case INDEX_op_neg_i32:
case INDEX_op_not_i32:
@@ -3496,10 +3451,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
case INDEX_op_ctpop_i64:
case INDEX_op_neg_i64:
case INDEX_op_not_i64:
@@ -3512,7 +3463,16 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_extract_i64:
- return &r_r;
+ return C_O1_I1(r, r);
+
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ return C_O0_I2(r, r);
case INDEX_op_add_i32:
case INDEX_op_and_i32:
@@ -3535,10 +3495,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i64:
case INDEX_op_setcond_i64:
- return &r_r_ri;
+ return C_O1_I2(r, r, ri);
+
case INDEX_op_mul_i32:
case INDEX_op_mul_i64:
- return &r_r_rI;
+ return C_O1_I2(r, r, rI);
+
case INDEX_op_div_i32:
case INDEX_op_divu_i32:
case INDEX_op_nand_i32:
@@ -3553,55 +3515,63 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_divu_i64:
case INDEX_op_mulsh_i64:
case INDEX_op_muluh_i64:
- return &r_r_r;
+ return C_O1_I2(r, r, r);
+
case INDEX_op_sub_i32:
- return &r_rI_ri;
+ return C_O1_I2(r, rI, ri);
case INDEX_op_add_i64:
- return &r_r_rT;
+ return C_O1_I2(r, r, rT);
case INDEX_op_or_i64:
case INDEX_op_xor_i64:
- return &r_r_rU;
+ return C_O1_I2(r, r, rU);
case INDEX_op_sub_i64:
- return &r_rI_rT;
+ return C_O1_I2(r, rI, rT);
case INDEX_op_clz_i32:
case INDEX_op_ctz_i32:
case INDEX_op_clz_i64:
case INDEX_op_ctz_i64:
- return &r_r_rZW;
+ return C_O1_I2(r, r, rZW);
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &r_ri;
+ return C_O0_I2(r, ri);
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
- return &movc;
+ return C_O1_I4(r, r, ri, rZ, rZ);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- return &dep;
+ return C_O1_I2(r, 0, rZ);
case INDEX_op_brcond2_i32:
- return &br2;
+ return C_O0_I4(r, r, ri, ri);
case INDEX_op_setcond2_i32:
- return &setc2;
+ return C_O1_I4(r, r, r, ri, ri);
case INDEX_op_add2_i64:
case INDEX_op_add2_i32:
- return &add2;
+ return C_O2_I4(r, r, r, r, rI, rZM);
case INDEX_op_sub2_i64:
case INDEX_op_sub2_i32:
- return &sub2;
+ return C_O2_I4(r, r, rI, rZM, r, r);
case INDEX_op_qemu_ld_i32:
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &r_L : &r_L_L);
+ ? C_O1_I1(r, L)
+ : C_O1_I2(r, L, L));
+
case INDEX_op_qemu_st_i32:
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &S_S : &S_S_S);
+ ? C_O0_I2(S, S)
+ : C_O0_I3(S, S, S));
+
case INDEX_op_qemu_ld_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+ : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L)
+ : C_O2_I2(L, L, L, L));
+
case INDEX_op_qemu_st_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &S_S
- : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S)
+ : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S)
+ : C_O0_I4(S, S, S, S));
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
@@ -3631,22 +3601,28 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ppc_mulou_vec:
case INDEX_op_ppc_pkum_vec:
case INDEX_op_dup2_vec:
- return &v_v_v;
+ return C_O1_I2(v, v, v);
+
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
- return &v_v;
+ return C_O1_I1(v, v);
+
case INDEX_op_dup_vec:
- return have_isa_3_00 ? &v_vr : &v_v;
+ return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v);
+
case INDEX_op_ld_vec:
- case INDEX_op_st_vec:
case INDEX_op_dupm_vec:
- return &v_r;
+ return C_O1_I1(v, r);
+
+ case INDEX_op_st_vec:
+ return C_O0_I2(v, r);
+
case INDEX_op_bitsel_vec:
case INDEX_op_ppc_msum_vec:
- return &v_v_v_v;
+ return C_O1_I3(v, v, v, v);
default:
- return NULL;
+ g_assert_not_reached();
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 18/22] tcg/riscv: Convert to tcg-target-conset.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (16 preceding siblings ...)
2020-12-23 6:01 ` [PATCH 17/22] tcg/ppc: " Richard Henderson
@ 2020-12-23 6:02 ` Richard Henderson
2021-01-07 17:30 ` Alistair Francis
2021-01-07 18:08 ` Peter Maydell
2020-12-23 6:02 ` [PATCH 19/22] tcg/s390: " Richard Henderson
` (4 subsequent siblings)
22 siblings, 2 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:02 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target-conset.h | 25 +++++++++++
tcg/riscv/tcg-target.h | 1 +
tcg/riscv/tcg-target.c.inc | 83 ++++++++++-------------------------
3 files changed, 49 insertions(+), 60 deletions(-)
create mode 100644 tcg/riscv/tcg-target-conset.h
diff --git a/tcg/riscv/tcg-target-conset.h b/tcg/riscv/tcg-target-conset.h
new file mode 100644
index 0000000000..116dd75db2
--- /dev/null
+++ b/tcg/riscv/tcg-target-conset.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * RISC-V target-specific constaint sets.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(LZ, L)
+C_O0_I2(rZ, r)
+C_O0_I2(rZ, rZ)
+C_O0_I3(LZ, L, L)
+C_O0_I3(LZ, LZ, L)
+C_O0_I4(LZ, LZ, L, L)
+C_O0_I4(rZ, rZ, rZ, rZ)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, L, L)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, rZ, rN)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, rZ, rZ, rZ, rZ)
+C_O2_I1(r, r, L)
+C_O2_I2(r, r, L, L)
+C_O2_I4(r, r, rZ, rZ, rM, rM)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 032439d806..a357962e01 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -175,5 +175,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_POOL_LABELS
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
+#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 33047c1951..d222692704 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1571,50 +1571,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static int tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r
- = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r
- = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef rZ_r
- = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef rZ_rZ
- = { .args_ct_str = { "rZ", "rZ" } };
- static const TCGTargetOpDef rZ_rZ_rZ_rZ
- = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef r_r_ri
- = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI
- = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_rZ_rN
- = { .args_ct_str = { "r", "rZ", "rN" } };
- static const TCGTargetOpDef r_rZ_rZ
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef r_rZ_rZ_rZ_rZ
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef r_L
- = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef r_r_L
- = { .args_ct_str = { "r", "r", "L" } };
- static const TCGTargetOpDef r_L_L
- = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef r_r_L_L
- = { .args_ct_str = { "r", "r", "L", "L" } };
- static const TCGTargetOpDef LZ_L
- = { .args_ct_str = { "LZ", "L" } };
- static const TCGTargetOpDef LZ_L_L
- = { .args_ct_str = { "LZ", "L", "L" } };
- static const TCGTargetOpDef LZ_LZ_L
- = { .args_ct_str = { "LZ", "LZ", "L" } };
- static const TCGTargetOpDef LZ_LZ_L_L
- = { .args_ct_str = { "LZ", "LZ", "L", "L" } };
- static const TCGTargetOpDef r_r_rZ_rZ_rM_rM
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
@@ -1646,7 +1607,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_ext_i32_i64:
- return &r_r;
+ return C_O1_I1(r, r);
case INDEX_op_st8_i32:
case INDEX_op_st16_i32:
@@ -1655,7 +1616,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
- return &rZ_r;
+ return C_O0_I2(rZ, r);
case INDEX_op_add_i32:
case INDEX_op_and_i32:
@@ -1665,11 +1626,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_and_i64:
case INDEX_op_or_i64:
case INDEX_op_xor_i64:
- return &r_r_rI;
+ return C_O1_I2(r, r, rI);
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
- return &r_rZ_rN;
+ return C_O1_I2(r, rZ, rN);
case INDEX_op_mul_i32:
case INDEX_op_mulsh_i32:
@@ -1687,7 +1648,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_rem_i64:
case INDEX_op_remu_i64:
case INDEX_op_setcond_i64:
- return &r_rZ_rZ;
+ return C_O1_I2(r, rZ, rZ);
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
@@ -1695,39 +1656,41 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_shl_i64:
case INDEX_op_shr_i64:
case INDEX_op_sar_i64:
- return &r_r_ri;
+ return C_O1_I2(r, r, ri);
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &rZ_rZ;
+ return C_O0_I2(rZ, rZ);
case INDEX_op_add2_i32:
case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
case INDEX_op_sub2_i64:
- return &r_r_rZ_rZ_rM_rM;
+ return C_O2_I4(r, r, rZ, rZ, rM, rM);
case INDEX_op_brcond2_i32:
- return &rZ_rZ_rZ_rZ;
+ return C_O0_I4(rZ, rZ, rZ, rZ);
case INDEX_op_setcond2_i32:
- return &r_rZ_rZ_rZ_rZ;
+ return C_O1_I4(r, rZ, rZ, rZ, rZ);
case INDEX_op_qemu_ld_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
case INDEX_op_qemu_st_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L;
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L));
case INDEX_op_qemu_ld_i64:
- return TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
- : &r_r_L_L;
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
+ : C_O2_I2(r, r, L, L));
case INDEX_op_qemu_st_i64:
- return TCG_TARGET_REG_BITS == 64 ? &LZ_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L
- : &LZ_LZ_L_L;
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L)
+ : C_O0_I4(LZ, LZ, L, L));
default:
- return NULL;
+ g_assert_not_reached();
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 19/22] tcg/s390: Convert to tcg-target-conset.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (17 preceding siblings ...)
2020-12-23 6:02 ` [PATCH 18/22] tcg/riscv: " Richard Henderson
@ 2020-12-23 6:02 ` Richard Henderson
2020-12-23 6:02 ` [PATCH 20/22] tcg/sparc: " Richard Henderson
` (3 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:02 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390/tcg-target-conset.h | 24 +++++++
tcg/s390/tcg-target.h | 1 +
tcg/s390/tcg-target.c.inc | 121 +++++++++++++++--------------------
3 files changed, 76 insertions(+), 70 deletions(-)
create mode 100644 tcg/s390/tcg-target-conset.h
diff --git a/tcg/s390/tcg-target-conset.h b/tcg/s390/tcg-target-conset.h
new file mode 100644
index 0000000000..e68baabbfd
--- /dev/null
+++ b/tcg/s390/tcg-target-conset.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * S390 target-specific constaint sets.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(L, L)
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, ri)
+C_O1_I2(r, 0, rI)
+C_O1_I2(r, 0, rJ)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, rZ, r)
+C_O1_I4(r, r, ri, r, 0)
+C_O1_I4(r, r, ri, rI, 0)
+C_O2_I2(b, a, 0, r)
+C_O2_I3(b, a, 0, 1, r)
+C_O2_I4(r, r, 0, 1, rA, r)
+C_O2_I4(r, r, 0, 1, ri, r)
+C_O2_I4(r, r, 0, 1, r, r)
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 63c8797bd3..78277a8d07 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -162,5 +162,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index d00d78f0b9..410f63104f 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -2274,27 +2274,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static int tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
- static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
- static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
- static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
- static const TCGTargetOpDef a2_r
- = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
- static const TCGTargetOpDef a2_ri
- = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
- static const TCGTargetOpDef a2_rA
- = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
@@ -2308,6 +2292,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64:
+ return C_O1_I1(r, r);
+
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
case INDEX_op_st16_i32:
@@ -2315,11 +2301,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
- return &r_r;
+ return C_O0_I2(r, r);
case INDEX_op_add_i32:
case INDEX_op_add_i64:
- return &r_r_ri;
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotl_i64:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_rotr_i64:
+ case INDEX_op_clz_i64:
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ return C_O1_I2(r, r, ri);
+
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
case INDEX_op_and_i32:
@@ -2328,35 +2325,33 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_or_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
- return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
+ return (s390_facilities & FACILITY_DISTINCT_OPS
+ ? C_O1_I2(r, r, ri)
+ : C_O1_I2(r, 0, ri));
case INDEX_op_mul_i32:
/* If we have the general-instruction-extensions, then we have
MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
- return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);
+ return (s390_facilities & FACILITY_GEN_INST_EXT
+ ? C_O1_I2(r, 0, ri)
+ : C_O1_I2(r, 0, rI));
+
case INDEX_op_mul_i64:
- return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
+ return (s390_facilities & FACILITY_GEN_INST_EXT
+ ? C_O1_I2(r, 0, rJ)
+ : C_O1_I2(r, 0, rI));
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
- return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
-
- case INDEX_op_shl_i64:
- case INDEX_op_shr_i64:
- case INDEX_op_sar_i64:
- return &r_r_ri;
-
- case INDEX_op_rotl_i32:
- case INDEX_op_rotl_i64:
- case INDEX_op_rotr_i32:
- case INDEX_op_rotr_i64:
- return &r_r_ri;
+ return (s390_facilities & FACILITY_DISTINCT_OPS
+ ? C_O1_I2(r, r, ri)
+ : C_O1_I2(r, 0, ri));
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &r_ri;
+ return C_O0_I2(r, ri);
case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64:
@@ -2379,63 +2374,49 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_extu_i32_i64:
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
- return &r_r;
-
- case INDEX_op_clz_i64:
- case INDEX_op_setcond_i32:
- case INDEX_op_setcond_i64:
- return &r_r_ri;
+ return C_O1_I1(r, r);
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
- return &r_L;
+ return C_O1_I1(r, L);
case INDEX_op_qemu_st_i64:
case INDEX_op_qemu_st_i32:
- return &L_L;
+ return C_O0_I2(L, L);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- {
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "rZ", "r" } };
- return &dep;
- }
+ return C_O1_I2(r, rZ, r);
+
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
- {
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "ri", "r", "0" } };
- static const TCGTargetOpDef movc_l
- = { .args_ct_str = { "r", "r", "ri", "rI", "0" } };
- return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc);
- }
+ return (s390_facilities & FACILITY_LOAD_ON_COND2
+ ? C_O1_I4(r, r, ri, rI, 0)
+ : C_O1_I4(r, r, ri, r, 0));
+
case INDEX_op_div2_i32:
case INDEX_op_div2_i64:
case INDEX_op_divu2_i32:
case INDEX_op_divu2_i64:
- {
- static const TCGTargetOpDef div2
- = { .args_ct_str = { "b", "a", "0", "1", "r" } };
- return &div2;
- }
+ return C_O2_I3(b, a, 0, 1, r);
+
case INDEX_op_mulu2_i64:
- {
- static const TCGTargetOpDef mul2
- = { .args_ct_str = { "b", "a", "0", "r" } };
- return &mul2;
- }
+ return C_O2_I2(b, a, 0, r);
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
- return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r);
+ return (s390_facilities & FACILITY_EXT_IMM
+ ? C_O2_I4(r, r, 0, 1, ri, r)
+ : C_O2_I4(r, r, 0, 1, r, r));
+
case INDEX_op_add2_i64:
case INDEX_op_sub2_i64:
- return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r);
+ return (s390_facilities & FACILITY_EXT_IMM
+ ? C_O2_I4(r, r, 0, 1, rA, r)
+ : C_O2_I4(r, r, 0, 1, r, r));
default:
- break;
+ g_assert_not_reached();
}
- return NULL;
}
static void query_s390_facilities(void)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 20/22] tcg/sparc: Convert to tcg-target-conset.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (18 preceding siblings ...)
2020-12-23 6:02 ` [PATCH 19/22] tcg/s390: " Richard Henderson
@ 2020-12-23 6:02 ` Richard Henderson
2020-12-23 6:02 ` [PATCH 21/22] tcg/tci: " Richard Henderson
` (2 subsequent siblings)
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:02 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/sparc/tcg-target-conset.h | 27 +++++++++++++
tcg/sparc/tcg-target.h | 1 +
tcg/sparc/tcg-target.c.inc | 75 +++++++++++------------------------
3 files changed, 51 insertions(+), 52 deletions(-)
create mode 100644 tcg/sparc/tcg-target-conset.h
diff --git a/tcg/sparc/tcg-target-conset.h b/tcg/sparc/tcg-target-conset.h
new file mode 100644
index 0000000000..fe7324af9a
--- /dev/null
+++ b/tcg/sparc/tcg-target-conset.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Sparc target-specific constaint sets.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(rZ, r)
+C_O0_I2(RZ, r)
+C_O0_I2(rZ, rJ)
+C_O0_I2(RZ, RJ)
+C_O0_I2(sZ, A)
+C_O0_I2(SZ, A)
+C_O1_I1(r, A)
+C_O1_I1(R, A)
+C_O1_I1(r, r)
+C_O1_I1(r, R)
+C_O1_I1(R, r)
+C_O1_I1(R, R)
+C_O1_I2(R, R, R)
+C_O1_I2(r, rZ, rJ)
+C_O1_I2(R, RZ, RJ)
+C_O1_I4(r, rZ, rJ, rI, 0)
+C_O1_I4(R, RZ, RJ, RI, 0)
+C_O2_I2(r, r, rZ, rJ)
+C_O2_I4(R, R, RZ, RZ, RJ, RI)
+C_O2_I4(r, r, rZ, rZ, rJ, rJ)
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 633841ebf2..1304c225b1 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -179,5 +179,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index c92742aaec..c225bdd7bd 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -1555,40 +1555,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static int tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } };
- static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } };
- static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } };
- static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } };
- static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } };
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } };
- static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } };
- static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } };
- static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } };
- static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } };
- static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } };
- static const TCGTargetOpDef r_rZ_rJ
- = { .args_ct_str = { "r", "rZ", "rJ" } };
- static const TCGTargetOpDef R_RZ_RJ
- = { .args_ct_str = { "R", "RZ", "RJ" } };
- static const TCGTargetOpDef r_r_rZ_rJ
- = { .args_ct_str = { "r", "r", "rZ", "rJ" } };
- static const TCGTargetOpDef movc_32
- = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } };
- static const TCGTargetOpDef movc_64
- = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } };
- static const TCGTargetOpDef add2_32
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } };
- static const TCGTargetOpDef add2_64
- = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
@@ -1597,12 +1568,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ld_i32:
case INDEX_op_neg_i32:
case INDEX_op_not_i32:
- return &r_r;
+ return C_O1_I1(r, r);
case INDEX_op_st8_i32:
case INDEX_op_st16_i32:
case INDEX_op_st_i32:
- return &rZ_r;
+ return C_O0_I2(rZ, r);
case INDEX_op_add_i32:
case INDEX_op_mul_i32:
@@ -1618,18 +1589,18 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
case INDEX_op_setcond_i32:
- return &r_rZ_rJ;
+ return C_O1_I2(r, rZ, rJ);
case INDEX_op_brcond_i32:
- return &rZ_rJ;
+ return C_O0_I2(rZ, rJ);
case INDEX_op_movcond_i32:
- return &movc_32;
+ return C_O1_I4(r, rZ, rJ, rI, 0);
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
- return &add2_32;
+ return C_O2_I4(r, r, rZ, rZ, rJ, rJ);
case INDEX_op_mulu2_i32:
case INDEX_op_muls2_i32:
- return &r_r_rZ_rJ;
+ return C_O2_I2(r, r, rZ, rJ);
case INDEX_op_ld8u_i64:
case INDEX_op_ld8s_i64:
@@ -1640,13 +1611,13 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ld_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
- return &R_r;
+ return C_O1_I1(R, r);
case INDEX_op_st8_i64:
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
- return &RZ_r;
+ return C_O0_I2(RZ, r);
case INDEX_op_add_i64:
case INDEX_op_mul_i64:
@@ -1662,39 +1633,39 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_shr_i64:
case INDEX_op_sar_i64:
case INDEX_op_setcond_i64:
- return &R_RZ_RJ;
+ return C_O1_I2(R, RZ, RJ);
case INDEX_op_neg_i64:
case INDEX_op_not_i64:
case INDEX_op_ext32s_i64:
case INDEX_op_ext32u_i64:
- return &R_R;
+ return C_O1_I1(R, R);
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
- return &r_R;
+ return C_O1_I1(r, R);
case INDEX_op_brcond_i64:
- return &RZ_RJ;
+ return C_O0_I2(RZ, RJ);
case INDEX_op_movcond_i64:
- return &movc_64;
+ return C_O1_I4(R, RZ, RJ, RI, 0);
case INDEX_op_add2_i64:
case INDEX_op_sub2_i64:
- return &add2_64;
+ return C_O2_I4(R, R, RZ, RZ, RJ, RI);
case INDEX_op_muluh_i64:
- return &R_R_R;
+ return C_O1_I2(R, R, R);
case INDEX_op_qemu_ld_i32:
- return &r_A;
+ return C_O1_I1(r, A);
case INDEX_op_qemu_ld_i64:
- return &R_A;
+ return C_O1_I1(R, A);
case INDEX_op_qemu_st_i32:
- return &sZ_A;
+ return C_O0_I2(sZ, A);
case INDEX_op_qemu_st_i64:
- return &SZ_A;
+ return C_O0_I2(SZ, A);
default:
- return NULL;
+ g_assert_not_reached();
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 21/22] tcg/tci: Convert to tcg-target-conset.h
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (19 preceding siblings ...)
2020-12-23 6:02 ` [PATCH 20/22] tcg/sparc: " Richard Henderson
@ 2020-12-23 6:02 ` Richard Henderson
2020-12-23 6:02 ` [PATCH 22/22] tcg: Remove TCG_TARGET_CONSET_H Richard Henderson
2020-12-23 6:33 ` [PATCH 00/22] tcg: backend constraints cleanup no-reply
22 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:02 UTC (permalink / raw)
To: qemu-devel
This does require finishing the conversion to tcg_target_op_def.
Remove quite a lot of ifdefs, since we can reference opcodes
even if they are not implemented.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target-conset.h | 20 +++
tcg/tci/tcg-target.h | 2 +
tcg/tci/tcg-target.c.inc | 343 +++++++++++++-----------------------
3 files changed, 147 insertions(+), 218 deletions(-)
create mode 100644 tcg/tci/tcg-target-conset.h
diff --git a/tcg/tci/tcg-target-conset.h b/tcg/tci/tcg-target-conset.h
new file mode 100644
index 0000000000..efcefab37e
--- /dev/null
+++ b/tcg/tci/tcg-target-conset.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * TCI target-specific constaint sets.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O0_I3(r, r, r)
+C_O0_I4(r, r, ri, ri)
+C_O0_I4(r, r, r, r)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, r)
+C_O1_I2(r, ri, ri)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, ri)
+C_O1_I4(r, r, r, ri, ri)
+C_O2_I1(r, r, r)
+C_O2_I2(r, r, r, r)
+C_O2_I4(r, r, r, r, r, r)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 8c1c1d265d..42b84a0e87 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -210,4 +210,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
/* no need to flush icache explicitly */
}
+#define TCG_TARGET_CONSET_H
+
#endif /* TCG_TARGET_H */
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 9ac6da2e21..f9fb6cb399 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -37,236 +37,143 @@
/* Bitfield n...m (in 32 bit value). */
#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
-/* Macros used in tcg_target_op_defs. */
-#define R "r"
-#define RI "ri"
-#if TCG_TARGET_REG_BITS == 32
-# define R64 "r", "r"
-#else
-# define R64 "r"
-#endif
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-# define L "r", "r"
-# define S "r", "r"
-#else
-# define L "r"
-# define S "r"
-#endif
+static int tcg_target_op_def(TCGOpcode op)
+{
+ switch (op) {
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld_i32:
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld_i64:
+ case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
+ case INDEX_op_neg_i32:
+ case INDEX_op_neg_i64:
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext8u_i32:
+ case INDEX_op_ext8u_i64:
+ case INDEX_op_ext16u_i32:
+ case INDEX_op_ext16u_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
+ return C_O1_I1(r, r);
-/* TODO: documentation. */
-static const TCGTargetOpDef tcg_target_op_defs[] = {
- { INDEX_op_exit_tb, { NULL } },
- { INDEX_op_goto_tb, { NULL } },
- { INDEX_op_br, { NULL } },
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ return C_O0_I2(r, r);
- { INDEX_op_ld8u_i32, { R, R } },
- { INDEX_op_ld8s_i32, { R, R } },
- { INDEX_op_ld16u_i32, { R, R } },
- { INDEX_op_ld16s_i32, { R, R } },
- { INDEX_op_ld_i32, { R, R } },
- { INDEX_op_st8_i32, { R, R } },
- { INDEX_op_st16_i32, { R, R } },
- { INDEX_op_st_i32, { R, R } },
+ case INDEX_op_div_i32:
+ case INDEX_op_div_i64:
+ case INDEX_op_divu_i32:
+ case INDEX_op_divu_i64:
+ case INDEX_op_rem_i32:
+ case INDEX_op_rem_i64:
+ case INDEX_op_remu_i32:
+ case INDEX_op_remu_i64:
+ return C_O1_I2(r, r, r);
- { INDEX_op_add_i32, { R, RI, RI } },
- { INDEX_op_sub_i32, { R, RI, RI } },
- { INDEX_op_mul_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_div_i32
- { INDEX_op_div_i32, { R, R, R } },
- { INDEX_op_divu_i32, { R, R, R } },
- { INDEX_op_rem_i32, { R, R, R } },
- { INDEX_op_remu_i32, { R, R, R } },
-#elif TCG_TARGET_HAS_div2_i32
- { INDEX_op_div2_i32, { R, R, "0", "1", R } },
- { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
-#endif
- /* TODO: Does R, RI, RI result in faster code than R, R, RI?
- If both operands are constants, we can optimize. */
- { INDEX_op_and_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_andc_i32
- { INDEX_op_andc_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_eqv_i32
- { INDEX_op_eqv_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nand_i32
- { INDEX_op_nand_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nor_i32
- { INDEX_op_nor_i32, { R, RI, RI } },
-#endif
- { INDEX_op_or_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_orc_i32
- { INDEX_op_orc_i32, { R, RI, RI } },
-#endif
- { INDEX_op_xor_i32, { R, RI, RI } },
- { INDEX_op_shl_i32, { R, RI, RI } },
- { INDEX_op_shr_i32, { R, RI, RI } },
- { INDEX_op_sar_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_rot_i32
- { INDEX_op_rotl_i32, { R, RI, RI } },
- { INDEX_op_rotr_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_deposit_i32
- { INDEX_op_deposit_i32, { R, "0", R } },
-#endif
+ case INDEX_op_add_i32:
+ case INDEX_op_add_i64:
+ case INDEX_op_sub_i32:
+ case INDEX_op_sub_i64:
+ case INDEX_op_mul_i32:
+ case INDEX_op_mul_i64:
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ case INDEX_op_andc_i32:
+ case INDEX_op_andc_i64:
+ case INDEX_op_eqv_i32:
+ case INDEX_op_eqv_i64:
+ case INDEX_op_nand_i32:
+ case INDEX_op_nand_i64:
+ case INDEX_op_nor_i32:
+ case INDEX_op_nor_i64:
+ case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
+ case INDEX_op_orc_i32:
+ case INDEX_op_orc_i64:
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
+ case INDEX_op_shl_i32:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i32:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i32:
+ case INDEX_op_sar_i64:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotl_i64:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_rotr_i64:
+ /* TODO: Does R, RI, RI result in faster code than R, R, RI? */
+ return C_O1_I2(r, ri, ri);
- { INDEX_op_brcond_i32, { R, RI } },
+ case INDEX_op_deposit_i32:
+ case INDEX_op_deposit_i64:
+ return C_O1_I2(r, 0, r);
- { INDEX_op_setcond_i32, { R, R, RI } },
-#if TCG_TARGET_REG_BITS == 64
- { INDEX_op_setcond_i64, { R, R, RI } },
-#endif /* TCG_TARGET_REG_BITS == 64 */
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ return C_O0_I2(r, ri);
+
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ return C_O1_I2(r, r, ri);
#if TCG_TARGET_REG_BITS == 32
/* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
- { INDEX_op_add2_i32, { R, R, R, R, R, R } },
- { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
- { INDEX_op_brcond2_i32, { R, R, RI, RI } },
- { INDEX_op_mulu2_i32, { R, R, R, R } },
- { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
+ case INDEX_op_add2_i32:
+ case INDEX_op_sub2_i32:
+ return C_O2_I4(r, r, r, r, r, r);
+ case INDEX_op_brcond2_i32:
+ return C_O0_I4(r, r, ri, ri);
+ case INDEX_op_mulu2_i32:
+ return C_O2_I2(r, r, r, r);
+ case INDEX_op_setcond2_i32
+ return C_O1_I4(r, r, r, ri, ri);
#endif
-#if TCG_TARGET_HAS_not_i32
- { INDEX_op_not_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_neg_i32
- { INDEX_op_neg_i32, { R, R } },
-#endif
+ case INDEX_op_qemu_ld_i32:
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O1_I1(r, r)
+ : C_O1_I2(r, r, r));
+ case INDEX_op_qemu_ld_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, r)
+ : C_O2_I2(r, r, r, r));
+ case INDEX_op_qemu_st_i32:
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O0_I2(r, r)
+ : C_O0_I3(r, r, r));
+ case INDEX_op_qemu_st_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(r, r, r)
+ : C_O0_I4(r, r, r, r));
-#if TCG_TARGET_REG_BITS == 64
- { INDEX_op_ld8u_i64, { R, R } },
- { INDEX_op_ld8s_i64, { R, R } },
- { INDEX_op_ld16u_i64, { R, R } },
- { INDEX_op_ld16s_i64, { R, R } },
- { INDEX_op_ld32u_i64, { R, R } },
- { INDEX_op_ld32s_i64, { R, R } },
- { INDEX_op_ld_i64, { R, R } },
-
- { INDEX_op_st8_i64, { R, R } },
- { INDEX_op_st16_i64, { R, R } },
- { INDEX_op_st32_i64, { R, R } },
- { INDEX_op_st_i64, { R, R } },
-
- { INDEX_op_add_i64, { R, RI, RI } },
- { INDEX_op_sub_i64, { R, RI, RI } },
- { INDEX_op_mul_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_div_i64
- { INDEX_op_div_i64, { R, R, R } },
- { INDEX_op_divu_i64, { R, R, R } },
- { INDEX_op_rem_i64, { R, R, R } },
- { INDEX_op_remu_i64, { R, R, R } },
-#elif TCG_TARGET_HAS_div2_i64
- { INDEX_op_div2_i64, { R, R, "0", "1", R } },
- { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
-#endif
- { INDEX_op_and_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_andc_i64
- { INDEX_op_andc_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_eqv_i64
- { INDEX_op_eqv_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nand_i64
- { INDEX_op_nand_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nor_i64
- { INDEX_op_nor_i64, { R, RI, RI } },
-#endif
- { INDEX_op_or_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_orc_i64
- { INDEX_op_orc_i64, { R, RI, RI } },
-#endif
- { INDEX_op_xor_i64, { R, RI, RI } },
- { INDEX_op_shl_i64, { R, RI, RI } },
- { INDEX_op_shr_i64, { R, RI, RI } },
- { INDEX_op_sar_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_rot_i64
- { INDEX_op_rotl_i64, { R, RI, RI } },
- { INDEX_op_rotr_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_deposit_i64
- { INDEX_op_deposit_i64, { R, "0", R } },
-#endif
- { INDEX_op_brcond_i64, { R, RI } },
-
-#if TCG_TARGET_HAS_ext8s_i64
- { INDEX_op_ext8s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16s_i64
- { INDEX_op_ext16s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext32s_i64
- { INDEX_op_ext32s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext8u_i64
- { INDEX_op_ext8u_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16u_i64
- { INDEX_op_ext16u_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext32u_i64
- { INDEX_op_ext32u_i64, { R, R } },
-#endif
- { INDEX_op_ext_i32_i64, { R, R } },
- { INDEX_op_extu_i32_i64, { R, R } },
-#if TCG_TARGET_HAS_bswap16_i64
- { INDEX_op_bswap16_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap32_i64
- { INDEX_op_bswap32_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap64_i64
- { INDEX_op_bswap64_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_not_i64
- { INDEX_op_not_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_neg_i64
- { INDEX_op_neg_i64, { R, R } },
-#endif
-#endif /* TCG_TARGET_REG_BITS == 64 */
-
- { INDEX_op_qemu_ld_i32, { R, L } },
- { INDEX_op_qemu_ld_i64, { R64, L } },
-
- { INDEX_op_qemu_st_i32, { R, S } },
- { INDEX_op_qemu_st_i64, { R64, S } },
-
-#if TCG_TARGET_HAS_ext8s_i32
- { INDEX_op_ext8s_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16s_i32
- { INDEX_op_ext16s_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext8u_i32
- { INDEX_op_ext8u_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16u_i32
- { INDEX_op_ext16u_i32, { R, R } },
-#endif
-
-#if TCG_TARGET_HAS_bswap16_i32
- { INDEX_op_bswap16_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap32_i32
- { INDEX_op_bswap32_i32, { R, R } },
-#endif
-
- { INDEX_op_mb, { } },
- { -1 },
-};
-
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-{
- int i, n = ARRAY_SIZE(tcg_target_op_defs);
-
- for (i = 0; i < n; ++i) {
- if (tcg_target_op_defs[i].op == op) {
- return &tcg_target_op_defs[i];
- }
+ default:
+ g_assert_not_reached();
}
- return NULL;
}
static const int tcg_target_reg_alloc_order[] = {
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 22/22] tcg: Remove TCG_TARGET_CONSET_H
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (20 preceding siblings ...)
2020-12-23 6:02 ` [PATCH 21/22] tcg/tci: " Richard Henderson
@ 2020-12-23 6:02 ` Richard Henderson
2021-01-07 17:31 ` Alistair Francis
2020-12-23 6:33 ` [PATCH 00/22] tcg: backend constraints cleanup no-reply
22 siblings, 1 reply; 34+ messages in thread
From: Richard Henderson @ 2020-12-23 6:02 UTC (permalink / raw)
To: qemu-devel
All backends have now been converted to tcg-target-conset.h,
so we can remove the fallback code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/tcg-target.h | 1 -
tcg/i386/tcg-target.h | 1 -
tcg/mips/tcg-target.h | 1 -
tcg/ppc/tcg-target.h | 1 -
tcg/riscv/tcg-target.h | 1 -
tcg/s390/tcg-target.h | 1 -
tcg/sparc/tcg-target.h | 1 -
tcg/tci/tcg-target.h | 2 --
tcg/tcg.c | 13 -------------
10 files changed, 23 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index a81f6dadf9..663dd0b95e 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -159,6 +159,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CONSET_H
#endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 918f09239a..17e771374d 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -146,6 +146,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 74a2566900..abd4ac7fc0 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -235,6 +235,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 688d691cda..c6b091d849 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -217,6 +217,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#ifdef CONFIG_SOFTMMU
#define TCG_TARGET_NEED_LDST_LABELS
#endif
-#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index c958faffb7..be10363956 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -185,6 +185,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index a357962e01..032439d806 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -175,6 +175,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_POOL_LABELS
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
-#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 78277a8d07..63c8797bd3 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -162,6 +162,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 1304c225b1..633841ebf2 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -179,6 +179,5 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CONSET_H
#endif
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 42b84a0e87..8c1c1d265d 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -210,6 +210,4 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
/* no need to flush icache explicitly */
}
-#define TCG_TARGET_CONSET_H
-
#endif /* TCG_TARGET_H */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index c58d728ca5..dd5b045d88 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -68,11 +68,7 @@
/* Forward declarations for functions declared in tcg-target.c.inc and
used here. */
static void tcg_target_init(TCGContext *s);
-#ifdef TCG_TARGET_CONSET_H
static int tcg_target_op_def(TCGOpcode);
-#else
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
-#endif
static void tcg_target_qemu_prologue(TCGContext *s);
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend);
@@ -344,7 +340,6 @@ static void set_jmp_reset_offset(TCGContext *s, int which)
s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
}
-#ifdef TCG_TARGET_CONSET_H
#define C_PFX1(P, A) P##A
#define C_PFX2(P, A, B) P##A##_##B
#define C_PFX3(P, A, B, C) P##A##_##B##_##C
@@ -457,8 +452,6 @@ static const TCGTargetOpDef constraint_sets[] = {
#define C_O2_I4(O1, O2, I1, I2, I3, I4) \
C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
-#endif /* TCG_TARGET_CONSET_H */
-
#include "tcg-target.c.inc"
/* compare a pointer @ptr and a tb_tc @s */
@@ -2367,16 +2360,10 @@ static void process_op_defs(TCGContext *s)
continue;
}
-#ifdef TCG_TARGET_CONSET_H
i = tcg_target_op_def(op);
/* Missing TCGTargetOpDef entry. */
tcg_debug_assert(i >= 0 && i < ARRAY_SIZE(constraint_sets));
tdefs = &constraint_sets[i];
-#else
- tdefs = tcg_target_op_def(op);
- /* Missing TCGTargetOpDef entry. */
- tcg_debug_assert(tdefs != NULL);
-#endif
for (i = 0; i < nb_args; i++) {
const char *ct_str = tdefs->args_ct_str[i];
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 00/22] tcg: backend constraints cleanup
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
` (21 preceding siblings ...)
2020-12-23 6:02 ` [PATCH 22/22] tcg: Remove TCG_TARGET_CONSET_H Richard Henderson
@ 2020-12-23 6:33 ` no-reply
22 siblings, 0 replies; 34+ messages in thread
From: no-reply @ 2020-12-23 6:33 UTC (permalink / raw)
To: richard.henderson; +Cc: qemu-devel
Patchew URL: https://patchew.org/QEMU/20201223060204.576856-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201223060204.576856-1-richard.henderson@linaro.org
Subject: [PATCH 00/22] tcg: backend constraints cleanup
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20201223060204.576856-1-richard.henderson@linaro.org -> patchew/20201223060204.576856-1-richard.henderson@linaro.org
Switched to a new branch 'test'
8b65955 tcg: Remove TCG_TARGET_CONSET_H
3a9c766 tcg/tci: Convert to tcg-target-conset.h
7e3d876 tcg/sparc: Convert to tcg-target-conset.h
759b112 tcg/s390: Convert to tcg-target-conset.h
c9e097a tcg/riscv: Convert to tcg-target-conset.h
6b86815 tcg/ppc: Convert to tcg-target-conset.h
5b5b4b5 tcg/mips: Convert to tcg-target-conset.h
8664281 tcg/arm: Convert to tcg-target-conset.h
80ce8a8 tcg/aarch64: Convert to tcg-target-conset.h
fbe649c tcg: Split out constraint sets to tcg-target-conset.h
c3f9af7 tcg: Remove TCG_TARGET_CONSTR_H
758fd8b tcg/sparc: Convert to tcg-target-constr.h
0c2e793 tcg/s390: Convert to tcg-target-constr.h
9c409ea tcg/riscv: Convert to tcg-target-constr.h
54c599f tcg/mips: Convert to tcg-target-constr.h
7231211 tcg/tci: Convert to tcg-target-constr.h
c641c2e tcg/ppc: Convert to tcg-target-constr.h
dc946e3 tcg/aarch64: Convert to tcg-target-constr.h
8cef9ef tcg/arm: Convert to tcg-target-constr.h
00f2363 tcg: Split out target constraints to tcg-target-constr.h
a23958f tcg/i386: Move constraint type check to tcg_target_const_match
940927d tcg/tci: Drop L and S constraints
=== OUTPUT BEGIN ===
1/22 Checking commit 940927ddc8e8 (tcg/tci: Drop L and S constraints)
2/22 Checking commit a23958fc7bde (tcg/i386: Move constraint type check to tcg_target_const_match)
3/22 Checking commit 00f236316045 (tcg: Split out target constraints to tcg-target-constr.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16:
new file mode 100644
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#187: FILE: tcg/tcg.c:2295:
+#define CONST(CASE, MASK) \
+ case CASE: def->args_ct[i].ct |= MASK; ct_str++; break;
ERROR: trailing statements should be on next line
#188: FILE: tcg/tcg.c:2296:
+ case CASE: def->args_ct[i].ct |= MASK; ct_str++; break;
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#189: FILE: tcg/tcg.c:2297:
+#define REGS(CASE, MASK) \
+ case CASE: def->args_ct[i].regs |= MASK; ct_str++; break;
ERROR: trailing statements should be on next line
#190: FILE: tcg/tcg.c:2298:
+ case CASE: def->args_ct[i].regs |= MASK; ct_str++; break;
total: 4 errors, 1 warnings, 177 lines checked
Patch 3/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/22 Checking commit 8cef9ef1733f (tcg/arm: Convert to tcg-target-constr.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 103 lines checked
Patch 4/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/22 Checking commit dc946e3eef6d (tcg/aarch64: Convert to tcg-target-constr.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 85 lines checked
Patch 5/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/22 Checking commit c641c2e55a80 (tcg/ppc: Convert to tcg-target-constr.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 107 lines checked
Patch 6/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/22 Checking commit 72312113a5a2 (tcg/tci: Convert to tcg-target-constr.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 35 lines checked
Patch 7/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/22 Checking commit 54c599f39de4 (tcg/mips: Convert to tcg-target-constr.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 99 lines checked
Patch 8/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/22 Checking commit 9c409ea55307 (tcg/riscv: Convert to tcg-target-constr.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 75 lines checked
Patch 9/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/22 Checking commit 0c2e793db503 (tcg/s390: Convert to tcg-target-constr.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 67 lines checked
Patch 10/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/22 Checking commit 758fd8bea2ca (tcg/sparc: Convert to tcg-target-constr.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 67 lines checked
Patch 11/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/22 Checking commit c3f9af77c862 (tcg: Remove TCG_TARGET_CONSTR_H)
13/22 Checking commit fbe649c12074 (tcg: Split out constraint sets to tcg-target-conset.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#14:
new file mode 100644
ERROR: Macros with complex values should be enclosed in parenthesis
#423: FILE: tcg/tcg.c:357:
+#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1),
ERROR: Macros with complex values should be enclosed in parenthesis
#424: FILE: tcg/tcg.c:358:
+#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2),
ERROR: Macros with complex values should be enclosed in parenthesis
#425: FILE: tcg/tcg.c:359:
+#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3),
ERROR: Macros with complex values should be enclosed in parenthesis
#426: FILE: tcg/tcg.c:360:
+#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4),
ERROR: Macros with complex values should be enclosed in parenthesis
#428: FILE: tcg/tcg.c:362:
+#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1),
ERROR: Macros with complex values should be enclosed in parenthesis
#429: FILE: tcg/tcg.c:363:
+#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2),
ERROR: Macros with complex values should be enclosed in parenthesis
#430: FILE: tcg/tcg.c:364:
+#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3),
ERROR: Macros with complex values should be enclosed in parenthesis
#431: FILE: tcg/tcg.c:365:
+#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
ERROR: Macros with complex values should be enclosed in parenthesis
#433: FILE: tcg/tcg.c:367:
+#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2),
ERROR: Macros with complex values should be enclosed in parenthesis
#435: FILE: tcg/tcg.c:369:
+#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1),
ERROR: Macros with complex values should be enclosed in parenthesis
#436: FILE: tcg/tcg.c:370:
+#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2),
ERROR: Macros with complex values should be enclosed in parenthesis
#437: FILE: tcg/tcg.c:371:
+#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3),
ERROR: Macros with complex values should be enclosed in parenthesis
#438: FILE: tcg/tcg.c:372:
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) \
+ C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4),
total: 13 errors, 1 warnings, 506 lines checked
Patch 13/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
14/22 Checking commit 80ce8a8cce5c (tcg/aarch64: Convert to tcg-target-conset.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 219 lines checked
Patch 14/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/22 Checking commit 86642819eb3e (tcg/arm: Convert to tcg-target-conset.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 187 lines checked
Patch 15/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
16/22 Checking commit 5b5b4b527edd (tcg/mips: Convert to tcg-target-conset.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 203 lines checked
Patch 16/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/22 Checking commit 6b8681521e36 (tcg/ppc: Convert to tcg-target-conset.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 265 lines checked
Patch 17/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/22 Checking commit c9e097afd8a3 (tcg/riscv: Convert to tcg-target-conset.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 175 lines checked
Patch 18/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
19/22 Checking commit 759b11287ddc (tcg/s390: Convert to tcg-target-conset.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 223 lines checked
Patch 19/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/22 Checking commit 7e3d876c1fff (tcg/sparc: Convert to tcg-target-conset.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
total: 0 errors, 1 warnings, 178 lines checked
Patch 20/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/22 Checking commit 3a9c766171ee (tcg/tci: Convert to tcg-target-conset.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15:
new file mode 100644
total: 0 errors, 1 warnings, 387 lines checked
Patch 21/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
22/22 Checking commit 8b65955e39e2 (tcg: Remove TCG_TARGET_CONSET_H)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20201223060204.576856-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 09/22] tcg/riscv: Convert to tcg-target-constr.h
2020-12-23 6:01 ` [PATCH 09/22] tcg/riscv: " Richard Henderson
@ 2021-01-07 17:26 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2021-01-07 17:26 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, Dec 22, 2020 at 10:13 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tcg/riscv/tcg-target-constr.h | 24 +++++++++++++++++++++
> tcg/riscv/tcg-target.h | 1 +
> tcg/riscv/tcg-target.c.inc | 39 -----------------------------------
> 3 files changed, 25 insertions(+), 39 deletions(-)
> create mode 100644 tcg/riscv/tcg-target-constr.h
>
> diff --git a/tcg/riscv/tcg-target-constr.h b/tcg/riscv/tcg-target-constr.h
> new file mode 100644
> index 0000000000..5daf2e6a5b
> --- /dev/null
> +++ b/tcg/riscv/tcg-target-constr.h
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * RISC-V target-specific operand constaints.
> + * Copyright (c) 2020 Linaro
> + */
> +
> +#define ALL_GENERAL_REGS 0xffffffffu
> +
> +#ifdef CONFIG_SOFTMMU
> +#define ALL_QLDST_REGS \
> + (ALL_GENERAL_REGS & ~((1 << TCG_REG_A0) | (1 << TCG_REG_A1) | \
> + (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | \
> + (1 << TCG_REG_A5)))
> +#else
> +#define ALL_QLDST_REGS ALL_GENERAL_REGS
> +#endif
> +
> +REGS('r', ALL_GENERAL_REGS)
> +REGS('L', ALL_QLDST_REGS)
> +
> +CONST('I', TCG_CT_CONST_S12)
> +CONST('N', TCG_CT_CONST_N12)
> +CONST('M', TCG_CT_CONST_M12)
> +CONST('Z', TCG_CT_CONST_ZERO)
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index 032439d806..ff8ff43a46 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -175,5 +175,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
> #define TCG_TARGET_NEED_POOL_LABELS
>
> #define TCG_TARGET_HAS_MEMORY_BSWAP 0
> +#define TCG_TARGET_CONSTR_H
>
> #endif
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index d536f3ccc1..33047c1951 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -131,45 +131,6 @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
> }
> }
>
> -/* parse target specific constraints */
> -static const char *target_parse_constraint(TCGArgConstraint *ct,
> - const char *ct_str, TCGType type)
> -{
> - switch (*ct_str++) {
> - case 'r':
> - ct->regs = 0xffffffff;
> - break;
> - case 'L':
> - /* qemu_ld/qemu_st constraint */
> - ct->regs = 0xffffffff;
> - /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
> -#if defined(CONFIG_SOFTMMU)
> - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
> - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
> - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
> - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
> - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
> -#endif
> - break;
> - case 'I':
> - ct->ct |= TCG_CT_CONST_S12;
> - break;
> - case 'N':
> - ct->ct |= TCG_CT_CONST_N12;
> - break;
> - case 'M':
> - ct->ct |= TCG_CT_CONST_M12;
> - break;
> - case 'Z':
> - /* we can use a zero immediate as a zero register argument. */
> - ct->ct |= TCG_CT_CONST_ZERO;
> - break;
> - default:
> - return NULL;
> - }
> - return ct_str;
> -}
> -
> /* test if a constant matches the constraint */
> static int tcg_target_const_match(tcg_target_long val, TCGType type,
> const TCGArgConstraint *arg_ct)
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 12/22] tcg: Remove TCG_TARGET_CONSTR_H
2020-12-23 6:01 ` [PATCH 12/22] tcg: Remove TCG_TARGET_CONSTR_H Richard Henderson
@ 2021-01-07 17:27 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2021-01-07 17:27 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, Dec 22, 2020 at 10:21 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> All backends have now been converted to tcg-target-constr.h,
> so we can remove the fallback code.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tcg/aarch64/tcg-target.h | 1 -
> tcg/arm/tcg-target.h | 1 -
> tcg/i386/tcg-target.h | 1 -
> tcg/mips/tcg-target.h | 1 -
> tcg/ppc/tcg-target.h | 1 -
> tcg/riscv/tcg-target.h | 1 -
> tcg/s390/tcg-target.h | 1 -
> tcg/sparc/tcg-target.h | 1 -
> tcg/tci/tcg-target.h | 2 --
> tcg/tcg.c | 16 ----------------
> 10 files changed, 26 deletions(-)
>
> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
> index ca7af5a589..663dd0b95e 100644
> --- a/tcg/aarch64/tcg-target.h
> +++ b/tcg/aarch64/tcg-target.h
> @@ -159,6 +159,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
> #define TCG_TARGET_NEED_LDST_LABELS
> #endif
> #define TCG_TARGET_NEED_POOL_LABELS
> -#define TCG_TARGET_CONSTR_H
>
> #endif /* AARCH64_TCG_TARGET_H */
> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
> index 6f058d6d9b..17e771374d 100644
> --- a/tcg/arm/tcg-target.h
> +++ b/tcg/arm/tcg-target.h
> @@ -146,6 +146,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
> #define TCG_TARGET_NEED_LDST_LABELS
> #endif
> #define TCG_TARGET_NEED_POOL_LABELS
> -#define TCG_TARGET_CONSTR_H
>
> #endif
> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
> index 7c405e166d..abd4ac7fc0 100644
> --- a/tcg/i386/tcg-target.h
> +++ b/tcg/i386/tcg-target.h
> @@ -235,6 +235,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
> #define TCG_TARGET_NEED_LDST_LABELS
> #endif
> #define TCG_TARGET_NEED_POOL_LABELS
> -#define TCG_TARGET_CONSTR_H
>
> #endif
> diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
> index f4a79bcad1..c6b091d849 100644
> --- a/tcg/mips/tcg-target.h
> +++ b/tcg/mips/tcg-target.h
> @@ -217,6 +217,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
> #ifdef CONFIG_SOFTMMU
> #define TCG_TARGET_NEED_LDST_LABELS
> #endif
> -#define TCG_TARGET_CONSTR_H
>
> #endif
> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
> index 78d3470f3c..be10363956 100644
> --- a/tcg/ppc/tcg-target.h
> +++ b/tcg/ppc/tcg-target.h
> @@ -185,6 +185,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
> #define TCG_TARGET_NEED_LDST_LABELS
> #endif
> #define TCG_TARGET_NEED_POOL_LABELS
> -#define TCG_TARGET_CONSTR_H
>
> #endif
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index ff8ff43a46..032439d806 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -175,6 +175,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
> #define TCG_TARGET_NEED_POOL_LABELS
>
> #define TCG_TARGET_HAS_MEMORY_BSWAP 0
> -#define TCG_TARGET_CONSTR_H
>
> #endif
> diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
> index 3aff3cc572..63c8797bd3 100644
> --- a/tcg/s390/tcg-target.h
> +++ b/tcg/s390/tcg-target.h
> @@ -162,6 +162,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
> #define TCG_TARGET_NEED_LDST_LABELS
> #endif
> #define TCG_TARGET_NEED_POOL_LABELS
> -#define TCG_TARGET_CONSTR_H
>
> #endif
> diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
> index bfee6191b3..633841ebf2 100644
> --- a/tcg/sparc/tcg-target.h
> +++ b/tcg/sparc/tcg-target.h
> @@ -179,6 +179,5 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
> void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
>
> #define TCG_TARGET_NEED_POOL_LABELS
> -#define TCG_TARGET_CONSTR_H
>
> #endif
> diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
> index cd3dee51bb..8c1c1d265d 100644
> --- a/tcg/tci/tcg-target.h
> +++ b/tcg/tci/tcg-target.h
> @@ -210,6 +210,4 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
> /* no need to flush icache explicitly */
> }
>
> -#define TCG_TARGET_CONSTR_H
> -
> #endif /* TCG_TARGET_H */
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index f5b53d739e..2bde926315 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -102,10 +102,6 @@ static void tcg_register_jit_int(void *buf, size_t size,
> __attribute__((unused));
>
> /* Forward declarations for functions declared and used in tcg-target.c.inc. */
> -#ifndef TCG_TARGET_CONSTR_H
> -static const char *target_parse_constraint(TCGArgConstraint *ct,
> - const char *ct_str, TCGType type);
> -#endif
> static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
> intptr_t arg2);
> static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
> @@ -2288,7 +2284,6 @@ static void process_op_defs(TCGContext *s)
> ct_str++;
> break;
>
> -#ifdef TCG_TARGET_CONSTR_H
> /* Include all of the target-specific constraints. */
>
> #undef CONST
> @@ -2304,17 +2299,6 @@ static void process_op_defs(TCGContext *s)
> default:
> /* Typo in TCGTargetOpDef constraint. */
> g_assert_not_reached();
> -#else
> - default:
> - {
> - TCGType type = (def->flags & TCG_OPF_64BIT
> - ? TCG_TYPE_I64 : TCG_TYPE_I32);
> - ct_str = target_parse_constraint(&def->args_ct[i],
> - ct_str, type);
> - /* Typo in TCGTargetOpDef constraint. */
> - tcg_debug_assert(ct_str != NULL);
> - }
> -#endif
> }
> }
> }
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 18/22] tcg/riscv: Convert to tcg-target-conset.h
2020-12-23 6:02 ` [PATCH 18/22] tcg/riscv: " Richard Henderson
@ 2021-01-07 17:30 ` Alistair Francis
2021-01-07 18:08 ` Peter Maydell
1 sibling, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2021-01-07 17:30 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, Dec 22, 2020 at 10:23 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tcg/riscv/tcg-target-conset.h | 25 +++++++++++
> tcg/riscv/tcg-target.h | 1 +
> tcg/riscv/tcg-target.c.inc | 83 ++++++++++-------------------------
> 3 files changed, 49 insertions(+), 60 deletions(-)
> create mode 100644 tcg/riscv/tcg-target-conset.h
>
> diff --git a/tcg/riscv/tcg-target-conset.h b/tcg/riscv/tcg-target-conset.h
> new file mode 100644
> index 0000000000..116dd75db2
> --- /dev/null
> +++ b/tcg/riscv/tcg-target-conset.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * RISC-V target-specific constaint sets.
> + * Copyright (c) 2020 Linaro
> + */
> +
> +C_O0_I1(r)
> +C_O0_I2(LZ, L)
> +C_O0_I2(rZ, r)
> +C_O0_I2(rZ, rZ)
> +C_O0_I3(LZ, L, L)
> +C_O0_I3(LZ, LZ, L)
> +C_O0_I4(LZ, LZ, L, L)
> +C_O0_I4(rZ, rZ, rZ, rZ)
> +C_O1_I1(r, L)
> +C_O1_I1(r, r)
> +C_O1_I2(r, L, L)
> +C_O1_I2(r, r, ri)
> +C_O1_I2(r, r, rI)
> +C_O1_I2(r, rZ, rN)
> +C_O1_I2(r, rZ, rZ)
> +C_O1_I4(r, rZ, rZ, rZ, rZ)
> +C_O2_I1(r, r, L)
> +C_O2_I2(r, r, L, L)
> +C_O2_I4(r, r, rZ, rZ, rM, rM)
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index 032439d806..a357962e01 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -175,5 +175,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
> #define TCG_TARGET_NEED_POOL_LABELS
>
> #define TCG_TARGET_HAS_MEMORY_BSWAP 0
> +#define TCG_TARGET_CONSET_H
>
> #endif
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 33047c1951..d222692704 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -1571,50 +1571,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> }
> }
>
> -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
> +static int tcg_target_op_def(TCGOpcode op)
> {
> - static const TCGTargetOpDef r
> - = { .args_ct_str = { "r" } };
> - static const TCGTargetOpDef r_r
> - = { .args_ct_str = { "r", "r" } };
> - static const TCGTargetOpDef rZ_r
> - = { .args_ct_str = { "rZ", "r" } };
> - static const TCGTargetOpDef rZ_rZ
> - = { .args_ct_str = { "rZ", "rZ" } };
> - static const TCGTargetOpDef rZ_rZ_rZ_rZ
> - = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
> - static const TCGTargetOpDef r_r_ri
> - = { .args_ct_str = { "r", "r", "ri" } };
> - static const TCGTargetOpDef r_r_rI
> - = { .args_ct_str = { "r", "r", "rI" } };
> - static const TCGTargetOpDef r_rZ_rN
> - = { .args_ct_str = { "r", "rZ", "rN" } };
> - static const TCGTargetOpDef r_rZ_rZ
> - = { .args_ct_str = { "r", "rZ", "rZ" } };
> - static const TCGTargetOpDef r_rZ_rZ_rZ_rZ
> - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
> - static const TCGTargetOpDef r_L
> - = { .args_ct_str = { "r", "L" } };
> - static const TCGTargetOpDef r_r_L
> - = { .args_ct_str = { "r", "r", "L" } };
> - static const TCGTargetOpDef r_L_L
> - = { .args_ct_str = { "r", "L", "L" } };
> - static const TCGTargetOpDef r_r_L_L
> - = { .args_ct_str = { "r", "r", "L", "L" } };
> - static const TCGTargetOpDef LZ_L
> - = { .args_ct_str = { "LZ", "L" } };
> - static const TCGTargetOpDef LZ_L_L
> - = { .args_ct_str = { "LZ", "L", "L" } };
> - static const TCGTargetOpDef LZ_LZ_L
> - = { .args_ct_str = { "LZ", "LZ", "L" } };
> - static const TCGTargetOpDef LZ_LZ_L_L
> - = { .args_ct_str = { "LZ", "LZ", "L", "L" } };
> - static const TCGTargetOpDef r_r_rZ_rZ_rM_rM
> - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } };
> -
> switch (op) {
> case INDEX_op_goto_ptr:
> - return &r;
> + return C_O0_I1(r);
>
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8s_i32:
> @@ -1646,7 +1607,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
> case INDEX_op_extrl_i64_i32:
> case INDEX_op_extrh_i64_i32:
> case INDEX_op_ext_i32_i64:
> - return &r_r;
> + return C_O1_I1(r, r);
>
> case INDEX_op_st8_i32:
> case INDEX_op_st16_i32:
> @@ -1655,7 +1616,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
> case INDEX_op_st16_i64:
> case INDEX_op_st32_i64:
> case INDEX_op_st_i64:
> - return &rZ_r;
> + return C_O0_I2(rZ, r);
>
> case INDEX_op_add_i32:
> case INDEX_op_and_i32:
> @@ -1665,11 +1626,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
> case INDEX_op_and_i64:
> case INDEX_op_or_i64:
> case INDEX_op_xor_i64:
> - return &r_r_rI;
> + return C_O1_I2(r, r, rI);
>
> case INDEX_op_sub_i32:
> case INDEX_op_sub_i64:
> - return &r_rZ_rN;
> + return C_O1_I2(r, rZ, rN);
>
> case INDEX_op_mul_i32:
> case INDEX_op_mulsh_i32:
> @@ -1687,7 +1648,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
> case INDEX_op_rem_i64:
> case INDEX_op_remu_i64:
> case INDEX_op_setcond_i64:
> - return &r_rZ_rZ;
> + return C_O1_I2(r, rZ, rZ);
>
> case INDEX_op_shl_i32:
> case INDEX_op_shr_i32:
> @@ -1695,39 +1656,41 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
> case INDEX_op_shl_i64:
> case INDEX_op_shr_i64:
> case INDEX_op_sar_i64:
> - return &r_r_ri;
> + return C_O1_I2(r, r, ri);
>
> case INDEX_op_brcond_i32:
> case INDEX_op_brcond_i64:
> - return &rZ_rZ;
> + return C_O0_I2(rZ, rZ);
>
> case INDEX_op_add2_i32:
> case INDEX_op_add2_i64:
> case INDEX_op_sub2_i32:
> case INDEX_op_sub2_i64:
> - return &r_r_rZ_rZ_rM_rM;
> + return C_O2_I4(r, r, rZ, rZ, rM, rM);
>
> case INDEX_op_brcond2_i32:
> - return &rZ_rZ_rZ_rZ;
> + return C_O0_I4(rZ, rZ, rZ, rZ);
>
> case INDEX_op_setcond2_i32:
> - return &r_rZ_rZ_rZ_rZ;
> + return C_O1_I4(r, rZ, rZ, rZ, rZ);
>
> case INDEX_op_qemu_ld_i32:
> - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
> + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
> + ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
> case INDEX_op_qemu_st_i32:
> - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L;
> + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
> + ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L));
> case INDEX_op_qemu_ld_i64:
> - return TCG_TARGET_REG_BITS == 64 ? &r_L
> - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
> - : &r_r_L_L;
> + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
> + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
> + : C_O2_I2(r, r, L, L));
> case INDEX_op_qemu_st_i64:
> - return TCG_TARGET_REG_BITS == 64 ? &LZ_L
> - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L
> - : &LZ_LZ_L_L;
> + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L)
> + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L)
> + : C_O0_I4(LZ, LZ, L, L));
>
> default:
> - return NULL;
> + g_assert_not_reached();
> }
> }
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 22/22] tcg: Remove TCG_TARGET_CONSET_H
2020-12-23 6:02 ` [PATCH 22/22] tcg: Remove TCG_TARGET_CONSET_H Richard Henderson
@ 2021-01-07 17:31 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2021-01-07 17:31 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, Dec 22, 2020 at 10:29 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> All backends have now been converted to tcg-target-conset.h,
> so we can remove the fallback code.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tcg/aarch64/tcg-target.h | 1 -
> tcg/arm/tcg-target.h | 1 -
> tcg/i386/tcg-target.h | 1 -
> tcg/mips/tcg-target.h | 1 -
> tcg/ppc/tcg-target.h | 1 -
> tcg/riscv/tcg-target.h | 1 -
> tcg/s390/tcg-target.h | 1 -
> tcg/sparc/tcg-target.h | 1 -
> tcg/tci/tcg-target.h | 2 --
> tcg/tcg.c | 13 -------------
> 10 files changed, 23 deletions(-)
>
> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
> index a81f6dadf9..663dd0b95e 100644
> --- a/tcg/aarch64/tcg-target.h
> +++ b/tcg/aarch64/tcg-target.h
> @@ -159,6 +159,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
> #define TCG_TARGET_NEED_LDST_LABELS
> #endif
> #define TCG_TARGET_NEED_POOL_LABELS
> -#define TCG_TARGET_CONSET_H
>
> #endif /* AARCH64_TCG_TARGET_H */
> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
> index 918f09239a..17e771374d 100644
> --- a/tcg/arm/tcg-target.h
> +++ b/tcg/arm/tcg-target.h
> @@ -146,6 +146,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
> #define TCG_TARGET_NEED_LDST_LABELS
> #endif
> #define TCG_TARGET_NEED_POOL_LABELS
> -#define TCG_TARGET_CONSET_H
>
> #endif
> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
> index 74a2566900..abd4ac7fc0 100644
> --- a/tcg/i386/tcg-target.h
> +++ b/tcg/i386/tcg-target.h
> @@ -235,6 +235,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
> #define TCG_TARGET_NEED_LDST_LABELS
> #endif
> #define TCG_TARGET_NEED_POOL_LABELS
> -#define TCG_TARGET_CONSET_H
>
> #endif
> diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
> index 688d691cda..c6b091d849 100644
> --- a/tcg/mips/tcg-target.h
> +++ b/tcg/mips/tcg-target.h
> @@ -217,6 +217,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
> #ifdef CONFIG_SOFTMMU
> #define TCG_TARGET_NEED_LDST_LABELS
> #endif
> -#define TCG_TARGET_CONSET_H
>
> #endif
> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
> index c958faffb7..be10363956 100644
> --- a/tcg/ppc/tcg-target.h
> +++ b/tcg/ppc/tcg-target.h
> @@ -185,6 +185,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
> #define TCG_TARGET_NEED_LDST_LABELS
> #endif
> #define TCG_TARGET_NEED_POOL_LABELS
> -#define TCG_TARGET_CONSET_H
>
> #endif
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index a357962e01..032439d806 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -175,6 +175,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
> #define TCG_TARGET_NEED_POOL_LABELS
>
> #define TCG_TARGET_HAS_MEMORY_BSWAP 0
> -#define TCG_TARGET_CONSET_H
>
> #endif
> diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
> index 78277a8d07..63c8797bd3 100644
> --- a/tcg/s390/tcg-target.h
> +++ b/tcg/s390/tcg-target.h
> @@ -162,6 +162,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
> #define TCG_TARGET_NEED_LDST_LABELS
> #endif
> #define TCG_TARGET_NEED_POOL_LABELS
> -#define TCG_TARGET_CONSET_H
>
> #endif
> diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
> index 1304c225b1..633841ebf2 100644
> --- a/tcg/sparc/tcg-target.h
> +++ b/tcg/sparc/tcg-target.h
> @@ -179,6 +179,5 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
> void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
>
> #define TCG_TARGET_NEED_POOL_LABELS
> -#define TCG_TARGET_CONSET_H
>
> #endif
> diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
> index 42b84a0e87..8c1c1d265d 100644
> --- a/tcg/tci/tcg-target.h
> +++ b/tcg/tci/tcg-target.h
> @@ -210,6 +210,4 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
> /* no need to flush icache explicitly */
> }
>
> -#define TCG_TARGET_CONSET_H
> -
> #endif /* TCG_TARGET_H */
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index c58d728ca5..dd5b045d88 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -68,11 +68,7 @@
> /* Forward declarations for functions declared in tcg-target.c.inc and
> used here. */
> static void tcg_target_init(TCGContext *s);
> -#ifdef TCG_TARGET_CONSET_H
> static int tcg_target_op_def(TCGOpcode);
> -#else
> -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
> -#endif
> static void tcg_target_qemu_prologue(TCGContext *s);
> static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
> intptr_t value, intptr_t addend);
> @@ -344,7 +340,6 @@ static void set_jmp_reset_offset(TCGContext *s, int which)
> s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
> }
>
> -#ifdef TCG_TARGET_CONSET_H
> #define C_PFX1(P, A) P##A
> #define C_PFX2(P, A, B) P##A##_##B
> #define C_PFX3(P, A, B, C) P##A##_##B##_##C
> @@ -457,8 +452,6 @@ static const TCGTargetOpDef constraint_sets[] = {
> #define C_O2_I4(O1, O2, I1, I2, I3, I4) \
> C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
>
> -#endif /* TCG_TARGET_CONSET_H */
> -
> #include "tcg-target.c.inc"
>
> /* compare a pointer @ptr and a tb_tc @s */
> @@ -2367,16 +2360,10 @@ static void process_op_defs(TCGContext *s)
> continue;
> }
>
> -#ifdef TCG_TARGET_CONSET_H
> i = tcg_target_op_def(op);
> /* Missing TCGTargetOpDef entry. */
> tcg_debug_assert(i >= 0 && i < ARRAY_SIZE(constraint_sets));
> tdefs = &constraint_sets[i];
> -#else
> - tdefs = tcg_target_op_def(op);
> - /* Missing TCGTargetOpDef entry. */
> - tcg_debug_assert(tdefs != NULL);
> -#endif
>
> for (i = 0; i < nb_args; i++) {
> const char *ct_str = tdefs->args_ct_str[i];
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 18/22] tcg/riscv: Convert to tcg-target-conset.h
2020-12-23 6:02 ` [PATCH 18/22] tcg/riscv: " Richard Henderson
2021-01-07 17:30 ` Alistair Francis
@ 2021-01-07 18:08 ` Peter Maydell
2021-01-07 19:01 ` Philippe Mathieu-Daudé
2021-01-07 19:15 ` Richard Henderson
1 sibling, 2 replies; 34+ messages in thread
From: Peter Maydell @ 2021-01-07 18:08 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Wed, 23 Dec 2020 at 06:25, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/riscv/tcg-target-conset.h | 25 +++++++++++
> tcg/riscv/tcg-target.h | 1 +
> tcg/riscv/tcg-target.c.inc | 83 ++++++++++-------------------------
> 3 files changed, 49 insertions(+), 60 deletions(-)
> create mode 100644 tcg/riscv/tcg-target-conset.h
>
> diff --git a/tcg/riscv/tcg-target-conset.h b/tcg/riscv/tcg-target-conset.h
> new file mode 100644
> index 0000000000..116dd75db2
> --- /dev/null
> +++ b/tcg/riscv/tcg-target-conset.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * RISC-V target-specific constaint sets.
"constraint"
> + * Copyright (c) 2020 Linaro
> + */
> +
(Also "conset.h" looks really like a typo for "const.h" which
is kinda confusing :-))
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 18/22] tcg/riscv: Convert to tcg-target-conset.h
2021-01-07 18:08 ` Peter Maydell
@ 2021-01-07 19:01 ` Philippe Mathieu-Daudé
2021-01-07 19:15 ` Richard Henderson
1 sibling, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-07 19:01 UTC (permalink / raw)
To: Peter Maydell, Richard Henderson; +Cc: QEMU Developers
On 1/7/21 7:08 PM, Peter Maydell wrote:
> On Wed, 23 Dec 2020 at 06:25, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> tcg/riscv/tcg-target-conset.h | 25 +++++++++++
>> tcg/riscv/tcg-target.h | 1 +
>> tcg/riscv/tcg-target.c.inc | 83 ++++++++++-------------------------
>> 3 files changed, 49 insertions(+), 60 deletions(-)
>> create mode 100644 tcg/riscv/tcg-target-conset.h
>>
>> diff --git a/tcg/riscv/tcg-target-conset.h b/tcg/riscv/tcg-target-conset.h
>> new file mode 100644
>> index 0000000000..116dd75db2
>> --- /dev/null
>> +++ b/tcg/riscv/tcg-target-conset.h
>> @@ -0,0 +1,25 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * RISC-V target-specific constaint sets.
>
> "constraint"
>
>> + * Copyright (c) 2020 Linaro
>> + */
>> +
>
> (Also "conset.h" looks really like a typo for "const.h" which
> is kinda confusing :-))
Isn't it an abbrev for "constraint sets"?
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 18/22] tcg/riscv: Convert to tcg-target-conset.h
2021-01-07 18:08 ` Peter Maydell
2021-01-07 19:01 ` Philippe Mathieu-Daudé
@ 2021-01-07 19:15 ` Richard Henderson
2021-01-07 19:50 ` Peter Maydell
1 sibling, 1 reply; 34+ messages in thread
From: Richard Henderson @ 2021-01-07 19:15 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On 1/7/21 8:08 AM, Peter Maydell wrote:
> (Also "conset.h" looks really like a typo for "const.h" which
> is kinda confusing :-))
Naming suggestions? :-)
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 18/22] tcg/riscv: Convert to tcg-target-conset.h
2021-01-07 19:15 ` Richard Henderson
@ 2021-01-07 19:50 ` Peter Maydell
0 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2021-01-07 19:50 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Thu, 7 Jan 2021 at 19:15, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 1/7/21 8:08 AM, Peter Maydell wrote:
> > (Also "conset.h" looks really like a typo for "const.h" which
> > is kinda confusing :-))
>
> Naming suggestions? :-)
tcg-target-con-set.h ?
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 13/22] tcg: Split out constraint sets to tcg-target-conset.h
2020-12-23 6:01 ` [PATCH 13/22] tcg: Split out constraint sets to tcg-target-conset.h Richard Henderson
@ 2021-01-12 11:55 ` Peter Maydell
0 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2021-01-12 11:55 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Wed, 23 Dec 2020 at 06:20, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This exports the constraint sets from tcg_target_op_def to
> a place we will be able to manipulate more in future.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/i386/tcg-target-conset.h | 44 ++++++++
> tcg/i386/tcg-target.h | 1 +
> tcg/tcg.c | 126 +++++++++++++++++++++++
> tcg/i386/tcg-target.c.inc | 189 ++++++++++++-----------------------
> 4 files changed, 236 insertions(+), 124 deletions(-)
> create mode 100644 tcg/i386/tcg-target-conset.h
>
> diff --git a/tcg/i386/tcg-target-conset.h b/tcg/i386/tcg-target-conset.h
> new file mode 100644
> index 0000000000..5a4f991d78
> --- /dev/null
> +++ b/tcg/i386/tcg-target-conset.h
> @@ -0,0 +1,44 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * i386 target-specific constaint sets.
"constraint"
> + * Copyright (c) 2020 Linaro
> + */
> +
> +C_O0_I1(r)
> +C_O0_I2(L, L)
> +C_O0_I2(qi, r)
> +C_O0_I2(re, r)
> +C_O0_I2(ri, r)
> +C_O0_I2(r, re)
> +C_O0_I2(x, r)
I'm afraid this is completely incomprehensible to me.
Can we have some documentation of what these macros are doing
(which we can then reference in the comment at the top of each
conset.h file)?
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 03/22] tcg: Split out target constraints to tcg-target-constr.h
2020-12-23 6:01 ` [PATCH 03/22] tcg: Split out target constraints to tcg-target-constr.h Richard Henderson
@ 2021-01-12 11:57 ` Peter Maydell
0 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2021-01-12 11:57 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Wed, 23 Dec 2020 at 06:09, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This eliminates the target-specific function target_parse_constraint
> and folds it into the single caller, process_op_defs. Since this is
> done directly into the switch statement, duplicates are compilation
> errors rather than silently ignored at runtime.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/i386/tcg-target-constr.h | 26 ++++++++++++++
> tcg/i386/tcg-target.h | 1 +
> tcg/tcg.c | 33 ++++++++++++++---
> tcg/i386/tcg-target.c.inc | 70 ++----------------------------------
> 4 files changed, 58 insertions(+), 72 deletions(-)
> create mode 100644 tcg/i386/tcg-target-constr.h
>
> diff --git a/tcg/i386/tcg-target-constr.h b/tcg/i386/tcg-target-constr.h
> new file mode 100644
> index 0000000000..e4a4886b6c
> --- /dev/null
> +++ b/tcg/i386/tcg-target-constr.h
> @@ -0,0 +1,26 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * i386 target-specific operand constaints.
"constraints"
> + * Copyright (c) 2020 Linaro
> + */
> +
> +REGS('a', 1u << TCG_REG_EAX)
> +REGS('b', 1u << TCG_REG_EBX)
> +REGS('c', 1u << TCG_REG_ECX)
> +REGS('d', 1u << TCG_REG_EDX)
> +REGS('S', 1u << TCG_REG_ESI)
> +REGS('D', 1u << TCG_REG_EDI)
> +
> +REGS('r', ALL_GENERAL_REGS)
> +REGS('x', ALL_VECTOR_REGS)
> +/* A register that can be used as a byte operand. */
> +REGS('q', ALL_BYTEL_REGS)
> +/* A register with an addressable second byte (e.g. %ah). */
> +REGS('Q', ALL_BYTEH_REGS)
> +/* qemu_ld/st address constraint */
> +REGS('L', ALL_GENERAL_REGS & ~((1 << TCG_REG_L0) | (1 << TCG_REG_L1)))
> +
> +CONST('e', TCG_CT_CONST_S32)
> +CONST('I', TCG_CT_CONST_I32)
> +CONST('W', TCG_CT_CONST_WSZ)
> +CONST('Z', TCG_CT_CONST_U32)
This is a little bit less obscure than the conset.h macros,
but it would still be nice to have some documentation of
what's actually going on here.
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2021-01-12 12:02 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-23 6:01 [PATCH 00/22] tcg: backend constraints cleanup Richard Henderson
2020-12-23 6:01 ` [PATCH 01/22] tcg/tci: Drop L and S constraints Richard Henderson
2020-12-23 6:01 ` [PATCH 02/22] tcg/i386: Move constraint type check to tcg_target_const_match Richard Henderson
2020-12-23 6:01 ` [PATCH 03/22] tcg: Split out target constraints to tcg-target-constr.h Richard Henderson
2021-01-12 11:57 ` Peter Maydell
2020-12-23 6:01 ` [PATCH 04/22] tcg/arm: Convert " Richard Henderson
2020-12-23 6:01 ` [PATCH 05/22] tcg/aarch64: " Richard Henderson
2020-12-23 6:01 ` [PATCH 06/22] tcg/ppc: " Richard Henderson
2020-12-23 6:01 ` [PATCH 07/22] tcg/tci: " Richard Henderson
2020-12-23 6:01 ` [PATCH 08/22] tcg/mips: " Richard Henderson
2020-12-23 6:01 ` [PATCH 09/22] tcg/riscv: " Richard Henderson
2021-01-07 17:26 ` Alistair Francis
2020-12-23 6:01 ` [PATCH 10/22] tcg/s390: " Richard Henderson
2020-12-23 6:01 ` [PATCH 11/22] tcg/sparc: " Richard Henderson
2020-12-23 6:01 ` [PATCH 12/22] tcg: Remove TCG_TARGET_CONSTR_H Richard Henderson
2021-01-07 17:27 ` Alistair Francis
2020-12-23 6:01 ` [PATCH 13/22] tcg: Split out constraint sets to tcg-target-conset.h Richard Henderson
2021-01-12 11:55 ` Peter Maydell
2020-12-23 6:01 ` [PATCH 14/22] tcg/aarch64: Convert " Richard Henderson
2020-12-23 6:01 ` [PATCH 15/22] tcg/arm: " Richard Henderson
2020-12-23 6:01 ` [PATCH 16/22] tcg/mips: " Richard Henderson
2020-12-23 6:01 ` [PATCH 17/22] tcg/ppc: " Richard Henderson
2020-12-23 6:02 ` [PATCH 18/22] tcg/riscv: " Richard Henderson
2021-01-07 17:30 ` Alistair Francis
2021-01-07 18:08 ` Peter Maydell
2021-01-07 19:01 ` Philippe Mathieu-Daudé
2021-01-07 19:15 ` Richard Henderson
2021-01-07 19:50 ` Peter Maydell
2020-12-23 6:02 ` [PATCH 19/22] tcg/s390: " Richard Henderson
2020-12-23 6:02 ` [PATCH 20/22] tcg/sparc: " Richard Henderson
2020-12-23 6:02 ` [PATCH 21/22] tcg/tci: " Richard Henderson
2020-12-23 6:02 ` [PATCH 22/22] tcg: Remove TCG_TARGET_CONSET_H Richard Henderson
2021-01-07 17:31 ` Alistair Francis
2020-12-23 6:33 ` [PATCH 00/22] tcg: backend constraints cleanup no-reply
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