* [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock @ 2020-12-23 12:23 Chris Wilson 2020-12-23 12:23 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Consolidate the CS timestamp clocks Chris Wilson ` (4 more replies) 0 siblings, 5 replies; 8+ messages in thread From: Chris Wilson @ 2020-12-23 12:23 UTC (permalink / raw) To: intel-gfx; +Cc: Chris Wilson We assume that both timestamps are driven off the same clock [reported to userspace as I915_PARAM_CS_TIMESTAMP_FREQUENCY]. Verify that this is so by reading the timestamp registers around a busywait (on an otherwise idle engine so there should be no preemptions). v2: Icelake (not ehl, nor tgl) seems to be using a fixed 80ns interval for, and only for, CTX_TIMESTAMP -- or it may be GPU frequency and the test is always running at maximum frequency?. As far as I can tell, this isolated change in behaviour is undocumented. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 203 ++++++++++++++++++- 1 file changed, 202 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index 163a10b07f85..d88504a5d69c 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -4,15 +4,215 @@ * Copyright © 2018 Intel Corporation */ -#include "intel_gpu_commands.h" +#include <linux/sort.h> #include "i915_selftest.h" +#include "intel_gpu_commands.h" +#include "intel_gt_clock_utils.h" #include "selftest_engine.h" #include "selftest_engine_heartbeat.h" #include "selftests/igt_atomic.h" #include "selftests/igt_flush_test.h" #include "selftests/igt_spinner.h" +#define COUNT 5 + +static int cmp_u64(const void *A, const void *B) +{ + const u64 *a = A, *b = B; + + return *a - *b; +} + +static u64 trifilter(u64 *a) +{ + sort(a, COUNT, sizeof(*a), cmp_u64, NULL); + return (a[1] + 2 * a[2] + a[3]) >> 2; +} + +static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) +{ + *cs++ = MI_SEMAPHORE_WAIT | + MI_SEMAPHORE_GLOBAL_GTT | + MI_SEMAPHORE_POLL | + op; + *cs++ = value; + *cs++ = offset; + *cs++ = 0; + + return cs; +} + +static u32 *emit_store(u32 *cs, u32 offset, u32 value) +{ + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; + *cs++ = offset; + *cs++ = 0; + *cs++ = value; + + return cs; +} + +static u32 *emit_srm(u32 *cs, i915_reg_t reg, u32 offset) +{ + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; + *cs++ = i915_mmio_reg_offset(reg); + *cs++ = offset; + *cs++ = 0; + + return cs; +} + +static void write_semaphore(u32 *x, u32 value) +{ + WRITE_ONCE(*x, value); + wmb(); +} + +static int __measure_timestamps(struct intel_context *ce, + u64 *dt, u64 *d_ring, u64 *d_ctx) +{ + struct intel_engine_cs *engine = ce->engine; + u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5); + u32 offset = i915_ggtt_offset(engine->status_page.vma); + struct i915_request *rq; + u32 *cs; + + rq = intel_context_create_request(ce); + if (IS_ERR(rq)) + return PTR_ERR(rq); + + cs = intel_ring_begin(rq, 28); + if (IS_ERR(cs)) { + i915_request_add(rq); + return PTR_ERR(cs); + } + + /* Signal & wait for start */ + cs = emit_store(cs, offset + 4008, 1); + cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_NEQ_SDD, 1); + + cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000); + cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004); + + /* Busy wait */ + cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_EQ_SDD, 1); + + cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016); + cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012); + + intel_ring_advance(rq, cs); + i915_request_get(rq); + i915_request_add(rq); + intel_engine_flush_submission(engine); + + /* Wait for the request to start executing, that then waits for us */ + while (READ_ONCE(sema[2]) == 0) + cpu_relax(); + + /* Run the request for a 100us, sampling timestamps before/after */ + preempt_disable(); + *dt = ktime_get_raw_fast_ns(); + write_semaphore(&sema[2], 0); + udelay(100); + write_semaphore(&sema[2], 1); + *dt = ktime_get_raw_fast_ns() - *dt; + preempt_enable(); + + if (i915_request_wait(rq, 0, HZ / 2) < 0) { + i915_request_put(rq); + return -ETIME; + } + i915_request_put(rq); + + pr_debug("%s CTX_TIMESTAMP: [%x, %x], RING_TIMESTAMP: [%x, %x]\n", + engine->name, sema[1], sema[3], sema[0], sema[4]); + + *d_ctx = sema[3] - sema[1]; + *d_ring = sema[4] - sema[0]; + return 0; +} + +static int __live_engine_timestamps(struct intel_engine_cs *engine) +{ + u64 s_ring[COUNT], s_ctx[COUNT], st[COUNT], d_ring, d_ctx, dt; + struct intel_context *ce; + int i, err = 0; + + ce = intel_context_create(engine); + if (IS_ERR(ce)) + return PTR_ERR(ce); + + for (i = 0; i < COUNT; i++) { + err = __measure_timestamps(ce, &st[i], &s_ring[i], &s_ctx[i]); + if (err) + break; + } + intel_context_put(ce); + if (err) + return err; + + dt = trifilter(st); + d_ring = trifilter(s_ring); + d_ctx = trifilter(s_ctx); + + pr_info("%s elapsed:%lldns, CTX_TIMESTAMP:%dns, RING_TIMESTAMP:%dns\n", + engine->name, dt, + intel_gt_clock_interval_to_ns(engine->gt, d_ctx), + intel_gt_clock_interval_to_ns(engine->gt, d_ring)); + + d_ring = intel_gt_clock_interval_to_ns(engine->gt, d_ring); + if (3 * dt > 4 * d_ring || 4 * dt < 3 * d_ring) { + pr_err("%s Mismatch between ring timestamp and walltime!\n", + engine->name); + return -EINVAL; + } + + d_ring = trifilter(s_ring); + d_ctx = trifilter(s_ctx); + + d_ctx *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz; + if (IS_ICELAKE(engine->i915)) + d_ring *= 12500000; /* Fixed 80ns for icl ctx timestamp? */ + else + d_ring *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz; + + if (3 * d_ctx > 4 * d_ring || 4 * d_ctx < 3 * d_ring) { + pr_err("%s Mismatch between ring and context timestamps!\n", + engine->name); + return -EINVAL; + } + + return 0; +} + +static int live_engine_timestamps(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + + /* + * Check that CS_TIMESTAMP / CTX_TIMESTAMP are in sync, i.e. share + * the same CS clock. + */ + + if (INTEL_GEN(gt->i915) < 8) + return 0; + + for_each_engine(engine, gt, id) { + int err; + + st_engine_heartbeat_disable(engine); + err = __live_engine_timestamps(engine); + st_engine_heartbeat_enable(engine); + if (err) + return err; + } + + return 0; +} + static int live_engine_busy_stats(void *arg) { struct intel_gt *gt = arg; @@ -179,6 +379,7 @@ static int live_engine_pm(void *arg) int live_engine_pm_selftests(struct intel_gt *gt) { static const struct i915_subtest tests[] = { + SUBTEST(live_engine_timestamps), SUBTEST(live_engine_busy_stats), SUBTEST(live_engine_pm), }; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/gt: Consolidate the CS timestamp clocks 2020-12-23 12:23 [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson @ 2020-12-23 12:23 ` Chris Wilson 2020-12-23 14:36 ` Mika Kuoppala 2020-12-23 14:56 ` [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock Mika Kuoppala ` (3 subsequent siblings) 4 siblings, 1 reply; 8+ messages in thread From: Chris Wilson @ 2020-12-23 12:23 UTC (permalink / raw) To: intel-gfx; +Cc: Chris Wilson Pull the GT clock information [used to derive CS timestamps and PM interval] under the GT so that is it local to the users. In doing so, we consolidate the two references for the same information, of which the runtime-info took note of a potential clock source override and scaling factors. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 20 +- drivers/gpu/drm/i915/gt/intel_context.h | 6 +- drivers/gpu/drm/i915/gt/intel_gt.c | 4 +- .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 197 ++++++++++++++---- .../gpu/drm/i915/gt/intel_gt_clock_utils.h | 8 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 + drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 6 +- drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +- drivers/gpu/drm/i915/i915_debugfs.c | 19 +- drivers/gpu/drm/i915/i915_drv.h | 12 -- drivers/gpu/drm/i915/i915_getparam.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_perf.c | 11 +- drivers/gpu/drm/i915/intel_device_info.c | 157 -------------- drivers/gpu/drm/i915/intel_device_info.h | 3 - drivers/gpu/drm/i915/selftests/i915_perf.c | 2 +- drivers/gpu/drm/i915/selftests/i915_request.c | 3 +- 17 files changed, 205 insertions(+), 256 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c index 8975717ace06..a0f10e8bbd21 100644 --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c @@ -404,34 +404,34 @@ static int frequency_show(struct seq_file *m, void *unused) seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); seq_printf(m, "CAGF: %dMHz\n", cagf); - seq_printf(m, "RP CUR UP EI: %d (%dns)\n", + seq_printf(m, "RP CUR UP EI: %d (%lldns)\n", rpcurupei, intel_gt_pm_interval_to_ns(gt, rpcurupei)); - seq_printf(m, "RP CUR UP: %d (%dns)\n", + seq_printf(m, "RP CUR UP: %d (%lldns)\n", rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup)); - seq_printf(m, "RP PREV UP: %d (%dns)\n", + seq_printf(m, "RP PREV UP: %d (%lldns)\n", rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup)); seq_printf(m, "Up threshold: %d%%\n", rps->power.up_threshold); - seq_printf(m, "RP UP EI: %d (%dns)\n", + seq_printf(m, "RP UP EI: %d (%lldns)\n", rpupei, intel_gt_pm_interval_to_ns(gt, rpupei)); - seq_printf(m, "RP UP THRESHOLD: %d (%dns)\n", + seq_printf(m, "RP UP THRESHOLD: %d (%lldns)\n", rpupt, intel_gt_pm_interval_to_ns(gt, rpupt)); - seq_printf(m, "RP CUR DOWN EI: %d (%dns)\n", + seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n", rpcurdownei, intel_gt_pm_interval_to_ns(gt, rpcurdownei)); - seq_printf(m, "RP CUR DOWN: %d (%dns)\n", + seq_printf(m, "RP CUR DOWN: %d (%lldns)\n", rpcurdown, intel_gt_pm_interval_to_ns(gt, rpcurdown)); - seq_printf(m, "RP PREV DOWN: %d (%dns)\n", + seq_printf(m, "RP PREV DOWN: %d (%lldns)\n", rpprevdown, intel_gt_pm_interval_to_ns(gt, rpprevdown)); seq_printf(m, "Down threshold: %d%%\n", rps->power.down_threshold); - seq_printf(m, "RP DOWN EI: %d (%dns)\n", + seq_printf(m, "RP DOWN EI: %d (%lldns)\n", rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei)); - seq_printf(m, "RP DOWN THRESHOLD: %d (%dns)\n", + seq_printf(m, "RP DOWN THRESHOLD: %d (%lldns)\n", rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt)); max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 : diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h index fda2eba81e22..2ce2ec639ba2 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.h +++ b/drivers/gpu/drm/i915/gt/intel_context.h @@ -248,16 +248,14 @@ intel_context_clear_nopreempt(struct intel_context *ce) static inline u64 intel_context_get_total_runtime_ns(struct intel_context *ce) { - const u32 period = - RUNTIME_INFO(ce->engine->i915)->cs_timestamp_period_ns; + const u32 period = ce->engine->gt->clock_period_ns; return READ_ONCE(ce->runtime.total) * period; } static inline u64 intel_context_get_avg_runtime_ns(struct intel_context *ce) { - const u32 period = - RUNTIME_INFO(ce->engine->i915)->cs_timestamp_period_ns; + const u32 period = ce->engine->gt->clock_period_ns; return mul_u32_u32(ewma_runtime_read(&ce->runtime.avg), period); } diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 44f1d51e5ae5..d8e1ab412634 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -46,6 +46,8 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt) int intel_gt_init_mmio(struct intel_gt *gt) { + intel_gt_init_clock_frequency(gt); + intel_uc_init_mmio(>->uc); intel_sseu_info_init(gt); @@ -546,8 +548,6 @@ int intel_gt_init(struct intel_gt *gt) */ intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); - intel_gt_init_clock_frequency(gt); - err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K); if (err) goto out_fw; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c index 999079686846..a4242ca8dcd7 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c @@ -7,34 +7,146 @@ #include "intel_gt.h" #include "intel_gt_clock_utils.h" -#define MHZ_12 12000000 /* 12MHz (24MHz/2), 83.333ns */ -#define MHZ_12_5 12500000 /* 12.5MHz (25MHz/2), 80ns */ -#define MHZ_19_2 19200000 /* 19.2MHz, 52.083ns */ +static u32 read_reference_ts_freq(struct intel_uncore *uncore) +{ + u32 ts_override = intel_uncore_read(uncore, GEN9_TIMESTAMP_OVERRIDE); + u32 base_freq, frac_freq; + + base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> + GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; + base_freq *= 1000000; + + frac_freq = ((ts_override & + GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> + GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); + frac_freq = 1000000 / (frac_freq + 1); + + return base_freq + frac_freq; +} + +static u32 gen10_get_crystal_clock_freq(struct intel_uncore *uncore, + u32 rpm_config_reg) +{ + u32 f19_2_mhz = 19200000; + u32 f24_mhz = 24000000; + u32 crystal_clock = + (rpm_config_reg & GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> + GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; -static u32 read_clock_frequency(const struct intel_gt *gt) + switch (crystal_clock) { + case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: + return f19_2_mhz; + case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: + return f24_mhz; + default: + MISSING_CASE(crystal_clock); + return 0; + } +} + +static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore, + u32 rpm_config_reg) { - if (INTEL_GEN(gt->i915) >= 11) { - u32 config; - - config = intel_uncore_read(gt->uncore, RPM_CONFIG0); - config &= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK; - config >>= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; - - switch (config) { - case 0: return MHZ_12; - case 1: - case 2: return MHZ_19_2; - default: - case 3: return MHZ_12_5; + u32 f19_2_mhz = 19200000; + u32 f24_mhz = 24000000; + u32 f25_mhz = 25000000; + u32 f38_4_mhz = 38400000; + u32 crystal_clock = + (rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> + GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; + + switch (crystal_clock) { + case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: + return f24_mhz; + case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: + return f19_2_mhz; + case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ: + return f38_4_mhz; + case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ: + return f25_mhz; + default: + MISSING_CASE(crystal_clock); + return 0; + } +} + +static u32 read_clock_frequency(struct intel_uncore *uncore) +{ + u32 f12_5_mhz = 12500000; + u32 f19_2_mhz = 19200000; + u32 f24_mhz = 24000000; + + if (INTEL_GEN(uncore->i915) <= 4) { + /* + * PRMs say: + * + * "The value in this register increments once every 16 + * hclks." (through the “Clocking Configuration” + * (“CLKCFG”) MCHBAR register) + */ + return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16; + } else if (INTEL_GEN(uncore->i915) <= 8) { + /* + * PRMs say: + * + * "The PCU TSC counts 10ns increments; this timestamp + * reflects bits 38:3 of the TSC (i.e. 80ns granularity, + * rolling over every 1.5 hours). + */ + return f12_5_mhz; + } else if (INTEL_GEN(uncore->i915) <= 9) { + u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); + u32 freq = 0; + + if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { + freq = read_reference_ts_freq(uncore); + } else { + freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz; + + /* + * Now figure out how the command stream's timestamp + * register increments from this frequency (it might + * increment only every few clock cycle). + */ + freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> + CTC_SHIFT_PARAMETER_SHIFT); } - } else if (INTEL_GEN(gt->i915) >= 9) { - if (IS_GEN9_LP(gt->i915)) - return MHZ_19_2; - else - return MHZ_12; - } else { - return MHZ_12_5; + + return freq; + } else if (INTEL_GEN(uncore->i915) <= 12) { + u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); + u32 freq = 0; + + /* + * First figure out the reference frequency. There are 2 ways + * we can compute the frequency, either through the + * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE + * tells us which one we should use. + */ + if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { + freq = read_reference_ts_freq(uncore); + } else { + u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0); + + if (INTEL_GEN(uncore->i915) <= 10) + freq = gen10_get_crystal_clock_freq(uncore, c0); + else + freq = gen11_get_crystal_clock_freq(uncore, c0); + + /* + * Now figure out how the command stream's timestamp + * register increments from this frequency (it might + * increment only every few clock cycle). + */ + freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); + } + + return freq; } + + MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n"); + return 0; } void intel_gt_init_clock_frequency(struct intel_gt *gt) @@ -43,20 +155,27 @@ void intel_gt_init_clock_frequency(struct intel_gt *gt) * Note that on gen11+, the clock frequency may be reconfigured. * We do not, and we assume nobody else does. */ - gt->clock_frequency = read_clock_frequency(gt); + gt->clock_frequency = read_clock_frequency(gt->uncore); + if (gt->clock_frequency) + gt->clock_period_ns = intel_gt_clock_interval_to_ns(gt, 1); + GT_TRACE(gt, - "Using clock frequency: %dkHz\n", - gt->clock_frequency / 1000); + "Using clock frequency: %dkHz, period: %dns, wrap: %lldms\n", + gt->clock_frequency / 1000, + gt->clock_period_ns, + div_u64(mul_u32_u32(gt->clock_period_ns, S32_MAX), + USEC_PER_SEC)); + } #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) void intel_gt_check_clock_frequency(const struct intel_gt *gt) { - if (gt->clock_frequency != read_clock_frequency(gt)) { + if (gt->clock_frequency != read_clock_frequency(gt->uncore)) { dev_err(gt->i915->drm.dev, "GT clock frequency changed, was %uHz, now %uHz!\n", gt->clock_frequency, - read_clock_frequency(gt)); + read_clock_frequency(gt->uncore)); } } #endif @@ -66,26 +185,24 @@ static u64 div_u64_roundup(u64 nom, u32 den) return div_u64(nom + den - 1, den); } -u32 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u32 count) +u64 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u64 count) { - return div_u64_roundup(mul_u32_u32(count, 1000 * 1000 * 1000), - gt->clock_frequency); + return div_u64_roundup(count * NSEC_PER_SEC, gt->clock_frequency); } -u32 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u32 count) +u64 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u64 count) { return intel_gt_clock_interval_to_ns(gt, 16 * count); } -u32 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u32 ns) +u64 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u64 ns) { - return div_u64_roundup(mul_u32_u32(gt->clock_frequency, ns), - 1000 * 1000 * 1000); + return div_u64_roundup(gt->clock_frequency * ns, NSEC_PER_SEC); } -u32 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u32 ns) +u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns) { - u32 val; + u64 val; /* * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS @@ -94,9 +211,9 @@ u32 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u32 ns) * EI/thresholds are "bad", leading to a very sluggish or even * frozen machine. */ - val = DIV_ROUND_UP(intel_gt_ns_to_clock_interval(gt, ns), 16); + val = div_u64_roundup(intel_gt_ns_to_clock_interval(gt, ns), 16); if (IS_GEN(gt->i915, 6)) - val = roundup(val, 25); + val = div_u64_roundup(val, 25) * 25; return val; } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h index f793c89f2cbd..8b03e97a85df 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h @@ -18,10 +18,10 @@ void intel_gt_check_clock_frequency(const struct intel_gt *gt); static inline void intel_gt_check_clock_frequency(const struct intel_gt *gt) {} #endif -u32 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u32 count); -u32 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u32 count); +u64 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u64 count); +u64 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u64 count); -u32 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u32 ns); -u32 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u32 ns); +u64 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u64 ns); +u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns); #endif /* __INTEL_GT_CLOCK_UTILS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index c7bde529feab..a83d3e18254d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -75,6 +75,7 @@ struct intel_gt { intel_wakeref_t awake; u32 clock_frequency; + u32 clock_period_ns; struct intel_llc llc; struct intel_rc6 rc6; diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index d88504a5d69c..ca080445695e 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -156,7 +156,7 @@ static int __live_engine_timestamps(struct intel_engine_cs *engine) d_ring = trifilter(s_ring); d_ctx = trifilter(s_ctx); - pr_info("%s elapsed:%lldns, CTX_TIMESTAMP:%dns, RING_TIMESTAMP:%dns\n", + pr_info("%s elapsed:%lldns, CTX_TIMESTAMP:%lldns, RING_TIMESTAMP:%lldns\n", engine->name, dt, intel_gt_clock_interval_to_ns(engine->gt, d_ctx), intel_gt_clock_interval_to_ns(engine->gt, d_ring)); @@ -171,11 +171,11 @@ static int __live_engine_timestamps(struct intel_engine_cs *engine) d_ring = trifilter(s_ring); d_ctx = trifilter(s_ctx); - d_ctx *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz; + d_ctx *= engine->gt->clock_frequency; if (IS_ICELAKE(engine->i915)) d_ring *= 12500000; /* Fixed 80ns for icl ctx timestamp? */ else - d_ring *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz; + d_ring *= engine->gt->clock_frequency; if (3 * d_ctx > 4 * d_ring || 4 * d_ctx < 3 * d_ring) { pr_err("%s Mismatch between ring and context timestamps!\n", diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c index 6180a47c1b51..5d911f724ebe 100644 --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c @@ -71,7 +71,7 @@ static int live_gt_clocks(void *arg) enum intel_engine_id id; int err = 0; - if (!RUNTIME_INFO(gt->i915)->cs_timestamp_frequency_hz) { /* unknown */ + if (!gt->clock_frequency) { /* unknown */ pr_info("CS_TIMESTAMP frequency unknown\n"); return 0; } @@ -112,12 +112,12 @@ static int live_gt_clocks(void *arg) measure_clocks(engine, &cycles, &dt); - time = i915_cs_timestamp_ticks_to_ns(engine->i915, cycles); - expected = i915_cs_timestamp_ns_to_ticks(engine->i915, dt); + time = intel_gt_clock_interval_to_ns(engine->gt, cycles); + expected = intel_gt_ns_to_clock_interval(engine->gt, dt); pr_info("%s: TIMESTAMP %d cycles [%lldns] in %lldns [%d cycles], using CS clock frequency of %uKHz\n", engine->name, cycles, time, dt, expected, - RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz / 1000); + engine->gt->clock_frequency / 1000); if (9 * time < 8 * dt || 8 * time > 9 * dt) { pr_err("%s: CS ticks did not match walltime!\n", diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index c72160e3702f..7332478a3dd5 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -635,27 +635,27 @@ static int i915_frequency_info(struct seq_file *m, void *unused) seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); seq_printf(m, "CAGF: %dMHz\n", cagf); - seq_printf(m, "RP CUR UP EI: %d (%dns)\n", + seq_printf(m, "RP CUR UP EI: %d (%lldns)\n", rpupei, intel_gt_pm_interval_to_ns(&dev_priv->gt, rpupei)); - seq_printf(m, "RP CUR UP: %d (%dun)\n", + seq_printf(m, "RP CUR UP: %d (%lldun)\n", rpcurup, intel_gt_pm_interval_to_ns(&dev_priv->gt, rpcurup)); - seq_printf(m, "RP PREV UP: %d (%dns)\n", + seq_printf(m, "RP PREV UP: %d (%lldns)\n", rpprevup, intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevup)); seq_printf(m, "Up threshold: %d%%\n", rps->power.up_threshold); - seq_printf(m, "RP CUR DOWN EI: %d (%dns)\n", + seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n", rpdownei, intel_gt_pm_interval_to_ns(&dev_priv->gt, rpdownei)); - seq_printf(m, "RP CUR DOWN: %d (%dns)\n", + seq_printf(m, "RP CUR DOWN: %d (%lldns)\n", rpcurdown, intel_gt_pm_interval_to_ns(&dev_priv->gt, rpcurdown)); - seq_printf(m, "RP PREV DOWN: %d (%dns)\n", + seq_printf(m, "RP PREV DOWN: %d (%lldns)\n", rpprevdown, intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevdown)); @@ -862,8 +862,9 @@ static int i915_engine_info(struct seq_file *m, void *unused) yesno(i915->gt.awake), atomic_read(&i915->gt.wakeref.count), ktime_to_ms(intel_gt_get_awake_time(&i915->gt))); - seq_printf(m, "CS timestamp frequency: %u Hz\n", - RUNTIME_INFO(i915)->cs_timestamp_frequency_hz); + seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", + i915->gt.clock_frequency, + i915->gt.clock_period_ns); p = drm_seq_file_printer(m); for_each_uabi_engine(engine, i915) @@ -949,7 +950,7 @@ i915_perf_noa_delay_set(void *data, u64 val) * This would lead to infinite waits as we're doing timestamp * difference on the CS with only 32bits. */ - if (i915_cs_timestamp_ns_to_ticks(i915, val) > U32_MAX) + if (intel_gt_ns_to_clock_interval(&i915->gt, val) > U32_MAX) return -EINVAL; atomic64_set(&i915->perf.noa_programming_delay, val); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4a8ff2a899a5..e38a10d5c128 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2003,16 +2003,4 @@ i915_coherent_map_type(struct drm_i915_private *i915) return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; } -static inline u64 i915_cs_timestamp_ns_to_ticks(struct drm_i915_private *i915, u64 val) -{ - return DIV_ROUND_UP_ULL(val * RUNTIME_INFO(i915)->cs_timestamp_frequency_hz, - 1000000000); -} - -static inline u64 i915_cs_timestamp_ticks_to_ns(struct drm_i915_private *i915, u64 val) -{ - return div_u64(val * 1000000000, - RUNTIME_INFO(i915)->cs_timestamp_frequency_hz); -} - #endif diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c index f96032c60a12..75c3bfc2486e 100644 --- a/drivers/gpu/drm/i915/i915_getparam.c +++ b/drivers/gpu/drm/i915/i915_getparam.c @@ -154,7 +154,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, return -ENODEV; break; case I915_PARAM_CS_TIMESTAMP_FREQUENCY: - value = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz; + value = i915->gt.clock_frequency; break; case I915_PARAM_MMAP_GTT_COHERENT: value = INTEL_INFO(i915)->has_coherent_ggtt; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index d8cac4c5881f..8b163ee1b86d 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -485,7 +485,7 @@ static void error_print_context(struct drm_i915_error_state_buf *m, const char *header, const struct i915_gem_context_coredump *ctx) { - const u32 period = RUNTIME_INFO(m->i915)->cs_timestamp_period_ns; + const u32 period = m->i915->gt.clock_period_ns; err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", header, ctx->comm, ctx->pid, ctx->sched_attr.priority, diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index f65c32bd970e..112ba5f2ce90 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -201,6 +201,7 @@ #include "gt/intel_execlists_submission.h" #include "gt/intel_gpu_commands.h" #include "gt/intel_gt.h" +#include "gt/intel_gt_clock_utils.h" #include "gt/intel_lrc.h" #include "gt/intel_ring.h" @@ -1637,7 +1638,8 @@ static int alloc_noa_wait(struct i915_perf_stream *stream) struct drm_i915_gem_object *bo; struct i915_vma *vma; const u64 delay_ticks = 0xffffffffffffffff - - i915_cs_timestamp_ns_to_ticks(i915, atomic64_read(&stream->perf->noa_programming_delay)); + intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt, + atomic64_read(&stream->perf->noa_programming_delay)); const u32 base = stream->engine->mmio_base; #define CS_GPR(x) GEN8_RING_CS_GPR(base, x) u32 *batch, *ts0, *cs, *jump; @@ -3518,7 +3520,8 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf, static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent) { - return i915_cs_timestamp_ticks_to_ns(perf->i915, 2ULL << exponent); + return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt, + 2ULL << exponent); } /** @@ -4372,8 +4375,8 @@ void i915_perf_init(struct drm_i915_private *i915) if (perf->ops.enable_metric_set) { mutex_init(&perf->lock); - oa_sample_rate_hard_limit = - RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 2; + /* Choose a representative limit */ + oa_sample_rate_hard_limit = i915->gt.clock_frequency / 2; mutex_init(&perf->metrics_lock); idr_init_base(&perf->metrics_idr, 1); diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index ef767f04c37c..f2d5ae59081e 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -117,150 +117,6 @@ void intel_device_info_print_runtime(const struct intel_runtime_info *info, struct drm_printer *p) { drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); - drm_printf(p, "CS timestamp frequency: %u Hz\n", - info->cs_timestamp_frequency_hz); -} - -static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) -{ - u32 ts_override = intel_uncore_read(&dev_priv->uncore, - GEN9_TIMESTAMP_OVERRIDE); - u32 base_freq, frac_freq; - - base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; - base_freq *= 1000000; - - frac_freq = ((ts_override & - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); - frac_freq = 1000000 / (frac_freq + 1); - - return base_freq + frac_freq; -} - -static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv, - u32 rpm_config_reg) -{ - u32 f19_2_mhz = 19200000; - u32 f24_mhz = 24000000; - u32 crystal_clock = (rpm_config_reg & - GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> - GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; - - switch (crystal_clock) { - case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: - return f19_2_mhz; - case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: - return f24_mhz; - default: - MISSING_CASE(crystal_clock); - return 0; - } -} - -static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv, - u32 rpm_config_reg) -{ - u32 f19_2_mhz = 19200000; - u32 f24_mhz = 24000000; - u32 f25_mhz = 25000000; - u32 f38_4_mhz = 38400000; - u32 crystal_clock = (rpm_config_reg & - GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> - GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; - - switch (crystal_clock) { - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: - return f24_mhz; - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: - return f19_2_mhz; - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ: - return f38_4_mhz; - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ: - return f25_mhz; - default: - MISSING_CASE(crystal_clock); - return 0; - } -} - -static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) -{ - struct intel_uncore *uncore = &dev_priv->uncore; - u32 f12_5_mhz = 12500000; - u32 f19_2_mhz = 19200000; - u32 f24_mhz = 24000000; - - if (INTEL_GEN(dev_priv) <= 4) { - /* PRMs say: - * - * "The value in this register increments once every 16 - * hclks." (through the “Clocking Configuration” - * (“CLKCFG”) MCHBAR register) - */ - return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000 / 16; - } else if (INTEL_GEN(dev_priv) <= 8) { - /* PRMs say: - * - * "The PCU TSC counts 10ns increments; this timestamp - * reflects bits 38:3 of the TSC (i.e. 80ns granularity, - * rolling over every 1.5 hours). - */ - return f12_5_mhz; - } else if (INTEL_GEN(dev_priv) <= 9) { - u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); - u32 freq = 0; - - if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { - freq = read_reference_ts_freq(dev_priv); - } else { - freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; - - /* Now figure out how the command stream's timestamp - * register increments from this frequency (it might - * increment only every few clock cycle). - */ - freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> - CTC_SHIFT_PARAMETER_SHIFT); - } - - return freq; - } else if (INTEL_GEN(dev_priv) <= 12) { - u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); - u32 freq = 0; - - /* First figure out the reference frequency. There are 2 ways - * we can compute the frequency, either through the - * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE - * tells us which one we should use. - */ - if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { - freq = read_reference_ts_freq(dev_priv); - } else { - u32 rpm_config_reg = intel_uncore_read(uncore, RPM_CONFIG0); - - if (INTEL_GEN(dev_priv) <= 10) - freq = gen10_get_crystal_clock_freq(dev_priv, - rpm_config_reg); - else - freq = gen11_get_crystal_clock_freq(dev_priv, - rpm_config_reg); - - /* Now figure out how the command stream's timestamp - * register increments from this frequency (it might - * increment only every few clock cycle). - */ - freq >>= 3 - ((rpm_config_reg & - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); - } - - return freq; - } - - MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n"); - return 0; } #undef INTEL_VGA_DEVICE @@ -505,19 +361,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) runtime->rawclk_freq = intel_read_rawclk(dev_priv); drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); - /* Initialize command stream timestamp frequency */ - runtime->cs_timestamp_frequency_hz = - read_timestamp_frequency(dev_priv); - if (runtime->cs_timestamp_frequency_hz) { - runtime->cs_timestamp_period_ns = - i915_cs_timestamp_ticks_to_ns(dev_priv, 1); - drm_dbg(&dev_priv->drm, - "CS timestamp wraparound in %lldms\n", - div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns, - S32_MAX), - USEC_PER_SEC)); - } - if (!HAS_DISPLAY(dev_priv)) { dev_priv->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index d92fa041c700..17d0fdb94d2d 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -224,9 +224,6 @@ struct intel_runtime_info { u8 num_scalers[I915_MAX_PIPES]; u32 rawclk_freq; - - u32 cs_timestamp_frequency_hz; - u32 cs_timestamp_period_ns; }; struct intel_driver_caps { diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c index debbac660519..e9d86dab8677 100644 --- a/drivers/gpu/drm/i915/selftests/i915_perf.c +++ b/drivers/gpu/drm/i915/selftests/i915_perf.c @@ -262,7 +262,7 @@ static int live_noa_delay(void *arg) delay = intel_read_status_page(stream->engine, 0x102); delay -= intel_read_status_page(stream->engine, 0x100); - delay = i915_cs_timestamp_ticks_to_ns(i915, delay); + delay = intel_gt_clock_interval_to_ns(stream->engine->gt, delay); pr_info("GPU delay: %uns, expected %lluns\n", delay, expected); diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index e424a6d1a68c..ddf76069066e 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -33,6 +33,7 @@ #include "gt/intel_engine_pm.h" #include "gt/intel_engine_user.h" #include "gt/intel_gt.h" +#include "gt/intel_gt_clock_utils.h" #include "gt/intel_gt_requests.h" #include "gt/selftest_engine_heartbeat.h" @@ -1560,7 +1561,7 @@ static u32 trifilter(u32 *a) static u64 cycles_to_ns(struct intel_engine_cs *engine, u32 cycles) { - u64 ns = i915_cs_timestamp_ticks_to_ns(engine->i915, cycles); + u64 ns = intel_gt_clock_interval_to_ns(engine->gt, cycles); return DIV_ROUND_CLOSEST(ns, 1 << TF_BIAS); } -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Consolidate the CS timestamp clocks 2020-12-23 12:23 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Consolidate the CS timestamp clocks Chris Wilson @ 2020-12-23 14:36 ` Mika Kuoppala 0 siblings, 0 replies; 8+ messages in thread From: Mika Kuoppala @ 2020-12-23 14:36 UTC (permalink / raw) To: Chris Wilson, intel-gfx; +Cc: Chris Wilson Chris Wilson <chris@chris-wilson.co.uk> writes: > Pull the GT clock information [used to derive CS timestamps and PM > interval] under the GT so that is it local to the users. In doing so, we > consolidate the two references for the same information, of which the > runtime-info took note of a potential clock source override and scaling > factors. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 20 +- > drivers/gpu/drm/i915/gt/intel_context.h | 6 +- > drivers/gpu/drm/i915/gt/intel_gt.c | 4 +- > .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 197 ++++++++++++++---- > .../gpu/drm/i915/gt/intel_gt_clock_utils.h | 8 +- > drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 + > drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 6 +- > drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +- > drivers/gpu/drm/i915/i915_debugfs.c | 19 +- > drivers/gpu/drm/i915/i915_drv.h | 12 -- > drivers/gpu/drm/i915/i915_getparam.c | 2 +- > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > drivers/gpu/drm/i915/i915_perf.c | 11 +- > drivers/gpu/drm/i915/intel_device_info.c | 157 -------------- > drivers/gpu/drm/i915/intel_device_info.h | 3 - > drivers/gpu/drm/i915/selftests/i915_perf.c | 2 +- > drivers/gpu/drm/i915/selftests/i915_request.c | 3 +- > 17 files changed, 205 insertions(+), 256 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c > index 8975717ace06..a0f10e8bbd21 100644 > --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c > +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c > @@ -404,34 +404,34 @@ static int frequency_show(struct seq_file *m, void *unused) > seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); > seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); > seq_printf(m, "CAGF: %dMHz\n", cagf); > - seq_printf(m, "RP CUR UP EI: %d (%dns)\n", > + seq_printf(m, "RP CUR UP EI: %d (%lldns)\n", > rpcurupei, > intel_gt_pm_interval_to_ns(gt, rpcurupei)); > - seq_printf(m, "RP CUR UP: %d (%dns)\n", > + seq_printf(m, "RP CUR UP: %d (%lldns)\n", > rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup)); > - seq_printf(m, "RP PREV UP: %d (%dns)\n", > + seq_printf(m, "RP PREV UP: %d (%lldns)\n", > rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup)); > seq_printf(m, "Up threshold: %d%%\n", > rps->power.up_threshold); > - seq_printf(m, "RP UP EI: %d (%dns)\n", > + seq_printf(m, "RP UP EI: %d (%lldns)\n", > rpupei, intel_gt_pm_interval_to_ns(gt, rpupei)); > - seq_printf(m, "RP UP THRESHOLD: %d (%dns)\n", > + seq_printf(m, "RP UP THRESHOLD: %d (%lldns)\n", > rpupt, intel_gt_pm_interval_to_ns(gt, rpupt)); > > - seq_printf(m, "RP CUR DOWN EI: %d (%dns)\n", > + seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n", > rpcurdownei, > intel_gt_pm_interval_to_ns(gt, rpcurdownei)); > - seq_printf(m, "RP CUR DOWN: %d (%dns)\n", > + seq_printf(m, "RP CUR DOWN: %d (%lldns)\n", > rpcurdown, > intel_gt_pm_interval_to_ns(gt, rpcurdown)); > - seq_printf(m, "RP PREV DOWN: %d (%dns)\n", > + seq_printf(m, "RP PREV DOWN: %d (%lldns)\n", > rpprevdown, > intel_gt_pm_interval_to_ns(gt, rpprevdown)); > seq_printf(m, "Down threshold: %d%%\n", > rps->power.down_threshold); > - seq_printf(m, "RP DOWN EI: %d (%dns)\n", > + seq_printf(m, "RP DOWN EI: %d (%lldns)\n", > rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei)); > - seq_printf(m, "RP DOWN THRESHOLD: %d (%dns)\n", > + seq_printf(m, "RP DOWN THRESHOLD: %d (%lldns)\n", > rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt)); > > max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 : > diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h > index fda2eba81e22..2ce2ec639ba2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_context.h > +++ b/drivers/gpu/drm/i915/gt/intel_context.h > @@ -248,16 +248,14 @@ intel_context_clear_nopreempt(struct intel_context *ce) > > static inline u64 intel_context_get_total_runtime_ns(struct intel_context *ce) > { > - const u32 period = > - RUNTIME_INFO(ce->engine->i915)->cs_timestamp_period_ns; > + const u32 period = ce->engine->gt->clock_period_ns; > > return READ_ONCE(ce->runtime.total) * period; > } > > static inline u64 intel_context_get_avg_runtime_ns(struct intel_context *ce) > { > - const u32 period = > - RUNTIME_INFO(ce->engine->i915)->cs_timestamp_period_ns; > + const u32 period = ce->engine->gt->clock_period_ns; > > return mul_u32_u32(ewma_runtime_read(&ce->runtime.avg), period); > } > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index 44f1d51e5ae5..d8e1ab412634 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -46,6 +46,8 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt) > > int intel_gt_init_mmio(struct intel_gt *gt) > { > + intel_gt_init_clock_frequency(gt); > + We will now probe it without forcewake_all umbrella but it should work by taking it's own. Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > intel_uc_init_mmio(>->uc); > intel_sseu_info_init(gt); > > @@ -546,8 +548,6 @@ int intel_gt_init(struct intel_gt *gt) > */ > intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); > > - intel_gt_init_clock_frequency(gt); > - > err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K); > if (err) > goto out_fw; > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c > index 999079686846..a4242ca8dcd7 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c > @@ -7,34 +7,146 @@ > #include "intel_gt.h" > #include "intel_gt_clock_utils.h" > > -#define MHZ_12 12000000 /* 12MHz (24MHz/2), 83.333ns */ > -#define MHZ_12_5 12500000 /* 12.5MHz (25MHz/2), 80ns */ > -#define MHZ_19_2 19200000 /* 19.2MHz, 52.083ns */ > +static u32 read_reference_ts_freq(struct intel_uncore *uncore) > +{ > + u32 ts_override = intel_uncore_read(uncore, GEN9_TIMESTAMP_OVERRIDE); > + u32 base_freq, frac_freq; > + > + base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> > + GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; > + base_freq *= 1000000; > + > + frac_freq = ((ts_override & > + GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> > + GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); > + frac_freq = 1000000 / (frac_freq + 1); > + > + return base_freq + frac_freq; > +} > + > +static u32 gen10_get_crystal_clock_freq(struct intel_uncore *uncore, > + u32 rpm_config_reg) > +{ > + u32 f19_2_mhz = 19200000; > + u32 f24_mhz = 24000000; > + u32 crystal_clock = > + (rpm_config_reg & GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> > + GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; > > -static u32 read_clock_frequency(const struct intel_gt *gt) > + switch (crystal_clock) { > + case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: > + return f19_2_mhz; > + case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: > + return f24_mhz; > + default: > + MISSING_CASE(crystal_clock); > + return 0; > + } > +} > + > +static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore, > + u32 rpm_config_reg) > { > - if (INTEL_GEN(gt->i915) >= 11) { > - u32 config; > - > - config = intel_uncore_read(gt->uncore, RPM_CONFIG0); > - config &= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK; > - config >>= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; > - > - switch (config) { > - case 0: return MHZ_12; > - case 1: > - case 2: return MHZ_19_2; > - default: > - case 3: return MHZ_12_5; > + u32 f19_2_mhz = 19200000; > + u32 f24_mhz = 24000000; > + u32 f25_mhz = 25000000; > + u32 f38_4_mhz = 38400000; > + u32 crystal_clock = > + (rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> > + GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; > + > + switch (crystal_clock) { > + case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: > + return f24_mhz; > + case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: > + return f19_2_mhz; > + case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ: > + return f38_4_mhz; > + case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ: > + return f25_mhz; > + default: > + MISSING_CASE(crystal_clock); > + return 0; > + } > +} > + > +static u32 read_clock_frequency(struct intel_uncore *uncore) > +{ > + u32 f12_5_mhz = 12500000; > + u32 f19_2_mhz = 19200000; > + u32 f24_mhz = 24000000; > + > + if (INTEL_GEN(uncore->i915) <= 4) { > + /* > + * PRMs say: > + * > + * "The value in this register increments once every 16 > + * hclks." (through the “Clocking Configuration” > + * (“CLKCFG”) MCHBAR register) > + */ > + return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16; > + } else if (INTEL_GEN(uncore->i915) <= 8) { > + /* > + * PRMs say: > + * > + * "The PCU TSC counts 10ns increments; this timestamp > + * reflects bits 38:3 of the TSC (i.e. 80ns granularity, > + * rolling over every 1.5 hours). > + */ > + return f12_5_mhz; > + } else if (INTEL_GEN(uncore->i915) <= 9) { > + u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); > + u32 freq = 0; > + > + if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { > + freq = read_reference_ts_freq(uncore); > + } else { > + freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz; > + > + /* > + * Now figure out how the command stream's timestamp > + * register increments from this frequency (it might > + * increment only every few clock cycle). > + */ > + freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> > + CTC_SHIFT_PARAMETER_SHIFT); > } > - } else if (INTEL_GEN(gt->i915) >= 9) { > - if (IS_GEN9_LP(gt->i915)) > - return MHZ_19_2; > - else > - return MHZ_12; > - } else { > - return MHZ_12_5; > + > + return freq; > + } else if (INTEL_GEN(uncore->i915) <= 12) { > + u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); > + u32 freq = 0; > + > + /* > + * First figure out the reference frequency. There are 2 ways > + * we can compute the frequency, either through the > + * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE > + * tells us which one we should use. > + */ > + if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { > + freq = read_reference_ts_freq(uncore); > + } else { > + u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0); > + > + if (INTEL_GEN(uncore->i915) <= 10) > + freq = gen10_get_crystal_clock_freq(uncore, c0); > + else > + freq = gen11_get_crystal_clock_freq(uncore, c0); > + > + /* > + * Now figure out how the command stream's timestamp > + * register increments from this frequency (it might > + * increment only every few clock cycle). > + */ > + freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> > + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); > + } > + > + return freq; > } > + > + MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n"); > + return 0; > } > > void intel_gt_init_clock_frequency(struct intel_gt *gt) > @@ -43,20 +155,27 @@ void intel_gt_init_clock_frequency(struct intel_gt *gt) > * Note that on gen11+, the clock frequency may be reconfigured. > * We do not, and we assume nobody else does. > */ > - gt->clock_frequency = read_clock_frequency(gt); > + gt->clock_frequency = read_clock_frequency(gt->uncore); > + if (gt->clock_frequency) > + gt->clock_period_ns = intel_gt_clock_interval_to_ns(gt, 1); > + > GT_TRACE(gt, > - "Using clock frequency: %dkHz\n", > - gt->clock_frequency / 1000); > + "Using clock frequency: %dkHz, period: %dns, wrap: %lldms\n", > + gt->clock_frequency / 1000, > + gt->clock_period_ns, > + div_u64(mul_u32_u32(gt->clock_period_ns, S32_MAX), > + USEC_PER_SEC)); > + > } > > #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) > void intel_gt_check_clock_frequency(const struct intel_gt *gt) > { > - if (gt->clock_frequency != read_clock_frequency(gt)) { > + if (gt->clock_frequency != read_clock_frequency(gt->uncore)) { > dev_err(gt->i915->drm.dev, > "GT clock frequency changed, was %uHz, now %uHz!\n", > gt->clock_frequency, > - read_clock_frequency(gt)); > + read_clock_frequency(gt->uncore)); > } > } > #endif > @@ -66,26 +185,24 @@ static u64 div_u64_roundup(u64 nom, u32 den) > return div_u64(nom + den - 1, den); > } > > -u32 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u32 count) > +u64 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u64 count) > { > - return div_u64_roundup(mul_u32_u32(count, 1000 * 1000 * 1000), > - gt->clock_frequency); > + return div_u64_roundup(count * NSEC_PER_SEC, gt->clock_frequency); > } > > -u32 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u32 count) > +u64 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u64 count) > { > return intel_gt_clock_interval_to_ns(gt, 16 * count); > } > > -u32 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u32 ns) > +u64 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u64 ns) > { > - return div_u64_roundup(mul_u32_u32(gt->clock_frequency, ns), > - 1000 * 1000 * 1000); > + return div_u64_roundup(gt->clock_frequency * ns, NSEC_PER_SEC); > } > > -u32 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u32 ns) > +u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns) > { > - u32 val; > + u64 val; > > /* > * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS > @@ -94,9 +211,9 @@ u32 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u32 ns) > * EI/thresholds are "bad", leading to a very sluggish or even > * frozen machine. > */ > - val = DIV_ROUND_UP(intel_gt_ns_to_clock_interval(gt, ns), 16); > + val = div_u64_roundup(intel_gt_ns_to_clock_interval(gt, ns), 16); > if (IS_GEN(gt->i915, 6)) > - val = roundup(val, 25); > + val = div_u64_roundup(val, 25) * 25; > > return val; > } > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h > index f793c89f2cbd..8b03e97a85df 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h > @@ -18,10 +18,10 @@ void intel_gt_check_clock_frequency(const struct intel_gt *gt); > static inline void intel_gt_check_clock_frequency(const struct intel_gt *gt) {} > #endif > > -u32 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u32 count); > -u32 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u32 count); > +u64 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u64 count); > +u64 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u64 count); > > -u32 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u32 ns); > -u32 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u32 ns); > +u64 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u64 ns); > +u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns); > > #endif /* __INTEL_GT_CLOCK_UTILS_H__ */ > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h > index c7bde529feab..a83d3e18254d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h > @@ -75,6 +75,7 @@ struct intel_gt { > intel_wakeref_t awake; > > u32 clock_frequency; > + u32 clock_period_ns; > > struct intel_llc llc; > struct intel_rc6 rc6; > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > index d88504a5d69c..ca080445695e 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > @@ -156,7 +156,7 @@ static int __live_engine_timestamps(struct intel_engine_cs *engine) > d_ring = trifilter(s_ring); > d_ctx = trifilter(s_ctx); > > - pr_info("%s elapsed:%lldns, CTX_TIMESTAMP:%dns, RING_TIMESTAMP:%dns\n", > + pr_info("%s elapsed:%lldns, CTX_TIMESTAMP:%lldns, RING_TIMESTAMP:%lldns\n", > engine->name, dt, > intel_gt_clock_interval_to_ns(engine->gt, d_ctx), > intel_gt_clock_interval_to_ns(engine->gt, d_ring)); > @@ -171,11 +171,11 @@ static int __live_engine_timestamps(struct intel_engine_cs *engine) > d_ring = trifilter(s_ring); > d_ctx = trifilter(s_ctx); > > - d_ctx *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz; > + d_ctx *= engine->gt->clock_frequency; > if (IS_ICELAKE(engine->i915)) > d_ring *= 12500000; /* Fixed 80ns for icl ctx timestamp? */ > else > - d_ring *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz; > + d_ring *= engine->gt->clock_frequency; > > if (3 * d_ctx > 4 * d_ring || 4 * d_ctx < 3 * d_ring) { > pr_err("%s Mismatch between ring and context timestamps!\n", > diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > index 6180a47c1b51..5d911f724ebe 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > @@ -71,7 +71,7 @@ static int live_gt_clocks(void *arg) > enum intel_engine_id id; > int err = 0; > > - if (!RUNTIME_INFO(gt->i915)->cs_timestamp_frequency_hz) { /* unknown */ > + if (!gt->clock_frequency) { /* unknown */ > pr_info("CS_TIMESTAMP frequency unknown\n"); > return 0; > } > @@ -112,12 +112,12 @@ static int live_gt_clocks(void *arg) > > measure_clocks(engine, &cycles, &dt); > > - time = i915_cs_timestamp_ticks_to_ns(engine->i915, cycles); > - expected = i915_cs_timestamp_ns_to_ticks(engine->i915, dt); > + time = intel_gt_clock_interval_to_ns(engine->gt, cycles); > + expected = intel_gt_ns_to_clock_interval(engine->gt, dt); > > pr_info("%s: TIMESTAMP %d cycles [%lldns] in %lldns [%d cycles], using CS clock frequency of %uKHz\n", > engine->name, cycles, time, dt, expected, > - RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz / 1000); > + engine->gt->clock_frequency / 1000); > > if (9 * time < 8 * dt || 8 * time > 9 * dt) { > pr_err("%s: CS ticks did not match walltime!\n", > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index c72160e3702f..7332478a3dd5 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -635,27 +635,27 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); > seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); > seq_printf(m, "CAGF: %dMHz\n", cagf); > - seq_printf(m, "RP CUR UP EI: %d (%dns)\n", > + seq_printf(m, "RP CUR UP EI: %d (%lldns)\n", > rpupei, > intel_gt_pm_interval_to_ns(&dev_priv->gt, rpupei)); > - seq_printf(m, "RP CUR UP: %d (%dun)\n", > + seq_printf(m, "RP CUR UP: %d (%lldun)\n", > rpcurup, > intel_gt_pm_interval_to_ns(&dev_priv->gt, rpcurup)); > - seq_printf(m, "RP PREV UP: %d (%dns)\n", > + seq_printf(m, "RP PREV UP: %d (%lldns)\n", > rpprevup, > intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevup)); > seq_printf(m, "Up threshold: %d%%\n", > rps->power.up_threshold); > > - seq_printf(m, "RP CUR DOWN EI: %d (%dns)\n", > + seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n", > rpdownei, > intel_gt_pm_interval_to_ns(&dev_priv->gt, > rpdownei)); > - seq_printf(m, "RP CUR DOWN: %d (%dns)\n", > + seq_printf(m, "RP CUR DOWN: %d (%lldns)\n", > rpcurdown, > intel_gt_pm_interval_to_ns(&dev_priv->gt, > rpcurdown)); > - seq_printf(m, "RP PREV DOWN: %d (%dns)\n", > + seq_printf(m, "RP PREV DOWN: %d (%lldns)\n", > rpprevdown, > intel_gt_pm_interval_to_ns(&dev_priv->gt, > rpprevdown)); > @@ -862,8 +862,9 @@ static int i915_engine_info(struct seq_file *m, void *unused) > yesno(i915->gt.awake), > atomic_read(&i915->gt.wakeref.count), > ktime_to_ms(intel_gt_get_awake_time(&i915->gt))); > - seq_printf(m, "CS timestamp frequency: %u Hz\n", > - RUNTIME_INFO(i915)->cs_timestamp_frequency_hz); > + seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", > + i915->gt.clock_frequency, > + i915->gt.clock_period_ns); > > p = drm_seq_file_printer(m); > for_each_uabi_engine(engine, i915) > @@ -949,7 +950,7 @@ i915_perf_noa_delay_set(void *data, u64 val) > * This would lead to infinite waits as we're doing timestamp > * difference on the CS with only 32bits. > */ > - if (i915_cs_timestamp_ns_to_ticks(i915, val) > U32_MAX) > + if (intel_gt_ns_to_clock_interval(&i915->gt, val) > U32_MAX) > return -EINVAL; > > atomic64_set(&i915->perf.noa_programming_delay, val); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 4a8ff2a899a5..e38a10d5c128 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2003,16 +2003,4 @@ i915_coherent_map_type(struct drm_i915_private *i915) > return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; > } > > -static inline u64 i915_cs_timestamp_ns_to_ticks(struct drm_i915_private *i915, u64 val) > -{ > - return DIV_ROUND_UP_ULL(val * RUNTIME_INFO(i915)->cs_timestamp_frequency_hz, > - 1000000000); > -} > - > -static inline u64 i915_cs_timestamp_ticks_to_ns(struct drm_i915_private *i915, u64 val) > -{ > - return div_u64(val * 1000000000, > - RUNTIME_INFO(i915)->cs_timestamp_frequency_hz); > -} > - > #endif > diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c > index f96032c60a12..75c3bfc2486e 100644 > --- a/drivers/gpu/drm/i915/i915_getparam.c > +++ b/drivers/gpu/drm/i915/i915_getparam.c > @@ -154,7 +154,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, > return -ENODEV; > break; > case I915_PARAM_CS_TIMESTAMP_FREQUENCY: > - value = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz; > + value = i915->gt.clock_frequency; > break; > case I915_PARAM_MMAP_GTT_COHERENT: > value = INTEL_INFO(i915)->has_coherent_ggtt; > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index d8cac4c5881f..8b163ee1b86d 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -485,7 +485,7 @@ static void error_print_context(struct drm_i915_error_state_buf *m, > const char *header, > const struct i915_gem_context_coredump *ctx) > { > - const u32 period = RUNTIME_INFO(m->i915)->cs_timestamp_period_ns; > + const u32 period = m->i915->gt.clock_period_ns; > > err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", > header, ctx->comm, ctx->pid, ctx->sched_attr.priority, > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index f65c32bd970e..112ba5f2ce90 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -201,6 +201,7 @@ > #include "gt/intel_execlists_submission.h" > #include "gt/intel_gpu_commands.h" > #include "gt/intel_gt.h" > +#include "gt/intel_gt_clock_utils.h" > #include "gt/intel_lrc.h" > #include "gt/intel_ring.h" > > @@ -1637,7 +1638,8 @@ static int alloc_noa_wait(struct i915_perf_stream *stream) > struct drm_i915_gem_object *bo; > struct i915_vma *vma; > const u64 delay_ticks = 0xffffffffffffffff - > - i915_cs_timestamp_ns_to_ticks(i915, atomic64_read(&stream->perf->noa_programming_delay)); > + intel_gt_ns_to_clock_interval(stream->perf->i915->ggtt.vm.gt, > + atomic64_read(&stream->perf->noa_programming_delay)); > const u32 base = stream->engine->mmio_base; > #define CS_GPR(x) GEN8_RING_CS_GPR(base, x) > u32 *batch, *ts0, *cs, *jump; > @@ -3518,7 +3520,8 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf, > > static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent) > { > - return i915_cs_timestamp_ticks_to_ns(perf->i915, 2ULL << exponent); > + return intel_gt_clock_interval_to_ns(perf->i915->ggtt.vm.gt, > + 2ULL << exponent); > } > > /** > @@ -4372,8 +4375,8 @@ void i915_perf_init(struct drm_i915_private *i915) > if (perf->ops.enable_metric_set) { > mutex_init(&perf->lock); > > - oa_sample_rate_hard_limit = > - RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 2; > + /* Choose a representative limit */ > + oa_sample_rate_hard_limit = i915->gt.clock_frequency / 2; > > mutex_init(&perf->metrics_lock); > idr_init_base(&perf->metrics_idr, 1); > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index ef767f04c37c..f2d5ae59081e 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -117,150 +117,6 @@ void intel_device_info_print_runtime(const struct intel_runtime_info *info, > struct drm_printer *p) > { > drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); > - drm_printf(p, "CS timestamp frequency: %u Hz\n", > - info->cs_timestamp_frequency_hz); > -} > - > -static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) > -{ > - u32 ts_override = intel_uncore_read(&dev_priv->uncore, > - GEN9_TIMESTAMP_OVERRIDE); > - u32 base_freq, frac_freq; > - > - base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> > - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; > - base_freq *= 1000000; > - > - frac_freq = ((ts_override & > - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> > - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); > - frac_freq = 1000000 / (frac_freq + 1); > - > - return base_freq + frac_freq; > -} > - > -static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv, > - u32 rpm_config_reg) > -{ > - u32 f19_2_mhz = 19200000; > - u32 f24_mhz = 24000000; > - u32 crystal_clock = (rpm_config_reg & > - GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> > - GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; > - > - switch (crystal_clock) { > - case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: > - return f19_2_mhz; > - case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: > - return f24_mhz; > - default: > - MISSING_CASE(crystal_clock); > - return 0; > - } > -} > - > -static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv, > - u32 rpm_config_reg) > -{ > - u32 f19_2_mhz = 19200000; > - u32 f24_mhz = 24000000; > - u32 f25_mhz = 25000000; > - u32 f38_4_mhz = 38400000; > - u32 crystal_clock = (rpm_config_reg & > - GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> > - GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; > - > - switch (crystal_clock) { > - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: > - return f24_mhz; > - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: > - return f19_2_mhz; > - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ: > - return f38_4_mhz; > - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ: > - return f25_mhz; > - default: > - MISSING_CASE(crystal_clock); > - return 0; > - } > -} > - > -static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) > -{ > - struct intel_uncore *uncore = &dev_priv->uncore; > - u32 f12_5_mhz = 12500000; > - u32 f19_2_mhz = 19200000; > - u32 f24_mhz = 24000000; > - > - if (INTEL_GEN(dev_priv) <= 4) { > - /* PRMs say: > - * > - * "The value in this register increments once every 16 > - * hclks." (through the “Clocking Configuration” > - * (“CLKCFG”) MCHBAR register) > - */ > - return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000 / 16; > - } else if (INTEL_GEN(dev_priv) <= 8) { > - /* PRMs say: > - * > - * "The PCU TSC counts 10ns increments; this timestamp > - * reflects bits 38:3 of the TSC (i.e. 80ns granularity, > - * rolling over every 1.5 hours). > - */ > - return f12_5_mhz; > - } else if (INTEL_GEN(dev_priv) <= 9) { > - u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); > - u32 freq = 0; > - > - if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { > - freq = read_reference_ts_freq(dev_priv); > - } else { > - freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; > - > - /* Now figure out how the command stream's timestamp > - * register increments from this frequency (it might > - * increment only every few clock cycle). > - */ > - freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> > - CTC_SHIFT_PARAMETER_SHIFT); > - } > - > - return freq; > - } else if (INTEL_GEN(dev_priv) <= 12) { > - u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); > - u32 freq = 0; > - > - /* First figure out the reference frequency. There are 2 ways > - * we can compute the frequency, either through the > - * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE > - * tells us which one we should use. > - */ > - if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { > - freq = read_reference_ts_freq(dev_priv); > - } else { > - u32 rpm_config_reg = intel_uncore_read(uncore, RPM_CONFIG0); > - > - if (INTEL_GEN(dev_priv) <= 10) > - freq = gen10_get_crystal_clock_freq(dev_priv, > - rpm_config_reg); > - else > - freq = gen11_get_crystal_clock_freq(dev_priv, > - rpm_config_reg); > - > - /* Now figure out how the command stream's timestamp > - * register increments from this frequency (it might > - * increment only every few clock cycle). > - */ > - freq >>= 3 - ((rpm_config_reg & > - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> > - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); > - } > - > - return freq; > - } > - > - MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n"); > - return 0; > } > > #undef INTEL_VGA_DEVICE > @@ -505,19 +361,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > runtime->rawclk_freq = intel_read_rawclk(dev_priv); > drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); > > - /* Initialize command stream timestamp frequency */ > - runtime->cs_timestamp_frequency_hz = > - read_timestamp_frequency(dev_priv); > - if (runtime->cs_timestamp_frequency_hz) { > - runtime->cs_timestamp_period_ns = > - i915_cs_timestamp_ticks_to_ns(dev_priv, 1); > - drm_dbg(&dev_priv->drm, > - "CS timestamp wraparound in %lldms\n", > - div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns, > - S32_MAX), > - USEC_PER_SEC)); > - } > - > if (!HAS_DISPLAY(dev_priv)) { > dev_priv->drm.driver_features &= ~(DRIVER_MODESET | > DRIVER_ATOMIC); > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index d92fa041c700..17d0fdb94d2d 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -224,9 +224,6 @@ struct intel_runtime_info { > u8 num_scalers[I915_MAX_PIPES]; > > u32 rawclk_freq; > - > - u32 cs_timestamp_frequency_hz; > - u32 cs_timestamp_period_ns; > }; > > struct intel_driver_caps { > diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c > index debbac660519..e9d86dab8677 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_perf.c > +++ b/drivers/gpu/drm/i915/selftests/i915_perf.c > @@ -262,7 +262,7 @@ static int live_noa_delay(void *arg) > > delay = intel_read_status_page(stream->engine, 0x102); > delay -= intel_read_status_page(stream->engine, 0x100); > - delay = i915_cs_timestamp_ticks_to_ns(i915, delay); > + delay = intel_gt_clock_interval_to_ns(stream->engine->gt, delay); > pr_info("GPU delay: %uns, expected %lluns\n", > delay, expected); > > diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c > index e424a6d1a68c..ddf76069066e 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_request.c > +++ b/drivers/gpu/drm/i915/selftests/i915_request.c > @@ -33,6 +33,7 @@ > #include "gt/intel_engine_pm.h" > #include "gt/intel_engine_user.h" > #include "gt/intel_gt.h" > +#include "gt/intel_gt_clock_utils.h" > #include "gt/intel_gt_requests.h" > #include "gt/selftest_engine_heartbeat.h" > > @@ -1560,7 +1561,7 @@ static u32 trifilter(u32 *a) > > static u64 cycles_to_ns(struct intel_engine_cs *engine, u32 cycles) > { > - u64 ns = i915_cs_timestamp_ticks_to_ns(engine->i915, cycles); > + u64 ns = intel_gt_clock_interval_to_ns(engine->gt, cycles); > > return DIV_ROUND_CLOSEST(ns, 1 << TF_BIAS); > } > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock 2020-12-23 12:23 [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson 2020-12-23 12:23 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Consolidate the CS timestamp clocks Chris Wilson @ 2020-12-23 14:56 ` Mika Kuoppala 2020-12-23 15:01 ` Chris Wilson 2020-12-23 17:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] " Patchwork ` (2 subsequent siblings) 4 siblings, 1 reply; 8+ messages in thread From: Mika Kuoppala @ 2020-12-23 14:56 UTC (permalink / raw) To: Chris Wilson, intel-gfx; +Cc: Chris Wilson Chris Wilson <chris@chris-wilson.co.uk> writes: > We assume that both timestamps are driven off the same clock [reported > to userspace as I915_PARAM_CS_TIMESTAMP_FREQUENCY]. Verify that this is > so by reading the timestamp registers around a busywait (on an otherwise > idle engine so there should be no preemptions). > > v2: Icelake (not ehl, nor tgl) seems to be using a fixed 80ns interval > for, and only for, CTX_TIMESTAMP -- or it may be GPU frequency and the > test is always running at maximum frequency?. As far as I can tell, this > isolated change in behaviour is undocumented. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 203 ++++++++++++++++++- > 1 file changed, 202 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > index 163a10b07f85..d88504a5d69c 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > @@ -4,15 +4,215 @@ > * Copyright © 2018 Intel Corporation > */ > > -#include "intel_gpu_commands.h" > +#include <linux/sort.h> > > #include "i915_selftest.h" > +#include "intel_gpu_commands.h" > +#include "intel_gt_clock_utils.h" > #include "selftest_engine.h" > #include "selftest_engine_heartbeat.h" > #include "selftests/igt_atomic.h" > #include "selftests/igt_flush_test.h" > #include "selftests/igt_spinner.h" > > +#define COUNT 5 > + > +static int cmp_u64(const void *A, const void *B) > +{ > + const u64 *a = A, *b = B; > + > + return *a - *b; > +} > + > +static u64 trifilter(u64 *a) > +{ > + sort(a, COUNT, sizeof(*a), cmp_u64, NULL); > + return (a[1] + 2 * a[2] + a[3]) >> 2; > +} > + > +static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) > +{ > + *cs++ = MI_SEMAPHORE_WAIT | > + MI_SEMAPHORE_GLOBAL_GTT | > + MI_SEMAPHORE_POLL | > + op; > + *cs++ = value; > + *cs++ = offset; > + *cs++ = 0; > + > + return cs; > +} > + > +static u32 *emit_store(u32 *cs, u32 offset, u32 value) > +{ > + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; > + *cs++ = offset; > + *cs++ = 0; > + *cs++ = value; > + > + return cs; > +} > + > +static u32 *emit_srm(u32 *cs, i915_reg_t reg, u32 offset) > +{ > + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; > + *cs++ = i915_mmio_reg_offset(reg); > + *cs++ = offset; > + *cs++ = 0; > + > + return cs; > +} > + > +static void write_semaphore(u32 *x, u32 value) > +{ > + WRITE_ONCE(*x, value); > + wmb(); > +} > + > +static int __measure_timestamps(struct intel_context *ce, > + u64 *dt, u64 *d_ring, u64 *d_ctx) > +{ > + struct intel_engine_cs *engine = ce->engine; > + u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5); > + u32 offset = i915_ggtt_offset(engine->status_page.vma); > + struct i915_request *rq; > + u32 *cs; > + > + rq = intel_context_create_request(ce); > + if (IS_ERR(rq)) > + return PTR_ERR(rq); > + > + cs = intel_ring_begin(rq, 28); > + if (IS_ERR(cs)) { > + i915_request_add(rq); > + return PTR_ERR(cs); > + } > + > + /* Signal & wait for start */ > + cs = emit_store(cs, offset + 4008, 1); > + cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_NEQ_SDD, 1); > + > + cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000); > + cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004); > + > + /* Busy wait */ > + cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_EQ_SDD, 1); > + > + cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016); > + cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012); > + > + intel_ring_advance(rq, cs); > + i915_request_get(rq); > + i915_request_add(rq); > + intel_engine_flush_submission(engine); > + > + /* Wait for the request to start executing, that then waits for us */ > + while (READ_ONCE(sema[2]) == 0) > + cpu_relax(); > + > + /* Run the request for a 100us, sampling timestamps before/after */ > + preempt_disable(); > + *dt = ktime_get_raw_fast_ns(); > + write_semaphore(&sema[2], 0); > + udelay(100); > + write_semaphore(&sema[2], 1); > + *dt = ktime_get_raw_fast_ns() - *dt; > + preempt_enable(); > + > + if (i915_request_wait(rq, 0, HZ / 2) < 0) { > + i915_request_put(rq); > + return -ETIME; > + } > + i915_request_put(rq); > + > + pr_debug("%s CTX_TIMESTAMP: [%x, %x], RING_TIMESTAMP: [%x, %x]\n", > + engine->name, sema[1], sema[3], sema[0], sema[4]); > + > + *d_ctx = sema[3] - sema[1]; > + *d_ring = sema[4] - sema[0]; > + return 0; > +} > + > +static int __live_engine_timestamps(struct intel_engine_cs *engine) > +{ > + u64 s_ring[COUNT], s_ctx[COUNT], st[COUNT], d_ring, d_ctx, dt; > + struct intel_context *ce; > + int i, err = 0; > + > + ce = intel_context_create(engine); > + if (IS_ERR(ce)) > + return PTR_ERR(ce); > + > + for (i = 0; i < COUNT; i++) { > + err = __measure_timestamps(ce, &st[i], &s_ring[i], &s_ctx[i]); > + if (err) > + break; > + } > + intel_context_put(ce); > + if (err) > + return err; > + > + dt = trifilter(st); > + d_ring = trifilter(s_ring); > + d_ctx = trifilter(s_ctx); > + > + pr_info("%s elapsed:%lldns, CTX_TIMESTAMP:%dns, RING_TIMESTAMP:%dns\n", > + engine->name, dt, > + intel_gt_clock_interval_to_ns(engine->gt, d_ctx), > + intel_gt_clock_interval_to_ns(engine->gt, d_ring)); > + > + d_ring = intel_gt_clock_interval_to_ns(engine->gt, d_ring); > + if (3 * dt > 4 * d_ring || 4 * dt < 3 * d_ring) { > + pr_err("%s Mismatch between ring timestamp and walltime!\n", > + engine->name); > + return -EINVAL; > + } > + > + d_ring = trifilter(s_ring); > + d_ctx = trifilter(s_ctx); > + > + d_ctx *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz; > + if (IS_ICELAKE(engine->i915)) > + d_ring *= 12500000; /* Fixed 80ns for icl ctx timestamp? */ This is...weird. But I am not going to argue against hardware. Will be interesting to see if this can find something funny. Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > + else > + d_ring *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz; > + > + if (3 * d_ctx > 4 * d_ring || 4 * d_ctx < 3 * d_ring) { > + pr_err("%s Mismatch between ring and context timestamps!\n", > + engine->name); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int live_engine_timestamps(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct intel_engine_cs *engine; > + enum intel_engine_id id; > + > + /* > + * Check that CS_TIMESTAMP / CTX_TIMESTAMP are in sync, i.e. share > + * the same CS clock. > + */ > + > + if (INTEL_GEN(gt->i915) < 8) > + return 0; > + > + for_each_engine(engine, gt, id) { > + int err; > + > + st_engine_heartbeat_disable(engine); > + err = __live_engine_timestamps(engine); > + st_engine_heartbeat_enable(engine); > + if (err) > + return err; > + } > + > + return 0; > +} > + > static int live_engine_busy_stats(void *arg) > { > struct intel_gt *gt = arg; > @@ -179,6 +379,7 @@ static int live_engine_pm(void *arg) > int live_engine_pm_selftests(struct intel_gt *gt) > { > static const struct i915_subtest tests[] = { > + SUBTEST(live_engine_timestamps), > SUBTEST(live_engine_busy_stats), > SUBTEST(live_engine_pm), > }; > -- > 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock 2020-12-23 14:56 ` [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock Mika Kuoppala @ 2020-12-23 15:01 ` Chris Wilson 0 siblings, 0 replies; 8+ messages in thread From: Chris Wilson @ 2020-12-23 15:01 UTC (permalink / raw) To: Mika Kuoppala, intel-gfx Quoting Mika Kuoppala (2020-12-23 14:56:06) > Chris Wilson <chris@chris-wilson.co.uk> writes: > > + d_ctx *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz; > > + if (IS_ICELAKE(engine->i915)) > > + d_ring *= 12500000; /* Fixed 80ns for icl ctx timestamp? */ > > This is...weird. But I am not going to argue against hardware. > > Will be interesting to see if this can find something funny. Well it already found the icl funny :( I didn't appreciate the joke myself. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock 2020-12-23 12:23 [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson 2020-12-23 12:23 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Consolidate the CS timestamp clocks Chris Wilson 2020-12-23 14:56 ` [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock Mika Kuoppala @ 2020-12-23 17:18 ` Patchwork 2020-12-23 17:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-12-23 22:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 4 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2020-12-23 17:18 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock URL : https://patchwork.freedesktop.org/series/85187/ State : warning == Summary == $ dim checkpatch origin/drm-tip cfe0bee68e21 drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock -:92: WARNING:MEMORY_BARRIER: memory barrier without comment #92: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:69: + wmb(); -:140: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #140: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:117: + udelay(100); total: 0 errors, 1 warnings, 1 checks, 223 lines checked 4664d259d344 drm/i915/gt: Consolidate the CS timestamp clocks _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock 2020-12-23 12:23 [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson ` (2 preceding siblings ...) 2020-12-23 17:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] " Patchwork @ 2020-12-23 17:48 ` Patchwork 2020-12-23 22:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 4 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2020-12-23 17:48 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 3437 bytes --] == Series Details == Series: series starting with [1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock URL : https://patchwork.freedesktop.org/series/85187/ State : success == Summary == CI Bug Log - changes from CI_DRM_9517 -> Patchwork_19204 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/index.html Known issues ------------ Here are the changes found in Patchwork_19204 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_suspend@basic-s3: - fi-skl-6600u: [PASS][1] -> [INCOMPLETE][2] ([i915#146] / [i915#198]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html * igt@gem_linear_blits@basic: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/fi-tgl-y/igt@gem_linear_blits@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/fi-tgl-y/igt@gem_linear_blits@basic.html * igt@i915_module_load@reload: - fi-kbl-7500u: [PASS][5] -> [DMESG-WARN][6] ([i915#2605]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/fi-kbl-7500u/igt@i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/fi-kbl-7500u/igt@i915_module_load@reload.html #### Possible fixes #### * igt@gem_mmap_gtt@basic: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/fi-tgl-y/igt@gem_mmap_gtt@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/fi-tgl-y/igt@gem_mmap_gtt@basic.html * igt@i915_selftest@live@active: - fi-icl-y: [DMESG-FAIL][9] ([i915#2291]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/fi-icl-y/igt@i915_selftest@live@active.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/fi-icl-y/igt@i915_selftest@live@active.html [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) ------------------------------ Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes ------------- * Linux: CI_DRM_9517 -> Patchwork_19204 CI-20190529: 20190529 CI_DRM_9517: 325ec6b5e94e6b2b5c9be9a8234fdf698c2ee18d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5920: 05dbccbbc2e57403730134580c4110bde85576f4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19204: 4664d259d344e97218f598d69d136d168195a87b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4664d259d344 drm/i915/gt: Consolidate the CS timestamp clocks cfe0bee68e21 drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/index.html [-- Attachment #1.2: Type: text/html, Size: 4231 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock 2020-12-23 12:23 [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson ` (3 preceding siblings ...) 2020-12-23 17:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2020-12-23 22:38 ` Patchwork 4 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2020-12-23 22:38 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 18133 bytes --] == Series Details == Series: series starting with [1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock URL : https://patchwork.freedesktop.org/series/85187/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9517_full -> Patchwork_19204_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_19204_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19204_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_19204_full: ### IGT changes ### #### Possible regressions #### * igt@gem_sync@basic-each: - shard-glk: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-glk4/igt@gem_sync@basic-each.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-glk8/igt@gem_sync@basic-each.html Known issues ------------ Here are the changes found in Patchwork_19204_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@bcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html * igt@gem_exec_reloc@basic-parallel: - shard-kbl: NOTRUN -> [TIMEOUT][5] ([i915#1729]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-kbl2/igt@gem_exec_reloc@basic-parallel.html * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#198]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-skl1/igt@i915_pm_backlight@fade_with_suspend.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl1/igt@i915_pm_backlight@fade_with_suspend.html * igt@i915_pm_dc@dc6-dpms: - shard-kbl: NOTRUN -> [FAIL][8] ([i915#454]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-kbl2/igt@i915_pm_dc@dc6-dpms.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#454]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-iclb8/igt@i915_pm_dc@dc6-psr.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-iclb6/igt@i915_pm_dc@dc6-psr.html * igt@kms_chamelium@dp-audio: - shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-glk4/igt@kms_chamelium@dp-audio.html * igt@kms_color_chamelium@pipe-b-ctm-limited-range: - shard-kbl: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-kbl2/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html * igt@kms_color_chamelium@pipe-d-degamma: - shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl1/igt@kms_color_chamelium@pipe-d-degamma.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen: - shard-skl: [PASS][14] -> [FAIL][15] ([i915#54]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html * igt@kms_cursor_crc@pipe-d-cursor-128x128-offscreen: - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271]) +32 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-kbl2/igt@kms_cursor_crc@pipe-d-cursor-128x128-offscreen.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#2346]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2642]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs: - shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2672]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-kbl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen: - shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271]) +41 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][22] -> [FAIL][23] ([i915#1188]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-skl6/igt@kms_hdr@bpc-switch-suspend.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d: - shard-glk: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#533]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-glk4/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: - shard-kbl: NOTRUN -> [FAIL][25] ([i915#265]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-skl: NOTRUN -> [FAIL][26] ([fdo#108145] / [i915#265]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: - shard-glk: NOTRUN -> [FAIL][27] ([fdo#108145] / [i915#265]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-glk4/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html * igt@kms_plane_cursor@pipe-d-viewport-size-256: - shard-glk: NOTRUN -> [SKIP][28] ([fdo#109271]) +16 similar issues [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-glk4/igt@kms_plane_cursor@pipe-d-viewport-size-256.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-iclb8/igt@kms_psr@psr2_sprite_render.html * igt@kms_writeback@writeback-check-output: - shard-skl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#2437]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl1/igt@kms_writeback@writeback-check-output.html * igt@perf@polling-small-buf: - shard-skl: NOTRUN -> [FAIL][32] ([i915#1722]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl8/igt@perf@polling-small-buf.html #### Possible fixes #### * {igt@gem_exec_balancer@fairslice}: - shard-iclb: [FAIL][33] ([i915#2802]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-iclb4/igt@gem_exec_balancer@fairslice.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-iclb6/igt@gem_exec_balancer@fairslice.html * {igt@gem_exec_fair@basic-none-solo@rcs0}: - shard-glk: [FAIL][35] ([i915#2842]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-glk9/igt@gem_exec_fair@basic-none-solo@rcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-glk1/igt@gem_exec_fair@basic-none-solo@rcs0.html * {igt@gem_exec_fair@basic-none@bcs0}: - shard-iclb: [FAIL][37] ([i915#2842]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-iclb8/igt@gem_exec_fair@basic-none@bcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-iclb8/igt@gem_exec_fair@basic-none@bcs0.html * {igt@gem_exec_fair@basic-none@rcs0}: - shard-kbl: [FAIL][39] ([i915#2842]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-kbl4/igt@gem_exec_fair@basic-none@rcs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-kbl3/igt@gem_exec_fair@basic-none@rcs0.html * {igt@gem_exec_schedule@u-fairslice@vcs0}: - shard-skl: [DMESG-WARN][41] ([i915#1610]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-skl10/igt@gem_exec_schedule@u-fairslice@vcs0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl1/igt@gem_exec_schedule@u-fairslice@vcs0.html * igt@i915_suspend@forcewake: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-kbl6/igt@i915_suspend@forcewake.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-kbl2/igt@i915_suspend@forcewake.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-random: - shard-skl: [FAIL][45] ([i915#54]) -> [PASS][46] +3 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1: - shard-kbl: [INCOMPLETE][47] ([i915#155] / [i915#180]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html * igt@kms_flip@plain-flip-fb-recreate@b-edp1: - shard-skl: [FAIL][49] ([i915#2122]) -> [PASS][50] +3 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl6/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][51] ([fdo#108145] / [i915#265]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html * igt@perf@polling: - shard-skl: [FAIL][55] ([i915#1542]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-skl1/igt@perf@polling.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl1/igt@perf@polling.html #### Warnings #### * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][57] ([i915#658]) -> [SKIP][58] ([i915#588]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-iclb4/igt@i915_pm_dc@dc3co-vpb-simulation.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][59] ([i915#1804] / [i915#2684]) -> [WARN][60] ([i915#2681] / [i915#2684]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html * igt@runner@aborted: - shard-kbl: ([FAIL][61], [FAIL][62], [FAIL][63], [FAIL][64]) ([i915#1814] / [i915#2295] / [i915#483] / [i915#602]) -> ([FAIL][65], [FAIL][66], [FAIL][67]) ([i915#1436] / [i915#1814] / [i915#2295] / [i915#483] / [i915#602]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-kbl1/igt@runner@aborted.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-kbl4/igt@runner@aborted.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-kbl6/igt@runner@aborted.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-kbl2/igt@runner@aborted.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-kbl4/igt@runner@aborted.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-kbl2/igt@runner@aborted.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-kbl6/igt@runner@aborted.html - shard-iclb: ([FAIL][68], [FAIL][69]) ([i915#1814] / [i915#2295] / [i915#2724] / [i915#483]) -> ([FAIL][70], [FAIL][71]) ([i915#1814] / [i915#2295] / [i915#2724]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-iclb7/igt@runner@aborted.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-iclb5/igt@runner@aborted.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-iclb4/igt@runner@aborted.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-iclb3/igt@runner@aborted.html - shard-skl: ([FAIL][72], [FAIL][73]) ([i915#2295] / [i915#2426]) -> [FAIL][74] ([i915#2295] / [i915#483]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-skl8/igt@runner@aborted.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9517/shard-skl10/igt@runner@aborted.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/shard-skl7/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722 [i915#1729]: https://gitlab.freedesktop.org/drm/intel/issues/1729 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724 [i915#2802]: https://gitlab.freedesktop.org/drm/intel/issues/2802 [i915#2804]: https://gitlab.freedesktop.org/drm/intel/issues/2804 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_9517 -> Patchwork_19204 CI-20190529: 20190529 CI_DRM_9517: 325ec6b5e94e6b2b5c9be9a8234fdf698c2ee18d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5920: 05dbccbbc2e57403730134580c4110bde85576f4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19204: 4664d259d344e97218f598d69d136d168195a87b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19204/index.html [-- Attachment #1.2: Type: text/html, Size: 22396 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-12-23 22:38 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-12-23 12:23 [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson 2020-12-23 12:23 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Consolidate the CS timestamp clocks Chris Wilson 2020-12-23 14:36 ` Mika Kuoppala 2020-12-23 14:56 ` [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clock Mika Kuoppala 2020-12-23 15:01 ` Chris Wilson 2020-12-23 17:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] " Patchwork 2020-12-23 17:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-12-23 22:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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