* [PATCH v3 3/5] soc: add polarfire soc system controller
@ 2020-12-23 16:33 ` conor.dooley
0 siblings, 0 replies; 4+ messages in thread
From: conor.dooley @ 2020-12-23 16:33 UTC (permalink / raw)
To: robh+dt, damien.lemoal, jassisinghbrar, aou, paul.walmsley,
palmer, devicetree, linux-riscv
Cc: lewis.hanly, cyril.jean, daire.mcnamara, atish.patra, anup.patel,
david.abdurachmanov, j.neuschaefer, Conor Dooley
From: Conor Dooley <conor.dooley@microchip.com>
This driver provides an interface for other drivers to access the
functions of the system controller on the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/microchip/Kconfig | 10 ++
drivers/soc/microchip/Makefile | 1 +
drivers/soc/microchip/mpfs-sys-controller.c | 127 ++++++++++++++++++++
5 files changed, 140 insertions(+)
create mode 100644 drivers/soc/microchip/Kconfig
create mode 100644 drivers/soc/microchip/Makefile
create mode 100644 drivers/soc/microchip/mpfs-sys-controller.c
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 425ab6f7e375..22cb097bcbdc 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -9,6 +9,7 @@ source "drivers/soc/bcm/Kconfig"
source "drivers/soc/fsl/Kconfig"
source "drivers/soc/imx/Kconfig"
source "drivers/soc/ixp4xx/Kconfig"
+source "drivers/soc/microchip/Kconfig"
source "drivers/soc/mediatek/Kconfig"
source "drivers/soc/qcom/Kconfig"
source "drivers/soc/renesas/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 36452bed86ef..fb084cf2d12e 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_GEMINI) += gemini/
obj-y += imx/
obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/
obj-$(CONFIG_SOC_XWAY) += lantiq/
+obj-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip/
obj-y += mediatek/
obj-y += amlogic/
obj-y += qcom/
diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig
new file mode 100644
index 000000000000..eb656b33156b
--- /dev/null
+++ b/drivers/soc/microchip/Kconfig
@@ -0,0 +1,10 @@
+config POLARFIRE_SOC_SYS_CTRL
+ tristate "POLARFIRE_SOC_SYS_CTRL"
+ depends on POLARFIRE_SOC_MAILBOX
+ help
+ This driver adds support for the PolarFire SoC (MPFS) system controller.
+
+ To compile this driver as a module, choose M here. the
+ module will be called mpfs_system_controller.
+
+ If unsure, say N.
diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile
new file mode 100644
index 000000000000..14489919fe4b
--- /dev/null
+++ b/drivers/soc/microchip/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL) += mpfs-sys-controller.o
diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c
new file mode 100644
index 000000000000..e8b44beb5ac5
--- /dev/null
+++ b/drivers/soc/microchip/mpfs-sys-controller.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Microchip PolarFire SoC (MPFS) system controller driver
+ *
+ * Copyright (c) 2020 Microchip Corporation. All rights reserved.
+ *
+ * Author: Conor Dooley <conor.dooley@microchip.com>
+ *
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+#include <linux/mailbox_client.h>
+#include <linux/platform_device.h>
+#include <soc/microchip/mpfs.h>
+
+static DEFINE_MUTEX(transaction_lock);
+
+struct mpfs_sys_controller {
+ struct mbox_client client;
+ struct mbox_chan *chan;
+ struct completion c;
+ u32 enabled;
+ void *response;
+ u16 response_size_bytes;
+};
+
+int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg,
+ void *response, u16 response_size_bytes)
+{
+ int ret;
+
+ mpfs_client->response = response;
+ mpfs_client->response_size_bytes = response_size_bytes;
+
+ mutex_lock_interruptible(&transaction_lock);
+
+ reinit_completion(&mpfs_client->c);
+
+ ret = mbox_send_message(mpfs_client->chan, msg);
+ if (ret >= 0) {
+ if (wait_for_completion_timeout(&mpfs_client->c, HZ)) {
+ ret = 0;
+ } else {
+ ret = -ETIMEDOUT;
+ dev_warn(mpfs_client->client.dev, "MPFS sys controller transaction timeout");
+ }
+ } else {
+ dev_err(mpfs_client->client.dev,
+ "mpfs sys controller transaction returned %d\r\n", ret);
+ }
+
+ mutex_unlock(&transaction_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(mpfs_blocking_transaction);
+
+static void rx_callback(struct mbox_client *client, void *msg)
+{
+ struct mpfs_sys_controller *mpfs_client =
+ container_of(client, struct mpfs_sys_controller, client);
+
+ memcpy(mpfs_client->response, (u8 *)msg, mpfs_client->response_size_bytes);
+
+ complete(&mpfs_client->c);
+}
+
+static int mpfs_sys_controller_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mpfs_sys_controller *mpfs_client;
+
+ mpfs_client = devm_kzalloc(dev, sizeof(*mpfs_client), GFP_KERNEL);
+ if (!mpfs_client)
+ return -ENOMEM;
+
+ mpfs_client->client.dev = dev;
+ mpfs_client->client.rx_callback = rx_callback;
+ mpfs_client->client.tx_block = 1U;
+
+ mpfs_client->chan = mbox_request_channel(&mpfs_client->client, 0);
+ if (IS_ERR(mpfs_client->chan))
+ return dev_err_probe(dev, PTR_ERR(mpfs_client->chan),
+ "Failed to get mbox channel\n");
+
+ init_completion(&mpfs_client->c);
+
+ platform_set_drvdata(pdev, mpfs_client);
+
+ dev_info(&pdev->dev, "Registered MPFS system controller driver\n");
+
+ return 0;
+}
+
+struct mpfs_sys_controller *
+mpfs_sys_controller_get(struct device_node *mss_node)
+{
+ struct platform_device *pdev = of_find_device_by_node(mss_node);
+
+ if (!pdev)
+ return NULL;
+
+ return platform_get_drvdata(pdev);
+}
+EXPORT_SYMBOL(mpfs_sys_controller_get);
+
+static const struct of_device_id mpfs_sys_controller_of_match[] = {
+ {.compatible = "microchip,polarfire-soc-sys-controller", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mpfs_sys_controller_of_match);
+
+static struct platform_driver mpfs_sys_controller_driver = {
+ .driver = {
+ .name = "mpfs-sys-controller",
+ .of_match_table = mpfs_sys_controller_of_match,
+ },
+ .probe = mpfs_sys_controller_probe,
+};
+module_platform_driver(mpfs_sys_controller_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
+MODULE_DESCRIPTION("MPFS system controller driver");
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v3 3/5] soc: add polarfire soc system controller
@ 2020-12-23 16:33 ` conor.dooley
0 siblings, 0 replies; 4+ messages in thread
From: conor.dooley @ 2020-12-23 16:33 UTC (permalink / raw)
To: robh+dt, damien.lemoal, jassisinghbrar, aou, paul.walmsley,
palmer, devicetree, linux-riscv
Cc: cyril.jean, david.abdurachmanov, daire.mcnamara, anup.patel,
j.neuschaefer, atish.patra, Conor Dooley, lewis.hanly
From: Conor Dooley <conor.dooley@microchip.com>
This driver provides an interface for other drivers to access the
functions of the system controller on the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/microchip/Kconfig | 10 ++
drivers/soc/microchip/Makefile | 1 +
drivers/soc/microchip/mpfs-sys-controller.c | 127 ++++++++++++++++++++
5 files changed, 140 insertions(+)
create mode 100644 drivers/soc/microchip/Kconfig
create mode 100644 drivers/soc/microchip/Makefile
create mode 100644 drivers/soc/microchip/mpfs-sys-controller.c
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 425ab6f7e375..22cb097bcbdc 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -9,6 +9,7 @@ source "drivers/soc/bcm/Kconfig"
source "drivers/soc/fsl/Kconfig"
source "drivers/soc/imx/Kconfig"
source "drivers/soc/ixp4xx/Kconfig"
+source "drivers/soc/microchip/Kconfig"
source "drivers/soc/mediatek/Kconfig"
source "drivers/soc/qcom/Kconfig"
source "drivers/soc/renesas/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 36452bed86ef..fb084cf2d12e 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_GEMINI) += gemini/
obj-y += imx/
obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/
obj-$(CONFIG_SOC_XWAY) += lantiq/
+obj-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip/
obj-y += mediatek/
obj-y += amlogic/
obj-y += qcom/
diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig
new file mode 100644
index 000000000000..eb656b33156b
--- /dev/null
+++ b/drivers/soc/microchip/Kconfig
@@ -0,0 +1,10 @@
+config POLARFIRE_SOC_SYS_CTRL
+ tristate "POLARFIRE_SOC_SYS_CTRL"
+ depends on POLARFIRE_SOC_MAILBOX
+ help
+ This driver adds support for the PolarFire SoC (MPFS) system controller.
+
+ To compile this driver as a module, choose M here. the
+ module will be called mpfs_system_controller.
+
+ If unsure, say N.
diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile
new file mode 100644
index 000000000000..14489919fe4b
--- /dev/null
+++ b/drivers/soc/microchip/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL) += mpfs-sys-controller.o
diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c
new file mode 100644
index 000000000000..e8b44beb5ac5
--- /dev/null
+++ b/drivers/soc/microchip/mpfs-sys-controller.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Microchip PolarFire SoC (MPFS) system controller driver
+ *
+ * Copyright (c) 2020 Microchip Corporation. All rights reserved.
+ *
+ * Author: Conor Dooley <conor.dooley@microchip.com>
+ *
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+#include <linux/mailbox_client.h>
+#include <linux/platform_device.h>
+#include <soc/microchip/mpfs.h>
+
+static DEFINE_MUTEX(transaction_lock);
+
+struct mpfs_sys_controller {
+ struct mbox_client client;
+ struct mbox_chan *chan;
+ struct completion c;
+ u32 enabled;
+ void *response;
+ u16 response_size_bytes;
+};
+
+int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg,
+ void *response, u16 response_size_bytes)
+{
+ int ret;
+
+ mpfs_client->response = response;
+ mpfs_client->response_size_bytes = response_size_bytes;
+
+ mutex_lock_interruptible(&transaction_lock);
+
+ reinit_completion(&mpfs_client->c);
+
+ ret = mbox_send_message(mpfs_client->chan, msg);
+ if (ret >= 0) {
+ if (wait_for_completion_timeout(&mpfs_client->c, HZ)) {
+ ret = 0;
+ } else {
+ ret = -ETIMEDOUT;
+ dev_warn(mpfs_client->client.dev, "MPFS sys controller transaction timeout");
+ }
+ } else {
+ dev_err(mpfs_client->client.dev,
+ "mpfs sys controller transaction returned %d\r\n", ret);
+ }
+
+ mutex_unlock(&transaction_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(mpfs_blocking_transaction);
+
+static void rx_callback(struct mbox_client *client, void *msg)
+{
+ struct mpfs_sys_controller *mpfs_client =
+ container_of(client, struct mpfs_sys_controller, client);
+
+ memcpy(mpfs_client->response, (u8 *)msg, mpfs_client->response_size_bytes);
+
+ complete(&mpfs_client->c);
+}
+
+static int mpfs_sys_controller_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mpfs_sys_controller *mpfs_client;
+
+ mpfs_client = devm_kzalloc(dev, sizeof(*mpfs_client), GFP_KERNEL);
+ if (!mpfs_client)
+ return -ENOMEM;
+
+ mpfs_client->client.dev = dev;
+ mpfs_client->client.rx_callback = rx_callback;
+ mpfs_client->client.tx_block = 1U;
+
+ mpfs_client->chan = mbox_request_channel(&mpfs_client->client, 0);
+ if (IS_ERR(mpfs_client->chan))
+ return dev_err_probe(dev, PTR_ERR(mpfs_client->chan),
+ "Failed to get mbox channel\n");
+
+ init_completion(&mpfs_client->c);
+
+ platform_set_drvdata(pdev, mpfs_client);
+
+ dev_info(&pdev->dev, "Registered MPFS system controller driver\n");
+
+ return 0;
+}
+
+struct mpfs_sys_controller *
+mpfs_sys_controller_get(struct device_node *mss_node)
+{
+ struct platform_device *pdev = of_find_device_by_node(mss_node);
+
+ if (!pdev)
+ return NULL;
+
+ return platform_get_drvdata(pdev);
+}
+EXPORT_SYMBOL(mpfs_sys_controller_get);
+
+static const struct of_device_id mpfs_sys_controller_of_match[] = {
+ {.compatible = "microchip,polarfire-soc-sys-controller", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mpfs_sys_controller_of_match);
+
+static struct platform_driver mpfs_sys_controller_driver = {
+ .driver = {
+ .name = "mpfs-sys-controller",
+ .of_match_table = mpfs_sys_controller_of_match,
+ },
+ .probe = mpfs_sys_controller_probe,
+};
+module_platform_driver(mpfs_sys_controller_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
+MODULE_DESCRIPTION("MPFS system controller driver");
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3 3/5] soc: add polarfire soc system controller
2020-12-23 16:33 ` conor.dooley
@ 2021-01-05 22:14 ` Jonathan Neuschäfer
-1 siblings, 0 replies; 4+ messages in thread
From: Jonathan Neuschäfer @ 2021-01-05 22:14 UTC (permalink / raw)
To: conor.dooley
Cc: robh+dt, damien.lemoal, jassisinghbrar, aou, paul.walmsley,
palmer, devicetree, linux-riscv, cyril.jean, david.abdurachmanov,
daire.mcnamara, anup.patel, j.neuschaefer, atish.patra,
lewis.hanly
[-- Attachment #1: Type: text/plain, Size: 2050 bytes --]
Hello,
On Wed, Dec 23, 2020 at 04:33:10PM +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> This driver provides an interface for other drivers to access the
> functions of the system controller on the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
[...]
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_GEMINI) += gemini/
> obj-y += imx/
> obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/
> obj-$(CONFIG_SOC_XWAY) += lantiq/
> +obj-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip/
CONFIG_SOC_MICROCHIP_POLARFIRE is more specific than a flag guarding
the microchip directory should (intuitively) be (because there may be
Microchip SoCs that are not Microchip PolarFire). Fortunately, since
mpfs-sys-controller.o itself is guarded by CONFIG_POLARFIRE_SOC_SYS_CTRL,
using "obj-y += microchip/" here should work without a problem.
[...]
> +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg,
> + void *response, u16 response_size_bytes)
> +{
> + int ret;
> +
> + mpfs_client->response = response;
> + mpfs_client->response_size_bytes = response_size_bytes;
> +
> + mutex_lock_interruptible(&transaction_lock);
> +
> + reinit_completion(&mpfs_client->c);
> +
> + ret = mbox_send_message(mpfs_client->chan, msg);
> + if (ret >= 0) {
> + if (wait_for_completion_timeout(&mpfs_client->c, HZ)) {
> + ret = 0;
> + } else {
> + ret = -ETIMEDOUT;
> + dev_warn(mpfs_client->client.dev, "MPFS sys controller transaction timeout");
\n is missing
> + }
> + } else {
> + dev_err(mpfs_client->client.dev,
> + "mpfs sys controller transaction returned %d\r\n", ret);
\r\n is quite unusual and probably unnecessary in printk-style
functions, \n is enough.
> + }
> +
> + mutex_unlock(&transaction_lock);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL(mpfs_blocking_transaction);
Best regards,
Jonathan Neuschäfer
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3 3/5] soc: add polarfire soc system controller
@ 2021-01-05 22:14 ` Jonathan Neuschäfer
0 siblings, 0 replies; 4+ messages in thread
From: Jonathan Neuschäfer @ 2021-01-05 22:14 UTC (permalink / raw)
To: conor.dooley
Cc: devicetree, damien.lemoal, aou, cyril.jean, david.abdurachmanov,
daire.mcnamara, jassisinghbrar, j.neuschaefer, atish.patra,
anup.patel, robh+dt, palmer, paul.walmsley, lewis.hanly,
linux-riscv
[-- Attachment #1.1: Type: text/plain, Size: 2050 bytes --]
Hello,
On Wed, Dec 23, 2020 at 04:33:10PM +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> This driver provides an interface for other drivers to access the
> functions of the system controller on the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
[...]
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_GEMINI) += gemini/
> obj-y += imx/
> obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/
> obj-$(CONFIG_SOC_XWAY) += lantiq/
> +obj-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip/
CONFIG_SOC_MICROCHIP_POLARFIRE is more specific than a flag guarding
the microchip directory should (intuitively) be (because there may be
Microchip SoCs that are not Microchip PolarFire). Fortunately, since
mpfs-sys-controller.o itself is guarded by CONFIG_POLARFIRE_SOC_SYS_CTRL,
using "obj-y += microchip/" here should work without a problem.
[...]
> +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg,
> + void *response, u16 response_size_bytes)
> +{
> + int ret;
> +
> + mpfs_client->response = response;
> + mpfs_client->response_size_bytes = response_size_bytes;
> +
> + mutex_lock_interruptible(&transaction_lock);
> +
> + reinit_completion(&mpfs_client->c);
> +
> + ret = mbox_send_message(mpfs_client->chan, msg);
> + if (ret >= 0) {
> + if (wait_for_completion_timeout(&mpfs_client->c, HZ)) {
> + ret = 0;
> + } else {
> + ret = -ETIMEDOUT;
> + dev_warn(mpfs_client->client.dev, "MPFS sys controller transaction timeout");
\n is missing
> + }
> + } else {
> + dev_err(mpfs_client->client.dev,
> + "mpfs sys controller transaction returned %d\r\n", ret);
\r\n is quite unusual and probably unnecessary in printk-style
functions, \n is enough.
> + }
> +
> + mutex_unlock(&transaction_lock);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL(mpfs_blocking_transaction);
Best regards,
Jonathan Neuschäfer
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-01-05 22:15 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-23 16:33 [PATCH v3 3/5] soc: add polarfire soc system controller conor.dooley
2020-12-23 16:33 ` conor.dooley
2021-01-05 22:14 ` Jonathan Neuschäfer
2021-01-05 22:14 ` Jonathan Neuschäfer
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.