[Intel-gfx] [PATCH 1/2] drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.c

[Intel-gfx] [PATCH 1/2] drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.c

[Imre Deak]

intel_dp_set_signal_levels() is needed for link training, so move it to
intel_dp_link_training.c.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c        | 18 ------------------
 drivers/gpu/drm/i915/display/intel_dp.h        |  3 ---
 .../drm/i915/display/intel_dp_link_training.c  | 18 ++++++++++++++++++
 .../drm/i915/display/intel_dp_link_training.h  |  2 ++
 4 files changed, 20 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f0e8aaac413c..88a6033d6867 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5003,24 +5003,6 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
 }
 
-void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
-				const struct intel_crtc_state *crtc_state)
-{
-	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	u8 train_set = intel_dp->train_set[0];
-
-	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
-		    train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
-		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
-	drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
-		    (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
-		    DP_TRAIN_PRE_EMPHASIS_SHIFT,
-		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
-		    " (max)" : "");
-
-	intel_dp->set_signal_levels(intel_dp, crtc_state);
-}
-
 void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 				       const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 4280a09fd8fd..4ebda4e43003 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -96,9 +96,6 @@ void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 				       const struct intel_crtc_state *crtc_state,
 				       u8 dp_train_pat);
-void
-intel_dp_set_signal_levels(struct intel_dp *intel_dp,
-			   const struct intel_crtc_state *crtc_state);
 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 			   u8 *link_bw, u8 *rate_select);
 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 91d3979902d0..7876e781f698 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -334,6 +334,24 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 	return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
 }
 
+void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
+				const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	u8 train_set = intel_dp->train_set[0];
+
+	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
+		    train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
+		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
+	drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
+		    (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
+		    DP_TRAIN_PRE_EMPHASIS_SHIFT,
+		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
+		    " (max)" : "");
+
+	intel_dp->set_signal_levels(intel_dp, crtc_state);
+}
+
 static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
 			  const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 86905aa24db7..c3110c032bc2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -17,6 +17,8 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state,
 			       enum drm_dp_phy dp_phy,
 			       const u8 link_status[DP_LINK_STATUS_SIZE]);
+void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
+				const struct intel_crtc_state *crtc_state);
 void intel_dp_start_link_train(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state);
 void intel_dp_stop_link_train(struct intel_dp *intel_dp,
-- 
2.25.1

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[Intel-gfx] [PATCH 2/2] drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode

[Imre Deak]

The DP PHY vswing/pre-emphasis level programming the driver does is
related to the DPTX -> first LTTPR link segment only. Accordingly it
should be only programmed when link training the first LTTPR and kept
as-is when training subsequent LTTPRs and the DPRX. For these latter
PHYs the vs/pe levels will be set in response to writing the
DP_TRAINING_LANEx_SET_PHY_REPEATERy DPCD registers (by an upstream LTTPR
TX PHY snooping this write access of its downstream LTTPR/DPRX RX PHY).
The above is also described in DP Standard v2.0 under 3.6.6.1.

While at it simplify and add the LTTPR that is link trained to the debug
message in intel_dp_set_signal_levels().

Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link training")
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 .../drm/i915/display/intel_dp_link_training.c | 19 +++++++++++--------
 .../drm/i915/display/intel_dp_link_training.h |  3 ++-
 3 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 88a6033d6867..16c563f1a515 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6057,7 +6057,7 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
 
 	intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
 
-	intel_dp_set_signal_levels(intel_dp, crtc_state);
+	intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
 
 	intel_dp_phy_pattern_update(intel_dp, crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 7876e781f698..d8c6d7054d11 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -335,21 +335,24 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 }
 
 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
-				const struct intel_crtc_state *crtc_state)
+				const struct intel_crtc_state *crtc_state,
+				enum drm_dp_phy dp_phy)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_set = intel_dp->train_set[0];
+	char phy_name[10];
 
-	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
+	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n",
 		    train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
-		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
-	drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
+		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "",
 		    (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 		    DP_TRAIN_PRE_EMPHASIS_SHIFT,
 		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
-		    " (max)" : "");
+		    " (max)" : "",
+		    intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
 
-	intel_dp->set_signal_levels(intel_dp, crtc_state);
+	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
+		intel_dp->set_signal_levels(intel_dp, crtc_state);
 }
 
 static bool
@@ -359,7 +362,7 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp,
 			  u8 dp_train_pat)
 {
 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
-	intel_dp_set_signal_levels(intel_dp, crtc_state);
+	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
 	return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
 }
 
@@ -373,7 +376,7 @@ intel_dp_update_link_train(struct intel_dp *intel_dp,
 			    DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
 	int ret;
 
-	intel_dp_set_signal_levels(intel_dp, crtc_state);
+	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
 
 	ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
 				intel_dp->train_set, crtc_state->lane_count);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index c3110c032bc2..6a1f76bd8c75 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -18,7 +18,8 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 			       enum drm_dp_phy dp_phy,
 			       const u8 link_status[DP_LINK_STATUS_SIZE]);
 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
-				const struct intel_crtc_state *crtc_state);
+				const struct intel_crtc_state *crtc_state,
+				enum drm_dp_phy dp_phy);
 void intel_dp_start_link_train(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state);
 void intel_dp_stop_link_train(struct intel_dp *intel_dp,
-- 
2.25.1

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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.c

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 23075 bytes --]

== Series Details ==

Series: series starting with [1/2] drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.c
URL   : https://patchwork.freedesktop.org/series/85304/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9531_full -> Patchwork_19224_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_19224_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19224_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_19224_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt:
    - shard-kbl:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html

  
Known issues
------------

  Here are the changes found in Patchwork_19224_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@legacy-engines-hang@blt:
    - shard-skl:          NOTRUN -> [SKIP][3] ([fdo#109271]) +13 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl9/igt@gem_ctx_persistence@legacy-engines-hang@blt.html

  * igt@gem_exec_endless@dispatch@rcs0:
    - shard-kbl:          [PASS][4] -> [INCOMPLETE][5] ([i915#2502])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-kbl1/igt@gem_exec_endless@dispatch@rcs0.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-kbl1/igt@gem_exec_endless@dispatch@rcs0.html

  * igt@gem_exec_reloc@basic-many-active@rcs0:
    - shard-glk:          [PASS][6] -> [FAIL][7] ([i915#2389])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-glk6/igt@gem_exec_reloc@basic-many-active@rcs0.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-glk3/igt@gem_exec_reloc@basic-many-active@rcs0.html

  * igt@gem_exec_schedule@smoketest-all:
    - shard-glk:          [PASS][8] -> [DMESG-WARN][9] ([i915#118] / [i915#95]) +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-glk7/igt@gem_exec_schedule@smoketest-all.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-glk5/igt@gem_exec_schedule@smoketest-all.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-tglb:         NOTRUN -> [SKIP][10] ([fdo#109312])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-tglb2/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gen7_exec_parse@bitmasks:
    - shard-tglb:         NOTRUN -> [SKIP][11] ([fdo#109289])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-tglb2/igt@gen7_exec_parse@bitmasks.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-skl:          [PASS][12] -> [INCOMPLETE][13] ([i915#198])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl1/igt@i915_suspend@fence-restore-untiled.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl6/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-skl:          [PASS][14] -> [FAIL][15] ([i915#2521])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl3/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-tglb:         NOTRUN -> [SKIP][16] ([i915#1769])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-tglb2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_chamelium@hdmi-aspect-ratio:
    - shard-glk:          NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-glk4/igt@kms_chamelium@hdmi-aspect-ratio.html
    - shard-tglb:         NOTRUN -> [SKIP][18] ([fdo#109284] / [fdo#111827]) +2 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-tglb2/igt@kms_chamelium@hdmi-aspect-ratio.html

  * igt@kms_color@pipe-b-ctm-max:
    - shard-skl:          [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl1/igt@kms_color@pipe-b-ctm-max.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl4/igt@kms_color@pipe-b-ctm-max.html

  * igt@kms_color_chamelium@pipe-a-ctm-0-75:
    - shard-kbl:          NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-kbl2/igt@kms_color_chamelium@pipe-a-ctm-0-75.html

  * igt@kms_color_chamelium@pipe-a-ctm-max:
    - shard-skl:          NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl9/igt@kms_color_chamelium@pipe-a-ctm-max.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([i915#54]) +6 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
    - shard-kbl:          NOTRUN -> [SKIP][25] ([fdo#109271]) +24 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-kbl2/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-hsw:          [PASS][26] -> [FAIL][27] ([i915#96])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-skl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#533])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl9/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-tglb:         [PASS][29] -> [FAIL][30] ([i915#2598])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-tglb6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([i915#79]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
    - shard-skl:          [PASS][33] -> [FAIL][34] ([i915#2122]) +3 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
    - shard-skl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#2642])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render:
    - shard-glk:          NOTRUN -> [SKIP][36] ([fdo#109271]) +11 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-glk4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render.html
    - shard-tglb:         NOTRUN -> [SKIP][37] ([fdo#111825]) +4 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-tglb2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [PASS][38] -> [FAIL][39] ([i915#1188])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
    - shard-kbl:          NOTRUN -> [FAIL][40] ([fdo#108145] / [i915#265])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-kbl2/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][41] -> [FAIL][42] ([fdo#108145] / [i915#265]) +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@perf@polling-parameterized:
    - shard-glk:          [PASS][43] -> [FAIL][44] ([i915#1542])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-glk2/igt@perf@polling-parameterized.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-glk2/igt@perf@polling-parameterized.html
    - shard-skl:          [PASS][45] -> [FAIL][46] ([i915#1542])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl5/igt@perf@polling-parameterized.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl5/igt@perf@polling-parameterized.html

  
#### Possible fixes ####

  * igt@gem_exec_balancer@waits:
    - shard-kbl:          [INCOMPLETE][47] -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-kbl6/igt@gem_exec_balancer@waits.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-kbl2/igt@gem_exec_balancer@waits.html

  * {igt@gem_exec_fair@basic-none-share@rcs0}:
    - shard-iclb:         [FAIL][49] ([i915#2842]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html

  * {igt@gem_exec_fair@basic-none-solo@rcs0}:
    - shard-kbl:          [FAIL][51] ([i915#2842]) -> [PASS][52] +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * {igt@gem_exec_fair@basic-throttle@rcs0}:
    - shard-glk:          [FAIL][53] ([i915#2842]) -> [PASS][54] +2 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-glk9/igt@gem_exec_fair@basic-throttle@rcs0.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html

  * {igt@gem_exec_schedule@u-fairslice@vcs0}:
    - shard-glk:          [DMESG-WARN][55] ([i915#1610]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-glk2/igt@gem_exec_schedule@u-fairslice@vcs0.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-glk4/igt@gem_exec_schedule@u-fairslice@vcs0.html

  * {igt@gem_exec_schedule@u-fairslice@vecs0}:
    - shard-tglb:         [DMESG-WARN][57] ([i915#2803]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-tglb1/igt@gem_exec_schedule@u-fairslice@vecs0.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-tglb2/igt@gem_exec_schedule@u-fairslice@vecs0.html

  * {igt@gem_vm_create@destroy-race}:
    - shard-tglb:         [TIMEOUT][59] ([i915#2795]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-tglb3/igt@gem_vm_create@destroy-race.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-tglb5/igt@gem_vm_create@destroy-race.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-skl:          [INCOMPLETE][61] ([i915#198] / [i915#2295]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl2/igt@gem_workarounds@suspend-resume-context.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl1/igt@gem_workarounds@suspend-resume-context.html

  * igt@kms_color@pipe-a-ctm-0-25:
    - shard-skl:          [DMESG-WARN][63] ([i915#1982]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl10/igt@kms_color@pipe-a-ctm-0-25.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl9/igt@kms_color@pipe-a-ctm-0-25.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen:
    - shard-skl:          [FAIL][65] ([i915#54]) -> [PASS][66] +10 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [FAIL][67] ([i915#2346] / [i915#533]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_hdr@bpc-switch:
    - shard-skl:          [FAIL][69] ([i915#1188]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl2/igt@kms_hdr@bpc-switch.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl3/igt@kms_hdr@bpc-switch.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][71] ([fdo#108145] / [i915#265]) -> [PASS][72] +1 similar issue
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][73] ([fdo#109441]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-iclb1/igt@kms_psr@psr2_cursor_render.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  * {igt@perf@non-zero-reason}:
    - shard-iclb:         [FAIL][75] ([i915#2804]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-iclb6/igt@perf@non-zero-reason.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-iclb5/igt@perf@non-zero-reason.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][77] ([i915#2681] / [i915#2684]) -> [WARN][78] ([i915#1804] / [i915#2684])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][79] ([i915#2681] / [i915#2684]) -> [WARN][80] ([i915#2684])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_async_flips@test-time-stamp:
    - shard-tglb:         [FAIL][81] ([i915#2597]) -> [FAIL][82] ([i915#2574])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-tglb3/igt@kms_async_flips@test-time-stamp.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-tglb1/igt@kms_async_flips@test-time-stamp.html

  * igt@runner@aborted:
    - shard-kbl:          [FAIL][83] ([i915#2295]) -> [FAIL][84] ([i915#2295] / [i915#483])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-kbl7/igt@runner@aborted.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-kbl4/igt@runner@aborted.html
    - shard-iclb:         [FAIL][85] ([i915#2295] / [i915#2724] / [i915#483]) -> [FAIL][86] ([i915#2295] / [i915#2724])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-iclb5/igt@runner@aborted.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-iclb3/igt@runner@aborted.html
    - shard-apl:          [FAIL][87] ([i915#2295]) -> ([FAIL][88], [FAIL][89], [FAIL][90]) ([i915#1610] / [i915#2295] / [i915#2426])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-apl1/igt@runner@aborted.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-apl6/igt@runner@aborted.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-apl8/igt@runner@aborted.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-apl8/igt@runner@aborted.html
    - shard-glk:          ([FAIL][91], [FAIL][92]) ([i915#2295] / [i915#2426] / [i915#483] / [k.org#202321]) -> [FAIL][93] ([i915#2295] / [i915#483] / [k.org#202321])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-glk3/igt@runner@aborted.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-glk2/igt@runner@aborted.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-glk7/igt@runner@aborted.html
    - shard-tglb:         ([FAIL][94], [FAIL][95]) ([i915#2295] / [i915#2426] / [i915#2667] / [i915#2803]) -> [FAIL][96] ([i915#2295] / [i915#2667])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-tglb1/igt@runner@aborted.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-tglb1/igt@runner@aborted.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-tglb2/igt@runner@aborted.html
    - shard-skl:          [FAIL][97] ([i915#2295] / [i915#483]) -> [FAIL][98] ([i915#2295])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9531/shard-skl3/igt@runner@aborted.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/shard-skl6/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2574]: https://gitlab.freedesktop.org/drm/intel/issues/2574
  [i915#2597]: https://gitlab.freedesktop.org/drm/intel/issues/2597
  [i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598
  [i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#2667]: https://gitlab.freedesktop.org/drm/intel/issues/2667
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
  [i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
  [i915#2795]: https://gitlab.freedesktop.org/drm/intel/issues/2795
  [i915#2803]: https://gitlab.freedesktop.org/drm/intel/issues/2803
  [i915#2804]: https://gitlab.freedesktop.org/drm/intel/issues/2804
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
  [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (11 -> 10)
------------------------------

  Missing    (1): pig-snb-2600 


Build changes
-------------

  * Linux: CI_DRM_9531 -> Patchwork_19224

  CI-20190529: 20190529
  CI_DRM_9531: 3be1a2da0514341aa8a57c8ad028b9194f2e2299 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5927: 728d6dc6bd8b187210655a7fea152cc24a41cbcb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19224: 61ed26450f0f9d16961269e365280449ec0e9be4 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19224/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.c

[Ville Syrjälä]

On Tue, Dec 29, 2020 at 07:22:00PM +0200, Imre Deak wrote:
> intel_dp_set_signal_levels() is needed for link training, so move it to
> intel_dp_link_training.c.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c        | 18 ------------------
>  drivers/gpu/drm/i915/display/intel_dp.h        |  3 ---
>  .../drm/i915/display/intel_dp_link_training.c  | 18 ++++++++++++++++++
>  .../drm/i915/display/intel_dp_link_training.h  |  2 ++
>  4 files changed, 20 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index f0e8aaac413c..88a6033d6867 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5003,24 +5003,6 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
>  	intel_de_posting_read(dev_priv, intel_dp->output_reg);
>  }
>  
> -void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> -				const struct intel_crtc_state *crtc_state)
> -{
> -	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	u8 train_set = intel_dp->train_set[0];
> -
> -	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
> -		    train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
> -		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
> -	drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
> -		    (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
> -		    DP_TRAIN_PRE_EMPHASIS_SHIFT,
> -		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
> -		    " (max)" : "");
> -
> -	intel_dp->set_signal_levels(intel_dp, crtc_state);
> -}
> -
>  void
>  intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>  				       const struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 4280a09fd8fd..4ebda4e43003 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -96,9 +96,6 @@ void
>  intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
>  				       const struct intel_crtc_state *crtc_state,
>  				       u8 dp_train_pat);
> -void
> -intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> -			   const struct intel_crtc_state *crtc_state);
>  void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
>  			   u8 *link_bw, u8 *rate_select);
>  bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 91d3979902d0..7876e781f698 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -334,6 +334,24 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>  	return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
>  }
>  
> +void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> +				const struct intel_crtc_state *crtc_state)

Can't it be static now? Hmm, apparently not due to the ad-hoc phy test
code. Oh well.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	u8 train_set = intel_dp->train_set[0];
> +
> +	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
> +		    train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
> +		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
> +	drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
> +		    (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
> +		    DP_TRAIN_PRE_EMPHASIS_SHIFT,
> +		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
> +		    " (max)" : "");
> +
> +	intel_dp->set_signal_levels(intel_dp, crtc_state);
> +}
> +
>  static bool
>  intel_dp_reset_link_train(struct intel_dp *intel_dp,
>  			  const struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> index 86905aa24db7..c3110c032bc2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> @@ -17,6 +17,8 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>  			       const struct intel_crtc_state *crtc_state,
>  			       enum drm_dp_phy dp_phy,
>  			       const u8 link_status[DP_LINK_STATUS_SIZE]);
> +void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> +				const struct intel_crtc_state *crtc_state);
>  void intel_dp_start_link_train(struct intel_dp *intel_dp,
>  			       const struct intel_crtc_state *crtc_state);
>  void intel_dp_stop_link_train(struct intel_dp *intel_dp,
> -- 
> 2.25.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode

[Ville Syrjälä]

On Tue, Dec 29, 2020 at 07:22:01PM +0200, Imre Deak wrote:
> The DP PHY vswing/pre-emphasis level programming the driver does is
> related to the DPTX -> first LTTPR link segment only. Accordingly it
> should be only programmed when link training the first LTTPR and kept
> as-is when training subsequent LTTPRs and the DPRX. For these latter
> PHYs the vs/pe levels will be set in response to writing the
> DP_TRAINING_LANEx_SET_PHY_REPEATERy DPCD registers (by an upstream LTTPR
> TX PHY snooping this write access of its downstream LTTPR/DPRX RX PHY).
> The above is also described in DP Standard v2.0 under 3.6.6.1.
> 
> While at it simplify and add the LTTPR that is link trained to the debug
> message in intel_dp_set_signal_levels().
> 
> Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link training")
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
>  .../drm/i915/display/intel_dp_link_training.c | 19 +++++++++++--------
>  .../drm/i915/display/intel_dp_link_training.h |  3 ++-
>  3 files changed, 14 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 88a6033d6867..16c563f1a515 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6057,7 +6057,7 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
>  
>  	intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
>  
> -	intel_dp_set_signal_levels(intel_dp, crtc_state);
> +	intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
>  
>  	intel_dp_phy_pattern_update(intel_dp, crtc_state);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 7876e781f698..d8c6d7054d11 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -335,21 +335,24 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>  }
>  
>  void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> -				const struct intel_crtc_state *crtc_state)
> +				const struct intel_crtc_state *crtc_state,
> +				enum drm_dp_phy dp_phy)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u8 train_set = intel_dp->train_set[0];
> +	char phy_name[10];
>  
> -	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
> +	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n",
>  		    train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
> -		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
> -	drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
> +		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "",
>  		    (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
>  		    DP_TRAIN_PRE_EMPHASIS_SHIFT,
>  		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
> -		    " (max)" : "");
> +		    " (max)" : "",
> +		    intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
>  
> -	intel_dp->set_signal_levels(intel_dp, crtc_state);
> +	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
> +		intel_dp->set_signal_levels(intel_dp, crtc_state);

The function name is a bit misleading now I guess since we're not
actually setting the signal levels here for the LTTPRs. But since
the debug print is here I guess we want to still call this. And as
usual I can't think of a better name for this, so I'm willing
to accept that slight inconsistency.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  }
>  
>  static bool
> @@ -359,7 +362,7 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp,
>  			  u8 dp_train_pat)
>  {
>  	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> -	intel_dp_set_signal_levels(intel_dp, crtc_state);
> +	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
>  	return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
>  }
>  
> @@ -373,7 +376,7 @@ intel_dp_update_link_train(struct intel_dp *intel_dp,
>  			    DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
>  	int ret;
>  
> -	intel_dp_set_signal_levels(intel_dp, crtc_state);
> +	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
>  
>  	ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
>  				intel_dp->train_set, crtc_state->lane_count);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> index c3110c032bc2..6a1f76bd8c75 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> @@ -18,7 +18,8 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>  			       enum drm_dp_phy dp_phy,
>  			       const u8 link_status[DP_LINK_STATUS_SIZE]);
>  void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> -				const struct intel_crtc_state *crtc_state);
> +				const struct intel_crtc_state *crtc_state,
> +				enum drm_dp_phy dp_phy);
>  void intel_dp_start_link_train(struct intel_dp *intel_dp,
>  			       const struct intel_crtc_state *crtc_state);
>  void intel_dp_stop_link_train(struct intel_dp *intel_dp,
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode

[Imre Deak]

On Tue, Jan 12, 2021 at 08:10:40PM +0200, Ville Syrjälä wrote:
> On Tue, Dec 29, 2020 at 07:22:01PM +0200, Imre Deak wrote:
> > The DP PHY vswing/pre-emphasis level programming the driver does is
> > related to the DPTX -> first LTTPR link segment only. Accordingly it
> > should be only programmed when link training the first LTTPR and kept
> > as-is when training subsequent LTTPRs and the DPRX. For these latter
> > PHYs the vs/pe levels will be set in response to writing the
> > DP_TRAINING_LANEx_SET_PHY_REPEATERy DPCD registers (by an upstream LTTPR
> > TX PHY snooping this write access of its downstream LTTPR/DPRX RX PHY).
> > The above is also described in DP Standard v2.0 under 3.6.6.1.
> > 
> > While at it simplify and add the LTTPR that is link trained to the debug
> > message in intel_dp_set_signal_levels().
> > 
> > Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link training")
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
> >  .../drm/i915/display/intel_dp_link_training.c | 19 +++++++++++--------
> >  .../drm/i915/display/intel_dp_link_training.h |  3 ++-
> >  3 files changed, 14 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 88a6033d6867..16c563f1a515 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -6057,7 +6057,7 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
> >  
> >  	intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
> >  
> > -	intel_dp_set_signal_levels(intel_dp, crtc_state);
> > +	intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
> >  
> >  	intel_dp_phy_pattern_update(intel_dp, crtc_state);
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index 7876e781f698..d8c6d7054d11 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -335,21 +335,24 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> >  }
> >  
> >  void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> > -				const struct intel_crtc_state *crtc_state)
> > +				const struct intel_crtc_state *crtc_state,
> > +				enum drm_dp_phy dp_phy)
> >  {
> >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >  	u8 train_set = intel_dp->train_set[0];
> > +	char phy_name[10];
> >  
> > -	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
> > +	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n",
> >  		    train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
> > -		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
> > -	drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
> > +		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "",
> >  		    (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
> >  		    DP_TRAIN_PRE_EMPHASIS_SHIFT,
> >  		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
> > -		    " (max)" : "");
> > +		    " (max)" : "",
> > +		    intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
> >  
> > -	intel_dp->set_signal_levels(intel_dp, crtc_state);
> > +	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
> > +		intel_dp->set_signal_levels(intel_dp, crtc_state);
> 
> The function name is a bit misleading now I guess since we're not
> actually setting the signal levels here for the LTTPRs. But since
> the debug print is here I guess we want to still call this. And as
> usual I can't think of a better name for this, so I'm willing
> to accept that slight inconsistency.

Agreed, will try to make that more consistent as a follow up.

Btw, checking again the callers of the above, looks like
intel_dp_process_phy_request() also misses the DPCD write for the vs/pe
settings.

> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> >  }
> >  
> >  static bool
> > @@ -359,7 +362,7 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp,
> >  			  u8 dp_train_pat)
> >  {
> >  	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> > -	intel_dp_set_signal_levels(intel_dp, crtc_state);
> > +	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
> >  	return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
> >  }
> >  
> > @@ -373,7 +376,7 @@ intel_dp_update_link_train(struct intel_dp *intel_dp,
> >  			    DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
> >  	int ret;
> >  
> > -	intel_dp_set_signal_levels(intel_dp, crtc_state);
> > +	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
> >  
> >  	ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
> >  				intel_dp->train_set, crtc_state->lane_count);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > index c3110c032bc2..6a1f76bd8c75 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > @@ -18,7 +18,8 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> >  			       enum drm_dp_phy dp_phy,
> >  			       const u8 link_status[DP_LINK_STATUS_SIZE]);
> >  void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> > -				const struct intel_crtc_state *crtc_state);
> > +				const struct intel_crtc_state *crtc_state,
> > +				enum drm_dp_phy dp_phy);
> >  void intel_dp_start_link_train(struct intel_dp *intel_dp,
> >  			       const struct intel_crtc_state *crtc_state);
> >  void intel_dp_stop_link_train(struct intel_dp *intel_dp,
> > -- 
> > 2.25.1
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode

[Almahallawy, Khaled]

On Tue, 2021-01-12 at 22:35 +0200, Imre Deak wrote:
> On Tue, Jan 12, 2021 at 08:10:40PM +0200, Ville Syrjälä wrote:
> > On Tue, Dec 29, 2020 at 07:22:01PM +0200, Imre Deak wrote:
> > > The DP PHY vswing/pre-emphasis level programming the driver does
> > > is
> > > related to the DPTX -> first LTTPR link segment only. Accordingly
> > > it
> > > should be only programmed when link training the first LTTPR and
> > > kept
> > > as-is when training subsequent LTTPRs and the DPRX. For these
> > > latter
> > > PHYs the vs/pe levels will be set in response to writing the
> > > DP_TRAINING_LANEx_SET_PHY_REPEATERy DPCD registers (by an
> > > upstream LTTPR
> > > TX PHY snooping this write access of its downstream LTTPR/DPRX RX
> > > PHY).
> > > The above is also described in DP Standard v2.0 under 3.6.6.1.
> > > 
> > > While at it simplify and add the LTTPR that is link trained to
> > > the debug
> > > message in intel_dp_set_signal_levels().
> > > 
> > > Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent
> > > mode link training")
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
> > >  .../drm/i915/display/intel_dp_link_training.c | 19 +++++++++++
> > > --------
> > >  .../drm/i915/display/intel_dp_link_training.h |  3 ++-
> > >  3 files changed, 14 insertions(+), 10 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 88a6033d6867..16c563f1a515 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -6057,7 +6057,7 @@ static void
> > > intel_dp_process_phy_request(struct intel_dp *intel_dp,
> > >  
> > >  	intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
> > >  
> > > -	intel_dp_set_signal_levels(intel_dp, crtc_state);
> > > +	intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
> > >  
> > >  	intel_dp_phy_pattern_update(intel_dp, crtc_state);
> > >  
> > > diff --git
> > > a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > index 7876e781f698..d8c6d7054d11 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > @@ -335,21 +335,24 @@ intel_dp_set_link_train(struct intel_dp
> > > *intel_dp,
> > >  }
> > >  
> > >  void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> > > -				const struct intel_crtc_state
> > > *crtc_state)
> > > +				const struct intel_crtc_state
> > > *crtc_state,
> > > +				enum drm_dp_phy dp_phy)
> > >  {
> > >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > >  	u8 train_set = intel_dp->train_set[0];
> > > +	char phy_name[10];
> > >  
> > > -	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
> > > +	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-
> > > emphasis level %d%s, at %s\n",
> > >  		    train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
> > > -		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" :
> > > "");
> > > -	drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
> > > +		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" :
> > > "",
> > >  		    (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
> > >  		    DP_TRAIN_PRE_EMPHASIS_SHIFT,
> > >  		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
> > > -		    " (max)" : "");
> > > +		    " (max)" : "",
> > > +		    intel_dp_phy_name(dp_phy, phy_name,
> > > sizeof(phy_name)));
> > >  
> > > -	intel_dp->set_signal_levels(intel_dp, crtc_state);
> > > +	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
> > > +		intel_dp->set_signal_levels(intel_dp, crtc_state);
> > 
> > The function name is a bit misleading now I guess since we're not
> > actually setting the signal levels here for the LTTPRs. But since
> > the debug print is here I guess we want to still call this. And as
> > usual I can't think of a better name for this, so I'm willing
> > to accept that slight inconsistency.
> 
> Agreed, will try to make that more consistent as a follow up.
> 
> Btw, checking again the callers of the above, looks like
> intel_dp_process_phy_request() also misses the DPCD write for the
> vs/pe
> settings.

In older compliance design this is patch I used for Chrome in order for
retimer to snoop swing/pre-emphasis levels (VLK-11829)
https://patchwork.freedesktop.org/patch/387249/


Thanks
Khaled

> 
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > >  }
> > >  
> > >  static bool
> > > @@ -359,7 +362,7 @@ intel_dp_reset_link_train(struct intel_dp
> > > *intel_dp,
> > >  			  u8 dp_train_pat)
> > >  {
> > >  	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> > > -	intel_dp_set_signal_levels(intel_dp, crtc_state);
> > > +	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
> > >  	return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
> > > dp_train_pat);
> > >  }
> > >  
> > > @@ -373,7 +376,7 @@ intel_dp_update_link_train(struct intel_dp
> > > *intel_dp,
> > >  			    DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
> > >  	int ret;
> > >  
> > > -	intel_dp_set_signal_levels(intel_dp, crtc_state);
> > > +	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
> > >  
> > >  	ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
> > >  				intel_dp->train_set, crtc_state-
> > > >lane_count);
> > > diff --git
> > > a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > > b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > > index c3110c032bc2..6a1f76bd8c75 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> > > @@ -18,7 +18,8 @@ void intel_dp_get_adjust_train(struct intel_dp
> > > *intel_dp,
> > >  			       enum drm_dp_phy dp_phy,
> > >  			       const u8
> > > link_status[DP_LINK_STATUS_SIZE]);
> > >  void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> > > -				const struct intel_crtc_state
> > > *crtc_state);
> > > +				const struct intel_crtc_state
> > > *crtc_state,
> > > +				enum drm_dp_phy dp_phy);
> > >  void intel_dp_start_link_train(struct intel_dp *intel_dp,
> > >  			       const struct intel_crtc_state
> > > *crtc_state);
> > >  void intel_dp_stop_link_train(struct intel_dp *intel_dp,
> > > -- 
> > > 2.25.1
> > 
> > -- 
> > Ville Syrjälä
> > Intel
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