[PATCH/RFC 0/6] R-Car V3U GPIO support

[PATCH/RFC 0/6] R-Car V3U GPIO support

[Geert Uytterhoeven]

	Hi all,

This RFC patch series adds support for the GPIO blocks on the R-Car V3U
(r8a77990) SoC.  This includes clock (incl. some drive-by fixes), DT
binding, driver, and DTS updates.

Due to lack of hardware, this is compile-tested only.

Thanks for your comments!

Geert Uytterhoeven (5):
  [RFC] clk: renesas: r8a779a0: Remove non-existent S2 clock
  [RFC] clk: renesas: r8a779a0: Fix parent of CBFUSA clock
  [RFC] clk: renesas: r8a779a0: Add PFC/GPIO clocks
  [RFC] dt-bindings: gpio: rcar: Add r8a779a0 support
  [RFC] arm64: dts: r8a779a0: Add GPIO nodes

Phong Hoang (1):
  [RFC] gpio: rcar: Add support for R-Car V3U

 .../bindings/gpio/renesas,rcar-gpio.yaml      |   3 +
 arch/arm64/boot/dts/renesas/r8a779a0.dtsi     | 140 ++++++++++++++++++
 drivers/clk/renesas/r8a779a0-cpg-mssr.c       |   8 +-
 drivers/gpio/gpio-rcar.c                      |  23 +++
 4 files changed, 172 insertions(+), 2 deletions(-)

-- 
2.17.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH/RFC 1/6] clk: renesas: r8a779a0: Remove non-existent S2 clock

[Geert Uytterhoeven]

The S2 internal core clock does not exist on R-Car V3U. Remove it.

Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 2a00eb82013f3829..496b7d3f94c8f65d 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -70,7 +70,6 @@ enum clk_ids {
 	CLK_PLL5_DIV2,
 	CLK_PLL5_DIV4,
 	CLK_S1,
-	CLK_S2,
 	CLK_S3,
 	CLK_SDSRC,
 	CLK_RPCSRC,
-- 
2.17.1

[PATCH/RFC 2/6] clk: renesas: r8a779a0: Fix parent of CBFUSA clock

[Geert Uytterhoeven]

According to Figure 8.1.1 ("Block Diagram of CPG (R-Car V3U-AD)") in the
R-Car V3U Series User's Manual Rev. 0.5, the parent of the CBFUSA clock
is EXTAL.

Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 496b7d3f94c8f65d..968be8206a480015 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -129,7 +129,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 	DEF_FIXED("icu",	R8A779A0_CLK_ICU,	CLK_PLL5_DIV4,	2, 1),
 	DEF_FIXED("icud2",	R8A779A0_CLK_ICUD2,	CLK_PLL5_DIV4,	4, 1),
 	DEF_FIXED("vcbus",	R8A779A0_CLK_VCBUS,	CLK_PLL5_DIV4,	1, 1),
-	DEF_FIXED("cbfusa",	R8A779A0_CLK_CBFUSA,	CLK_MAIN,	2, 1),
+	DEF_FIXED("cbfusa",	R8A779A0_CLK_CBFUSA,	CLK_EXTAL,	2, 1),
 
 	DEF_DIV6P1("mso",	R8A779A0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),
 	DEF_DIV6P1("canfd",	R8A779A0_CLK_CANFD,	CLK_PLL5_DIV4,	0x878),
-- 
2.17.1

[PATCH/RFC 3/6] clk: renesas: r8a779a0: Add PFC/GPIO clocks

[Geert Uytterhoeven]

Add the module clocks used by the Pin Function Controller (PFC) and
General Purpose Input/Output (GPIO) blocks, and their parent clock CP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested on actual hardware.

Note that the BSP uses MAIN instead of EXTAL, just like for the CBFUSA
clock.  However, according to Figure 8.1.1 ("Block Diagram of CPG (R-Car
V3U-AD)") in the R-Car V3U Series User's Manual Rev. 0.5, the parent of
the CP clock is EXTAL, which matches earlier R-Car Gen3 SoCs.
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 968be8206a480015..9d414ad9dd4469d2 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -130,6 +130,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 	DEF_FIXED("icud2",	R8A779A0_CLK_ICUD2,	CLK_PLL5_DIV4,	4, 1),
 	DEF_FIXED("vcbus",	R8A779A0_CLK_VCBUS,	CLK_PLL5_DIV4,	1, 1),
 	DEF_FIXED("cbfusa",	R8A779A0_CLK_CBFUSA,	CLK_EXTAL,	2, 1),
+	DEF_FIXED("cp",		R8A779A0_CLK_CP,	CLK_EXTAL,	2, 1),
 
 	DEF_DIV6P1("mso",	R8A779A0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),
 	DEF_DIV6P1("canfd",	R8A779A0_CLK_CANFD,	CLK_PLL5_DIV4,	0x878),
@@ -180,6 +181,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
 	DEF_MOD("vin35",	827,	R8A779A0_CLK_S1D1),
 	DEF_MOD("vin36",	828,	R8A779A0_CLK_S1D1),
 	DEF_MOD("vin37",	829,	R8A779A0_CLK_S1D1),
+	DEF_MOD("pfc0",		915,	R8A779A0_CLK_CP),
+	DEF_MOD("pfc1",		916,	R8A779A0_CLK_CP),
+	DEF_MOD("pfc2",		917,	R8A779A0_CLK_CP),
+	DEF_MOD("pfc3",		918,	R8A779A0_CLK_CP),
 };
 
 static spinlock_t cpg_lock;
-- 
2.17.1

[PATCH/RFC 4/6] dt-bindings: gpio: rcar: Add r8a779a0 support

[Geert Uytterhoeven]

Document the compatible value for the GPIO block in the Renesas R-Car
V3U (R8A779A0) SoC.

While this GPIO block is mostly compatible with GPIO blocks on R-Car
Gen3 SoCs, there are small differences, and one of the new registers
needs to be configured differently from its initial reset state.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested on actual hardware.
---
 Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml b/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml
index 5026662e45081b6c..f2541739ee3b9f7c 100644
--- a/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml
@@ -48,6 +48,9 @@ properties:
               - renesas,gpio-r8a77995     # R-Car D3
           - const: renesas,rcar-gen3-gpio # R-Car Gen3 or RZ/G2
 
+      - items:
+          - const: renesas,gpio-r8a779a0  # R-Car V3U
+
   reg:
     maxItems: 1
 
-- 
2.17.1

[PATCH/RFC 5/6] gpio: rcar: Add support for R-Car V3U

[Geert Uytterhoeven]

From: Phong Hoang <phong.hoang.wz@renesas.com>

Add support for the R-Car V3U (r8a779a0) SoC.
This includes support for the new "General Input Enable" register to
control input enable.

Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested on actual hardware.

Should input be enabled unconditionally, as recommended by the Hardware
Manual for backwards compatibility with existing software?
As per (errata?) commit ae9550f635533b1c ("gpio-rcar: Use OUTDT when
reading GPIOs configured as output"), the gpio-rcar driver does not use
the INDT register to read the status of a GPIO line when configured for
output.
---
 drivers/gpio/gpio-rcar.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index a924cf8ac8df7f8f..44d09a0028db49e9 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -42,6 +42,7 @@ struct gpio_rcar_priv {
 	atomic_t wakeup_path;
 	bool has_outdtsel;
 	bool has_both_edge_trigger;
+	bool has_inen;
 	struct gpio_rcar_bank_info bank_info;
 };
 
@@ -58,6 +59,7 @@ struct gpio_rcar_priv {
 #define FILONOFF 0x28	/* Chattering Prevention On/Off Register */
 #define OUTDTSEL 0x40	/* Output Data Select Register */
 #define BOTHEDGE 0x4c	/* One Edge/Both Edge Select Register */
+#define INEN 0x50	/* General Input Enable Register */
 
 #define RCAR_MAX_GPIO_PER_BANK		32
 
@@ -126,6 +128,10 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
 	if (p->has_both_edge_trigger)
 		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
 
+	/* Select "Input Enable" in INEN */
+	if (p->has_inen)
+		gpio_rcar_modify_bit(p, INEN, hwirq, true);
+
 	/* Select "Interrupt Input Mode" in IOINTSEL */
 	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 
@@ -231,6 +237,10 @@ static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
 	/* Configure positive logic in POSNEG */
 	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
 
+	/* Select "Input Enable/Disable" in INEN */
+	if (p->has_inen)
+		gpio_rcar_modify_bit(p, INEN, gpio, !output);
+
 	/* Select "General Input/Output Mode" in IOINTSEL */
 	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
 
@@ -349,16 +359,25 @@ static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
 struct gpio_rcar_info {
 	bool has_outdtsel;
 	bool has_both_edge_trigger;
+	bool has_inen;
 };
 
 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
 	.has_outdtsel = false,
 	.has_both_edge_trigger = false,
+	.has_inen = false,
 };
 
 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
 	.has_outdtsel = true,
 	.has_both_edge_trigger = true,
+	.has_inen = false,
+};
+
+static const struct gpio_rcar_info gpio_rcar_info_v3u = {
+	.has_outdtsel = true,
+	.has_both_edge_trigger = true,
+	.has_inen = true,
 };
 
 static const struct of_device_id gpio_rcar_of_table[] = {
@@ -389,6 +408,9 @@ static const struct of_device_id gpio_rcar_of_table[] = {
 		.compatible = "renesas,gpio-r8a7796",
 		/* Gen3 GPIO is identical to Gen2. */
 		.data = &gpio_rcar_info_gen2,
+	}, {
+		.compatible = "renesas,gpio-r8a779a0",
+		.data = &gpio_rcar_info_v3u,
 	}, {
 		.compatible = "renesas,rcar-gen1-gpio",
 		.data = &gpio_rcar_info_gen1,
@@ -419,6 +441,7 @@ static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
 	info = of_device_get_match_data(p->dev);
 	p->has_outdtsel = info->has_outdtsel;
 	p->has_both_edge_trigger = info->has_both_edge_trigger;
+	p->has_inen = info->has_inen;
 
 	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
 	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
-- 
2.17.1

[PATCH/RFC 6/6] arm64: dts: r8a779a0: Add GPIO nodes

[Geert Uytterhoeven]

Add device nodes for the General Purpose Input/Output (GPIO) block on
the Renesas R-Car V3u (r8a779a0) SoC.

As there is no node for the PFC yet, all "gpio-ranges" properties are
commented out.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This needs verification on real hardware, as the hardware manual is
unclear w.r.t. the following points:
  - Module clocks and interrupt mappings,
  - There are more/multiple resets for the PFC[0-3] in the Software
    Reset/Reset Clearing Registers 12, 13, and 14.
    The BSP picked up a different set.
---
 arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 140 ++++++++++++++++++++++
 1 file changed, 140 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index bc81e6a761d32034..1482bdf1cceb40ee 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -70,6 +70,146 @@
 		#size-cells = <2>;
 		ranges;
 
+		gpio0: gpio@e6058180 {
+			compatible = "renesas,gpio-r8a779a0";
+			reg = <0 0xe6058180 0 0x54>;
+			interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 916>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets =  <&cpg 916>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			// gpio-ranges = <&pfc 0 0 28>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio1: gpio@e6050180 {
+			compatible = "renesas,gpio-r8a779a0";
+			reg = <0 0xe6050180 0 0x54>;
+			interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 915>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets =  <&cpg 915>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			// gpio-ranges = <&pfc 0 32 31>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio@e6050980 {
+			compatible = "renesas,gpio-r8a779a0";
+			reg = <0 0xe6050980 0 0x54>;
+			interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 915>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets =  <&cpg 915>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			// gpio-ranges = <&pfc 0 64 25>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio3: gpio@e6058980 {
+			compatible = "renesas,gpio-r8a779a0";
+			reg = <0 0xe6058980 0 0x54>;
+			interrupts = <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 916>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets =  <&cpg 916>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			// gpio-ranges = <&pfc 0 96 17>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio4: gpio@e6060180 {
+			compatible = "renesas,gpio-r8a779a0";
+			reg = <0 0xe6060180 0 0x54>;
+			interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 917>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets =  <&cpg 917>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			// gpio-ranges = <&pfc 0 128 27>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio5: gpio@e6060980 {
+			compatible = "renesas,gpio-r8a779a0";
+			reg = <0 0xe6060980 0 0x54>;
+			interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 917>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets =  <&cpg 917>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			// gpio-ranges = <&pfc 0 160 21>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio6: gpio@e6068180 {
+			compatible = "renesas,gpio-r8a779a0";
+			reg = <0 0xe6068180 0 0x54>;
+			interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 918>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets =  <&cpg 918>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			// gpio-ranges = <&pfc 0 192 21>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio7: gpio@e6068980 {
+			compatible = "renesas,gpio-r8a779a0";
+			reg = <0 0xe6068980 0 0x54>;
+			interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 918>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets =  <&cpg 918>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			// gpio-ranges = <&pfc 0 224 21>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio8: gpio@e6069180 {
+			compatible = "renesas,gpio-r8a779a0";
+			reg = <0 0xe6069180 0 0x54>;
+			interrupts = <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 918>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets =  <&cpg 918>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			// gpio-ranges = <&pfc 0 256 21>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio9: gpio@e6069980 {
+			compatible = "renesas,gpio-r8a779a0";
+			reg = <0 0xe6069980 0 0x54>;
+			interrupts = <GIC_SPI 868 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 918>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets =  <&cpg 918>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			// gpio-ranges = <&pfc 0 288 21>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
 		cpg: clock-controller@e6150000 {
 			compatible = "renesas,r8a779a0-cpg-mssr";
 			reg = <0 0xe6150000 0 0x4000>;
-- 
2.17.1

Re: [PATCH/RFC 5/6] gpio: rcar: Add support for R-Car V3U

[Geert Uytterhoeven]

On Mon, Oct 19, 2020 at 2:06 PM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> From: Phong Hoang <phong.hoang.wz@renesas.com>
>
> Add support for the R-Car V3U (r8a779a0) SoC.
> This includes support for the new "General Input Enable" register to
> control input enable.
>
> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Untested on actual hardware.
>
> Should input be enabled unconditionally, as recommended by the Hardware
> Manual for backwards compatibility with existing software?
> As per (errata?) commit ae9550f635533b1c ("gpio-rcar: Use OUTDT when
> reading GPIOs configured as output"), the gpio-rcar driver does not use
> the INDT register to read the status of a GPIO line when configured for
> output.

More investigation:
  1. On SH7734, R-Car Gen1, R-Car Gen2, and RZ/G1, INDT only reflects
     the state of the input pin if the GPIO is configured for input
     (documented, verified on R-Car M2-W),
  2. On R-Car Gen3 and RZ/G2, INDT always reflects the state of the
     input pin (documented, verified on R-Car H3/M3-W/M3-N),
  3. On R-Car V3U, input enable can be configured explicitly through the
      new INEN register (documented, unverified).

Given register accesses are slow, I think it makes sense to enable input
explicitly and unconditionally on R-Car V3U, and always use INDT to read
pin state on R-Car Gen3 and V3U.

Thanks for your comments!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH/RFC 1/6] clk: renesas: r8a779a0: Remove non-existent S2 clock

[Yoshihiro Shimoda]

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Monday, October 19, 2020 9:06 PM
> 
> The S2 internal core clock does not exist on R-Car V3U. Remove it.
> 
> Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thank you for the patch!

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Best regards,
Yoshihiro Shimoda

RE: [PATCH/RFC 2/6] clk: renesas: r8a779a0: Fix parent of CBFUSA clock

[Yoshihiro Shimoda]

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Monday, October 19, 2020 9:06 PM
> 
> According to Figure 8.1.1 ("Block Diagram of CPG (R-Car V3U-AD)") in the
> R-Car V3U Series User's Manual Rev. 0.5, the parent of the CBFUSA clock
> is EXTAL.
> 
> Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thank you for the patch!

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Best regards,
Yoshihiro Shimoda

RE: [PATCH/RFC 3/6] clk: renesas: r8a779a0: Add PFC/GPIO clocks

[Yoshihiro Shimoda]

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Monday, October 19, 2020 9:06 PM
> 
> Add the module clocks used by the Pin Function Controller (PFC) and
> General Purpose Input/Output (GPIO) blocks, and their parent clock CP.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Untested on actual hardware.
> 
> Note that the BSP uses MAIN instead of EXTAL, just like for the CBFUSA
> clock.  However, according to Figure 8.1.1 ("Block Diagram of CPG (R-Car
> V3U-AD)") in the R-Car V3U Series User's Manual Rev. 0.5, the parent of
> the CP clock is EXTAL, which matches earlier R-Car Gen3 SoCs.

Thank you for the patch!

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Best regards,
Yoshihiro Shimoda

RE: [PATCH/RFC 3/6] clk: renesas: r8a779a0: Add PFC/GPIO clocks

[Yoshihiro Shimoda]

Hi Geert-san again,

> From: Yoshihiro Shimoda, Sent: Wednesday, October 21, 2020 4:41 PM
> 
> Hi Geert-san,
> 
> > From: Geert Uytterhoeven, Sent: Monday, October 19, 2020 9:06 PM
> >
> > Add the module clocks used by the Pin Function Controller (PFC) and
> > General Purpose Input/Output (GPIO) blocks, and their parent clock CP.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > Untested on actual hardware.
> >
> > Note that the BSP uses MAIN instead of EXTAL, just like for the CBFUSA
> > clock.  However, according to Figure 8.1.1 ("Block Diagram of CPG (R-Car
> > V3U-AD)") in the R-Car V3U Series User's Manual Rev. 0.5, the parent of
> > the CP clock is EXTAL, which matches earlier R-Car Gen3 SoCs.
> 
> Thank you for the patch!
> 
> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

I'm afraid but, since the upstream code doesn't have the following "vin3[567]"
lines, we should remove it from this patch. After fixed it,
you can use my Reviewed-by :)

>@@ -180,6 +181,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
> 	DEF_MOD("vin35",	827,	R8A779A0_CLK_S1D1),
> 	DEF_MOD("vin36",	828,	R8A779A0_CLK_S1D1),
> 	DEF_MOD("vin37",	829,	R8A779A0_CLK_S1D1),

Best regards,
Yoshihiro Shimoda

Re: [PATCH/RFC 3/6] clk: renesas: r8a779a0: Add PFC/GPIO clocks

[Geert Uytterhoeven]

Hi Shimoda-san,

On Wed, Oct 21, 2020 at 10:07 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> > From: Yoshihiro Shimoda, Sent: Wednesday, October 21, 2020 4:41 PM
> > > From: Geert Uytterhoeven, Sent: Monday, October 19, 2020 9:06 PM
> > >
> > > Add the module clocks used by the Pin Function Controller (PFC) and
> > > General Purpose Input/Output (GPIO) blocks, and their parent clock CP.
> > >
> > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > ---
> > > Untested on actual hardware.
> > >
> > > Note that the BSP uses MAIN instead of EXTAL, just like for the CBFUSA
> > > clock.  However, according to Figure 8.1.1 ("Block Diagram of CPG (R-Car
> > > V3U-AD)") in the R-Car V3U Series User's Manual Rev. 0.5, the parent of
> > > the CP clock is EXTAL, which matches earlier R-Car Gen3 SoCs.
> >
> > Thank you for the patch!
> >
> > Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> I'm afraid but, since the upstream code doesn't have the following "vin3[567]"
> lines, we should remove it from this patch. After fixed it,
> you can use my Reviewed-by :)

Right, I had marked Jacopo's VIN clock patch for application to
renesas-clk-for-v5.11, but haven't actually done that, only in my local
tree.

But probably it does make sense to reorder the patches, and apply the
GPIO one first.

> >@@ -180,6 +181,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
> >       DEF_MOD("vin35",        827,    R8A779A0_CLK_S1D1),
> >       DEF_MOD("vin36",        828,    R8A779A0_CLK_S1D1),
> >       DEF_MOD("vin37",        829,    R8A779A0_CLK_S1D1),

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH/RFC 5/6] gpio: rcar: Add support for R-Car V3U

[Ulrich Hecht]

Thank you for your patch!

> On 10/19/2020 2:06 PM Geert Uytterhoeven <geert+renesas@glider.be> wrote:
> 
>  
> From: Phong Hoang <phong.hoang.wz@renesas.com>
> 
> Add support for the R-Car V3U (r8a779a0) SoC.
> This includes support for the new "General Input Enable" register to
> control input enable.
> 
> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Untested on actual hardware.
> 
> Should input be enabled unconditionally, as recommended by the Hardware
> Manual for backwards compatibility with existing software?
> As per (errata?) commit ae9550f635533b1c ("gpio-rcar: Use OUTDT when
> reading GPIOs configured as output"), the gpio-rcar driver does not use
> the INDT register to read the status of a GPIO line when configured for
> output.
> ---
>  drivers/gpio/gpio-rcar.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
> index a924cf8ac8df7f8f..44d09a0028db49e9 100644
> --- a/drivers/gpio/gpio-rcar.c
> +++ b/drivers/gpio/gpio-rcar.c
> @@ -42,6 +42,7 @@ struct gpio_rcar_priv {
>  	atomic_t wakeup_path;
>  	bool has_outdtsel;
>  	bool has_both_edge_trigger;
> +	bool has_inen;
>  	struct gpio_rcar_bank_info bank_info;
>  };
>  
> @@ -58,6 +59,7 @@ struct gpio_rcar_priv {
>  #define FILONOFF 0x28	/* Chattering Prevention On/Off Register */
>  #define OUTDTSEL 0x40	/* Output Data Select Register */
>  #define BOTHEDGE 0x4c	/* One Edge/Both Edge Select Register */
> +#define INEN 0x50	/* General Input Enable Register */
>  
>  #define RCAR_MAX_GPIO_PER_BANK		32
>  
> @@ -126,6 +128,10 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
>  	if (p->has_both_edge_trigger)
>  		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
>  
> +	/* Select "Input Enable" in INEN */
> +	if (p->has_inen)
> +		gpio_rcar_modify_bit(p, INEN, hwirq, true);
> +
>  	/* Select "Interrupt Input Mode" in IOINTSEL */
>  	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
>  
> @@ -231,6 +237,10 @@ static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
>  	/* Configure positive logic in POSNEG */
>  	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
>  
> +	/* Select "Input Enable/Disable" in INEN */

Nit: It's always called "Input Enable" in the DS.

> +	if (p->has_inen)
> +		gpio_rcar_modify_bit(p, INEN, gpio, !output);
> +
>  	/* Select "General Input/Output Mode" in IOINTSEL */
>  	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
>  
> @@ -349,16 +359,25 @@ static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
>  struct gpio_rcar_info {
>  	bool has_outdtsel;
>  	bool has_both_edge_trigger;
> +	bool has_inen;
>  };
>  
>  static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
>  	.has_outdtsel = false,
>  	.has_both_edge_trigger = false,
> +	.has_inen = false,
>  };
>  
>  static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
>  	.has_outdtsel = true,
>  	.has_both_edge_trigger = true,
> +	.has_inen = false,
> +};
> +
> +static const struct gpio_rcar_info gpio_rcar_info_v3u = {
> +	.has_outdtsel = true,
> +	.has_both_edge_trigger = true,
> +	.has_inen = true,
>  };
>  
>  static const struct of_device_id gpio_rcar_of_table[] = {
> @@ -389,6 +408,9 @@ static const struct of_device_id gpio_rcar_of_table[] = {
>  		.compatible = "renesas,gpio-r8a7796",
>  		/* Gen3 GPIO is identical to Gen2. */
>  		.data = &gpio_rcar_info_gen2,
> +	}, {
> +		.compatible = "renesas,gpio-r8a779a0",
> +		.data = &gpio_rcar_info_v3u,
>  	}, {
>  		.compatible = "renesas,rcar-gen1-gpio",
>  		.data = &gpio_rcar_info_gen1,
> @@ -419,6 +441,7 @@ static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
>  	info = of_device_get_match_data(p->dev);
>  	p->has_outdtsel = info->has_outdtsel;
>  	p->has_both_edge_trigger = info->has_both_edge_trigger;
> +	p->has_inen = info->has_inen;
>  
>  	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
>  	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
> -- 
> 2.17.1

Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>

CU
Uli

Re: [PATCH/RFC 5/6] gpio: rcar: Add support for R-Car V3U

[Ulrich Hecht]

> On 10/20/2020 10:22 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > Should input be enabled unconditionally, as recommended by the Hardware
> > Manual for backwards compatibility with existing software?
> > As per (errata?) commit ae9550f635533b1c ("gpio-rcar: Use OUTDT when
> > reading GPIOs configured as output"), the gpio-rcar driver does not use
> > the INDT register to read the status of a GPIO line when configured for
> > output.
> 
> More investigation:
>   1. On SH7734, R-Car Gen1, R-Car Gen2, and RZ/G1, INDT only reflects
>      the state of the input pin if the GPIO is configured for input
>      (documented, verified on R-Car M2-W),
>   2. On R-Car Gen3 and RZ/G2, INDT always reflects the state of the
>      input pin (documented, verified on R-Car H3/M3-W/M3-N),
>   3. On R-Car V3U, input enable can be configured explicitly through the
>       new INEN register (documented, unverified).
> 
> Given register accesses are slow, I think it makes sense to enable input
> explicitly and unconditionally on R-Car V3U, and always use INDT to read
> pin state on R-Car Gen3 and V3U.

That sounds like a good solution to me.

CU
Uli

Re: [PATCH/RFC 1/6] clk: renesas: r8a779a0: Remove non-existent S2 clock

[Wolfram Sang]

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On Mon, Oct 19, 2020 at 02:06:09PM +0200, Geert Uytterhoeven wrote:
> The S2 internal core clock does not exist on R-Car V3U. Remove it.
> 
> Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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Re: [PATCH/RFC 2/6] clk: renesas: r8a779a0: Fix parent of CBFUSA clock

[Wolfram Sang]

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On Mon, Oct 19, 2020 at 02:06:10PM +0200, Geert Uytterhoeven wrote:
> According to Figure 8.1.1 ("Block Diagram of CPG (R-Car V3U-AD)") in the
> R-Car V3U Series User's Manual Rev. 0.5, the parent of the CBFUSA clock
> is EXTAL.
> 
> Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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Re: [PATCH/RFC 3/6] clk: renesas: r8a779a0: Add PFC/GPIO clocks

[Wolfram Sang]

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On Mon, Oct 19, 2020 at 02:06:11PM +0200, Geert Uytterhoeven wrote:
> Add the module clocks used by the Pin Function Controller (PFC) and
> General Purpose Input/Output (GPIO) blocks, and their parent clock CP.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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Re: [PATCH/RFC 4/6] dt-bindings: gpio: rcar: Add r8a779a0 support

[Wolfram Sang]

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On Mon, Oct 19, 2020 at 02:06:12PM +0200, Geert Uytterhoeven wrote:
> Document the compatible value for the GPIO block in the Renesas R-Car
> V3U (R8A779A0) SoC.
> 
> While this GPIO block is mostly compatible with GPIO blocks on R-Car
> Gen3 SoCs, there are small differences, and one of the new registers
> needs to be configured differently from its initial reset state.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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Re: [PATCH/RFC 6/6] arm64: dts: r8a779a0: Add GPIO nodes

[Wolfram Sang]

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On Mon, Oct 19, 2020 at 02:06:14PM +0200, Geert Uytterhoeven wrote:
> Add device nodes for the General Purpose Input/Output (GPIO) block on
> the Renesas R-Car V3u (r8a779a0) SoC.
> 
> As there is no node for the PFC yet, all "gpio-ranges" properties are
> commented out.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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