* [PATCH RESEND v2] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
@ 2021-01-04 0:43 ` Alexandre Belloni
0 siblings, 0 replies; 7+ messages in thread
From: Alexandre Belloni @ 2021-01-04 0:43 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Vladimir Zapolskiy, linux-arm-kernel, linux-kernel,
Alexandre Belloni, Gregory CLEMENT
This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7.
The lpc32xx clock driver is not able to actually change the PLL rate as
this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK,
then stop the PLL, update the register, restart the PLL and wait for the
PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK
PLL.
Currently, the HCLK driver simply updates the registers but this has no
real effect and all the clock rate calculation end up being wrong. This is
especially annoying for the peripheral (e.g. UARTs, I2C, SPI).
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Arnd,
This is a very important fix that was sent back in may and october 2019 without
any reply from the maintainers, please consider applying it so it can be
backported on v5.10.
arch/arm/boot/dts/lpc32xx.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 3a5cfb0ddb20..c87066d6c995 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -326,9 +326,6 @@ clk: clock-controller@0 {
clocks = <&xtal_32k>, <&xtal>;
clock-names = "xtal_32k", "xtal";
-
- assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
- assigned-clock-rates = <208000000>;
};
};
--
2.29.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH RESEND v2] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
@ 2021-01-04 0:43 ` Alexandre Belloni
0 siblings, 0 replies; 7+ messages in thread
From: Alexandre Belloni @ 2021-01-04 0:43 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Gregory CLEMENT, Alexandre Belloni, linux-kernel,
linux-arm-kernel, Vladimir Zapolskiy
This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7.
The lpc32xx clock driver is not able to actually change the PLL rate as
this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK,
then stop the PLL, update the register, restart the PLL and wait for the
PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK
PLL.
Currently, the HCLK driver simply updates the registers but this has no
real effect and all the clock rate calculation end up being wrong. This is
especially annoying for the peripheral (e.g. UARTs, I2C, SPI).
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Arnd,
This is a very important fix that was sent back in may and october 2019 without
any reply from the maintainers, please consider applying it so it can be
backported on v5.10.
arch/arm/boot/dts/lpc32xx.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 3a5cfb0ddb20..c87066d6c995 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -326,9 +326,6 @@ clk: clock-controller@0 {
clocks = <&xtal_32k>, <&xtal>;
clock-names = "xtal_32k", "xtal";
-
- assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
- assigned-clock-rates = <208000000>;
};
};
--
2.29.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH RESEND v2] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
@ 2021-02-03 9:03 ` Alexandre Belloni
0 siblings, 0 replies; 7+ messages in thread
From: Alexandre Belloni @ 2021-02-03 9:03 UTC (permalink / raw)
To: Arnd Bergmann, soc
Cc: Vladimir Zapolskiy, linux-arm-kernel, linux-kernel,
Alexandre Belloni, Gregory CLEMENT
This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7.
The lpc32xx clock driver is not able to actually change the PLL rate as
this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK,
then stop the PLL, update the register, restart the PLL and wait for the
PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK
PLL.
Currently, the HCLK driver simply updates the registers but this has no
real effect and all the clock rate calculation end up being wrong. This is
especially annoying for the peripheral (e.g. UARTs, I2C, SPI).
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Arnd,
This is a very important fix that was sent back in may and october 2019 without
any reply from the maintainers, please consider applying it so it can be
backported on v5.10.
arch/arm/boot/dts/lpc32xx.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 3a5cfb0ddb20..c87066d6c995 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -326,9 +326,6 @@ clk: clock-controller@0 {
clocks = <&xtal_32k>, <&xtal>;
clock-names = "xtal_32k", "xtal";
-
- assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
- assigned-clock-rates = <208000000>;
};
};
--
2.29.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH RESEND v2] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
@ 2021-02-03 9:03 ` Alexandre Belloni
0 siblings, 0 replies; 7+ messages in thread
From: Alexandre Belloni @ 2021-02-03 9:03 UTC (permalink / raw)
To: Arnd Bergmann, soc
Cc: Gregory CLEMENT, Alexandre Belloni, linux-kernel,
linux-arm-kernel, Vladimir Zapolskiy
This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7.
The lpc32xx clock driver is not able to actually change the PLL rate as
this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK,
then stop the PLL, update the register, restart the PLL and wait for the
PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK
PLL.
Currently, the HCLK driver simply updates the registers but this has no
real effect and all the clock rate calculation end up being wrong. This is
especially annoying for the peripheral (e.g. UARTs, I2C, SPI).
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Arnd,
This is a very important fix that was sent back in may and october 2019 without
any reply from the maintainers, please consider applying it so it can be
backported on v5.10.
arch/arm/boot/dts/lpc32xx.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 3a5cfb0ddb20..c87066d6c995 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -326,9 +326,6 @@ clk: clock-controller@0 {
clocks = <&xtal_32k>, <&xtal>;
clock-names = "xtal_32k", "xtal";
-
- assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
- assigned-clock-rates = <208000000>;
};
};
--
2.29.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH RESEND v2] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
2021-02-03 9:03 ` Alexandre Belloni
(?)
@ 2021-02-03 12:10 ` patchwork-bot+linux-soc
-1 siblings, 0 replies; 7+ messages in thread
From: patchwork-bot+linux-soc @ 2021-02-03 12:10 UTC (permalink / raw)
To: Alexandre Belloni; +Cc: soc
Hello:
This patch was applied to soc/soc.git (refs/heads/arm/fixes):
On Wed, 3 Feb 2021 10:03:20 +0100 you wrote:
> This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7.
>
> The lpc32xx clock driver is not able to actually change the PLL rate as
> this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK,
> then stop the PLL, update the register, restart the PLL and wait for the
> PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK
> PLL.
>
> [...]
Here is the summary with links:
- [RESEND,v2] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
https://git.kernel.org/soc/soc/c/5638159f6d93
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH RESEND v2] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
@ 2021-02-03 12:31 ` Arnd Bergmann
0 siblings, 0 replies; 7+ messages in thread
From: Arnd Bergmann @ 2021-02-03 12:31 UTC (permalink / raw)
To: soc, Alexandre Belloni
Cc: Arnd Bergmann, Vladimir Zapolskiy, linux-kernel, Gregory CLEMENT,
linux-arm-kernel
From: Arnd Bergmann <arnd@arndb.de>
On Wed, 3 Feb 2021 10:03:20 +0100, Alexandre Belloni wrote:
> This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7.
>
> The lpc32xx clock driver is not able to actually change the PLL rate as
> this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK,
> then stop the PLL, update the register, restart the PLL and wait for the
> PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK
> PLL.
>
> [...]
Applied to arm/fixes, thanks!
[1/1] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
commit: 5638159f6d93b99ec9743ac7f65563fca3cf413d
Arnd
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH RESEND v2] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
@ 2021-02-03 12:31 ` Arnd Bergmann
0 siblings, 0 replies; 7+ messages in thread
From: Arnd Bergmann @ 2021-02-03 12:31 UTC (permalink / raw)
To: soc, Alexandre Belloni
Cc: linux-arm-kernel, Gregory CLEMENT, linux-kernel, Arnd Bergmann,
Vladimir Zapolskiy
From: Arnd Bergmann <arnd@arndb.de>
On Wed, 3 Feb 2021 10:03:20 +0100, Alexandre Belloni wrote:
> This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7.
>
> The lpc32xx clock driver is not able to actually change the PLL rate as
> this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK,
> then stop the PLL, update the register, restart the PLL and wait for the
> PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK
> PLL.
>
> [...]
Applied to arm/fixes, thanks!
[1/1] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
commit: 5638159f6d93b99ec9743ac7f65563fca3cf413d
Arnd
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-02-03 12:32 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2021-01-04 0:43 [PATCH RESEND v2] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL Alexandre Belloni
2021-01-04 0:43 ` Alexandre Belloni
2021-02-03 9:03 Alexandre Belloni
2021-02-03 9:03 ` Alexandre Belloni
2021-02-03 12:10 ` patchwork-bot+linux-soc
2021-02-03 12:31 ` Arnd Bergmann
2021-02-03 12:31 ` Arnd Bergmann
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