[PULL 0/3] tcg patch queue

[PULL 0/3] tcg patch queue

[Richard Henderson]

The following changes since commit 41192db338588051f21501abc13743e62b0a5605:

  Merge remote-tracking branch 'remotes/ehabkost-gl/tags/machine-next-pull-request' into staging (2021-01-01 22:57:15 +0000)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210104

for you to fetch changes up to a66424ba17d661007dc13d78c9e3014ccbaf0efb:

  tcg: Add tcg_gen_bswap_tl alias (2021-01-04 06:32:58 -1000)

----------------------------------------------------------------
Fix vector clear issue.
Fix riscv host shift issue.
Add tcg_gen_bswap_tl.

----------------------------------------------------------------
Richard Henderson (2):
      tcg: Use memset for large vector byte replication
      tcg: Add tcg_gen_bswap_tl alias

Zihao Yu (1):
      tcg/riscv: Fix illegal shift instructions

 accel/tcg/tcg-runtime.h     | 11 +++++++++++
 include/exec/helper-proto.h |  4 ++++
 include/tcg/tcg-op.h        |  2 ++
 tcg/tcg-op-gvec.c           | 32 ++++++++++++++++++++++++++++++++
 tcg/riscv/tcg-target.c.inc  | 12 ++++++------
 5 files changed, 55 insertions(+), 6 deletions(-)

[PULL 1/3] tcg: Use memset for large vector byte replication

[Richard Henderson]

In f47db80cc07, we handled odd-sized tail clearing for
the case of hosts that have vector operations, but did
not handle the case of hosts that do not have vector ops.

This was ok until e2e7168a214b, which changed the encoding
of simd_desc such that the odd sizes are impossible.

Add memset as a tcg helper, and use that for all out-of-line
byte stores to vectors.  This includes, but is not limited to,
the tail clearing operation in question.

Cc: qemu-stable@nongnu.org
Buglink: https://bugs.launchpad.net/bugs/1907817
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/tcg-runtime.h     | 11 +++++++++++
 include/exec/helper-proto.h |  4 ++++
 tcg/tcg-op-gvec.c           | 32 ++++++++++++++++++++++++++++++++
 3 files changed, 47 insertions(+)

diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index 4eda24e63a..2e36d6eb0c 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -28,6 +28,17 @@ DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env)
 
 DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env)
 
+#ifndef IN_HELPER_PROTO
+/*
+ * Pass calls to memset directly to libc, without a thunk in qemu.
+ * Do not re-declare memset, especially since we fudge the type here;
+ * we assume sizeof(void *) == sizeof(size_t), which is true for
+ * all supported hosts.
+ */
+#define helper_memset memset
+DEF_HELPER_FLAGS_3(memset, TCG_CALL_NO_RWG, ptr, ptr, int, ptr)
+#endif /* IN_HELPER_PROTO */
+
 #ifdef CONFIG_SOFTMMU
 
 DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG,
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
index a0a8d9aa46..659f9298e8 100644
--- a/include/exec/helper-proto.h
+++ b/include/exec/helper-proto.h
@@ -35,11 +35,15 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
                             dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \
                             dh_ctype(t7));
 
+#define IN_HELPER_PROTO
+
 #include "helper.h"
 #include "trace/generated-helpers.h"
 #include "tcg-runtime.h"
 #include "plugin-helpers.h"
 
+#undef IN_HELPER_PROTO
+
 #undef DEF_HELPER_FLAGS_0
 #undef DEF_HELPER_FLAGS_1
 #undef DEF_HELPER_FLAGS_2
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index ddbe06b71a..1a41dfa908 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -547,6 +547,9 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,
         in_c = dup_const(vece, in_c);
         if (in_c == 0) {
             oprsz = maxsz;
+            vece = MO_8;
+        } else if (in_c == dup_const(MO_8, in_c)) {
+            vece = MO_8;
         }
     }
 
@@ -628,6 +631,35 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,
     /* Otherwise implement out of line.  */
     t_ptr = tcg_temp_new_ptr();
     tcg_gen_addi_ptr(t_ptr, cpu_env, dofs);
+
+    /*
+     * This may be expand_clr for the tail of an operation, e.g.
+     * oprsz == 8 && maxsz == 64.  The size of the clear is misaligned
+     * wrt simd_desc and will assert.  Simply pass all replicated byte
+     * stores through to memset.
+     */
+    if (oprsz == maxsz && vece == MO_8) {
+        TCGv_ptr t_size = tcg_const_ptr(oprsz);
+        TCGv_i32 t_val;
+
+        if (in_32) {
+            t_val = in_32;
+        } else if (in_64) {
+            t_val = tcg_temp_new_i32();
+            tcg_gen_extrl_i64_i32(t_val, in_64);
+        } else {
+            t_val = tcg_const_i32(in_c);
+        }
+        gen_helper_memset(t_ptr, t_ptr, t_val, t_size);
+
+        if (!in_32) {
+            tcg_temp_free_i32(t_val);
+        }
+        tcg_temp_free_ptr(t_size);
+        tcg_temp_free_ptr(t_ptr);
+        return;
+    }
+
     t_desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0));
 
     if (vece == MO_64) {
-- 
2.25.1

[PULL 2/3] tcg/riscv: Fix illegal shift instructions

[Richard Henderson]

From: Zihao Yu <yuzihao@ict.ac.cn>

Out-of-range shifts have undefined results, but must not trap.
Mask off immediate shift counts to solve this problem.

This bug can be reproduced by running the following guest instructions:

  xor %ecx,%ecx
  sar %cl,%eax
  cmovne %edi,%eax

After optimization, the tcg opcodes of the sar are

  movi_i32 tmp3,$0xffffffffffffffff  pref=all
  sar_i32 tmp3,eax,tmp3              dead: 2  pref=all
  mov_i32 cc_dst,eax                 sync: 0  dead: 1 pref=0xffc0300
  mov_i32 cc_src,tmp3                sync: 0  dead: 0 1  pref=all
  movi_i32 cc_op,$0x31               sync: 0  dead: 0  pref=all

The sar_i32 opcode is a shift by -1, which unmasked generates

  0x200808d618:  fffa5b9b          illegal

Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn>
Message-Id: <20201216081206.9628-1-yuzihao@ict.ac.cn>
[rth: Reworded the patch description.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target.c.inc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index d536f3ccc1..4089e29cd9 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1462,14 +1462,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 
     case INDEX_op_shl_i32:
         if (c2) {
-            tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2);
+            tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2 & 0x1f);
         } else {
             tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2);
         }
         break;
     case INDEX_op_shl_i64:
         if (c2) {
-            tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2);
+            tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2 & 0x3f);
         } else {
             tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2);
         }
@@ -1477,14 +1477,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 
     case INDEX_op_shr_i32:
         if (c2) {
-            tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2);
+            tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2 & 0x1f);
         } else {
             tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2);
         }
         break;
     case INDEX_op_shr_i64:
         if (c2) {
-            tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2);
+            tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2 & 0x3f);
         } else {
             tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2);
         }
@@ -1492,14 +1492,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 
     case INDEX_op_sar_i32:
         if (c2) {
-            tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2);
+            tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2 & 0x1f);
         } else {
             tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2);
         }
         break;
     case INDEX_op_sar_i64:
         if (c2) {
-            tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2);
+            tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2 & 0x3f);
         } else {
             tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2);
         }
-- 
2.25.1

[PULL 3/3] tcg: Add tcg_gen_bswap_tl alias

[Richard Henderson]

The alias is intended to indicate that the bswap is for the
entire target_long.  This should avoid ifdefs on some targets.

Reviewed-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg-op.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 5abf17fecc..5b3bdacc39 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -1085,6 +1085,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
 #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
+#define tcg_gen_bswap_tl tcg_gen_bswap64_i64
 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
 #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
 #define tcg_gen_andc_tl tcg_gen_andc_i64
@@ -1197,6 +1198,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
 #define tcg_gen_ext32s_tl tcg_gen_mov_i32
 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
+#define tcg_gen_bswap_tl tcg_gen_bswap32_i32
 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
 #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
 #define tcg_gen_andc_tl tcg_gen_andc_i32
-- 
2.25.1

Re: [PULL 0/3] tcg patch queue

[Peter Maydell]

On Mon, 4 Jan 2021 at 17:35, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 41192db338588051f21501abc13743e62b0a5605:
>
>   Merge remote-tracking branch 'remotes/ehabkost-gl/tags/machine-next-pull-request' into staging (2021-01-01 22:57:15 +0000)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210104
>
> for you to fetch changes up to a66424ba17d661007dc13d78c9e3014ccbaf0efb:
>
>   tcg: Add tcg_gen_bswap_tl alias (2021-01-04 06:32:58 -1000)
>
> ----------------------------------------------------------------
> Fix vector clear issue.
> Fix riscv host shift issue.
> Add tcg_gen_bswap_tl.


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM

Re: [PULL 0/3] tcg patch queue

[Richard Henderson]

On 6/2/22 08:13, Richard Henderson wrote:
> The following changes since commit 1e62a82574fc28e64deca589a23cf55ada2e1a7d:
> 
>    Merge tag 'm68k-for-7.1-pull-request' of https://github.com/vivier/qemu-m68k into staging (2022-06-02 06:30:24 -0700)
> 
> are available in the Git repository at:
> 
>    https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220602
> 
> for you to fetch changes up to 94bcc91b2e95e02ec57ed18d5a5e7cb75aa19a50:
> 
>    tcg/aarch64: Fix illegal insn from out-of-range shli (2022-06-02 08:09:46 -0700)
> 
> ----------------------------------------------------------------
> Add tcg_gen_mov_ptr.
> Fix tcg/i386 encoding of avx512 vpsraq.
> Fix tcg/aarch64 handling of out-of-range shli.

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.


r~



> 
> ----------------------------------------------------------------
> Richard Henderson (3):
>        tcg: Add tcg_gen_mov_ptr
>        tcg/i386: Fix encoding of OPC_VPSRAQ for INDEX_op_sars_vec
>        tcg/aarch64: Fix illegal insn from out-of-range shli
> 
>   include/tcg/tcg-op.h         | 5 +++++
>   tcg/aarch64/tcg-target.c.inc | 2 +-
>   tcg/i386/tcg-target.c.inc    | 2 +-
>   3 files changed, 7 insertions(+), 2 deletions(-)

[PULL 0/3] tcg patch queue

[Richard Henderson]

The following changes since commit 1e62a82574fc28e64deca589a23cf55ada2e1a7d:

  Merge tag 'm68k-for-7.1-pull-request' of https://github.com/vivier/qemu-m68k into staging (2022-06-02 06:30:24 -0700)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220602

for you to fetch changes up to 94bcc91b2e95e02ec57ed18d5a5e7cb75aa19a50:

  tcg/aarch64: Fix illegal insn from out-of-range shli (2022-06-02 08:09:46 -0700)

----------------------------------------------------------------
Add tcg_gen_mov_ptr.
Fix tcg/i386 encoding of avx512 vpsraq.
Fix tcg/aarch64 handling of out-of-range shli.

----------------------------------------------------------------
Richard Henderson (3):
      tcg: Add tcg_gen_mov_ptr
      tcg/i386: Fix encoding of OPC_VPSRAQ for INDEX_op_sars_vec
      tcg/aarch64: Fix illegal insn from out-of-range shli

 include/tcg/tcg-op.h         | 5 +++++
 tcg/aarch64/tcg-target.c.inc | 2 +-
 tcg/i386/tcg-target.c.inc    | 2 +-
 3 files changed, 7 insertions(+), 2 deletions(-)

Re: [PULL 0/3] tcg patch queue

[Peter Maydell]

On Mon, 28 Feb 2022 at 18:09, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 00483d386901173e84c7965f9f0d678791a75e01:
>
>   Merge remote-tracking branch 'remotes/shorne/tags/or1k-pull-request' into staging (2022-02-28 11:27:16 +0000)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220228
>
> for you to fetch changes up to 2ccf40f00e3f29d85d4ff48a9a98870059002290:
>
>   tcg/tci: Use tcg_out_ldst in tcg_out_st (2022-02-28 08:04:10 -1000)
>
> ----------------------------------------------------------------
> Fix typecode generation for tcg helpers
> Fix single stepping into interrupt handlers
> Fix out-of-range offsets for stores in TCI
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.

-- PMM

[PULL 0/3] tcg patch queue

[Richard Henderson]

The following changes since commit 00483d386901173e84c7965f9f0d678791a75e01:

  Merge remote-tracking branch 'remotes/shorne/tags/or1k-pull-request' into staging (2022-02-28 11:27:16 +0000)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220228

for you to fetch changes up to 2ccf40f00e3f29d85d4ff48a9a98870059002290:

  tcg/tci: Use tcg_out_ldst in tcg_out_st (2022-02-28 08:04:10 -1000)

----------------------------------------------------------------
Fix typecode generation for tcg helpers
Fix single stepping into interrupt handlers
Fix out-of-range offsets for stores in TCI

----------------------------------------------------------------
Luc Michel (1):
      accel/tcg/cpu-exec: Fix precise single-stepping after interrupt

Richard Henderson (2):
      tcg: Remove dh_alias indirection for dh_typecode
      tcg/tci: Use tcg_out_ldst in tcg_out_st

 include/exec/helper-head.h   | 19 ++++++++++---------
 target/hppa/helper.h         |  2 ++
 target/i386/ops_sse_header.h |  3 +++
 target/m68k/helper.h         |  1 +
 target/ppc/helper.h          |  3 +++
 accel/tcg/cpu-exec.c         |  8 ++++++--
 tcg/tci/tcg-target.c.inc     |  5 ++---
 7 files changed, 27 insertions(+), 14 deletions(-)

Re: [PULL 0/3] tcg patch queue

[Peter Maydell]

On Fri, 11 Dec 2020 at 01:10, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 2ecfc0657afa5d29a373271b342f704a1a3c6737:
>
>   Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-12-10' into staging (2020-12-10 17:01:05 +0000)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20201210
>
> for you to fetch changes up to 9e2658d62ebc23efe7df43fc0e306f129510d874:
>
>   accel/tcg: rename tcg-cpus functions to match module name (2020-12-10 17:44:10 -0600)
>
> ----------------------------------------------------------------
> Split CpusAccel for tcg variants
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM

[PULL 0/3] tcg patch queue

[Richard Henderson]

The following changes since commit 2ecfc0657afa5d29a373271b342f704a1a3c6737:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-12-10' into staging (2020-12-10 17:01:05 +0000)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20201210

for you to fetch changes up to 9e2658d62ebc23efe7df43fc0e306f129510d874:

  accel/tcg: rename tcg-cpus functions to match module name (2020-12-10 17:44:10 -0600)

----------------------------------------------------------------
Split CpusAccel for tcg variants

----------------------------------------------------------------
Claudio Fontana (3):
      accel/tcg: split CpusAccel into three TCG variants
      accel/tcg: split tcg_start_vcpu_thread
      accel/tcg: rename tcg-cpus functions to match module name

 accel/tcg/tcg-cpus-icount.h |  17 ++
 accel/tcg/tcg-cpus-rr.h     |  21 ++
 accel/tcg/tcg-cpus.h        |  12 +-
 accel/tcg/tcg-all.c         |  13 +-
 accel/tcg/tcg-cpus-icount.c | 147 +++++++++++++
 accel/tcg/tcg-cpus-mttcg.c  | 140 ++++++++++++
 accel/tcg/tcg-cpus-rr.c     | 305 ++++++++++++++++++++++++++
 accel/tcg/tcg-cpus.c        | 506 +-------------------------------------------
 softmmu/icount.c            |   2 +-
 accel/tcg/meson.build       |   9 +-
 10 files changed, 670 insertions(+), 502 deletions(-)
 create mode 100644 accel/tcg/tcg-cpus-icount.h
 create mode 100644 accel/tcg/tcg-cpus-rr.h
 create mode 100644 accel/tcg/tcg-cpus-icount.c
 create mode 100644 accel/tcg/tcg-cpus-mttcg.c
 create mode 100644 accel/tcg/tcg-cpus-rr.c

Re: [PULL 0/3] tcg patch queue

[Richard Henderson]

On 11/2/20 5:57 AM, Peter Maydell wrote:
> On Tue, 27 Oct 2020 at 16:51, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> ----------------------------------------------------------------
>> Optimize across branches.
>> Add logging for cpu_io_recompile.
> 
> Igor2 reported on IRC that this seems to cause a crash when
> using an hppa guest. This is apparently happening on a proprietary
> disk image, so no reproducible test case, but the logging of
> the tail end of -d in_asm,op is at:
>  http://igor2.repo.hu/tmp/in_asm_op.log
> 
> QEMU asserts with
> ../tcg/tcg.c:3346: tcg fatal error
> 
> The TB in question involves several conditional branches; the
> generated TCG ops look OK to me, and reverting the two commits
> b4cb76e6208cf6b5b and cd0372c515c4732d8b fixes the crash.
> (We didn't test reverting only one of the two commits separately.)

Ok, thanks, I'll look into it.


r~

Re: [PULL 0/3] tcg patch queue

[Peter Maydell]

On Tue, 27 Oct 2020 at 16:51, Richard Henderson
<richard.henderson@linaro.org> wrote:
> ----------------------------------------------------------------
> Optimize across branches.
> Add logging for cpu_io_recompile.

Igor2 reported on IRC that this seems to cause a crash when
using an hppa guest. This is apparently happening on a proprietary
disk image, so no reproducible test case, but the logging of
the tail end of -d in_asm,op is at:
 http://igor2.repo.hu/tmp/in_asm_op.log

QEMU asserts with
../tcg/tcg.c:3346: tcg fatal error

The TB in question involves several conditional branches; the
generated TCG ops look OK to me, and reverting the two commits
b4cb76e6208cf6b5b and cd0372c515c4732d8b fixes the crash.
(We didn't test reverting only one of the two commits separately.)

thanks
-- PMM

Re: [PULL 0/3] tcg patch queue

[Peter Maydell]

On Tue, 27 Oct 2020 at 16:51, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 4a74626970ab4ea475263d155b10fb75c9af0b33:
>
>   Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2020-10-27 11:28:46 +0000)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20201027
>
> for you to fetch changes up to 1d705e8a5bbfe36294081baa45ab68a9ad987f33:
>
>   accel/tcg: Add CPU_LOG_EXEC tracing for cpu_io_recompile() (2020-10-27 09:48:07 -0700)
>
> ----------------------------------------------------------------
> Optimize across branches.
> Add logging for cpu_io_recompile.
>
> ----------------------------------------------------------------
> Peter Maydell (1):
>       accel/tcg: Add CPU_LOG_EXEC tracing for cpu_io_recompile()
>
> Richard Henderson (2):
>       tcg: Do not kill globals at conditional branches
>       tcg/optimize: Flush data at labels not TCG_OPF_BB_END


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.

-- PMM

[PULL 0/3] tcg patch queue

[Richard Henderson]

The following changes since commit 4a74626970ab4ea475263d155b10fb75c9af0b33:

  Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2020-10-27 11:28:46 +0000)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20201027

for you to fetch changes up to 1d705e8a5bbfe36294081baa45ab68a9ad987f33:

  accel/tcg: Add CPU_LOG_EXEC tracing for cpu_io_recompile() (2020-10-27 09:48:07 -0700)

----------------------------------------------------------------
Optimize across branches.
Add logging for cpu_io_recompile.

----------------------------------------------------------------
Peter Maydell (1):
      accel/tcg: Add CPU_LOG_EXEC tracing for cpu_io_recompile()

Richard Henderson (2):
      tcg: Do not kill globals at conditional branches
      tcg/optimize: Flush data at labels not TCG_OPF_BB_END

 include/tcg/tcg-opc.h     |  7 +++---
 include/tcg/tcg.h         |  4 +++-
 accel/tcg/translate-all.c |  4 ++++
 tcg/optimize.c            | 35 +++++++++++++++---------------
 tcg/tcg.c                 | 55 +++++++++++++++++++++++++++++++++++++++++++++--
 5 files changed, 82 insertions(+), 23 deletions(-)

Re: [PULL 0/3] tcg patch queue

[Peter Maydell]

On Thu, 13 Feb 2020 at 00:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:
>
>   Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging (2020-02-10 18:09:14 +0000)
>
> are available in the Git repository at:
>
>   https://github.com/rth7680/qemu.git tags/pull-tcg-20200212
>
> for you to fetch changes up to 2445971604c1cfd3ec484457159f4ac300fb04d2:
>
>   tcg: Add tcg_gen_gvec_5_ptr (2020-02-12 14:58:36 -0800)
>
> ----------------------------------------------------------------
> Fix breakpoint invalidation.
> Add support for tcg helpers with 7 arguments.
> Add support for gvec helpers with 5 arguments.
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.

-- PMM

[PULL 0/3] tcg patch queue

[Richard Henderson]

The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:

  Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging (2020-02-10 18:09:14 +0000)

are available in the Git repository at:

  https://github.com/rth7680/qemu.git tags/pull-tcg-20200212

for you to fetch changes up to 2445971604c1cfd3ec484457159f4ac300fb04d2:

  tcg: Add tcg_gen_gvec_5_ptr (2020-02-12 14:58:36 -0800)

----------------------------------------------------------------
Fix breakpoint invalidation.
Add support for tcg helpers with 7 arguments.
Add support for gvec helpers with 5 arguments.

----------------------------------------------------------------
Max Filippov (1):
      exec: flush CPU TB cache in breakpoint_invalidate

Richard Henderson (1):
      tcg: Add tcg_gen_gvec_5_ptr

Taylor Simpson (1):
      tcg: Add support for a helper with 7 arguments

 include/exec/helper-gen.h   | 13 +++++++++++++
 include/exec/helper-head.h  |  2 ++
 include/exec/helper-proto.h |  6 ++++++
 include/exec/helper-tcg.h   |  7 +++++++
 include/tcg/tcg-op-gvec.h   |  7 +++++++
 exec.c                      | 15 +++++++--------
 tcg/tcg-op-gvec.c           | 32 ++++++++++++++++++++++++++++++++
 7 files changed, 74 insertions(+), 8 deletions(-)