* [PATCH v3 0/6] dt-bindings: display: Convert DWC HDMI TX bindings to YAML
@ 2021-01-05 6:08 ` Laurent Pinchart
0 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:08 UTC (permalink / raw)
To: dri-devel
Cc: devicetree, Sandy Huang, linux-renesas-soc, Chen-Yu Tsai,
Rob Herring, Maxime Ripard, Mark Yao
Hello,
This patch series attempts a conversion of the DWC HDMI TX DT bindings
to YAML. It's mostly identical to v2, with Mark Yao's e-mail address
updated, tags picked, a small MAINTAINERS updated, and the series now
sent to the devicetree@vger.kernel.org mailing list.
The DWC HDMI TX is an HDMI transmitter IP core from Synopsys, integrated
in various SoCs with different glue layers. As such, some properties are
defined in a common document, but sometimes need to be overridden by
platform-specific bindings.
Patch 1/6 adds a base schema for the common properties, based on the
existing dw_hdmi.txt document. Patches 2/6 to 4/6 then convert the
platform-specific bindings for Renesas, NXP and Rockchip SoCs. Patch 5/6
replaces the reference to dw_hdmi.txt in the Allwinner bindings with a
reference to the YAML base schema, and patch 6/6 drops dw_hdmi.txt.
Compared to v1 (sent as an RFC), the base schema now works properly on
all three platforms, and the schemas have been converted to use the OF
graph schema. A more detailed changelog is available in individual
patches.
I have volunteered Philipp Zabel and Mark Yao as maintainers for the
i.MX6 and Rockchip bindings respectively. Please let me know if you
would prefer a different maintainer, or ack the respective patch if this
is fine with you.
Laurent Pinchart (6):
dt-bindings: display: bridge: Add YAML schema for Synopsys DW-HDMI
dt-bindings: display: bridge: renesas,dw-hdmi: Convert binding to YAML
dt-bindings: display: imx: hdmi: Convert binding to YAML
dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
dt-bindings: display: sun8i-a83t-dw-hdmi: Reference dw-hdmi YAML
schema
dt-bindings: display: bridge: Remove deprecated dw_hdmi.txt
.../display/allwinner,sun8i-a83t-dw-hdmi.yaml | 4 +-
.../bindings/display/bridge/dw_hdmi.txt | 33 ----
.../display/bridge/renesas,dw-hdmi.txt | 88 ----------
.../display/bridge/renesas,dw-hdmi.yaml | 128 ++++++++++++++
.../display/bridge/synopsys,dw-hdmi.yaml | 58 +++++++
.../bindings/display/imx/fsl,imx6-hdmi.yaml | 130 ++++++++++++++
.../devicetree/bindings/display/imx/hdmi.txt | 65 -------
.../display/rockchip/dw_hdmi-rockchip.txt | 74 --------
.../display/rockchip/rockchip,dw-hdmi.yaml | 158 ++++++++++++++++++
MAINTAINERS | 2 +-
10 files changed, 477 insertions(+), 263 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
delete mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
create mode 100644 Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
delete mode 100644 Documentation/devicetree/bindings/display/imx/hdmi.txt
delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
--
Regards,
Laurent Pinchart
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 32+ messages in thread* [PATCH v3 1/6] dt-bindings: display: bridge: Add YAML schema for Synopsys DW-HDMI
2021-01-05 6:08 ` Laurent Pinchart
@ 2021-01-05 6:08 ` Laurent Pinchart
-1 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:08 UTC (permalink / raw)
To: dri-devel
Cc: linux-renesas-soc, devicetree, Rob Herring, Sandy Huang,
Chen-Yu Tsai, Maxime Ripard, Philipp Zabel, Mark Yao
Add a .yaml schema containing the common properties for the Synopsys
DesignWare HDMI TX controller. This isn't a full device tree binding
specification, but is meant to be referenced by platform-specific
bindings for the IP core.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
Changes since v1:
- Add default to reg-io-width property
- Add additionalProperties
- Rebase on top of OF graph schema, dropped redundant properties
- Drop cec clock as it's device-specific
- Increase max clocks to 5 to accommodate the Rockchip DW-HDMI
---
.../display/bridge/synopsys,dw-hdmi.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
new file mode 100644
index 000000000000..96c4bc06dbe7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common Properties for Synopsys DesignWare HDMI TX Controller
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description: |
+ This document defines device tree properties for the Synopsys DesignWare HDMI
+ TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
+ binding specification by itself but is meant to be referenced by device tree
+ bindings for the platform-specific integrations of the DWC HDMI TX.
+
+ When referenced from platform device tree bindings the properties defined in
+ this document are defined as follows. The platform device tree bindings are
+ responsible for defining whether each property is required or optional.
+
+properties:
+ reg:
+ maxItems: 1
+
+ reg-io-width:
+ description:
+ Width (in bytes) of the registers specified by the reg property.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [1, 4]
+ default: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 5
+ items:
+ - description: The bus clock for either AHB and APB
+ - description: The internal register configuration clock
+ additionalItems: true
+
+ clock-names:
+ minItems: 2
+ maxItems: 5
+ items:
+ - const: iahb
+ - const: isfr
+ additionalItems: true
+
+ interrupts:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+additionalProperties: true
+
+...
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 1/6] dt-bindings: display: bridge: Add YAML schema for Synopsys DW-HDMI
@ 2021-01-05 6:08 ` Laurent Pinchart
0 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:08 UTC (permalink / raw)
To: dri-devel
Cc: devicetree, Sandy Huang, linux-renesas-soc, Chen-Yu Tsai,
Rob Herring, Maxime Ripard, Mark Yao
Add a .yaml schema containing the common properties for the Synopsys
DesignWare HDMI TX controller. This isn't a full device tree binding
specification, but is meant to be referenced by platform-specific
bindings for the IP core.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
Changes since v1:
- Add default to reg-io-width property
- Add additionalProperties
- Rebase on top of OF graph schema, dropped redundant properties
- Drop cec clock as it's device-specific
- Increase max clocks to 5 to accommodate the Rockchip DW-HDMI
---
.../display/bridge/synopsys,dw-hdmi.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
new file mode 100644
index 000000000000..96c4bc06dbe7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common Properties for Synopsys DesignWare HDMI TX Controller
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description: |
+ This document defines device tree properties for the Synopsys DesignWare HDMI
+ TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
+ binding specification by itself but is meant to be referenced by device tree
+ bindings for the platform-specific integrations of the DWC HDMI TX.
+
+ When referenced from platform device tree bindings the properties defined in
+ this document are defined as follows. The platform device tree bindings are
+ responsible for defining whether each property is required or optional.
+
+properties:
+ reg:
+ maxItems: 1
+
+ reg-io-width:
+ description:
+ Width (in bytes) of the registers specified by the reg property.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [1, 4]
+ default: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 5
+ items:
+ - description: The bus clock for either AHB and APB
+ - description: The internal register configuration clock
+ additionalItems: true
+
+ clock-names:
+ minItems: 2
+ maxItems: 5
+ items:
+ - const: iahb
+ - const: isfr
+ additionalItems: true
+
+ interrupts:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+additionalProperties: true
+
+...
--
Regards,
Laurent Pinchart
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/6] dt-bindings: display: bridge: Add YAML schema for Synopsys DW-HDMI
2021-01-05 6:08 ` Laurent Pinchart
@ 2021-01-05 6:10 ` Laurent Pinchart
-1 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:10 UTC (permalink / raw)
To: Laurent Pinchart
Cc: dri-devel, devicetree, Sandy Huang, linux-renesas-soc,
Chen-Yu Tsai, Rob Herring, Maxime Ripard, Mark Yao
On Tue, Jan 05, 2021 at 08:08:13AM +0200, Laurent Pinchart wrote:
> Add a .yaml schema containing the common properties for the Synopsys
> DesignWare HDMI TX controller. This isn't a full device tree binding
> specification, but is meant to be referenced by platform-specific
> bindings for the IP core.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
I forgot to add
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
here.
> ---
> Changes since v1:
>
> - Add default to reg-io-width property
> - Add additionalProperties
> - Rebase on top of OF graph schema, dropped redundant properties
> - Drop cec clock as it's device-specific
> - Increase max clocks to 5 to accommodate the Rockchip DW-HDMI
> ---
> .../display/bridge/synopsys,dw-hdmi.yaml | 58 +++++++++++++++++++
> 1 file changed, 58 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
> new file mode 100644
> index 000000000000..96c4bc06dbe7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Common Properties for Synopsys DesignWare HDMI TX Controller
> +
> +maintainers:
> + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> +
> +description: |
> + This document defines device tree properties for the Synopsys DesignWare HDMI
> + TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
> + binding specification by itself but is meant to be referenced by device tree
> + bindings for the platform-specific integrations of the DWC HDMI TX.
> +
> + When referenced from platform device tree bindings the properties defined in
> + this document are defined as follows. The platform device tree bindings are
> + responsible for defining whether each property is required or optional.
> +
> +properties:
> + reg:
> + maxItems: 1
> +
> + reg-io-width:
> + description:
> + Width (in bytes) of the registers specified by the reg property.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [1, 4]
> + default: 1
> +
> + clocks:
> + minItems: 2
> + maxItems: 5
> + items:
> + - description: The bus clock for either AHB and APB
> + - description: The internal register configuration clock
> + additionalItems: true
> +
> + clock-names:
> + minItems: 2
> + maxItems: 5
> + items:
> + - const: iahb
> + - const: isfr
> + additionalItems: true
> +
> + interrupts:
> + maxItems: 1
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> +additionalProperties: true
> +
> +...
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/6] dt-bindings: display: bridge: Add YAML schema for Synopsys DW-HDMI
@ 2021-01-05 6:10 ` Laurent Pinchart
0 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:10 UTC (permalink / raw)
To: Laurent Pinchart
Cc: devicetree, Sandy Huang, dri-devel, linux-renesas-soc,
Chen-Yu Tsai, Rob Herring, Maxime Ripard, Mark Yao
On Tue, Jan 05, 2021 at 08:08:13AM +0200, Laurent Pinchart wrote:
> Add a .yaml schema containing the common properties for the Synopsys
> DesignWare HDMI TX controller. This isn't a full device tree binding
> specification, but is meant to be referenced by platform-specific
> bindings for the IP core.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
I forgot to add
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
here.
> ---
> Changes since v1:
>
> - Add default to reg-io-width property
> - Add additionalProperties
> - Rebase on top of OF graph schema, dropped redundant properties
> - Drop cec clock as it's device-specific
> - Increase max clocks to 5 to accommodate the Rockchip DW-HDMI
> ---
> .../display/bridge/synopsys,dw-hdmi.yaml | 58 +++++++++++++++++++
> 1 file changed, 58 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
> new file mode 100644
> index 000000000000..96c4bc06dbe7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Common Properties for Synopsys DesignWare HDMI TX Controller
> +
> +maintainers:
> + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> +
> +description: |
> + This document defines device tree properties for the Synopsys DesignWare HDMI
> + TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
> + binding specification by itself but is meant to be referenced by device tree
> + bindings for the platform-specific integrations of the DWC HDMI TX.
> +
> + When referenced from platform device tree bindings the properties defined in
> + this document are defined as follows. The platform device tree bindings are
> + responsible for defining whether each property is required or optional.
> +
> +properties:
> + reg:
> + maxItems: 1
> +
> + reg-io-width:
> + description:
> + Width (in bytes) of the registers specified by the reg property.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [1, 4]
> + default: 1
> +
> + clocks:
> + minItems: 2
> + maxItems: 5
> + items:
> + - description: The bus clock for either AHB and APB
> + - description: The internal register configuration clock
> + additionalItems: true
> +
> + clock-names:
> + minItems: 2
> + maxItems: 5
> + items:
> + - const: iahb
> + - const: isfr
> + additionalItems: true
> +
> + interrupts:
> + maxItems: 1
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> +additionalProperties: true
> +
> +...
--
Regards,
Laurent Pinchart
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/6] dt-bindings: display: bridge: Add YAML schema for Synopsys DW-HDMI
2021-01-05 6:08 ` Laurent Pinchart
@ 2021-01-11 22:45 ` Rob Herring
-1 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2021-01-11 22:45 UTC (permalink / raw)
To: Laurent Pinchart
Cc: dri-devel, linux-renesas-soc, devicetree, Sandy Huang,
Chen-Yu Tsai, Maxime Ripard, Philipp Zabel, Mark Yao
On Tue, Jan 05, 2021 at 08:08:13AM +0200, Laurent Pinchart wrote:
> Add a .yaml schema containing the common properties for the Synopsys
> DesignWare HDMI TX controller. This isn't a full device tree binding
> specification, but is meant to be referenced by platform-specific
> bindings for the IP core.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> Changes since v1:
>
> - Add default to reg-io-width property
> - Add additionalProperties
> - Rebase on top of OF graph schema, dropped redundant properties
> - Drop cec clock as it's device-specific
> - Increase max clocks to 5 to accommodate the Rockchip DW-HDMI
> ---
> .../display/bridge/synopsys,dw-hdmi.yaml | 58 +++++++++++++++++++
> 1 file changed, 58 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
> new file mode 100644
> index 000000000000..96c4bc06dbe7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Common Properties for Synopsys DesignWare HDMI TX Controller
> +
> +maintainers:
> + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> +
> +description: |
> + This document defines device tree properties for the Synopsys DesignWare HDMI
> + TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
> + binding specification by itself but is meant to be referenced by device tree
> + bindings for the platform-specific integrations of the DWC HDMI TX.
> +
> + When referenced from platform device tree bindings the properties defined in
> + this document are defined as follows. The platform device tree bindings are
> + responsible for defining whether each property is required or optional.
> +
> +properties:
> + reg:
> + maxItems: 1
> +
> + reg-io-width:
> + description:
> + Width (in bytes) of the registers specified by the reg property.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [1, 4]
> + default: 1
> +
> + clocks:
> + minItems: 2
> + maxItems: 5
> + items:
> + - description: The bus clock for either AHB and APB
> + - description: The internal register configuration clock
> + additionalItems: true
> +
> + clock-names:
> + minItems: 2
> + maxItems: 5
> + items:
> + - const: iahb
> + - const: isfr
> + additionalItems: true
> +
> + interrupts:
> + maxItems: 1
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
'ports' should probably be dropped if what each 'port' is is not defined
here. Any users will have to define 'ports' and the child nodes.
Reviewed-by: Rob Herring <robh@kernel.org>
> +
> +additionalProperties: true
> +
> +...
> --
> Regards,
>
> Laurent Pinchart
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/6] dt-bindings: display: bridge: Add YAML schema for Synopsys DW-HDMI
@ 2021-01-11 22:45 ` Rob Herring
0 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2021-01-11 22:45 UTC (permalink / raw)
To: Laurent Pinchart
Cc: devicetree, Sandy Huang, dri-devel, linux-renesas-soc,
Chen-Yu Tsai, Maxime Ripard, Mark Yao
On Tue, Jan 05, 2021 at 08:08:13AM +0200, Laurent Pinchart wrote:
> Add a .yaml schema containing the common properties for the Synopsys
> DesignWare HDMI TX controller. This isn't a full device tree binding
> specification, but is meant to be referenced by platform-specific
> bindings for the IP core.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> Changes since v1:
>
> - Add default to reg-io-width property
> - Add additionalProperties
> - Rebase on top of OF graph schema, dropped redundant properties
> - Drop cec clock as it's device-specific
> - Increase max clocks to 5 to accommodate the Rockchip DW-HDMI
> ---
> .../display/bridge/synopsys,dw-hdmi.yaml | 58 +++++++++++++++++++
> 1 file changed, 58 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
> new file mode 100644
> index 000000000000..96c4bc06dbe7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Common Properties for Synopsys DesignWare HDMI TX Controller
> +
> +maintainers:
> + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> +
> +description: |
> + This document defines device tree properties for the Synopsys DesignWare HDMI
> + TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
> + binding specification by itself but is meant to be referenced by device tree
> + bindings for the platform-specific integrations of the DWC HDMI TX.
> +
> + When referenced from platform device tree bindings the properties defined in
> + this document are defined as follows. The platform device tree bindings are
> + responsible for defining whether each property is required or optional.
> +
> +properties:
> + reg:
> + maxItems: 1
> +
> + reg-io-width:
> + description:
> + Width (in bytes) of the registers specified by the reg property.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [1, 4]
> + default: 1
> +
> + clocks:
> + minItems: 2
> + maxItems: 5
> + items:
> + - description: The bus clock for either AHB and APB
> + - description: The internal register configuration clock
> + additionalItems: true
> +
> + clock-names:
> + minItems: 2
> + maxItems: 5
> + items:
> + - const: iahb
> + - const: isfr
> + additionalItems: true
> +
> + interrupts:
> + maxItems: 1
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
'ports' should probably be dropped if what each 'port' is is not defined
here. Any users will have to define 'ports' and the child nodes.
Reviewed-by: Rob Herring <robh@kernel.org>
> +
> +additionalProperties: true
> +
> +...
> --
> Regards,
>
> Laurent Pinchart
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 2/6] dt-bindings: display: bridge: renesas,dw-hdmi: Convert binding to YAML
2021-01-05 6:08 ` Laurent Pinchart
@ 2021-01-05 6:08 ` Laurent Pinchart
-1 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:08 UTC (permalink / raw)
To: dri-devel
Cc: linux-renesas-soc, devicetree, Rob Herring, Sandy Huang,
Chen-Yu Tsai, Maxime Ripard, Philipp Zabel, Mark Yao
Convert the Renesas R-Car DWC HDMI TX text binding to YAML.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
Changes since v2:
- Update MAINTAINERS
Changes since v1:
- Drop the part numbers in comments, only keep the SoC names
- Use unevaluatedProperties instead of additionalProperties
- Only specify maxItems for clocks and clock-names
- Drop reg, interrupts, #address-cells and #size-cells as they're
checked in the base schema
- Use one size and address cell in example
- Rebase on top of OF graph schema, dropped redundant properties
- Fix identation for enum entries
---
.../display/bridge/renesas,dw-hdmi.txt | 88 ------------
.../display/bridge/renesas,dw-hdmi.yaml | 128 ++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 129 insertions(+), 89 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
deleted file mode 100644
index 3f6072651182..000000000000
--- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-Renesas Gen3 DWC HDMI TX Encoder
-================================
-
-The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
-with a companion PHY IP.
-
-These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
-Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
-following device-specific properties.
-
-
-Required properties:
-
-- compatible : Shall contain one or more of
- - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
- - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
- - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
- - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
- - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
- - "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
- - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
- - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible
- HDMI TX
-
- When compatible with generic versions, nodes must list the SoC-specific
- version corresponding to the platform first, followed by the
- family-specific version.
-
-- reg: See dw_hdmi.txt.
-- interrupts: HDMI interrupt number
-- clocks: See dw_hdmi.txt.
-- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
-- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0
- corresponding to the video input of the controller and one port numbered 1
- corresponding to its HDMI output, and one port numbered 2 corresponding to
- sound input of the controller. Each port shall have a single endpoint.
-
-Optional properties:
-
-- power-domains: Shall reference the power domain that contains the DWC HDMI,
- if any.
-
-
-Example:
-
- hdmi0: hdmi@fead0000 {
- compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
- reg = <0 0xfead0000 0 0x10000>;
- interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
- clock-names = "iahb", "isfr";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- dw_hdmi0_in: endpoint {
- remote-endpoint = <&du_out_hdmi0>;
- };
- };
- port@1 {
- reg = <1>;
- rcar_dw_hdmi0_out: endpoint {
- remote-endpoint = <&hdmi0_con>;
- };
- };
- port@2 {
- reg = <2>;
- rcar_dw_hdmi0_sound_in: endpoint {
- remote-endpoint = <&hdmi_sound_out>;
- };
- };
- };
- };
-
- hdmi0-out {
- compatible = "hdmi-connector";
- label = "HDMI0 OUT";
- type = "a";
-
- port {
- hdmi0_con: endpoint {
- remote-endpoint = <&rcar_dw_hdmi0_out>;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
new file mode 100644
index 000000000000..23b940c3aff6
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
@@ -0,0 +1,128 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car DWC HDMI TX Encoder
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description: |
+ The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+ with a companion PHY IP.
+
+allOf:
+ - $ref: synopsys,dw-hdmi.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
+ - renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX
+ - renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX
+ - renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX
+ - renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX
+ - renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX
+ - renesas,r8a77965-hdmi # for R-Car M3-N compatible HDMI TX
+ - const: renesas,rcar-gen3-hdmi
+
+ reg-io-width:
+ const: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ maxItems: 2
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Parallel RGB input port
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: HDMI output port
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Sound input port
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - ports
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/r8a7795-sysc.h>
+
+ hdmi@fead0000 {
+ compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
+ reg = <0xfead0000 0x10000>;
+ interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
+ clock-names = "iahb", "isfr";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dw_hdmi0_in: endpoint {
+ remote-endpoint = <&du_out_hdmi0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ rcar_dw_hdmi0_sound_in: endpoint {
+ remote-endpoint = <&hdmi_sound_out>;
+ };
+ };
+ };
+ };
+
+ hdmi0-out {
+ compatible = "hdmi-connector";
+ label = "HDMI0 OUT";
+ type = "a";
+
+ port {
+ hdmi0_con: endpoint {
+ remote-endpoint = <&rcar_dw_hdmi0_out>;
+ };
+ };
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 22663c2cb3a8..e83a867d96d8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5903,7 +5903,7 @@ L: dri-devel@lists.freedesktop.org
L: linux-renesas-soc@vger.kernel.org
S: Supported
T: git git://linuxtv.org/pinchartl/media drm/du/next
-F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
+F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
F: Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml
F: Documentation/devicetree/bindings/display/renesas,du.yaml
F: drivers/gpu/drm/rcar-du/
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 2/6] dt-bindings: display: bridge: renesas, dw-hdmi: Convert binding to YAML
@ 2021-01-05 6:08 ` Laurent Pinchart
0 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:08 UTC (permalink / raw)
To: dri-devel
Cc: devicetree, Sandy Huang, linux-renesas-soc, Chen-Yu Tsai,
Rob Herring, Maxime Ripard, Mark Yao
Convert the Renesas R-Car DWC HDMI TX text binding to YAML.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
Changes since v2:
- Update MAINTAINERS
Changes since v1:
- Drop the part numbers in comments, only keep the SoC names
- Use unevaluatedProperties instead of additionalProperties
- Only specify maxItems for clocks and clock-names
- Drop reg, interrupts, #address-cells and #size-cells as they're
checked in the base schema
- Use one size and address cell in example
- Rebase on top of OF graph schema, dropped redundant properties
- Fix identation for enum entries
---
.../display/bridge/renesas,dw-hdmi.txt | 88 ------------
.../display/bridge/renesas,dw-hdmi.yaml | 128 ++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 129 insertions(+), 89 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
deleted file mode 100644
index 3f6072651182..000000000000
--- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-Renesas Gen3 DWC HDMI TX Encoder
-================================
-
-The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
-with a companion PHY IP.
-
-These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
-Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
-following device-specific properties.
-
-
-Required properties:
-
-- compatible : Shall contain one or more of
- - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
- - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
- - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
- - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
- - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
- - "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
- - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
- - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible
- HDMI TX
-
- When compatible with generic versions, nodes must list the SoC-specific
- version corresponding to the platform first, followed by the
- family-specific version.
-
-- reg: See dw_hdmi.txt.
-- interrupts: HDMI interrupt number
-- clocks: See dw_hdmi.txt.
-- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
-- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0
- corresponding to the video input of the controller and one port numbered 1
- corresponding to its HDMI output, and one port numbered 2 corresponding to
- sound input of the controller. Each port shall have a single endpoint.
-
-Optional properties:
-
-- power-domains: Shall reference the power domain that contains the DWC HDMI,
- if any.
-
-
-Example:
-
- hdmi0: hdmi@fead0000 {
- compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
- reg = <0 0xfead0000 0 0x10000>;
- interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
- clock-names = "iahb", "isfr";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- dw_hdmi0_in: endpoint {
- remote-endpoint = <&du_out_hdmi0>;
- };
- };
- port@1 {
- reg = <1>;
- rcar_dw_hdmi0_out: endpoint {
- remote-endpoint = <&hdmi0_con>;
- };
- };
- port@2 {
- reg = <2>;
- rcar_dw_hdmi0_sound_in: endpoint {
- remote-endpoint = <&hdmi_sound_out>;
- };
- };
- };
- };
-
- hdmi0-out {
- compatible = "hdmi-connector";
- label = "HDMI0 OUT";
- type = "a";
-
- port {
- hdmi0_con: endpoint {
- remote-endpoint = <&rcar_dw_hdmi0_out>;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
new file mode 100644
index 000000000000..23b940c3aff6
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
@@ -0,0 +1,128 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car DWC HDMI TX Encoder
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description: |
+ The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+ with a companion PHY IP.
+
+allOf:
+ - $ref: synopsys,dw-hdmi.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
+ - renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX
+ - renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX
+ - renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX
+ - renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX
+ - renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX
+ - renesas,r8a77965-hdmi # for R-Car M3-N compatible HDMI TX
+ - const: renesas,rcar-gen3-hdmi
+
+ reg-io-width:
+ const: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ maxItems: 2
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Parallel RGB input port
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: HDMI output port
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Sound input port
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - ports
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/r8a7795-sysc.h>
+
+ hdmi@fead0000 {
+ compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
+ reg = <0xfead0000 0x10000>;
+ interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
+ clock-names = "iahb", "isfr";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dw_hdmi0_in: endpoint {
+ remote-endpoint = <&du_out_hdmi0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ rcar_dw_hdmi0_sound_in: endpoint {
+ remote-endpoint = <&hdmi_sound_out>;
+ };
+ };
+ };
+ };
+
+ hdmi0-out {
+ compatible = "hdmi-connector";
+ label = "HDMI0 OUT";
+ type = "a";
+
+ port {
+ hdmi0_con: endpoint {
+ remote-endpoint = <&rcar_dw_hdmi0_out>;
+ };
+ };
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 22663c2cb3a8..e83a867d96d8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5903,7 +5903,7 @@ L: dri-devel@lists.freedesktop.org
L: linux-renesas-soc@vger.kernel.org
S: Supported
T: git git://linuxtv.org/pinchartl/media drm/du/next
-F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
+F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
F: Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml
F: Documentation/devicetree/bindings/display/renesas,du.yaml
F: drivers/gpu/drm/rcar-du/
--
Regards,
Laurent Pinchart
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v3 2/6] dt-bindings: display: bridge: renesas,dw-hdmi: Convert binding to YAML
2021-01-05 6:08 ` [PATCH v3 2/6] dt-bindings: display: bridge: renesas, dw-hdmi: " Laurent Pinchart
@ 2021-01-11 22:49 ` Rob Herring
-1 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2021-01-11 22:49 UTC (permalink / raw)
To: Laurent Pinchart
Cc: dri-devel, linux-renesas-soc, devicetree, Sandy Huang,
Chen-Yu Tsai, Maxime Ripard, Philipp Zabel, Mark Yao
On Tue, Jan 05, 2021 at 08:08:14AM +0200, Laurent Pinchart wrote:
> Convert the Renesas R-Car DWC HDMI TX text binding to YAML.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> Changes since v2:
>
> - Update MAINTAINERS
>
> Changes since v1:
>
> - Drop the part numbers in comments, only keep the SoC names
> - Use unevaluatedProperties instead of additionalProperties
> - Only specify maxItems for clocks and clock-names
> - Drop reg, interrupts, #address-cells and #size-cells as they're
> checked in the base schema
> - Use one size and address cell in example
> - Rebase on top of OF graph schema, dropped redundant properties
> - Fix identation for enum entries
> ---
> .../display/bridge/renesas,dw-hdmi.txt | 88 ------------
> .../display/bridge/renesas,dw-hdmi.yaml | 128 ++++++++++++++++++
> MAINTAINERS | 2 +-
> 3 files changed, 129 insertions(+), 89 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
> create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
> deleted file mode 100644
> index 3f6072651182..000000000000
> --- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
> +++ /dev/null
> @@ -1,88 +0,0 @@
> -Renesas Gen3 DWC HDMI TX Encoder
> -================================
> -
> -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> -with a companion PHY IP.
> -
> -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> -following device-specific properties.
> -
> -
> -Required properties:
> -
> -- compatible : Shall contain one or more of
> - - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
> - - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
> - - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
> - - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
> - - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
> - - "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
> - - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
> - - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible
> - HDMI TX
> -
> - When compatible with generic versions, nodes must list the SoC-specific
> - version corresponding to the platform first, followed by the
> - family-specific version.
> -
> -- reg: See dw_hdmi.txt.
> -- interrupts: HDMI interrupt number
> -- clocks: See dw_hdmi.txt.
> -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> -- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0
> - corresponding to the video input of the controller and one port numbered 1
> - corresponding to its HDMI output, and one port numbered 2 corresponding to
> - sound input of the controller. Each port shall have a single endpoint.
> -
> -Optional properties:
> -
> -- power-domains: Shall reference the power domain that contains the DWC HDMI,
> - if any.
> -
> -
> -Example:
> -
> - hdmi0: hdmi@fead0000 {
> - compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
> - reg = <0 0xfead0000 0 0x10000>;
> - interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
> - clock-names = "iahb", "isfr";
> - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - port@0 {
> - reg = <0>;
> - dw_hdmi0_in: endpoint {
> - remote-endpoint = <&du_out_hdmi0>;
> - };
> - };
> - port@1 {
> - reg = <1>;
> - rcar_dw_hdmi0_out: endpoint {
> - remote-endpoint = <&hdmi0_con>;
> - };
> - };
> - port@2 {
> - reg = <2>;
> - rcar_dw_hdmi0_sound_in: endpoint {
> - remote-endpoint = <&hdmi_sound_out>;
> - };
> - };
> - };
> - };
> -
> - hdmi0-out {
> - compatible = "hdmi-connector";
> - label = "HDMI0 OUT";
> - type = "a";
> -
> - port {
> - hdmi0_con: endpoint {
> - remote-endpoint = <&rcar_dw_hdmi0_out>;
> - };
> - };
> - };
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
> new file mode 100644
> index 000000000000..23b940c3aff6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
> @@ -0,0 +1,128 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas R-Car DWC HDMI TX Encoder
> +
> +maintainers:
> + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> +
> +description: |
> + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> + with a companion PHY IP.
> +
> +allOf:
> + - $ref: synopsys,dw-hdmi.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
> + - renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX
> + - renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX
> + - renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX
> + - renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX
> + - renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX
> + - renesas,r8a77965-hdmi # for R-Car M3-N compatible HDMI TX
> + - const: renesas,rcar-gen3-hdmi
> +
> + reg-io-width:
> + const: 1
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + maxItems: 2
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
This should be '#/properties/port' instead. '#/$defs/port-base' is if
you have additional port or endpoint properties.
> + unevaluatedProperties: false
And you can then drop this.
With those fixes,
Reviewed-by: Rob Herring <robh@kernel.org>
> + description: Parallel RGB input port
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: HDMI output port
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: Sound input port
> +
> + required:
> + - port@0
> + - port@1
> + - port@2
> +
> + power-domains:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - ports
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/r8a7795-sysc.h>
> +
> + hdmi@fead0000 {
> + compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
> + reg = <0xfead0000 0x10000>;
> + interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
> + clock-names = "iahb", "isfr";
> + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + dw_hdmi0_in: endpoint {
> + remote-endpoint = <&du_out_hdmi0>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + rcar_dw_hdmi0_out: endpoint {
> + remote-endpoint = <&hdmi0_con>;
> + };
> + };
> + port@2 {
> + reg = <2>;
> + rcar_dw_hdmi0_sound_in: endpoint {
> + remote-endpoint = <&hdmi_sound_out>;
> + };
> + };
> + };
> + };
> +
> + hdmi0-out {
> + compatible = "hdmi-connector";
> + label = "HDMI0 OUT";
> + type = "a";
> +
> + port {
> + hdmi0_con: endpoint {
> + remote-endpoint = <&rcar_dw_hdmi0_out>;
> + };
> + };
> + };
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 22663c2cb3a8..e83a867d96d8 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -5903,7 +5903,7 @@ L: dri-devel@lists.freedesktop.org
> L: linux-renesas-soc@vger.kernel.org
> S: Supported
> T: git git://linuxtv.org/pinchartl/media drm/du/next
> -F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
> +F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
> F: Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml
> F: Documentation/devicetree/bindings/display/renesas,du.yaml
> F: drivers/gpu/drm/rcar-du/
> --
> Regards,
>
> Laurent Pinchart
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3 2/6] dt-bindings: display: bridge: renesas,dw-hdmi: Convert binding to YAML
@ 2021-01-11 22:49 ` Rob Herring
0 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2021-01-11 22:49 UTC (permalink / raw)
To: Laurent Pinchart
Cc: devicetree, Sandy Huang, dri-devel, linux-renesas-soc,
Chen-Yu Tsai, Maxime Ripard, Mark Yao
On Tue, Jan 05, 2021 at 08:08:14AM +0200, Laurent Pinchart wrote:
> Convert the Renesas R-Car DWC HDMI TX text binding to YAML.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> Changes since v2:
>
> - Update MAINTAINERS
>
> Changes since v1:
>
> - Drop the part numbers in comments, only keep the SoC names
> - Use unevaluatedProperties instead of additionalProperties
> - Only specify maxItems for clocks and clock-names
> - Drop reg, interrupts, #address-cells and #size-cells as they're
> checked in the base schema
> - Use one size and address cell in example
> - Rebase on top of OF graph schema, dropped redundant properties
> - Fix identation for enum entries
> ---
> .../display/bridge/renesas,dw-hdmi.txt | 88 ------------
> .../display/bridge/renesas,dw-hdmi.yaml | 128 ++++++++++++++++++
> MAINTAINERS | 2 +-
> 3 files changed, 129 insertions(+), 89 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
> create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
> deleted file mode 100644
> index 3f6072651182..000000000000
> --- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
> +++ /dev/null
> @@ -1,88 +0,0 @@
> -Renesas Gen3 DWC HDMI TX Encoder
> -================================
> -
> -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> -with a companion PHY IP.
> -
> -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> -following device-specific properties.
> -
> -
> -Required properties:
> -
> -- compatible : Shall contain one or more of
> - - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
> - - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
> - - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
> - - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
> - - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
> - - "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
> - - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
> - - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible
> - HDMI TX
> -
> - When compatible with generic versions, nodes must list the SoC-specific
> - version corresponding to the platform first, followed by the
> - family-specific version.
> -
> -- reg: See dw_hdmi.txt.
> -- interrupts: HDMI interrupt number
> -- clocks: See dw_hdmi.txt.
> -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> -- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0
> - corresponding to the video input of the controller and one port numbered 1
> - corresponding to its HDMI output, and one port numbered 2 corresponding to
> - sound input of the controller. Each port shall have a single endpoint.
> -
> -Optional properties:
> -
> -- power-domains: Shall reference the power domain that contains the DWC HDMI,
> - if any.
> -
> -
> -Example:
> -
> - hdmi0: hdmi@fead0000 {
> - compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
> - reg = <0 0xfead0000 0 0x10000>;
> - interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
> - clock-names = "iahb", "isfr";
> - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - port@0 {
> - reg = <0>;
> - dw_hdmi0_in: endpoint {
> - remote-endpoint = <&du_out_hdmi0>;
> - };
> - };
> - port@1 {
> - reg = <1>;
> - rcar_dw_hdmi0_out: endpoint {
> - remote-endpoint = <&hdmi0_con>;
> - };
> - };
> - port@2 {
> - reg = <2>;
> - rcar_dw_hdmi0_sound_in: endpoint {
> - remote-endpoint = <&hdmi_sound_out>;
> - };
> - };
> - };
> - };
> -
> - hdmi0-out {
> - compatible = "hdmi-connector";
> - label = "HDMI0 OUT";
> - type = "a";
> -
> - port {
> - hdmi0_con: endpoint {
> - remote-endpoint = <&rcar_dw_hdmi0_out>;
> - };
> - };
> - };
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
> new file mode 100644
> index 000000000000..23b940c3aff6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
> @@ -0,0 +1,128 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas R-Car DWC HDMI TX Encoder
> +
> +maintainers:
> + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> +
> +description: |
> + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> + with a companion PHY IP.
> +
> +allOf:
> + - $ref: synopsys,dw-hdmi.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
> + - renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX
> + - renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX
> + - renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX
> + - renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX
> + - renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX
> + - renesas,r8a77965-hdmi # for R-Car M3-N compatible HDMI TX
> + - const: renesas,rcar-gen3-hdmi
> +
> + reg-io-width:
> + const: 1
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + maxItems: 2
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
This should be '#/properties/port' instead. '#/$defs/port-base' is if
you have additional port or endpoint properties.
> + unevaluatedProperties: false
And you can then drop this.
With those fixes,
Reviewed-by: Rob Herring <robh@kernel.org>
> + description: Parallel RGB input port
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: HDMI output port
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: Sound input port
> +
> + required:
> + - port@0
> + - port@1
> + - port@2
> +
> + power-domains:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - ports
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/r8a7795-sysc.h>
> +
> + hdmi@fead0000 {
> + compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
> + reg = <0xfead0000 0x10000>;
> + interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
> + clock-names = "iahb", "isfr";
> + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + dw_hdmi0_in: endpoint {
> + remote-endpoint = <&du_out_hdmi0>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + rcar_dw_hdmi0_out: endpoint {
> + remote-endpoint = <&hdmi0_con>;
> + };
> + };
> + port@2 {
> + reg = <2>;
> + rcar_dw_hdmi0_sound_in: endpoint {
> + remote-endpoint = <&hdmi_sound_out>;
> + };
> + };
> + };
> + };
> +
> + hdmi0-out {
> + compatible = "hdmi-connector";
> + label = "HDMI0 OUT";
> + type = "a";
> +
> + port {
> + hdmi0_con: endpoint {
> + remote-endpoint = <&rcar_dw_hdmi0_out>;
> + };
> + };
> + };
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 22663c2cb3a8..e83a867d96d8 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -5903,7 +5903,7 @@ L: dri-devel@lists.freedesktop.org
> L: linux-renesas-soc@vger.kernel.org
> S: Supported
> T: git git://linuxtv.org/pinchartl/media drm/du/next
> -F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
> +F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
> F: Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml
> F: Documentation/devicetree/bindings/display/renesas,du.yaml
> F: drivers/gpu/drm/rcar-du/
> --
> Regards,
>
> Laurent Pinchart
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 3/6] dt-bindings: display: imx: hdmi: Convert binding to YAML
2021-01-05 6:08 ` Laurent Pinchart
@ 2021-01-05 6:08 ` Laurent Pinchart
-1 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:08 UTC (permalink / raw)
To: dri-devel
Cc: linux-renesas-soc, devicetree, Rob Herring, Sandy Huang,
Chen-Yu Tsai, Maxime Ripard, Philipp Zabel, Mark Yao
Convert the i.MX6 HDMI TX text binding to YAML.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
Changes since v1:
- Only specify maxItems for clocks
- Drop reg and interrupts as they're checked in the base schema
- Rebase on top of OF graph schema, dropped redundant properties
- Fix identation for enum entries
- Drop clock-names items, use maxItems only
---
.../bindings/display/imx/fsl,imx6-hdmi.yaml | 130 ++++++++++++++++++
.../devicetree/bindings/display/imx/hdmi.txt | 65 ---------
2 files changed, 130 insertions(+), 65 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
delete mode 100644 Documentation/devicetree/bindings/display/imx/hdmi.txt
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
new file mode 100644
index 000000000000..f9b131bb3339
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 DWC HDMI TX Encoder
+
+maintainers:
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+ with a companion PHY IP.
+
+allOf:
+ - $ref: ../bridge/synopsys,dw-hdmi.yaml#
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx6dl-hdmi
+ - fsl,imx6q-hdmi
+
+ reg-io-width:
+ const: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ maxItems: 2
+
+ ddc-i2c-bus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The HDMI DDC bus can be connected to either a system I2C master or the
+ functionally-reduced I2C master contained in the DWC HDMI. When connected
+ to a system I2C master this property contains a phandle to that I2C
+ master controller.
+
+ gpr:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the iomuxc-gpr region containing the HDMI multiplexer control
+ register.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: |
+ This device has four video ports, corresponding to the four inputs of the
+ HDMI multiplexer. Each port shall have a single endpoint.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: First input of the HDMI multiplexer
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Second input of the HDMI multiplexer
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Third input of the HDMI multiplexer
+
+ port@3:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Fourth input of the HDMI multiplexer
+
+ anyOf:
+ - required:
+ - port@0
+ - required:
+ - port@1
+ - required:
+ - port@2
+ - required:
+ - port@3
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpr
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx6qdl-clock.h>
+
+ hdmi: hdmi@120000 {
+ reg = <0x00120000 0x9000>;
+ interrupts = <0 115 0x04>;
+ gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
+ <&clks IMX6QDL_CLK_HDMI_ISFR>;
+ clock-names = "iahb", "isfr";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_hdmi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_hdmi>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/display/imx/hdmi.txt b/Documentation/devicetree/bindings/display/imx/hdmi.txt
deleted file mode 100644
index 6d021e71c9cf..000000000000
--- a/Documentation/devicetree/bindings/display/imx/hdmi.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-Freescale i.MX6 DWC HDMI TX Encoder
-===================================
-
-The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
-with a companion PHY IP.
-
-These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
-Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
-following device-specific properties.
-
-
-Required properties:
-
-- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
-- reg: See dw_hdmi.txt.
-- interrupts: HDMI interrupt number
-- clocks: See dw_hdmi.txt.
-- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
-- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
- numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
- Each port shall have a single endpoint.
-- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
- multiplexer control register.
-
-Optional properties
-
-- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
- or the functionally-reduced I2C master contained in the DWC HDMI. When
- connected to a system I2C master this property contains a phandle to that
- I2C master controller.
-
-
-Example:
-
- gpr: iomuxc-gpr@20e0000 {
- /* ... */
- };
-
- hdmi: hdmi@120000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6q-hdmi";
- reg = <0x00120000 0x9000>;
- interrupts = <0 115 0x04>;
- gpr = <&gpr>;
- clocks = <&clks 123>, <&clks 124>;
- clock-names = "iahb", "isfr";
- ddc-i2c-bus = <&i2c2>;
-
- port@0 {
- reg = <0>;
-
- hdmi_mux_0: endpoint {
- remote-endpoint = <&ipu1_di0_hdmi>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- hdmi_mux_1: endpoint {
- remote-endpoint = <&ipu1_di1_hdmi>;
- };
- };
- };
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 3/6] dt-bindings: display: imx: hdmi: Convert binding to YAML
@ 2021-01-05 6:08 ` Laurent Pinchart
0 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:08 UTC (permalink / raw)
To: dri-devel
Cc: devicetree, Sandy Huang, linux-renesas-soc, Chen-Yu Tsai,
Rob Herring, Maxime Ripard, Mark Yao
Convert the i.MX6 HDMI TX text binding to YAML.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
Changes since v1:
- Only specify maxItems for clocks
- Drop reg and interrupts as they're checked in the base schema
- Rebase on top of OF graph schema, dropped redundant properties
- Fix identation for enum entries
- Drop clock-names items, use maxItems only
---
.../bindings/display/imx/fsl,imx6-hdmi.yaml | 130 ++++++++++++++++++
.../devicetree/bindings/display/imx/hdmi.txt | 65 ---------
2 files changed, 130 insertions(+), 65 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
delete mode 100644 Documentation/devicetree/bindings/display/imx/hdmi.txt
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
new file mode 100644
index 000000000000..f9b131bb3339
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 DWC HDMI TX Encoder
+
+maintainers:
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+ with a companion PHY IP.
+
+allOf:
+ - $ref: ../bridge/synopsys,dw-hdmi.yaml#
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx6dl-hdmi
+ - fsl,imx6q-hdmi
+
+ reg-io-width:
+ const: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ maxItems: 2
+
+ ddc-i2c-bus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The HDMI DDC bus can be connected to either a system I2C master or the
+ functionally-reduced I2C master contained in the DWC HDMI. When connected
+ to a system I2C master this property contains a phandle to that I2C
+ master controller.
+
+ gpr:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the iomuxc-gpr region containing the HDMI multiplexer control
+ register.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: |
+ This device has four video ports, corresponding to the four inputs of the
+ HDMI multiplexer. Each port shall have a single endpoint.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: First input of the HDMI multiplexer
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Second input of the HDMI multiplexer
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Third input of the HDMI multiplexer
+
+ port@3:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Fourth input of the HDMI multiplexer
+
+ anyOf:
+ - required:
+ - port@0
+ - required:
+ - port@1
+ - required:
+ - port@2
+ - required:
+ - port@3
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpr
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx6qdl-clock.h>
+
+ hdmi: hdmi@120000 {
+ reg = <0x00120000 0x9000>;
+ interrupts = <0 115 0x04>;
+ gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
+ <&clks IMX6QDL_CLK_HDMI_ISFR>;
+ clock-names = "iahb", "isfr";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_hdmi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_hdmi>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/display/imx/hdmi.txt b/Documentation/devicetree/bindings/display/imx/hdmi.txt
deleted file mode 100644
index 6d021e71c9cf..000000000000
--- a/Documentation/devicetree/bindings/display/imx/hdmi.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-Freescale i.MX6 DWC HDMI TX Encoder
-===================================
-
-The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
-with a companion PHY IP.
-
-These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
-Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
-following device-specific properties.
-
-
-Required properties:
-
-- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
-- reg: See dw_hdmi.txt.
-- interrupts: HDMI interrupt number
-- clocks: See dw_hdmi.txt.
-- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
-- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
- numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
- Each port shall have a single endpoint.
-- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
- multiplexer control register.
-
-Optional properties
-
-- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
- or the functionally-reduced I2C master contained in the DWC HDMI. When
- connected to a system I2C master this property contains a phandle to that
- I2C master controller.
-
-
-Example:
-
- gpr: iomuxc-gpr@20e0000 {
- /* ... */
- };
-
- hdmi: hdmi@120000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6q-hdmi";
- reg = <0x00120000 0x9000>;
- interrupts = <0 115 0x04>;
- gpr = <&gpr>;
- clocks = <&clks 123>, <&clks 124>;
- clock-names = "iahb", "isfr";
- ddc-i2c-bus = <&i2c2>;
-
- port@0 {
- reg = <0>;
-
- hdmi_mux_0: endpoint {
- remote-endpoint = <&ipu1_di0_hdmi>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- hdmi_mux_1: endpoint {
- remote-endpoint = <&ipu1_di1_hdmi>;
- };
- };
- };
--
Regards,
Laurent Pinchart
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v3 3/6] dt-bindings: display: imx: hdmi: Convert binding to YAML
2021-01-05 6:08 ` Laurent Pinchart
@ 2021-01-11 22:57 ` Rob Herring
-1 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2021-01-11 22:57 UTC (permalink / raw)
To: Laurent Pinchart
Cc: dri-devel, linux-renesas-soc, devicetree, Sandy Huang,
Chen-Yu Tsai, Maxime Ripard, Philipp Zabel, Mark Yao
On Tue, Jan 05, 2021 at 08:08:15AM +0200, Laurent Pinchart wrote:
> Convert the i.MX6 HDMI TX text binding to YAML.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> Changes since v1:
>
> - Only specify maxItems for clocks
> - Drop reg and interrupts as they're checked in the base schema
> - Rebase on top of OF graph schema, dropped redundant properties
> - Fix identation for enum entries
> - Drop clock-names items, use maxItems only
> ---
> .../bindings/display/imx/fsl,imx6-hdmi.yaml | 130 ++++++++++++++++++
> .../devicetree/bindings/display/imx/hdmi.txt | 65 ---------
> 2 files changed, 130 insertions(+), 65 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
> delete mode 100644 Documentation/devicetree/bindings/display/imx/hdmi.txt
>
> diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
> new file mode 100644
> index 000000000000..f9b131bb3339
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
> @@ -0,0 +1,130 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX6 DWC HDMI TX Encoder
> +
> +maintainers:
> + - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> + with a companion PHY IP.
> +
> +allOf:
> + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx6dl-hdmi
> + - fsl,imx6q-hdmi
> +
> + reg-io-width:
> + const: 1
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + maxItems: 2
> +
> + ddc-i2c-bus:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + The HDMI DDC bus can be connected to either a system I2C master or the
> + functionally-reduced I2C master contained in the DWC HDMI. When connected
> + to a system I2C master this property contains a phandle to that I2C
> + master controller.
This should be deprecated as it should be in the connector node. But
that's a separate issue.
> +
> + gpr:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to the iomuxc-gpr region containing the HDMI multiplexer control
> + register.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> + description: |
> + This device has four video ports, corresponding to the four inputs of the
> + HDMI multiplexer. Each port shall have a single endpoint.
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: First input of the HDMI multiplexer
muxing should have been endpoints rather than ports...
Anyways, same 'port' issues here. With those fixes:
Reviewed-by: Rob Herring <robh@kernel.org>
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: Second input of the HDMI multiplexer
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: Third input of the HDMI multiplexer
> +
> + port@3:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: Fourth input of the HDMI multiplexer
> +
> + anyOf:
> + - required:
> + - port@0
> + - required:
> + - port@1
> + - required:
> + - port@2
> + - required:
> + - port@3
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - gpr
> + - interrupts
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx6qdl-clock.h>
> +
> + hdmi: hdmi@120000 {
> + reg = <0x00120000 0x9000>;
> + interrupts = <0 115 0x04>;
> + gpr = <&gpr>;
> + clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
> + <&clks IMX6QDL_CLK_HDMI_ISFR>;
> + clock-names = "iahb", "isfr";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + hdmi_mux_0: endpoint {
> + remote-endpoint = <&ipu1_di0_hdmi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + hdmi_mux_1: endpoint {
> + remote-endpoint = <&ipu1_di1_hdmi>;
> + };
> + };
> + };
> + };
> +
> +...
> diff --git a/Documentation/devicetree/bindings/display/imx/hdmi.txt b/Documentation/devicetree/bindings/display/imx/hdmi.txt
> deleted file mode 100644
> index 6d021e71c9cf..000000000000
> --- a/Documentation/devicetree/bindings/display/imx/hdmi.txt
> +++ /dev/null
> @@ -1,65 +0,0 @@
> -Freescale i.MX6 DWC HDMI TX Encoder
> -===================================
> -
> -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> -with a companion PHY IP.
> -
> -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> -following device-specific properties.
> -
> -
> -Required properties:
> -
> -- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
> -- reg: See dw_hdmi.txt.
> -- interrupts: HDMI interrupt number
> -- clocks: See dw_hdmi.txt.
> -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> -- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
> - numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
> - Each port shall have a single endpoint.
> -- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
> - multiplexer control register.
> -
> -Optional properties
> -
> -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
> - or the functionally-reduced I2C master contained in the DWC HDMI. When
> - connected to a system I2C master this property contains a phandle to that
> - I2C master controller.
> -
> -
> -Example:
> -
> - gpr: iomuxc-gpr@20e0000 {
> - /* ... */
> - };
> -
> - hdmi: hdmi@120000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,imx6q-hdmi";
> - reg = <0x00120000 0x9000>;
> - interrupts = <0 115 0x04>;
> - gpr = <&gpr>;
> - clocks = <&clks 123>, <&clks 124>;
> - clock-names = "iahb", "isfr";
> - ddc-i2c-bus = <&i2c2>;
> -
> - port@0 {
> - reg = <0>;
> -
> - hdmi_mux_0: endpoint {
> - remote-endpoint = <&ipu1_di0_hdmi>;
> - };
> - };
> -
> - port@1 {
> - reg = <1>;
> -
> - hdmi_mux_1: endpoint {
> - remote-endpoint = <&ipu1_di1_hdmi>;
> - };
> - };
> - };
> --
> Regards,
>
> Laurent Pinchart
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3 3/6] dt-bindings: display: imx: hdmi: Convert binding to YAML
@ 2021-01-11 22:57 ` Rob Herring
0 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2021-01-11 22:57 UTC (permalink / raw)
To: Laurent Pinchart
Cc: devicetree, Sandy Huang, dri-devel, linux-renesas-soc,
Chen-Yu Tsai, Maxime Ripard, Mark Yao
On Tue, Jan 05, 2021 at 08:08:15AM +0200, Laurent Pinchart wrote:
> Convert the i.MX6 HDMI TX text binding to YAML.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> Changes since v1:
>
> - Only specify maxItems for clocks
> - Drop reg and interrupts as they're checked in the base schema
> - Rebase on top of OF graph schema, dropped redundant properties
> - Fix identation for enum entries
> - Drop clock-names items, use maxItems only
> ---
> .../bindings/display/imx/fsl,imx6-hdmi.yaml | 130 ++++++++++++++++++
> .../devicetree/bindings/display/imx/hdmi.txt | 65 ---------
> 2 files changed, 130 insertions(+), 65 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
> delete mode 100644 Documentation/devicetree/bindings/display/imx/hdmi.txt
>
> diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
> new file mode 100644
> index 000000000000..f9b131bb3339
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
> @@ -0,0 +1,130 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX6 DWC HDMI TX Encoder
> +
> +maintainers:
> + - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> + with a companion PHY IP.
> +
> +allOf:
> + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx6dl-hdmi
> + - fsl,imx6q-hdmi
> +
> + reg-io-width:
> + const: 1
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + maxItems: 2
> +
> + ddc-i2c-bus:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + The HDMI DDC bus can be connected to either a system I2C master or the
> + functionally-reduced I2C master contained in the DWC HDMI. When connected
> + to a system I2C master this property contains a phandle to that I2C
> + master controller.
This should be deprecated as it should be in the connector node. But
that's a separate issue.
> +
> + gpr:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to the iomuxc-gpr region containing the HDMI multiplexer control
> + register.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> + description: |
> + This device has four video ports, corresponding to the four inputs of the
> + HDMI multiplexer. Each port shall have a single endpoint.
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: First input of the HDMI multiplexer
muxing should have been endpoints rather than ports...
Anyways, same 'port' issues here. With those fixes:
Reviewed-by: Rob Herring <robh@kernel.org>
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: Second input of the HDMI multiplexer
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: Third input of the HDMI multiplexer
> +
> + port@3:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: Fourth input of the HDMI multiplexer
> +
> + anyOf:
> + - required:
> + - port@0
> + - required:
> + - port@1
> + - required:
> + - port@2
> + - required:
> + - port@3
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - gpr
> + - interrupts
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx6qdl-clock.h>
> +
> + hdmi: hdmi@120000 {
> + reg = <0x00120000 0x9000>;
> + interrupts = <0 115 0x04>;
> + gpr = <&gpr>;
> + clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
> + <&clks IMX6QDL_CLK_HDMI_ISFR>;
> + clock-names = "iahb", "isfr";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + hdmi_mux_0: endpoint {
> + remote-endpoint = <&ipu1_di0_hdmi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + hdmi_mux_1: endpoint {
> + remote-endpoint = <&ipu1_di1_hdmi>;
> + };
> + };
> + };
> + };
> +
> +...
> diff --git a/Documentation/devicetree/bindings/display/imx/hdmi.txt b/Documentation/devicetree/bindings/display/imx/hdmi.txt
> deleted file mode 100644
> index 6d021e71c9cf..000000000000
> --- a/Documentation/devicetree/bindings/display/imx/hdmi.txt
> +++ /dev/null
> @@ -1,65 +0,0 @@
> -Freescale i.MX6 DWC HDMI TX Encoder
> -===================================
> -
> -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> -with a companion PHY IP.
> -
> -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> -following device-specific properties.
> -
> -
> -Required properties:
> -
> -- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
> -- reg: See dw_hdmi.txt.
> -- interrupts: HDMI interrupt number
> -- clocks: See dw_hdmi.txt.
> -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> -- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
> - numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
> - Each port shall have a single endpoint.
> -- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
> - multiplexer control register.
> -
> -Optional properties
> -
> -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
> - or the functionally-reduced I2C master contained in the DWC HDMI. When
> - connected to a system I2C master this property contains a phandle to that
> - I2C master controller.
> -
> -
> -Example:
> -
> - gpr: iomuxc-gpr@20e0000 {
> - /* ... */
> - };
> -
> - hdmi: hdmi@120000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,imx6q-hdmi";
> - reg = <0x00120000 0x9000>;
> - interrupts = <0 115 0x04>;
> - gpr = <&gpr>;
> - clocks = <&clks 123>, <&clks 124>;
> - clock-names = "iahb", "isfr";
> - ddc-i2c-bus = <&i2c2>;
> -
> - port@0 {
> - reg = <0>;
> -
> - hdmi_mux_0: endpoint {
> - remote-endpoint = <&ipu1_di0_hdmi>;
> - };
> - };
> -
> - port@1 {
> - reg = <1>;
> -
> - hdmi_mux_1: endpoint {
> - remote-endpoint = <&ipu1_di1_hdmi>;
> - };
> - };
> - };
> --
> Regards,
>
> Laurent Pinchart
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
2021-01-05 6:08 ` Laurent Pinchart
@ 2021-01-05 6:08 ` Laurent Pinchart
-1 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:08 UTC (permalink / raw)
To: dri-devel
Cc: linux-renesas-soc, devicetree, Rob Herring, Sandy Huang,
Chen-Yu Tsai, Maxime Ripard, Philipp Zabel, Mark Yao
Convert the Rockchip HDMI TX text binding to YAML.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
Changes since v2:
- Use Mark's @gmail.com e-mail address as the @rock-chips.com address
bounces
Changes since v1:
- Drop pinctrl-0 and pinctrl-1
- Use unevaluatedProperties instead of additionalProperties
- Drop reg and interrupts as they're checked in the base schema
- Rebase on top of OF graph schema, dropped redundant properties
- Fix identation for enum entries
- Tidy up clock names
---
.../display/rockchip/dw_hdmi-rockchip.txt | 74 --------
.../display/rockchip/rockchip,dw-hdmi.yaml | 158 ++++++++++++++++++
2 files changed, 158 insertions(+), 74 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
deleted file mode 100644
index 3d32ce137e7f..000000000000
--- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-Rockchip DWC HDMI TX Encoder
-============================
-
-The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
-with a companion PHY IP.
-
-These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
-Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
-following device-specific properties.
-
-
-Required properties:
-
-- compatible: should be one of the following:
- "rockchip,rk3228-dw-hdmi"
- "rockchip,rk3288-dw-hdmi"
- "rockchip,rk3328-dw-hdmi"
- "rockchip,rk3399-dw-hdmi"
-- reg: See dw_hdmi.txt.
-- reg-io-width: See dw_hdmi.txt. Shall be 4.
-- interrupts: HDMI interrupt number
-- clocks: See dw_hdmi.txt.
-- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
-- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
- corresponding to the video input of the controller. The port shall have two
- endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
-- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
-
-Optional properties
-
-- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
- or the functionally-reduced I2C master contained in the DWC HDMI. When
- connected to a system I2C master this property contains a phandle to that
- I2C master controller.
-- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
-- clock-names: May contain "cec" as defined in dw_hdmi.txt.
-- clock-names: May contain "grf", power for grf io.
-- clock-names: May contain "vpll", external clock for some hdmi phy.
-- phys: from general PHY binding: the phandle for the PHY device.
-- phy-names: Should be "hdmi" if phys references an external phy.
-
-Optional pinctrl entry:
-- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
- will switch to the unwedge pinctrl state for 10ms if it ever gets an
- i2c timeout. It's intended that this unwedge pinctrl entry will
- cause the SDA line to be driven low to work around a hardware
- errata.
-
-Example:
-
-hdmi: hdmi@ff980000 {
- compatible = "rockchip,rk3288-dw-hdmi";
- reg = <0xff980000 0x20000>;
- reg-io-width = <4>;
- ddc-i2c-bus = <&i2c5>;
- rockchip,grf = <&grf>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
- clock-names = "iahb", "isfr";
- ports {
- hdmi_in: port {
- #address-cells = <1>;
- #size-cells = <0>;
- hdmi_in_vopb: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vopb_out_hdmi>;
- };
- hdmi_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_hdmi>;
- };
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
new file mode 100644
index 000000000000..d3b2f87f152a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -0,0 +1,158 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip DWC HDMI TX Encoder
+
+maintainers:
+ - Mark Yao <markyao0591@gmail.com>
+
+description: |
+ The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+ with a companion PHY IP.
+
+allOf:
+ - $ref: ../bridge/synopsys,dw-hdmi.yaml#
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3228-dw-hdmi
+ - rockchip,rk3288-dw-hdmi
+ - rockchip,rk3328-dw-hdmi
+ - rockchip,rk3399-dw-hdmi
+
+ reg-io-width:
+ const: 4
+
+ clocks:
+ minItems: 2
+ maxItems: 5
+ items:
+ - {}
+ - {}
+ # The next three clocks are all optional, but shall be specified in this
+ # order when present.
+ - description: The HDMI CEC controller main clock
+ - description: Power for GRF IO
+ - description: External clock for some HDMI PHY
+
+ clock-names:
+ minItems: 2
+ maxItems: 5
+ items:
+ - {}
+ - {}
+ - enum:
+ - cec
+ - grf
+ - vpll
+ - enum:
+ - grf
+ - vpll
+ - const: vpll
+
+ ddc-i2c-bus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The HDMI DDC bus can be connected to either a system I2C master or the
+ functionally-reduced I2C master contained in the DWC HDMI. When connected
+ to a system I2C master this property contains a phandle to that I2C
+ master controller.
+
+ phys:
+ maxItems: 1
+ description: The HDMI PHY
+
+ phy-names:
+ const: hdmi
+
+ pinctrl-names:
+ description:
+ The unwedge pinctrl entry shall drive the DDC SDA line low. This is
+ intended to work around a hardware errata that can cause the DDC I2C
+ bus to be wedged.
+ items:
+ - const: default
+ - const: unwedge
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Input of the DWC HDMI TX
+
+ properties:
+ endpoint@0:
+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
+ unevaluatedProperties: false
+ description: Connection to the VOPB
+
+ endpoint@1:
+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
+ unevaluatedProperties: false
+ description: Connection to the VOPL
+
+ required:
+ - endpoint@0
+ - endpoint@1
+
+ required:
+ - port
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the GRF to mux vopl/vopb.
+
+required:
+ - compatible
+ - reg
+ - reg-io-width
+ - clocks
+ - clock-names
+ - interrupts
+ - ports
+ - rockchip,grf
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3288-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ hdmi: hdmi@ff980000 {
+ compatible = "rockchip,rk3288-dw-hdmi";
+ reg = <0xff980000 0x20000>;
+ reg-io-width = <4>;
+ ddc-i2c-bus = <&i2c5>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
+ clock-names = "iahb", "isfr";
+
+ ports {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_hdmi>;
+ };
+ hdmi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_hdmi>;
+ };
+ };
+ };
+ };
+
+...
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
@ 2021-01-05 6:08 ` Laurent Pinchart
0 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:08 UTC (permalink / raw)
To: dri-devel
Cc: devicetree, Sandy Huang, linux-renesas-soc, Chen-Yu Tsai,
Rob Herring, Maxime Ripard, Mark Yao
Convert the Rockchip HDMI TX text binding to YAML.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
Changes since v2:
- Use Mark's @gmail.com e-mail address as the @rock-chips.com address
bounces
Changes since v1:
- Drop pinctrl-0 and pinctrl-1
- Use unevaluatedProperties instead of additionalProperties
- Drop reg and interrupts as they're checked in the base schema
- Rebase on top of OF graph schema, dropped redundant properties
- Fix identation for enum entries
- Tidy up clock names
---
.../display/rockchip/dw_hdmi-rockchip.txt | 74 --------
.../display/rockchip/rockchip,dw-hdmi.yaml | 158 ++++++++++++++++++
2 files changed, 158 insertions(+), 74 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
deleted file mode 100644
index 3d32ce137e7f..000000000000
--- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-Rockchip DWC HDMI TX Encoder
-============================
-
-The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
-with a companion PHY IP.
-
-These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
-Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
-following device-specific properties.
-
-
-Required properties:
-
-- compatible: should be one of the following:
- "rockchip,rk3228-dw-hdmi"
- "rockchip,rk3288-dw-hdmi"
- "rockchip,rk3328-dw-hdmi"
- "rockchip,rk3399-dw-hdmi"
-- reg: See dw_hdmi.txt.
-- reg-io-width: See dw_hdmi.txt. Shall be 4.
-- interrupts: HDMI interrupt number
-- clocks: See dw_hdmi.txt.
-- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
-- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
- corresponding to the video input of the controller. The port shall have two
- endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
-- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
-
-Optional properties
-
-- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
- or the functionally-reduced I2C master contained in the DWC HDMI. When
- connected to a system I2C master this property contains a phandle to that
- I2C master controller.
-- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
-- clock-names: May contain "cec" as defined in dw_hdmi.txt.
-- clock-names: May contain "grf", power for grf io.
-- clock-names: May contain "vpll", external clock for some hdmi phy.
-- phys: from general PHY binding: the phandle for the PHY device.
-- phy-names: Should be "hdmi" if phys references an external phy.
-
-Optional pinctrl entry:
-- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
- will switch to the unwedge pinctrl state for 10ms if it ever gets an
- i2c timeout. It's intended that this unwedge pinctrl entry will
- cause the SDA line to be driven low to work around a hardware
- errata.
-
-Example:
-
-hdmi: hdmi@ff980000 {
- compatible = "rockchip,rk3288-dw-hdmi";
- reg = <0xff980000 0x20000>;
- reg-io-width = <4>;
- ddc-i2c-bus = <&i2c5>;
- rockchip,grf = <&grf>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
- clock-names = "iahb", "isfr";
- ports {
- hdmi_in: port {
- #address-cells = <1>;
- #size-cells = <0>;
- hdmi_in_vopb: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vopb_out_hdmi>;
- };
- hdmi_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_hdmi>;
- };
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
new file mode 100644
index 000000000000..d3b2f87f152a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -0,0 +1,158 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip DWC HDMI TX Encoder
+
+maintainers:
+ - Mark Yao <markyao0591@gmail.com>
+
+description: |
+ The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+ with a companion PHY IP.
+
+allOf:
+ - $ref: ../bridge/synopsys,dw-hdmi.yaml#
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3228-dw-hdmi
+ - rockchip,rk3288-dw-hdmi
+ - rockchip,rk3328-dw-hdmi
+ - rockchip,rk3399-dw-hdmi
+
+ reg-io-width:
+ const: 4
+
+ clocks:
+ minItems: 2
+ maxItems: 5
+ items:
+ - {}
+ - {}
+ # The next three clocks are all optional, but shall be specified in this
+ # order when present.
+ - description: The HDMI CEC controller main clock
+ - description: Power for GRF IO
+ - description: External clock for some HDMI PHY
+
+ clock-names:
+ minItems: 2
+ maxItems: 5
+ items:
+ - {}
+ - {}
+ - enum:
+ - cec
+ - grf
+ - vpll
+ - enum:
+ - grf
+ - vpll
+ - const: vpll
+
+ ddc-i2c-bus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The HDMI DDC bus can be connected to either a system I2C master or the
+ functionally-reduced I2C master contained in the DWC HDMI. When connected
+ to a system I2C master this property contains a phandle to that I2C
+ master controller.
+
+ phys:
+ maxItems: 1
+ description: The HDMI PHY
+
+ phy-names:
+ const: hdmi
+
+ pinctrl-names:
+ description:
+ The unwedge pinctrl entry shall drive the DDC SDA line low. This is
+ intended to work around a hardware errata that can cause the DDC I2C
+ bus to be wedged.
+ items:
+ - const: default
+ - const: unwedge
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Input of the DWC HDMI TX
+
+ properties:
+ endpoint@0:
+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
+ unevaluatedProperties: false
+ description: Connection to the VOPB
+
+ endpoint@1:
+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
+ unevaluatedProperties: false
+ description: Connection to the VOPL
+
+ required:
+ - endpoint@0
+ - endpoint@1
+
+ required:
+ - port
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the GRF to mux vopl/vopb.
+
+required:
+ - compatible
+ - reg
+ - reg-io-width
+ - clocks
+ - clock-names
+ - interrupts
+ - ports
+ - rockchip,grf
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3288-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ hdmi: hdmi@ff980000 {
+ compatible = "rockchip,rk3288-dw-hdmi";
+ reg = <0xff980000 0x20000>;
+ reg-io-width = <4>;
+ ddc-i2c-bus = <&i2c5>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
+ clock-names = "iahb", "isfr";
+
+ ports {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_hdmi>;
+ };
+ hdmi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_hdmi>;
+ };
+ };
+ };
+ };
+
+...
--
Regards,
Laurent Pinchart
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
2021-01-05 6:08 ` Laurent Pinchart
@ 2021-01-06 15:17 ` Laurent Pinchart
-1 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-06 15:17 UTC (permalink / raw)
To: Rob Herring
Cc: dri-devel, devicetree, Sandy Huang, linux-renesas-soc,
Chen-Yu Tsai, Maxime Ripard, Mark Yao
Hi Rob,
Given that the maintainers property is mandatory in the schema, what's
the procedure when no maintainer steps up for a converter YAML binding ?
On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> Convert the Rockchip HDMI TX text binding to YAML.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> Changes since v2:
>
> - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> bounces
>
> Changes since v1:
>
> - Drop pinctrl-0 and pinctrl-1
> - Use unevaluatedProperties instead of additionalProperties
> - Drop reg and interrupts as they're checked in the base schema
> - Rebase on top of OF graph schema, dropped redundant properties
> - Fix identation for enum entries
> - Tidy up clock names
> ---
> .../display/rockchip/dw_hdmi-rockchip.txt | 74 --------
> .../display/rockchip/rockchip,dw-hdmi.yaml | 158 ++++++++++++++++++
> 2 files changed, 158 insertions(+), 74 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> deleted file mode 100644
> index 3d32ce137e7f..000000000000
> --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> +++ /dev/null
> @@ -1,74 +0,0 @@
> -Rockchip DWC HDMI TX Encoder
> -============================
> -
> -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> -with a companion PHY IP.
> -
> -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> -following device-specific properties.
> -
> -
> -Required properties:
> -
> -- compatible: should be one of the following:
> - "rockchip,rk3228-dw-hdmi"
> - "rockchip,rk3288-dw-hdmi"
> - "rockchip,rk3328-dw-hdmi"
> - "rockchip,rk3399-dw-hdmi"
> -- reg: See dw_hdmi.txt.
> -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> -- interrupts: HDMI interrupt number
> -- clocks: See dw_hdmi.txt.
> -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
> - corresponding to the video input of the controller. The port shall have two
> - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
> -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> -
> -Optional properties
> -
> -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
> - or the functionally-reduced I2C master contained in the DWC HDMI. When
> - connected to a system I2C master this property contains a phandle to that
> - I2C master controller.
> -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> -- clock-names: May contain "grf", power for grf io.
> -- clock-names: May contain "vpll", external clock for some hdmi phy.
> -- phys: from general PHY binding: the phandle for the PHY device.
> -- phy-names: Should be "hdmi" if phys references an external phy.
> -
> -Optional pinctrl entry:
> -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> - i2c timeout. It's intended that this unwedge pinctrl entry will
> - cause the SDA line to be driven low to work around a hardware
> - errata.
> -
> -Example:
> -
> -hdmi: hdmi@ff980000 {
> - compatible = "rockchip,rk3288-dw-hdmi";
> - reg = <0xff980000 0x20000>;
> - reg-io-width = <4>;
> - ddc-i2c-bus = <&i2c5>;
> - rockchip,grf = <&grf>;
> - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> - clock-names = "iahb", "isfr";
> - ports {
> - hdmi_in: port {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - hdmi_in_vopb: endpoint@0 {
> - reg = <0>;
> - remote-endpoint = <&vopb_out_hdmi>;
> - };
> - hdmi_in_vopl: endpoint@1 {
> - reg = <1>;
> - remote-endpoint = <&vopl_out_hdmi>;
> - };
> - };
> - };
> -};
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> new file mode 100644
> index 000000000000..d3b2f87f152a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> @@ -0,0 +1,158 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip DWC HDMI TX Encoder
> +
> +maintainers:
> + - Mark Yao <markyao0591@gmail.com>
> +
> +description: |
> + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> + with a companion PHY IP.
> +
> +allOf:
> + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rk3228-dw-hdmi
> + - rockchip,rk3288-dw-hdmi
> + - rockchip,rk3328-dw-hdmi
> + - rockchip,rk3399-dw-hdmi
> +
> + reg-io-width:
> + const: 4
> +
> + clocks:
> + minItems: 2
> + maxItems: 5
> + items:
> + - {}
> + - {}
> + # The next three clocks are all optional, but shall be specified in this
> + # order when present.
> + - description: The HDMI CEC controller main clock
> + - description: Power for GRF IO
> + - description: External clock for some HDMI PHY
> +
> + clock-names:
> + minItems: 2
> + maxItems: 5
> + items:
> + - {}
> + - {}
> + - enum:
> + - cec
> + - grf
> + - vpll
> + - enum:
> + - grf
> + - vpll
> + - const: vpll
> +
> + ddc-i2c-bus:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + The HDMI DDC bus can be connected to either a system I2C master or the
> + functionally-reduced I2C master contained in the DWC HDMI. When connected
> + to a system I2C master this property contains a phandle to that I2C
> + master controller.
> +
> + phys:
> + maxItems: 1
> + description: The HDMI PHY
> +
> + phy-names:
> + const: hdmi
> +
> + pinctrl-names:
> + description:
> + The unwedge pinctrl entry shall drive the DDC SDA line low. This is
> + intended to work around a hardware errata that can cause the DDC I2C
> + bus to be wedged.
> + items:
> + - const: default
> + - const: unwedge
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: Input of the DWC HDMI TX
> +
> + properties:
> + endpoint@0:
> + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> + unevaluatedProperties: false
> + description: Connection to the VOPB
> +
> + endpoint@1:
> + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> + unevaluatedProperties: false
> + description: Connection to the VOPL
> +
> + required:
> + - endpoint@0
> + - endpoint@1
> +
> + required:
> + - port
> +
> + rockchip,grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to the GRF to mux vopl/vopb.
> +
> +required:
> + - compatible
> + - reg
> + - reg-io-width
> + - clocks
> + - clock-names
> + - interrupts
> + - ports
> + - rockchip,grf
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/rk3288-cru.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + hdmi: hdmi@ff980000 {
> + compatible = "rockchip,rk3288-dw-hdmi";
> + reg = <0xff980000 0x20000>;
> + reg-io-width = <4>;
> + ddc-i2c-bus = <&i2c5>;
> + rockchip,grf = <&grf>;
> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> + clock-names = "iahb", "isfr";
> +
> + ports {
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + hdmi_in_vopb: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&vopb_out_hdmi>;
> + };
> + hdmi_in_vopl: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&vopl_out_hdmi>;
> + };
> + };
> + };
> + };
> +
> +...
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
@ 2021-01-06 15:17 ` Laurent Pinchart
0 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-06 15:17 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, Sandy Huang, dri-devel, linux-renesas-soc,
Chen-Yu Tsai, Maxime Ripard, Mark Yao
Hi Rob,
Given that the maintainers property is mandatory in the schema, what's
the procedure when no maintainer steps up for a converter YAML binding ?
On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> Convert the Rockchip HDMI TX text binding to YAML.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> Changes since v2:
>
> - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> bounces
>
> Changes since v1:
>
> - Drop pinctrl-0 and pinctrl-1
> - Use unevaluatedProperties instead of additionalProperties
> - Drop reg and interrupts as they're checked in the base schema
> - Rebase on top of OF graph schema, dropped redundant properties
> - Fix identation for enum entries
> - Tidy up clock names
> ---
> .../display/rockchip/dw_hdmi-rockchip.txt | 74 --------
> .../display/rockchip/rockchip,dw-hdmi.yaml | 158 ++++++++++++++++++
> 2 files changed, 158 insertions(+), 74 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> deleted file mode 100644
> index 3d32ce137e7f..000000000000
> --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> +++ /dev/null
> @@ -1,74 +0,0 @@
> -Rockchip DWC HDMI TX Encoder
> -============================
> -
> -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> -with a companion PHY IP.
> -
> -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> -following device-specific properties.
> -
> -
> -Required properties:
> -
> -- compatible: should be one of the following:
> - "rockchip,rk3228-dw-hdmi"
> - "rockchip,rk3288-dw-hdmi"
> - "rockchip,rk3328-dw-hdmi"
> - "rockchip,rk3399-dw-hdmi"
> -- reg: See dw_hdmi.txt.
> -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> -- interrupts: HDMI interrupt number
> -- clocks: See dw_hdmi.txt.
> -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
> - corresponding to the video input of the controller. The port shall have two
> - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
> -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> -
> -Optional properties
> -
> -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
> - or the functionally-reduced I2C master contained in the DWC HDMI. When
> - connected to a system I2C master this property contains a phandle to that
> - I2C master controller.
> -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> -- clock-names: May contain "grf", power for grf io.
> -- clock-names: May contain "vpll", external clock for some hdmi phy.
> -- phys: from general PHY binding: the phandle for the PHY device.
> -- phy-names: Should be "hdmi" if phys references an external phy.
> -
> -Optional pinctrl entry:
> -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> - i2c timeout. It's intended that this unwedge pinctrl entry will
> - cause the SDA line to be driven low to work around a hardware
> - errata.
> -
> -Example:
> -
> -hdmi: hdmi@ff980000 {
> - compatible = "rockchip,rk3288-dw-hdmi";
> - reg = <0xff980000 0x20000>;
> - reg-io-width = <4>;
> - ddc-i2c-bus = <&i2c5>;
> - rockchip,grf = <&grf>;
> - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> - clock-names = "iahb", "isfr";
> - ports {
> - hdmi_in: port {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - hdmi_in_vopb: endpoint@0 {
> - reg = <0>;
> - remote-endpoint = <&vopb_out_hdmi>;
> - };
> - hdmi_in_vopl: endpoint@1 {
> - reg = <1>;
> - remote-endpoint = <&vopl_out_hdmi>;
> - };
> - };
> - };
> -};
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> new file mode 100644
> index 000000000000..d3b2f87f152a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> @@ -0,0 +1,158 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip DWC HDMI TX Encoder
> +
> +maintainers:
> + - Mark Yao <markyao0591@gmail.com>
> +
> +description: |
> + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> + with a companion PHY IP.
> +
> +allOf:
> + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rk3228-dw-hdmi
> + - rockchip,rk3288-dw-hdmi
> + - rockchip,rk3328-dw-hdmi
> + - rockchip,rk3399-dw-hdmi
> +
> + reg-io-width:
> + const: 4
> +
> + clocks:
> + minItems: 2
> + maxItems: 5
> + items:
> + - {}
> + - {}
> + # The next three clocks are all optional, but shall be specified in this
> + # order when present.
> + - description: The HDMI CEC controller main clock
> + - description: Power for GRF IO
> + - description: External clock for some HDMI PHY
> +
> + clock-names:
> + minItems: 2
> + maxItems: 5
> + items:
> + - {}
> + - {}
> + - enum:
> + - cec
> + - grf
> + - vpll
> + - enum:
> + - grf
> + - vpll
> + - const: vpll
> +
> + ddc-i2c-bus:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + The HDMI DDC bus can be connected to either a system I2C master or the
> + functionally-reduced I2C master contained in the DWC HDMI. When connected
> + to a system I2C master this property contains a phandle to that I2C
> + master controller.
> +
> + phys:
> + maxItems: 1
> + description: The HDMI PHY
> +
> + phy-names:
> + const: hdmi
> +
> + pinctrl-names:
> + description:
> + The unwedge pinctrl entry shall drive the DDC SDA line low. This is
> + intended to work around a hardware errata that can cause the DDC I2C
> + bus to be wedged.
> + items:
> + - const: default
> + - const: unwedge
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: Input of the DWC HDMI TX
> +
> + properties:
> + endpoint@0:
> + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> + unevaluatedProperties: false
> + description: Connection to the VOPB
> +
> + endpoint@1:
> + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> + unevaluatedProperties: false
> + description: Connection to the VOPL
> +
> + required:
> + - endpoint@0
> + - endpoint@1
> +
> + required:
> + - port
> +
> + rockchip,grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to the GRF to mux vopl/vopb.
> +
> +required:
> + - compatible
> + - reg
> + - reg-io-width
> + - clocks
> + - clock-names
> + - interrupts
> + - ports
> + - rockchip,grf
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/rk3288-cru.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + hdmi: hdmi@ff980000 {
> + compatible = "rockchip,rk3288-dw-hdmi";
> + reg = <0xff980000 0x20000>;
> + reg-io-width = <4>;
> + ddc-i2c-bus = <&i2c5>;
> + rockchip,grf = <&grf>;
> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> + clock-names = "iahb", "isfr";
> +
> + ports {
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + hdmi_in_vopb: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&vopb_out_hdmi>;
> + };
> + hdmi_in_vopl: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&vopl_out_hdmi>;
> + };
> + };
> + };
> + };
> +
> +...
--
Regards,
Laurent Pinchart
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
2021-01-06 15:17 ` Laurent Pinchart
@ 2021-01-11 23:01 ` Rob Herring
-1 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2021-01-11 23:01 UTC (permalink / raw)
To: Laurent Pinchart
Cc: dri-devel, devicetree, Sandy Huang, linux-renesas-soc,
Chen-Yu Tsai, Maxime Ripard, Mark Yao
On Wed, Jan 06, 2021 at 05:17:55PM +0200, Laurent Pinchart wrote:
> Hi Rob,
>
> Given that the maintainers property is mandatory in the schema, what's
> the procedure when no maintainer steps up for a converter YAML binding ?
Delete it if no one cares...
Typically we just put a subsystem or platform maintainer.
>
> On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> > Convert the Rockchip HDMI TX text binding to YAML.
> >
> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > ---
> > Changes since v2:
> >
> > - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> > bounces
> >
> > Changes since v1:
> >
> > - Drop pinctrl-0 and pinctrl-1
> > - Use unevaluatedProperties instead of additionalProperties
> > - Drop reg and interrupts as they're checked in the base schema
> > - Rebase on top of OF graph schema, dropped redundant properties
> > - Fix identation for enum entries
> > - Tidy up clock names
> > ---
> > .../display/rockchip/dw_hdmi-rockchip.txt | 74 --------
> > .../display/rockchip/rockchip,dw-hdmi.yaml | 158 ++++++++++++++++++
> > 2 files changed, 158 insertions(+), 74 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > deleted file mode 100644
> > index 3d32ce137e7f..000000000000
> > --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > +++ /dev/null
> > @@ -1,74 +0,0 @@
> > -Rockchip DWC HDMI TX Encoder
> > -============================
> > -
> > -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > -with a companion PHY IP.
> > -
> > -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> > -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> > -following device-specific properties.
> > -
> > -
> > -Required properties:
> > -
> > -- compatible: should be one of the following:
> > - "rockchip,rk3228-dw-hdmi"
> > - "rockchip,rk3288-dw-hdmi"
> > - "rockchip,rk3328-dw-hdmi"
> > - "rockchip,rk3399-dw-hdmi"
> > -- reg: See dw_hdmi.txt.
> > -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> > -- interrupts: HDMI interrupt number
> > -- clocks: See dw_hdmi.txt.
> > -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> > -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
> > - corresponding to the video input of the controller. The port shall have two
> > - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
> > -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> > -
> > -Optional properties
> > -
> > -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
> > - or the functionally-reduced I2C master contained in the DWC HDMI. When
> > - connected to a system I2C master this property contains a phandle to that
> > - I2C master controller.
> > -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> > -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> > -- clock-names: May contain "grf", power for grf io.
> > -- clock-names: May contain "vpll", external clock for some hdmi phy.
> > -- phys: from general PHY binding: the phandle for the PHY device.
> > -- phy-names: Should be "hdmi" if phys references an external phy.
> > -
> > -Optional pinctrl entry:
> > -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> > - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> > - i2c timeout. It's intended that this unwedge pinctrl entry will
> > - cause the SDA line to be driven low to work around a hardware
> > - errata.
> > -
> > -Example:
> > -
> > -hdmi: hdmi@ff980000 {
> > - compatible = "rockchip,rk3288-dw-hdmi";
> > - reg = <0xff980000 0x20000>;
> > - reg-io-width = <4>;
> > - ddc-i2c-bus = <&i2c5>;
> > - rockchip,grf = <&grf>;
> > - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> > - clock-names = "iahb", "isfr";
> > - ports {
> > - hdmi_in: port {
> > - #address-cells = <1>;
> > - #size-cells = <0>;
> > - hdmi_in_vopb: endpoint@0 {
> > - reg = <0>;
> > - remote-endpoint = <&vopb_out_hdmi>;
> > - };
> > - hdmi_in_vopl: endpoint@1 {
> > - reg = <1>;
> > - remote-endpoint = <&vopl_out_hdmi>;
> > - };
> > - };
> > - };
> > -};
> > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > new file mode 100644
> > index 000000000000..d3b2f87f152a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > @@ -0,0 +1,158 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Rockchip DWC HDMI TX Encoder
> > +
> > +maintainers:
> > + - Mark Yao <markyao0591@gmail.com>
> > +
> > +description: |
> > + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > + with a companion PHY IP.
> > +
> > +allOf:
> > + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - rockchip,rk3228-dw-hdmi
> > + - rockchip,rk3288-dw-hdmi
> > + - rockchip,rk3328-dw-hdmi
> > + - rockchip,rk3399-dw-hdmi
> > +
> > + reg-io-width:
> > + const: 4
> > +
> > + clocks:
> > + minItems: 2
> > + maxItems: 5
> > + items:
> > + - {}
> > + - {}
> > + # The next three clocks are all optional, but shall be specified in this
> > + # order when present.
> > + - description: The HDMI CEC controller main clock
> > + - description: Power for GRF IO
> > + - description: External clock for some HDMI PHY
> > +
> > + clock-names:
> > + minItems: 2
> > + maxItems: 5
> > + items:
> > + - {}
> > + - {}
> > + - enum:
> > + - cec
> > + - grf
> > + - vpll
> > + - enum:
> > + - grf
> > + - vpll
> > + - const: vpll
> > +
> > + ddc-i2c-bus:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + The HDMI DDC bus can be connected to either a system I2C master or the
> > + functionally-reduced I2C master contained in the DWC HDMI. When connected
> > + to a system I2C master this property contains a phandle to that I2C
> > + master controller.
> > +
> > + phys:
> > + maxItems: 1
> > + description: The HDMI PHY
> > +
> > + phy-names:
> > + const: hdmi
> > +
> > + pinctrl-names:
> > + description:
> > + The unwedge pinctrl entry shall drive the DDC SDA line low. This is
> > + intended to work around a hardware errata that can cause the DDC I2C
> > + bus to be wedged.
> > + items:
> > + - const: default
> > + - const: unwedge
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
> > + properties:
> > + port:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
> > + unevaluatedProperties: false
> > + description: Input of the DWC HDMI TX
> > +
> > + properties:
> > + endpoint@0:
> > + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> > + unevaluatedProperties: false
> > + description: Connection to the VOPB
> > +
> > + endpoint@1:
> > + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> > + unevaluatedProperties: false
> > + description: Connection to the VOPL
> > +
> > + required:
> > + - endpoint@0
> > + - endpoint@1
> > +
> > + required:
> > + - port
> > +
> > + rockchip,grf:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + phandle to the GRF to mux vopl/vopb.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-io-width
> > + - clocks
> > + - clock-names
> > + - interrupts
> > + - ports
> > + - rockchip,grf
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/rk3288-cru.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > + hdmi: hdmi@ff980000 {
> > + compatible = "rockchip,rk3288-dw-hdmi";
> > + reg = <0xff980000 0x20000>;
> > + reg-io-width = <4>;
> > + ddc-i2c-bus = <&i2c5>;
> > + rockchip,grf = <&grf>;
> > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> > + clock-names = "iahb", "isfr";
> > +
> > + ports {
> > + port {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + hdmi_in_vopb: endpoint@0 {
> > + reg = <0>;
> > + remote-endpoint = <&vopb_out_hdmi>;
> > + };
> > + hdmi_in_vopl: endpoint@1 {
> > + reg = <1>;
> > + remote-endpoint = <&vopl_out_hdmi>;
> > + };
> > + };
> > + };
> > + };
> > +
> > +...
>
> --
> Regards,
>
> Laurent Pinchart
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
@ 2021-01-11 23:01 ` Rob Herring
0 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2021-01-11 23:01 UTC (permalink / raw)
To: Laurent Pinchart
Cc: devicetree, Sandy Huang, dri-devel, linux-renesas-soc,
Chen-Yu Tsai, Maxime Ripard, Mark Yao
On Wed, Jan 06, 2021 at 05:17:55PM +0200, Laurent Pinchart wrote:
> Hi Rob,
>
> Given that the maintainers property is mandatory in the schema, what's
> the procedure when no maintainer steps up for a converter YAML binding ?
Delete it if no one cares...
Typically we just put a subsystem or platform maintainer.
>
> On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> > Convert the Rockchip HDMI TX text binding to YAML.
> >
> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > ---
> > Changes since v2:
> >
> > - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> > bounces
> >
> > Changes since v1:
> >
> > - Drop pinctrl-0 and pinctrl-1
> > - Use unevaluatedProperties instead of additionalProperties
> > - Drop reg and interrupts as they're checked in the base schema
> > - Rebase on top of OF graph schema, dropped redundant properties
> > - Fix identation for enum entries
> > - Tidy up clock names
> > ---
> > .../display/rockchip/dw_hdmi-rockchip.txt | 74 --------
> > .../display/rockchip/rockchip,dw-hdmi.yaml | 158 ++++++++++++++++++
> > 2 files changed, 158 insertions(+), 74 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > deleted file mode 100644
> > index 3d32ce137e7f..000000000000
> > --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > +++ /dev/null
> > @@ -1,74 +0,0 @@
> > -Rockchip DWC HDMI TX Encoder
> > -============================
> > -
> > -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > -with a companion PHY IP.
> > -
> > -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> > -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> > -following device-specific properties.
> > -
> > -
> > -Required properties:
> > -
> > -- compatible: should be one of the following:
> > - "rockchip,rk3228-dw-hdmi"
> > - "rockchip,rk3288-dw-hdmi"
> > - "rockchip,rk3328-dw-hdmi"
> > - "rockchip,rk3399-dw-hdmi"
> > -- reg: See dw_hdmi.txt.
> > -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> > -- interrupts: HDMI interrupt number
> > -- clocks: See dw_hdmi.txt.
> > -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> > -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
> > - corresponding to the video input of the controller. The port shall have two
> > - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
> > -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> > -
> > -Optional properties
> > -
> > -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
> > - or the functionally-reduced I2C master contained in the DWC HDMI. When
> > - connected to a system I2C master this property contains a phandle to that
> > - I2C master controller.
> > -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> > -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> > -- clock-names: May contain "grf", power for grf io.
> > -- clock-names: May contain "vpll", external clock for some hdmi phy.
> > -- phys: from general PHY binding: the phandle for the PHY device.
> > -- phy-names: Should be "hdmi" if phys references an external phy.
> > -
> > -Optional pinctrl entry:
> > -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> > - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> > - i2c timeout. It's intended that this unwedge pinctrl entry will
> > - cause the SDA line to be driven low to work around a hardware
> > - errata.
> > -
> > -Example:
> > -
> > -hdmi: hdmi@ff980000 {
> > - compatible = "rockchip,rk3288-dw-hdmi";
> > - reg = <0xff980000 0x20000>;
> > - reg-io-width = <4>;
> > - ddc-i2c-bus = <&i2c5>;
> > - rockchip,grf = <&grf>;
> > - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> > - clock-names = "iahb", "isfr";
> > - ports {
> > - hdmi_in: port {
> > - #address-cells = <1>;
> > - #size-cells = <0>;
> > - hdmi_in_vopb: endpoint@0 {
> > - reg = <0>;
> > - remote-endpoint = <&vopb_out_hdmi>;
> > - };
> > - hdmi_in_vopl: endpoint@1 {
> > - reg = <1>;
> > - remote-endpoint = <&vopl_out_hdmi>;
> > - };
> > - };
> > - };
> > -};
> > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > new file mode 100644
> > index 000000000000..d3b2f87f152a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > @@ -0,0 +1,158 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Rockchip DWC HDMI TX Encoder
> > +
> > +maintainers:
> > + - Mark Yao <markyao0591@gmail.com>
> > +
> > +description: |
> > + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > + with a companion PHY IP.
> > +
> > +allOf:
> > + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - rockchip,rk3228-dw-hdmi
> > + - rockchip,rk3288-dw-hdmi
> > + - rockchip,rk3328-dw-hdmi
> > + - rockchip,rk3399-dw-hdmi
> > +
> > + reg-io-width:
> > + const: 4
> > +
> > + clocks:
> > + minItems: 2
> > + maxItems: 5
> > + items:
> > + - {}
> > + - {}
> > + # The next three clocks are all optional, but shall be specified in this
> > + # order when present.
> > + - description: The HDMI CEC controller main clock
> > + - description: Power for GRF IO
> > + - description: External clock for some HDMI PHY
> > +
> > + clock-names:
> > + minItems: 2
> > + maxItems: 5
> > + items:
> > + - {}
> > + - {}
> > + - enum:
> > + - cec
> > + - grf
> > + - vpll
> > + - enum:
> > + - grf
> > + - vpll
> > + - const: vpll
> > +
> > + ddc-i2c-bus:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + The HDMI DDC bus can be connected to either a system I2C master or the
> > + functionally-reduced I2C master contained in the DWC HDMI. When connected
> > + to a system I2C master this property contains a phandle to that I2C
> > + master controller.
> > +
> > + phys:
> > + maxItems: 1
> > + description: The HDMI PHY
> > +
> > + phy-names:
> > + const: hdmi
> > +
> > + pinctrl-names:
> > + description:
> > + The unwedge pinctrl entry shall drive the DDC SDA line low. This is
> > + intended to work around a hardware errata that can cause the DDC I2C
> > + bus to be wedged.
> > + items:
> > + - const: default
> > + - const: unwedge
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
> > + properties:
> > + port:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
> > + unevaluatedProperties: false
> > + description: Input of the DWC HDMI TX
> > +
> > + properties:
> > + endpoint@0:
> > + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> > + unevaluatedProperties: false
> > + description: Connection to the VOPB
> > +
> > + endpoint@1:
> > + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> > + unevaluatedProperties: false
> > + description: Connection to the VOPL
> > +
> > + required:
> > + - endpoint@0
> > + - endpoint@1
> > +
> > + required:
> > + - port
> > +
> > + rockchip,grf:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + phandle to the GRF to mux vopl/vopb.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-io-width
> > + - clocks
> > + - clock-names
> > + - interrupts
> > + - ports
> > + - rockchip,grf
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/rk3288-cru.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > + hdmi: hdmi@ff980000 {
> > + compatible = "rockchip,rk3288-dw-hdmi";
> > + reg = <0xff980000 0x20000>;
> > + reg-io-width = <4>;
> > + ddc-i2c-bus = <&i2c5>;
> > + rockchip,grf = <&grf>;
> > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> > + clock-names = "iahb", "isfr";
> > +
> > + ports {
> > + port {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + hdmi_in_vopb: endpoint@0 {
> > + reg = <0>;
> > + remote-endpoint = <&vopb_out_hdmi>;
> > + };
> > + hdmi_in_vopl: endpoint@1 {
> > + reg = <1>;
> > + remote-endpoint = <&vopl_out_hdmi>;
> > + };
> > + };
> > + };
> > + };
> > +
> > +...
>
> --
> Regards,
>
> Laurent Pinchart
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^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
2021-01-11 23:01 ` Rob Herring
@ 2021-01-11 23:09 ` Laurent Pinchart
-1 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-11 23:09 UTC (permalink / raw)
To: Rob Herring
Cc: dri-devel, devicetree, Sandy Huang, linux-renesas-soc,
Chen-Yu Tsai, Maxime Ripard, Mark Yao
Hi Rob,
On Mon, Jan 11, 2021 at 05:01:36PM -0600, Rob Herring wrote:
> On Wed, Jan 06, 2021 at 05:17:55PM +0200, Laurent Pinchart wrote:
> > Hi Rob,
> >
> > Given that the maintainers property is mandatory in the schema, what's
> > the procedure when no maintainer steps up for a converter YAML binding ?
>
> Delete it if no one cares...
>
> Typically we just put a subsystem or platform maintainer.
Do you mean dropping dw_hdmi-rockchip.txt completely, even if it's in
use by a driver ?
> > On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> > > Convert the Rockchip HDMI TX text binding to YAML.
> > >
> > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > ---
> > > Changes since v2:
> > >
> > > - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> > > bounces
> > >
> > > Changes since v1:
> > >
> > > - Drop pinctrl-0 and pinctrl-1
> > > - Use unevaluatedProperties instead of additionalProperties
> > > - Drop reg and interrupts as they're checked in the base schema
> > > - Rebase on top of OF graph schema, dropped redundant properties
> > > - Fix identation for enum entries
> > > - Tidy up clock names
> > > ---
> > > .../display/rockchip/dw_hdmi-rockchip.txt | 74 --------
> > > .../display/rockchip/rockchip,dw-hdmi.yaml | 158 ++++++++++++++++++
> > > 2 files changed, 158 insertions(+), 74 deletions(-)
> > > delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > > deleted file mode 100644
> > > index 3d32ce137e7f..000000000000
> > > --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > > +++ /dev/null
> > > @@ -1,74 +0,0 @@
> > > -Rockchip DWC HDMI TX Encoder
> > > -============================
> > > -
> > > -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > > -with a companion PHY IP.
> > > -
> > > -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> > > -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> > > -following device-specific properties.
> > > -
> > > -
> > > -Required properties:
> > > -
> > > -- compatible: should be one of the following:
> > > - "rockchip,rk3228-dw-hdmi"
> > > - "rockchip,rk3288-dw-hdmi"
> > > - "rockchip,rk3328-dw-hdmi"
> > > - "rockchip,rk3399-dw-hdmi"
> > > -- reg: See dw_hdmi.txt.
> > > -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> > > -- interrupts: HDMI interrupt number
> > > -- clocks: See dw_hdmi.txt.
> > > -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> > > -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
> > > - corresponding to the video input of the controller. The port shall have two
> > > - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
> > > -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> > > -
> > > -Optional properties
> > > -
> > > -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
> > > - or the functionally-reduced I2C master contained in the DWC HDMI. When
> > > - connected to a system I2C master this property contains a phandle to that
> > > - I2C master controller.
> > > -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> > > -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> > > -- clock-names: May contain "grf", power for grf io.
> > > -- clock-names: May contain "vpll", external clock for some hdmi phy.
> > > -- phys: from general PHY binding: the phandle for the PHY device.
> > > -- phy-names: Should be "hdmi" if phys references an external phy.
> > > -
> > > -Optional pinctrl entry:
> > > -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> > > - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> > > - i2c timeout. It's intended that this unwedge pinctrl entry will
> > > - cause the SDA line to be driven low to work around a hardware
> > > - errata.
> > > -
> > > -Example:
> > > -
> > > -hdmi: hdmi@ff980000 {
> > > - compatible = "rockchip,rk3288-dw-hdmi";
> > > - reg = <0xff980000 0x20000>;
> > > - reg-io-width = <4>;
> > > - ddc-i2c-bus = <&i2c5>;
> > > - rockchip,grf = <&grf>;
> > > - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > > - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> > > - clock-names = "iahb", "isfr";
> > > - ports {
> > > - hdmi_in: port {
> > > - #address-cells = <1>;
> > > - #size-cells = <0>;
> > > - hdmi_in_vopb: endpoint@0 {
> > > - reg = <0>;
> > > - remote-endpoint = <&vopb_out_hdmi>;
> > > - };
> > > - hdmi_in_vopl: endpoint@1 {
> > > - reg = <1>;
> > > - remote-endpoint = <&vopl_out_hdmi>;
> > > - };
> > > - };
> > > - };
> > > -};
> > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > > new file mode 100644
> > > index 000000000000..d3b2f87f152a
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > > @@ -0,0 +1,158 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Rockchip DWC HDMI TX Encoder
> > > +
> > > +maintainers:
> > > + - Mark Yao <markyao0591@gmail.com>
> > > +
> > > +description: |
> > > + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > > + with a companion PHY IP.
> > > +
> > > +allOf:
> > > + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> > > +
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - rockchip,rk3228-dw-hdmi
> > > + - rockchip,rk3288-dw-hdmi
> > > + - rockchip,rk3328-dw-hdmi
> > > + - rockchip,rk3399-dw-hdmi
> > > +
> > > + reg-io-width:
> > > + const: 4
> > > +
> > > + clocks:
> > > + minItems: 2
> > > + maxItems: 5
> > > + items:
> > > + - {}
> > > + - {}
> > > + # The next three clocks are all optional, but shall be specified in this
> > > + # order when present.
> > > + - description: The HDMI CEC controller main clock
> > > + - description: Power for GRF IO
> > > + - description: External clock for some HDMI PHY
> > > +
> > > + clock-names:
> > > + minItems: 2
> > > + maxItems: 5
> > > + items:
> > > + - {}
> > > + - {}
> > > + - enum:
> > > + - cec
> > > + - grf
> > > + - vpll
> > > + - enum:
> > > + - grf
> > > + - vpll
> > > + - const: vpll
> > > +
> > > + ddc-i2c-bus:
> > > + $ref: /schemas/types.yaml#/definitions/phandle
> > > + description:
> > > + The HDMI DDC bus can be connected to either a system I2C master or the
> > > + functionally-reduced I2C master contained in the DWC HDMI. When connected
> > > + to a system I2C master this property contains a phandle to that I2C
> > > + master controller.
> > > +
> > > + phys:
> > > + maxItems: 1
> > > + description: The HDMI PHY
> > > +
> > > + phy-names:
> > > + const: hdmi
> > > +
> > > + pinctrl-names:
> > > + description:
> > > + The unwedge pinctrl entry shall drive the DDC SDA line low. This is
> > > + intended to work around a hardware errata that can cause the DDC I2C
> > > + bus to be wedged.
> > > + items:
> > > + - const: default
> > > + - const: unwedge
> > > +
> > > + ports:
> > > + $ref: /schemas/graph.yaml#/properties/ports
> > > +
> > > + properties:
> > > + port:
> > > + $ref: /schemas/graph.yaml#/$defs/port-base
> > > + unevaluatedProperties: false
> > > + description: Input of the DWC HDMI TX
> > > +
> > > + properties:
> > > + endpoint@0:
> > > + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> > > + unevaluatedProperties: false
> > > + description: Connection to the VOPB
> > > +
> > > + endpoint@1:
> > > + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> > > + unevaluatedProperties: false
> > > + description: Connection to the VOPL
> > > +
> > > + required:
> > > + - endpoint@0
> > > + - endpoint@1
> > > +
> > > + required:
> > > + - port
> > > +
> > > + rockchip,grf:
> > > + $ref: /schemas/types.yaml#/definitions/phandle
> > > + description:
> > > + phandle to the GRF to mux vopl/vopb.
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - reg-io-width
> > > + - clocks
> > > + - clock-names
> > > + - interrupts
> > > + - ports
> > > + - rockchip,grf
> > > +
> > > +unevaluatedProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/clock/rk3288-cru.h>
> > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > + #include <dt-bindings/interrupt-controller/irq.h>
> > > +
> > > + hdmi: hdmi@ff980000 {
> > > + compatible = "rockchip,rk3288-dw-hdmi";
> > > + reg = <0xff980000 0x20000>;
> > > + reg-io-width = <4>;
> > > + ddc-i2c-bus = <&i2c5>;
> > > + rockchip,grf = <&grf>;
> > > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> > > + clock-names = "iahb", "isfr";
> > > +
> > > + ports {
> > > + port {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + hdmi_in_vopb: endpoint@0 {
> > > + reg = <0>;
> > > + remote-endpoint = <&vopb_out_hdmi>;
> > > + };
> > > + hdmi_in_vopl: endpoint@1 {
> > > + reg = <1>;
> > > + remote-endpoint = <&vopl_out_hdmi>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > +...
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
@ 2021-01-11 23:09 ` Laurent Pinchart
0 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-11 23:09 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, Sandy Huang, dri-devel, linux-renesas-soc,
Chen-Yu Tsai, Maxime Ripard, Mark Yao
Hi Rob,
On Mon, Jan 11, 2021 at 05:01:36PM -0600, Rob Herring wrote:
> On Wed, Jan 06, 2021 at 05:17:55PM +0200, Laurent Pinchart wrote:
> > Hi Rob,
> >
> > Given that the maintainers property is mandatory in the schema, what's
> > the procedure when no maintainer steps up for a converter YAML binding ?
>
> Delete it if no one cares...
>
> Typically we just put a subsystem or platform maintainer.
Do you mean dropping dw_hdmi-rockchip.txt completely, even if it's in
use by a driver ?
> > On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> > > Convert the Rockchip HDMI TX text binding to YAML.
> > >
> > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > ---
> > > Changes since v2:
> > >
> > > - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> > > bounces
> > >
> > > Changes since v1:
> > >
> > > - Drop pinctrl-0 and pinctrl-1
> > > - Use unevaluatedProperties instead of additionalProperties
> > > - Drop reg and interrupts as they're checked in the base schema
> > > - Rebase on top of OF graph schema, dropped redundant properties
> > > - Fix identation for enum entries
> > > - Tidy up clock names
> > > ---
> > > .../display/rockchip/dw_hdmi-rockchip.txt | 74 --------
> > > .../display/rockchip/rockchip,dw-hdmi.yaml | 158 ++++++++++++++++++
> > > 2 files changed, 158 insertions(+), 74 deletions(-)
> > > delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > > deleted file mode 100644
> > > index 3d32ce137e7f..000000000000
> > > --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > > +++ /dev/null
> > > @@ -1,74 +0,0 @@
> > > -Rockchip DWC HDMI TX Encoder
> > > -============================
> > > -
> > > -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > > -with a companion PHY IP.
> > > -
> > > -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> > > -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> > > -following device-specific properties.
> > > -
> > > -
> > > -Required properties:
> > > -
> > > -- compatible: should be one of the following:
> > > - "rockchip,rk3228-dw-hdmi"
> > > - "rockchip,rk3288-dw-hdmi"
> > > - "rockchip,rk3328-dw-hdmi"
> > > - "rockchip,rk3399-dw-hdmi"
> > > -- reg: See dw_hdmi.txt.
> > > -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> > > -- interrupts: HDMI interrupt number
> > > -- clocks: See dw_hdmi.txt.
> > > -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> > > -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
> > > - corresponding to the video input of the controller. The port shall have two
> > > - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
> > > -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> > > -
> > > -Optional properties
> > > -
> > > -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
> > > - or the functionally-reduced I2C master contained in the DWC HDMI. When
> > > - connected to a system I2C master this property contains a phandle to that
> > > - I2C master controller.
> > > -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> > > -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> > > -- clock-names: May contain "grf", power for grf io.
> > > -- clock-names: May contain "vpll", external clock for some hdmi phy.
> > > -- phys: from general PHY binding: the phandle for the PHY device.
> > > -- phy-names: Should be "hdmi" if phys references an external phy.
> > > -
> > > -Optional pinctrl entry:
> > > -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> > > - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> > > - i2c timeout. It's intended that this unwedge pinctrl entry will
> > > - cause the SDA line to be driven low to work around a hardware
> > > - errata.
> > > -
> > > -Example:
> > > -
> > > -hdmi: hdmi@ff980000 {
> > > - compatible = "rockchip,rk3288-dw-hdmi";
> > > - reg = <0xff980000 0x20000>;
> > > - reg-io-width = <4>;
> > > - ddc-i2c-bus = <&i2c5>;
> > > - rockchip,grf = <&grf>;
> > > - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > > - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> > > - clock-names = "iahb", "isfr";
> > > - ports {
> > > - hdmi_in: port {
> > > - #address-cells = <1>;
> > > - #size-cells = <0>;
> > > - hdmi_in_vopb: endpoint@0 {
> > > - reg = <0>;
> > > - remote-endpoint = <&vopb_out_hdmi>;
> > > - };
> > > - hdmi_in_vopl: endpoint@1 {
> > > - reg = <1>;
> > > - remote-endpoint = <&vopl_out_hdmi>;
> > > - };
> > > - };
> > > - };
> > > -};
> > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > > new file mode 100644
> > > index 000000000000..d3b2f87f152a
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > > @@ -0,0 +1,158 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Rockchip DWC HDMI TX Encoder
> > > +
> > > +maintainers:
> > > + - Mark Yao <markyao0591@gmail.com>
> > > +
> > > +description: |
> > > + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > > + with a companion PHY IP.
> > > +
> > > +allOf:
> > > + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> > > +
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - rockchip,rk3228-dw-hdmi
> > > + - rockchip,rk3288-dw-hdmi
> > > + - rockchip,rk3328-dw-hdmi
> > > + - rockchip,rk3399-dw-hdmi
> > > +
> > > + reg-io-width:
> > > + const: 4
> > > +
> > > + clocks:
> > > + minItems: 2
> > > + maxItems: 5
> > > + items:
> > > + - {}
> > > + - {}
> > > + # The next three clocks are all optional, but shall be specified in this
> > > + # order when present.
> > > + - description: The HDMI CEC controller main clock
> > > + - description: Power for GRF IO
> > > + - description: External clock for some HDMI PHY
> > > +
> > > + clock-names:
> > > + minItems: 2
> > > + maxItems: 5
> > > + items:
> > > + - {}
> > > + - {}
> > > + - enum:
> > > + - cec
> > > + - grf
> > > + - vpll
> > > + - enum:
> > > + - grf
> > > + - vpll
> > > + - const: vpll
> > > +
> > > + ddc-i2c-bus:
> > > + $ref: /schemas/types.yaml#/definitions/phandle
> > > + description:
> > > + The HDMI DDC bus can be connected to either a system I2C master or the
> > > + functionally-reduced I2C master contained in the DWC HDMI. When connected
> > > + to a system I2C master this property contains a phandle to that I2C
> > > + master controller.
> > > +
> > > + phys:
> > > + maxItems: 1
> > > + description: The HDMI PHY
> > > +
> > > + phy-names:
> > > + const: hdmi
> > > +
> > > + pinctrl-names:
> > > + description:
> > > + The unwedge pinctrl entry shall drive the DDC SDA line low. This is
> > > + intended to work around a hardware errata that can cause the DDC I2C
> > > + bus to be wedged.
> > > + items:
> > > + - const: default
> > > + - const: unwedge
> > > +
> > > + ports:
> > > + $ref: /schemas/graph.yaml#/properties/ports
> > > +
> > > + properties:
> > > + port:
> > > + $ref: /schemas/graph.yaml#/$defs/port-base
> > > + unevaluatedProperties: false
> > > + description: Input of the DWC HDMI TX
> > > +
> > > + properties:
> > > + endpoint@0:
> > > + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> > > + unevaluatedProperties: false
> > > + description: Connection to the VOPB
> > > +
> > > + endpoint@1:
> > > + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> > > + unevaluatedProperties: false
> > > + description: Connection to the VOPL
> > > +
> > > + required:
> > > + - endpoint@0
> > > + - endpoint@1
> > > +
> > > + required:
> > > + - port
> > > +
> > > + rockchip,grf:
> > > + $ref: /schemas/types.yaml#/definitions/phandle
> > > + description:
> > > + phandle to the GRF to mux vopl/vopb.
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - reg-io-width
> > > + - clocks
> > > + - clock-names
> > > + - interrupts
> > > + - ports
> > > + - rockchip,grf
> > > +
> > > +unevaluatedProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/clock/rk3288-cru.h>
> > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > + #include <dt-bindings/interrupt-controller/irq.h>
> > > +
> > > + hdmi: hdmi@ff980000 {
> > > + compatible = "rockchip,rk3288-dw-hdmi";
> > > + reg = <0xff980000 0x20000>;
> > > + reg-io-width = <4>;
> > > + ddc-i2c-bus = <&i2c5>;
> > > + rockchip,grf = <&grf>;
> > > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> > > + clock-names = "iahb", "isfr";
> > > +
> > > + ports {
> > > + port {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + hdmi_in_vopb: endpoint@0 {
> > > + reg = <0>;
> > > + remote-endpoint = <&vopb_out_hdmi>;
> > > + };
> > > + hdmi_in_vopl: endpoint@1 {
> > > + reg = <1>;
> > > + remote-endpoint = <&vopl_out_hdmi>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > +...
--
Regards,
Laurent Pinchart
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
2021-01-05 6:08 ` Laurent Pinchart
@ 2021-01-11 23:12 ` Rob Herring
-1 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2021-01-11 23:12 UTC (permalink / raw)
To: Laurent Pinchart
Cc: dri-devel, linux-renesas-soc, devicetree, Sandy Huang,
Chen-Yu Tsai, Maxime Ripard, Philipp Zabel, Mark Yao
On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> Convert the Rockchip HDMI TX text binding to YAML.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> Changes since v2:
>
> - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> bounces
>
> Changes since v1:
>
> - Drop pinctrl-0 and pinctrl-1
> - Use unevaluatedProperties instead of additionalProperties
> - Drop reg and interrupts as they're checked in the base schema
> - Rebase on top of OF graph schema, dropped redundant properties
> - Fix identation for enum entries
> - Tidy up clock names
> ---
> .../display/rockchip/dw_hdmi-rockchip.txt | 74 --------
> .../display/rockchip/rockchip,dw-hdmi.yaml | 158 ++++++++++++++++++
> 2 files changed, 158 insertions(+), 74 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> deleted file mode 100644
> index 3d32ce137e7f..000000000000
> --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> +++ /dev/null
> @@ -1,74 +0,0 @@
> -Rockchip DWC HDMI TX Encoder
> -============================
> -
> -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> -with a companion PHY IP.
> -
> -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> -following device-specific properties.
> -
> -
> -Required properties:
> -
> -- compatible: should be one of the following:
> - "rockchip,rk3228-dw-hdmi"
> - "rockchip,rk3288-dw-hdmi"
> - "rockchip,rk3328-dw-hdmi"
> - "rockchip,rk3399-dw-hdmi"
> -- reg: See dw_hdmi.txt.
> -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> -- interrupts: HDMI interrupt number
> -- clocks: See dw_hdmi.txt.
> -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
> - corresponding to the video input of the controller. The port shall have two
> - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
> -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> -
> -Optional properties
> -
> -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
> - or the functionally-reduced I2C master contained in the DWC HDMI. When
> - connected to a system I2C master this property contains a phandle to that
> - I2C master controller.
> -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> -- clock-names: May contain "grf", power for grf io.
> -- clock-names: May contain "vpll", external clock for some hdmi phy.
> -- phys: from general PHY binding: the phandle for the PHY device.
> -- phy-names: Should be "hdmi" if phys references an external phy.
> -
> -Optional pinctrl entry:
> -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> - i2c timeout. It's intended that this unwedge pinctrl entry will
> - cause the SDA line to be driven low to work around a hardware
> - errata.
> -
> -Example:
> -
> -hdmi: hdmi@ff980000 {
> - compatible = "rockchip,rk3288-dw-hdmi";
> - reg = <0xff980000 0x20000>;
> - reg-io-width = <4>;
> - ddc-i2c-bus = <&i2c5>;
> - rockchip,grf = <&grf>;
> - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> - clock-names = "iahb", "isfr";
> - ports {
> - hdmi_in: port {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - hdmi_in_vopb: endpoint@0 {
> - reg = <0>;
> - remote-endpoint = <&vopb_out_hdmi>;
> - };
> - hdmi_in_vopl: endpoint@1 {
> - reg = <1>;
> - remote-endpoint = <&vopl_out_hdmi>;
> - };
> - };
> - };
> -};
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> new file mode 100644
> index 000000000000..d3b2f87f152a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> @@ -0,0 +1,158 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip DWC HDMI TX Encoder
> +
> +maintainers:
> + - Mark Yao <markyao0591@gmail.com>
> +
> +description: |
> + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> + with a companion PHY IP.
> +
> +allOf:
> + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rk3228-dw-hdmi
> + - rockchip,rk3288-dw-hdmi
> + - rockchip,rk3328-dw-hdmi
> + - rockchip,rk3399-dw-hdmi
> +
> + reg-io-width:
> + const: 4
> +
> + clocks:
> + minItems: 2
> + maxItems: 5
> + items:
> + - {}
> + - {}
> + # The next three clocks are all optional, but shall be specified in this
> + # order when present.
> + - description: The HDMI CEC controller main clock
> + - description: Power for GRF IO
> + - description: External clock for some HDMI PHY
> +
> + clock-names:
> + minItems: 2
> + maxItems: 5
> + items:
> + - {}
> + - {}
> + - enum:
> + - cec
> + - grf
> + - vpll
> + - enum:
> + - grf
> + - vpll
> + - const: vpll
> +
> + ddc-i2c-bus:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + The HDMI DDC bus can be connected to either a system I2C master or the
> + functionally-reduced I2C master contained in the DWC HDMI. When connected
> + to a system I2C master this property contains a phandle to that I2C
> + master controller.
> +
> + phys:
> + maxItems: 1
> + description: The HDMI PHY
> +
> + phy-names:
> + const: hdmi
> +
> + pinctrl-names:
> + description:
> + The unwedge pinctrl entry shall drive the DDC SDA line low. This is
> + intended to work around a hardware errata that can cause the DDC I2C
> + bus to be wedged.
> + items:
> + - const: default
> + - const: unwedge
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port:
> + $ref: /schemas/graph.yaml#/$defs/port-base
In this case, this is correct since you have endpoint definitions.
> + unevaluatedProperties: false
> + description: Input of the DWC HDMI TX
> +
> + properties:
> + endpoint@0:
> + $ref: /schemas/graph.yaml#/$defs/endpoint-base
#/properties/endpoint
> + unevaluatedProperties: false
> + description: Connection to the VOPB
Oh good, we've done muxing both ways...
> +
> + endpoint@1:
> + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> + unevaluatedProperties: false
> + description: Connection to the VOPL
> +
> + required:
> + - endpoint@0
> + - endpoint@1
> +
> + required:
> + - port
> +
> + rockchip,grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to the GRF to mux vopl/vopb.
> +
> +required:
> + - compatible
> + - reg
> + - reg-io-width
> + - clocks
> + - clock-names
> + - interrupts
> + - ports
> + - rockchip,grf
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/rk3288-cru.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + hdmi: hdmi@ff980000 {
> + compatible = "rockchip,rk3288-dw-hdmi";
> + reg = <0xff980000 0x20000>;
> + reg-io-width = <4>;
> + ddc-i2c-bus = <&i2c5>;
> + rockchip,grf = <&grf>;
> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> + clock-names = "iahb", "isfr";
> +
> + ports {
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + hdmi_in_vopb: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&vopb_out_hdmi>;
> + };
> + hdmi_in_vopl: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&vopl_out_hdmi>;
> + };
> + };
> + };
> + };
> +
> +...
> --
> Regards,
>
> Laurent Pinchart
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
@ 2021-01-11 23:12 ` Rob Herring
0 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2021-01-11 23:12 UTC (permalink / raw)
To: Laurent Pinchart
Cc: devicetree, Sandy Huang, dri-devel, linux-renesas-soc,
Chen-Yu Tsai, Maxime Ripard, Mark Yao
On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> Convert the Rockchip HDMI TX text binding to YAML.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> Changes since v2:
>
> - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> bounces
>
> Changes since v1:
>
> - Drop pinctrl-0 and pinctrl-1
> - Use unevaluatedProperties instead of additionalProperties
> - Drop reg and interrupts as they're checked in the base schema
> - Rebase on top of OF graph schema, dropped redundant properties
> - Fix identation for enum entries
> - Tidy up clock names
> ---
> .../display/rockchip/dw_hdmi-rockchip.txt | 74 --------
> .../display/rockchip/rockchip,dw-hdmi.yaml | 158 ++++++++++++++++++
> 2 files changed, 158 insertions(+), 74 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> deleted file mode 100644
> index 3d32ce137e7f..000000000000
> --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> +++ /dev/null
> @@ -1,74 +0,0 @@
> -Rockchip DWC HDMI TX Encoder
> -============================
> -
> -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> -with a companion PHY IP.
> -
> -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> -following device-specific properties.
> -
> -
> -Required properties:
> -
> -- compatible: should be one of the following:
> - "rockchip,rk3228-dw-hdmi"
> - "rockchip,rk3288-dw-hdmi"
> - "rockchip,rk3328-dw-hdmi"
> - "rockchip,rk3399-dw-hdmi"
> -- reg: See dw_hdmi.txt.
> -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> -- interrupts: HDMI interrupt number
> -- clocks: See dw_hdmi.txt.
> -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
> - corresponding to the video input of the controller. The port shall have two
> - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
> -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> -
> -Optional properties
> -
> -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
> - or the functionally-reduced I2C master contained in the DWC HDMI. When
> - connected to a system I2C master this property contains a phandle to that
> - I2C master controller.
> -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> -- clock-names: May contain "grf", power for grf io.
> -- clock-names: May contain "vpll", external clock for some hdmi phy.
> -- phys: from general PHY binding: the phandle for the PHY device.
> -- phy-names: Should be "hdmi" if phys references an external phy.
> -
> -Optional pinctrl entry:
> -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> - i2c timeout. It's intended that this unwedge pinctrl entry will
> - cause the SDA line to be driven low to work around a hardware
> - errata.
> -
> -Example:
> -
> -hdmi: hdmi@ff980000 {
> - compatible = "rockchip,rk3288-dw-hdmi";
> - reg = <0xff980000 0x20000>;
> - reg-io-width = <4>;
> - ddc-i2c-bus = <&i2c5>;
> - rockchip,grf = <&grf>;
> - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> - clock-names = "iahb", "isfr";
> - ports {
> - hdmi_in: port {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - hdmi_in_vopb: endpoint@0 {
> - reg = <0>;
> - remote-endpoint = <&vopb_out_hdmi>;
> - };
> - hdmi_in_vopl: endpoint@1 {
> - reg = <1>;
> - remote-endpoint = <&vopl_out_hdmi>;
> - };
> - };
> - };
> -};
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> new file mode 100644
> index 000000000000..d3b2f87f152a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> @@ -0,0 +1,158 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip DWC HDMI TX Encoder
> +
> +maintainers:
> + - Mark Yao <markyao0591@gmail.com>
> +
> +description: |
> + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> + with a companion PHY IP.
> +
> +allOf:
> + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rk3228-dw-hdmi
> + - rockchip,rk3288-dw-hdmi
> + - rockchip,rk3328-dw-hdmi
> + - rockchip,rk3399-dw-hdmi
> +
> + reg-io-width:
> + const: 4
> +
> + clocks:
> + minItems: 2
> + maxItems: 5
> + items:
> + - {}
> + - {}
> + # The next three clocks are all optional, but shall be specified in this
> + # order when present.
> + - description: The HDMI CEC controller main clock
> + - description: Power for GRF IO
> + - description: External clock for some HDMI PHY
> +
> + clock-names:
> + minItems: 2
> + maxItems: 5
> + items:
> + - {}
> + - {}
> + - enum:
> + - cec
> + - grf
> + - vpll
> + - enum:
> + - grf
> + - vpll
> + - const: vpll
> +
> + ddc-i2c-bus:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + The HDMI DDC bus can be connected to either a system I2C master or the
> + functionally-reduced I2C master contained in the DWC HDMI. When connected
> + to a system I2C master this property contains a phandle to that I2C
> + master controller.
> +
> + phys:
> + maxItems: 1
> + description: The HDMI PHY
> +
> + phy-names:
> + const: hdmi
> +
> + pinctrl-names:
> + description:
> + The unwedge pinctrl entry shall drive the DDC SDA line low. This is
> + intended to work around a hardware errata that can cause the DDC I2C
> + bus to be wedged.
> + items:
> + - const: default
> + - const: unwedge
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port:
> + $ref: /schemas/graph.yaml#/$defs/port-base
In this case, this is correct since you have endpoint definitions.
> + unevaluatedProperties: false
> + description: Input of the DWC HDMI TX
> +
> + properties:
> + endpoint@0:
> + $ref: /schemas/graph.yaml#/$defs/endpoint-base
#/properties/endpoint
> + unevaluatedProperties: false
> + description: Connection to the VOPB
Oh good, we've done muxing both ways...
> +
> + endpoint@1:
> + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> + unevaluatedProperties: false
> + description: Connection to the VOPL
> +
> + required:
> + - endpoint@0
> + - endpoint@1
> +
> + required:
> + - port
> +
> + rockchip,grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to the GRF to mux vopl/vopb.
> +
> +required:
> + - compatible
> + - reg
> + - reg-io-width
> + - clocks
> + - clock-names
> + - interrupts
> + - ports
> + - rockchip,grf
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/rk3288-cru.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + hdmi: hdmi@ff980000 {
> + compatible = "rockchip,rk3288-dw-hdmi";
> + reg = <0xff980000 0x20000>;
> + reg-io-width = <4>;
> + ddc-i2c-bus = <&i2c5>;
> + rockchip,grf = <&grf>;
> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> + clock-names = "iahb", "isfr";
> +
> + ports {
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + hdmi_in_vopb: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&vopb_out_hdmi>;
> + };
> + hdmi_in_vopl: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&vopl_out_hdmi>;
> + };
> + };
> + };
> + };
> +
> +...
> --
> Regards,
>
> Laurent Pinchart
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
2021-01-11 23:12 ` Rob Herring
@ 2021-01-12 4:54 ` Laurent Pinchart
-1 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-12 4:54 UTC (permalink / raw)
To: Rob Herring
Cc: Laurent Pinchart, dri-devel, linux-renesas-soc, devicetree,
Sandy Huang, Chen-Yu Tsai, Maxime Ripard, Philipp Zabel,
Mark Yao
Hi Rob,
On Mon, Jan 11, 2021 at 05:12:58PM -0600, Rob Herring wrote:
> On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> > Convert the Rockchip HDMI TX text binding to YAML.
> >
> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > ---
> > Changes since v2:
> >
> > - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> > bounces
> >
> > Changes since v1:
> >
> > - Drop pinctrl-0 and pinctrl-1
> > - Use unevaluatedProperties instead of additionalProperties
> > - Drop reg and interrupts as they're checked in the base schema
> > - Rebase on top of OF graph schema, dropped redundant properties
> > - Fix identation for enum entries
> > - Tidy up clock names
> > ---
> > .../display/rockchip/dw_hdmi-rockchip.txt | 74 --------
> > .../display/rockchip/rockchip,dw-hdmi.yaml | 158 ++++++++++++++++++
> > 2 files changed, 158 insertions(+), 74 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > deleted file mode 100644
> > index 3d32ce137e7f..000000000000
> > --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > +++ /dev/null
> > @@ -1,74 +0,0 @@
> > -Rockchip DWC HDMI TX Encoder
> > -============================
> > -
> > -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > -with a companion PHY IP.
> > -
> > -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> > -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> > -following device-specific properties.
> > -
> > -
> > -Required properties:
> > -
> > -- compatible: should be one of the following:
> > - "rockchip,rk3228-dw-hdmi"
> > - "rockchip,rk3288-dw-hdmi"
> > - "rockchip,rk3328-dw-hdmi"
> > - "rockchip,rk3399-dw-hdmi"
> > -- reg: See dw_hdmi.txt.
> > -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> > -- interrupts: HDMI interrupt number
> > -- clocks: See dw_hdmi.txt.
> > -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> > -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
> > - corresponding to the video input of the controller. The port shall have two
> > - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
> > -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> > -
> > -Optional properties
> > -
> > -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
> > - or the functionally-reduced I2C master contained in the DWC HDMI. When
> > - connected to a system I2C master this property contains a phandle to that
> > - I2C master controller.
> > -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> > -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> > -- clock-names: May contain "grf", power for grf io.
> > -- clock-names: May contain "vpll", external clock for some hdmi phy.
> > -- phys: from general PHY binding: the phandle for the PHY device.
> > -- phy-names: Should be "hdmi" if phys references an external phy.
> > -
> > -Optional pinctrl entry:
> > -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> > - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> > - i2c timeout. It's intended that this unwedge pinctrl entry will
> > - cause the SDA line to be driven low to work around a hardware
> > - errata.
> > -
> > -Example:
> > -
> > -hdmi: hdmi@ff980000 {
> > - compatible = "rockchip,rk3288-dw-hdmi";
> > - reg = <0xff980000 0x20000>;
> > - reg-io-width = <4>;
> > - ddc-i2c-bus = <&i2c5>;
> > - rockchip,grf = <&grf>;
> > - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> > - clock-names = "iahb", "isfr";
> > - ports {
> > - hdmi_in: port {
> > - #address-cells = <1>;
> > - #size-cells = <0>;
> > - hdmi_in_vopb: endpoint@0 {
> > - reg = <0>;
> > - remote-endpoint = <&vopb_out_hdmi>;
> > - };
> > - hdmi_in_vopl: endpoint@1 {
> > - reg = <1>;
> > - remote-endpoint = <&vopl_out_hdmi>;
> > - };
> > - };
> > - };
> > -};
> > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > new file mode 100644
> > index 000000000000..d3b2f87f152a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > @@ -0,0 +1,158 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Rockchip DWC HDMI TX Encoder
> > +
> > +maintainers:
> > + - Mark Yao <markyao0591@gmail.com>
> > +
> > +description: |
> > + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > + with a companion PHY IP.
> > +
> > +allOf:
> > + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - rockchip,rk3228-dw-hdmi
> > + - rockchip,rk3288-dw-hdmi
> > + - rockchip,rk3328-dw-hdmi
> > + - rockchip,rk3399-dw-hdmi
> > +
> > + reg-io-width:
> > + const: 4
> > +
> > + clocks:
> > + minItems: 2
> > + maxItems: 5
> > + items:
> > + - {}
> > + - {}
> > + # The next three clocks are all optional, but shall be specified in this
> > + # order when present.
> > + - description: The HDMI CEC controller main clock
> > + - description: Power for GRF IO
> > + - description: External clock for some HDMI PHY
> > +
> > + clock-names:
> > + minItems: 2
> > + maxItems: 5
> > + items:
> > + - {}
> > + - {}
> > + - enum:
> > + - cec
> > + - grf
> > + - vpll
> > + - enum:
> > + - grf
> > + - vpll
> > + - const: vpll
> > +
> > + ddc-i2c-bus:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + The HDMI DDC bus can be connected to either a system I2C master or the
> > + functionally-reduced I2C master contained in the DWC HDMI. When connected
> > + to a system I2C master this property contains a phandle to that I2C
> > + master controller.
> > +
> > + phys:
> > + maxItems: 1
> > + description: The HDMI PHY
> > +
> > + phy-names:
> > + const: hdmi
> > +
> > + pinctrl-names:
> > + description:
> > + The unwedge pinctrl entry shall drive the DDC SDA line low. This is
> > + intended to work around a hardware errata that can cause the DDC I2C
> > + bus to be wedged.
> > + items:
> > + - const: default
> > + - const: unwedge
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
> > + properties:
> > + port:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
>
> In this case, this is correct since you have endpoint definitions.
>
> > + unevaluatedProperties: false
> > + description: Input of the DWC HDMI TX
> > +
> > + properties:
> > + endpoint@0:
> > + $ref: /schemas/graph.yaml#/$defs/endpoint-base
>
> #/properties/endpoint
>
> > + unevaluatedProperties: false
> > + description: Connection to the VOPB
>
> Oh good, we've done muxing both ways...
Isn't it nice ? :-S
Are endpoints the right way though ? When the mux is internal to an IP
core, there are multiple physical input ports.
> > +
> > + endpoint@1:
> > + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> > + unevaluatedProperties: false
> > + description: Connection to the VOPL
> > +
> > + required:
> > + - endpoint@0
> > + - endpoint@1
> > +
> > + required:
> > + - port
> > +
> > + rockchip,grf:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + phandle to the GRF to mux vopl/vopb.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-io-width
> > + - clocks
> > + - clock-names
> > + - interrupts
> > + - ports
> > + - rockchip,grf
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/rk3288-cru.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > + hdmi: hdmi@ff980000 {
> > + compatible = "rockchip,rk3288-dw-hdmi";
> > + reg = <0xff980000 0x20000>;
> > + reg-io-width = <4>;
> > + ddc-i2c-bus = <&i2c5>;
> > + rockchip,grf = <&grf>;
> > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> > + clock-names = "iahb", "isfr";
> > +
> > + ports {
> > + port {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + hdmi_in_vopb: endpoint@0 {
> > + reg = <0>;
> > + remote-endpoint = <&vopb_out_hdmi>;
> > + };
> > + hdmi_in_vopl: endpoint@1 {
> > + reg = <1>;
> > + remote-endpoint = <&vopl_out_hdmi>;
> > + };
> > + };
> > + };
> > + };
> > +
> > +...
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
@ 2021-01-12 4:54 ` Laurent Pinchart
0 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-12 4:54 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, Laurent Pinchart, Sandy Huang, dri-devel,
linux-renesas-soc, Chen-Yu Tsai, Maxime Ripard, Mark Yao
Hi Rob,
On Mon, Jan 11, 2021 at 05:12:58PM -0600, Rob Herring wrote:
> On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> > Convert the Rockchip HDMI TX text binding to YAML.
> >
> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > ---
> > Changes since v2:
> >
> > - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> > bounces
> >
> > Changes since v1:
> >
> > - Drop pinctrl-0 and pinctrl-1
> > - Use unevaluatedProperties instead of additionalProperties
> > - Drop reg and interrupts as they're checked in the base schema
> > - Rebase on top of OF graph schema, dropped redundant properties
> > - Fix identation for enum entries
> > - Tidy up clock names
> > ---
> > .../display/rockchip/dw_hdmi-rockchip.txt | 74 --------
> > .../display/rockchip/rockchip,dw-hdmi.yaml | 158 ++++++++++++++++++
> > 2 files changed, 158 insertions(+), 74 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > deleted file mode 100644
> > index 3d32ce137e7f..000000000000
> > --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > +++ /dev/null
> > @@ -1,74 +0,0 @@
> > -Rockchip DWC HDMI TX Encoder
> > -============================
> > -
> > -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > -with a companion PHY IP.
> > -
> > -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> > -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> > -following device-specific properties.
> > -
> > -
> > -Required properties:
> > -
> > -- compatible: should be one of the following:
> > - "rockchip,rk3228-dw-hdmi"
> > - "rockchip,rk3288-dw-hdmi"
> > - "rockchip,rk3328-dw-hdmi"
> > - "rockchip,rk3399-dw-hdmi"
> > -- reg: See dw_hdmi.txt.
> > -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> > -- interrupts: HDMI interrupt number
> > -- clocks: See dw_hdmi.txt.
> > -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> > -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
> > - corresponding to the video input of the controller. The port shall have two
> > - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
> > -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> > -
> > -Optional properties
> > -
> > -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
> > - or the functionally-reduced I2C master contained in the DWC HDMI. When
> > - connected to a system I2C master this property contains a phandle to that
> > - I2C master controller.
> > -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> > -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> > -- clock-names: May contain "grf", power for grf io.
> > -- clock-names: May contain "vpll", external clock for some hdmi phy.
> > -- phys: from general PHY binding: the phandle for the PHY device.
> > -- phy-names: Should be "hdmi" if phys references an external phy.
> > -
> > -Optional pinctrl entry:
> > -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> > - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> > - i2c timeout. It's intended that this unwedge pinctrl entry will
> > - cause the SDA line to be driven low to work around a hardware
> > - errata.
> > -
> > -Example:
> > -
> > -hdmi: hdmi@ff980000 {
> > - compatible = "rockchip,rk3288-dw-hdmi";
> > - reg = <0xff980000 0x20000>;
> > - reg-io-width = <4>;
> > - ddc-i2c-bus = <&i2c5>;
> > - rockchip,grf = <&grf>;
> > - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> > - clock-names = "iahb", "isfr";
> > - ports {
> > - hdmi_in: port {
> > - #address-cells = <1>;
> > - #size-cells = <0>;
> > - hdmi_in_vopb: endpoint@0 {
> > - reg = <0>;
> > - remote-endpoint = <&vopb_out_hdmi>;
> > - };
> > - hdmi_in_vopl: endpoint@1 {
> > - reg = <1>;
> > - remote-endpoint = <&vopl_out_hdmi>;
> > - };
> > - };
> > - };
> > -};
> > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > new file mode 100644
> > index 000000000000..d3b2f87f152a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > @@ -0,0 +1,158 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Rockchip DWC HDMI TX Encoder
> > +
> > +maintainers:
> > + - Mark Yao <markyao0591@gmail.com>
> > +
> > +description: |
> > + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > + with a companion PHY IP.
> > +
> > +allOf:
> > + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - rockchip,rk3228-dw-hdmi
> > + - rockchip,rk3288-dw-hdmi
> > + - rockchip,rk3328-dw-hdmi
> > + - rockchip,rk3399-dw-hdmi
> > +
> > + reg-io-width:
> > + const: 4
> > +
> > + clocks:
> > + minItems: 2
> > + maxItems: 5
> > + items:
> > + - {}
> > + - {}
> > + # The next three clocks are all optional, but shall be specified in this
> > + # order when present.
> > + - description: The HDMI CEC controller main clock
> > + - description: Power for GRF IO
> > + - description: External clock for some HDMI PHY
> > +
> > + clock-names:
> > + minItems: 2
> > + maxItems: 5
> > + items:
> > + - {}
> > + - {}
> > + - enum:
> > + - cec
> > + - grf
> > + - vpll
> > + - enum:
> > + - grf
> > + - vpll
> > + - const: vpll
> > +
> > + ddc-i2c-bus:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + The HDMI DDC bus can be connected to either a system I2C master or the
> > + functionally-reduced I2C master contained in the DWC HDMI. When connected
> > + to a system I2C master this property contains a phandle to that I2C
> > + master controller.
> > +
> > + phys:
> > + maxItems: 1
> > + description: The HDMI PHY
> > +
> > + phy-names:
> > + const: hdmi
> > +
> > + pinctrl-names:
> > + description:
> > + The unwedge pinctrl entry shall drive the DDC SDA line low. This is
> > + intended to work around a hardware errata that can cause the DDC I2C
> > + bus to be wedged.
> > + items:
> > + - const: default
> > + - const: unwedge
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
> > + properties:
> > + port:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
>
> In this case, this is correct since you have endpoint definitions.
>
> > + unevaluatedProperties: false
> > + description: Input of the DWC HDMI TX
> > +
> > + properties:
> > + endpoint@0:
> > + $ref: /schemas/graph.yaml#/$defs/endpoint-base
>
> #/properties/endpoint
>
> > + unevaluatedProperties: false
> > + description: Connection to the VOPB
>
> Oh good, we've done muxing both ways...
Isn't it nice ? :-S
Are endpoints the right way though ? When the mux is internal to an IP
core, there are multiple physical input ports.
> > +
> > + endpoint@1:
> > + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> > + unevaluatedProperties: false
> > + description: Connection to the VOPL
> > +
> > + required:
> > + - endpoint@0
> > + - endpoint@1
> > +
> > + required:
> > + - port
> > +
> > + rockchip,grf:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + phandle to the GRF to mux vopl/vopb.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-io-width
> > + - clocks
> > + - clock-names
> > + - interrupts
> > + - ports
> > + - rockchip,grf
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/rk3288-cru.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > + hdmi: hdmi@ff980000 {
> > + compatible = "rockchip,rk3288-dw-hdmi";
> > + reg = <0xff980000 0x20000>;
> > + reg-io-width = <4>;
> > + ddc-i2c-bus = <&i2c5>;
> > + rockchip,grf = <&grf>;
> > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
> > + clock-names = "iahb", "isfr";
> > +
> > + ports {
> > + port {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + hdmi_in_vopb: endpoint@0 {
> > + reg = <0>;
> > + remote-endpoint = <&vopb_out_hdmi>;
> > + };
> > + hdmi_in_vopl: endpoint@1 {
> > + reg = <1>;
> > + remote-endpoint = <&vopl_out_hdmi>;
> > + };
> > + };
> > + };
> > + };
> > +
> > +...
--
Regards,
Laurent Pinchart
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 5/6] dt-bindings: display: sun8i-a83t-dw-hdmi: Reference dw-hdmi YAML schema
2021-01-05 6:08 ` Laurent Pinchart
@ 2021-01-05 6:08 ` Laurent Pinchart
-1 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:08 UTC (permalink / raw)
To: dri-devel
Cc: linux-renesas-soc, devicetree, Rob Herring, Sandy Huang,
Chen-Yu Tsai, Maxime Ripard, Philipp Zabel, Mark Yao
Replace the reference to the DWC HDMI text DT binding with a reference
to the YAML equivalent.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
.../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
index fa4769a0b26e..5cbf655c3a07 100644
--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
@@ -12,8 +12,8 @@ description: |
and CEC.
These DT bindings follow the Synopsys DWC HDMI TX bindings defined
- in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with
- the following device-specific properties.
+ in bridge/synopsys,dw-hdmi.yaml with the following device-specific
+ properties.
maintainers:
- Chen-Yu Tsai <wens@csie.org>
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 5/6] dt-bindings: display: sun8i-a83t-dw-hdmi: Reference dw-hdmi YAML schema
@ 2021-01-05 6:08 ` Laurent Pinchart
0 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:08 UTC (permalink / raw)
To: dri-devel
Cc: devicetree, Sandy Huang, linux-renesas-soc, Chen-Yu Tsai,
Rob Herring, Maxime Ripard, Mark Yao
Replace the reference to the DWC HDMI text DT binding with a reference
to the YAML equivalent.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
.../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
index fa4769a0b26e..5cbf655c3a07 100644
--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
@@ -12,8 +12,8 @@ description: |
and CEC.
These DT bindings follow the Synopsys DWC HDMI TX bindings defined
- in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with
- the following device-specific properties.
+ in bridge/synopsys,dw-hdmi.yaml with the following device-specific
+ properties.
maintainers:
- Chen-Yu Tsai <wens@csie.org>
--
Regards,
Laurent Pinchart
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 6/6] dt-bindings: display: bridge: Remove deprecated dw_hdmi.txt
2021-01-05 6:08 ` Laurent Pinchart
@ 2021-01-05 6:08 ` Laurent Pinchart
-1 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:08 UTC (permalink / raw)
To: dri-devel
Cc: linux-renesas-soc, devicetree, Rob Herring, Sandy Huang,
Chen-Yu Tsai, Maxime Ripard, Philipp Zabel, Mark Yao
dw_hdmi.txt has been replaced with synopsys,dw-hdmi.yaml, and all
references to the old file have been converted. Remove it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../bindings/display/bridge/dw_hdmi.txt | 33 -------------------
1 file changed, 33 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt b/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
deleted file mode 100644
index 33bf981fbe33..000000000000
--- a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Synopsys DesignWare HDMI TX Encoder
-===================================
-
-This document defines device tree properties for the Synopsys DesignWare HDMI
-TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
-specification by itself but is meant to be referenced by platform-specific
-device tree bindings.
-
-When referenced from platform device tree bindings the properties defined in
-this document are defined as follows. The platform device tree bindings are
-responsible for defining whether each property is required or optional.
-
-- reg: Memory mapped base address and length of the DWC HDMI TX registers.
-
-- reg-io-width: Width of the registers specified by the reg property. The
- value is expressed in bytes and must be equal to 1 or 4 if specified. The
- register width defaults to 1 if the property is not present.
-
-- interrupts: Reference to the DWC HDMI TX interrupt.
-
-- clocks: References to all the clocks specified in the clock-names property
- as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
-
-- clock-names: The DWC HDMI TX uses the following clocks.
-
- - "iahb" is the bus clock for either AHB and APB (mandatory).
- - "isfr" is the internal register configuration clock (mandatory).
- - "cec" is the HDMI CEC controller main clock (optional).
-
-- ports: The connectivity of the DWC HDMI TX with the rest of the system is
- expressed in using ports as specified in the device graph bindings defined
- in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
- is platform-specific.
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 6/6] dt-bindings: display: bridge: Remove deprecated dw_hdmi.txt
@ 2021-01-05 6:08 ` Laurent Pinchart
0 siblings, 0 replies; 32+ messages in thread
From: Laurent Pinchart @ 2021-01-05 6:08 UTC (permalink / raw)
To: dri-devel
Cc: devicetree, Sandy Huang, linux-renesas-soc, Chen-Yu Tsai,
Rob Herring, Maxime Ripard, Mark Yao
dw_hdmi.txt has been replaced with synopsys,dw-hdmi.yaml, and all
references to the old file have been converted. Remove it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../bindings/display/bridge/dw_hdmi.txt | 33 -------------------
1 file changed, 33 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt b/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
deleted file mode 100644
index 33bf981fbe33..000000000000
--- a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Synopsys DesignWare HDMI TX Encoder
-===================================
-
-This document defines device tree properties for the Synopsys DesignWare HDMI
-TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
-specification by itself but is meant to be referenced by platform-specific
-device tree bindings.
-
-When referenced from platform device tree bindings the properties defined in
-this document are defined as follows. The platform device tree bindings are
-responsible for defining whether each property is required or optional.
-
-- reg: Memory mapped base address and length of the DWC HDMI TX registers.
-
-- reg-io-width: Width of the registers specified by the reg property. The
- value is expressed in bytes and must be equal to 1 or 4 if specified. The
- register width defaults to 1 if the property is not present.
-
-- interrupts: Reference to the DWC HDMI TX interrupt.
-
-- clocks: References to all the clocks specified in the clock-names property
- as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
-
-- clock-names: The DWC HDMI TX uses the following clocks.
-
- - "iahb" is the bus clock for either AHB and APB (mandatory).
- - "isfr" is the internal register configuration clock (mandatory).
- - "cec" is the HDMI CEC controller main clock (optional).
-
-- ports: The connectivity of the DWC HDMI TX with the rest of the system is
- expressed in using ports as specified in the device graph bindings defined
- in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
- is platform-specific.
--
Regards,
Laurent Pinchart
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