* [dpdk-dev] [PATCH v2 1/6] net/bnxt: add support for 58818 chip family
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
@ 2021-01-03 3:46 ` Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
` (5 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-03 3:46 UTC (permalink / raw)
To: dev; +Cc: Kalesh AP
[-- Attachment #1: Type: text/plain, Size: 8903 bytes --]
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
The new chip (Stingray 2) is part of the P5 chip family with a number
of changes:
1. Implement the epoch doorbell bit for 58818 chip. With the new doorbell
infrastructure and the unbounded index logic, now set the epoch
doorbell bit to support proper doorbell operation on the new chip.
Toggle epoch bit of all rings when it's wrapped to support doorbell
overflow checking.
2. Get the legacy doorbell size from firmware. Legacy doorbell support has
been removed in Stingray 2. So, the fast path doorbell pages start from
the base of the BAR. Drivers need to use legacy_l2_db_space_size_kb
field in the hwrm_func_qcfg_output response to get the legacy doorbell
page offset from the BAR.
3. Set VALID doorbell bit on 58818 chip family. This class of chip has
a valid doorbell bit added and it needs to be set.
4. Use "chip_num" returned by firmware. The "chip_num" field in the
HWRM_VER_GET output returns the chip number. Use this value to identify
chip category for 58818 chip family.
5. Added device ids for Stingray2 PF/VF devices.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
doc/guides/rel_notes/release_21_02.rst | 6 ++++++
drivers/net/bnxt/bnxt.h | 15 +++++++++++++++
drivers/net/bnxt/bnxt_cpr.h | 7 ++++++-
drivers/net/bnxt/bnxt_ethdev.c | 9 +++++++++
drivers/net/bnxt/bnxt_hwrm.c | 6 ++++++
drivers/net/bnxt/bnxt_ring.c | 19 +++++++++++++++----
6 files changed, 57 insertions(+), 5 deletions(-)
diff --git a/doc/guides/rel_notes/release_21_02.rst b/doc/guides/rel_notes/release_21_02.rst
index 706cbf8f0..b1bb2d867 100644
--- a/doc/guides/rel_notes/release_21_02.rst
+++ b/doc/guides/rel_notes/release_21_02.rst
@@ -55,6 +55,12 @@ New Features
Also, make sure to start the actual text at the margin.
=======================================================
+* **Updated Broadcom bnxt driver.**
+
+ Updated the Broadcom bnxt driver with fixes and improvements, including:
+
+ * Added support for Stingray2 device.
+
Removed Items
-------------
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 8374e9fad..0d3998f20 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -66,6 +66,10 @@
#define BROADCOM_DEV_ID_58804 0xd804
#define BROADCOM_DEV_ID_58808 0x16f0
#define BROADCOM_DEV_ID_58802_VF 0xd800
+#define BROADCOM_DEV_ID_58812 0xd812
+#define BROADCOM_DEV_ID_58814 0xd814
+#define BROADCOM_DEV_ID_58818 0xd818
+#define BROADCOM_DEV_ID_58818_VF 0xd82e
#define BROADCOM_DEV_957508_N2100 0x5208
#define IS_BNXT_DEV_957508_N2100(bp) \
@@ -367,14 +371,20 @@ struct bnxt_coal {
};
/* 64-bit doorbell */
+#define DBR_EPOCH_MASK 0x01000000UL
+#define DBR_EPOCH_SFT 24
#define DBR_XID_SFT 32
#define DBR_PATH_L2 (0x1ULL << 56)
+#define DBR_VALID (0x1ULL << 58)
#define DBR_TYPE_SQ (0x0ULL << 60)
#define DBR_TYPE_SRQ (0x2ULL << 60)
#define DBR_TYPE_CQ (0x4ULL << 60)
#define DBR_TYPE_NQ (0xaULL << 60)
#define DBR_TYPE_NQ_ARM (0xbULL << 60)
+#define DB_PF_OFFSET 0x10000
+#define DB_VF_OFFSET 0x4000
+
#define BNXT_RSS_TBL_SIZE_P5 512U
#define BNXT_RSS_ENTRIES_PER_CTX_P5 64
#define BNXT_MAX_RSS_CTXTS_P5 \
@@ -601,6 +611,7 @@ struct bnxt {
struct rte_eth_dev *eth_dev;
struct rte_pci_device *pdev;
void *doorbell_base;
+ int legacy_db_size;
uint32_t flags;
#define BNXT_FLAG_REGISTERED BIT(0)
@@ -649,6 +660,10 @@ struct bnxt {
#define BNXT_TRUFLOW_EN(bp) ((bp)->flags & BNXT_FLAG_TRUFLOW_EN)
#define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
+ uint16_t chip_num;
+#define CHIP_NUM_58818 0xd818
+#define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818)
+
uint32_t fw_cap;
#define BNXT_FW_CAP_HOT_RESET BIT(0)
#define BNXT_FW_CAP_IF_CHANGE BIT(1)
diff --git a/drivers/net/bnxt/bnxt_cpr.h b/drivers/net/bnxt/bnxt_cpr.h
index a763f6006..30635fcc1 100644
--- a/drivers/net/bnxt/bnxt_cpr.h
+++ b/drivers/net/bnxt/bnxt_cpr.h
@@ -81,9 +81,14 @@ struct bnxt_db_info {
};
bool db_64;
uint32_t db_ring_mask;
+ uint32_t db_epoch_mask;
+ uint32_t db_epoch_shift;
};
-#define DB_RING_IDX(db, idx) ((idx) & (db)->db_ring_mask)
+#define DB_EPOCH(db, idx) (((idx) & (db)->db_epoch_mask) << \
+ ((db)->db_epoch_shift))
+#define DB_RING_IDX(db, idx) (((idx) & (db)->db_ring_mask) | \
+ DB_EPOCH(db, idx))
struct bnxt_ring;
struct bnxt_cp_ring_info {
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 0788d263d..02ab87bba 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -80,6 +80,10 @@ static const struct rte_pci_id bnxt_pci_id_map[] = {
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
{ .vendor_id = 0, /* sentinel */ },
};
@@ -3979,6 +3983,7 @@ static bool bnxt_vf_pciid(uint16_t device_id)
case BROADCOM_DEV_ID_58802_VF:
case BROADCOM_DEV_ID_57500_VF1:
case BROADCOM_DEV_ID_57500_VF2:
+ case BROADCOM_DEV_ID_58818_VF:
/* FALLTHROUGH */
return true;
default:
@@ -4001,6 +4006,10 @@ static bool bnxt_p5_device(uint16_t device_id)
case BROADCOM_DEV_ID_57502_MF2:
case BROADCOM_DEV_ID_57500_VF1:
case BROADCOM_DEV_ID_57500_VF2:
+ case BROADCOM_DEV_ID_58812:
+ case BROADCOM_DEV_ID_58814:
+ case BROADCOM_DEV_ID_58818:
+ case BROADCOM_DEV_ID_58818_VF:
/* FALLTHROUGH */
return true;
default:
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 73647fba8..36c229de1 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1129,6 +1129,9 @@ int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
PMD_DRV_LOG(ERR, "Unsupported request length\n");
rc = -EINVAL;
}
+
+ bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
+
bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
@@ -3207,6 +3210,9 @@ int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
break;
}
+ bp->legacy_db_size =
+ rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
+
HWRM_UNLOCK();
return rc;
diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c
index adddf9bc4..75b541bdc 100644
--- a/drivers/net/bnxt/bnxt_ring.c
+++ b/drivers/net/bnxt/bnxt_ring.c
@@ -346,10 +346,7 @@ static void bnxt_set_db(struct bnxt *bp,
uint32_t ring_mask)
{
if (BNXT_CHIP_P5(bp)) {
- if (BNXT_PF(bp))
- db->doorbell = (char *)bp->doorbell_base + 0x10000;
- else
- db->doorbell = (char *)bp->doorbell_base + 0x4000;
+ int db_offset = DB_PF_OFFSET;
switch (ring_type) {
case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
@@ -365,6 +362,14 @@ static void bnxt_set_db(struct bnxt *bp,
db->db_key64 = DBR_PATH_L2;
break;
}
+ if (BNXT_CHIP_SR2(bp)) {
+ db->db_key64 |= DBR_VALID;
+ db_offset = bp->legacy_db_size;
+ } else if (BNXT_VF(bp)) {
+ db_offset = DB_VF_OFFSET;
+ }
+
+ db->doorbell = (char *)bp->doorbell_base + db_offset;
db->db_key64 |= (uint64_t)fid << DBR_XID_SFT;
db->db_64 = true;
} else {
@@ -383,6 +388,12 @@ static void bnxt_set_db(struct bnxt *bp,
db->db_64 = false;
}
db->db_ring_mask = ring_mask;
+
+ if (BNXT_CHIP_SR2(bp)) {
+ db->db_epoch_mask = db->db_ring_mask + 1;
+ db->db_epoch_shift = DBR_EPOCH_SFT -
+ rte_log2_u32(db->db_epoch_mask);
+ }
}
static int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index,
--
2.21.1 (Apple Git-122.3)
--
This electronic communication and the information and any files transmitted
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v2 2/6] net/bnxt: add new RX checksum mode
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
@ 2021-01-03 3:46 ` Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
` (4 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-03 3:46 UTC (permalink / raw)
To: dev; +Cc: Kalesh AP
[-- Attachment #1: Type: text/plain, Size: 2937 bytes --]
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
The 58818 chips support two different checksum modes.
Host driver has to register with FW which checksum mode it
prefers to use. DPDK driver want to use "cs_all_ok_mode=1".
FW advertises the support of the different checksum modes
on per VNIC basis in the HWRM_VNIC_QCAPS response.
Driver should use HWRM_VNIC_CFG to configure the needed
checksum mode.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 1 +
drivers/net/bnxt/bnxt_hwrm.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 0d3998f20..14f52b2c4 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -679,6 +679,7 @@ struct bnxt {
uint32_t vnic_cap_flags;
#define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0)
#define BNXT_VNIC_CAP_OUTER_RSS BIT(1)
+#define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2)
unsigned int rx_nr_rings;
unsigned int rx_cp_nr_rings;
unsigned int rx_num_qs_per_vnic;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 36c229de1..350fe2f97 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -860,6 +860,9 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
+ if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
+ bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
+
bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
HWRM_UNLOCK();
@@ -1961,6 +1964,11 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
+ if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
+ enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
+ req.rx_csum_v2_mode =
+ HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
+ }
goto config_mru;
}
--
2.21.1 (Apple Git-122.3)
--
This electronic communication and the information and any files transmitted
with it, or attached to it, are confidential and are intended solely for
the use of the individual or entity to whom it is addressed and may contain
information that is confidential, legally privileged, protected by privacy
laws, or otherwise restricted from disclosure to anyone else. If you are
not the intended recipient or the person responsible for delivering the
e-mail to the intended recipient, you are hereby notified that any use,
copying, distributing, dissemination, forwarding, printing, or copying of
this e-mail is strictly prohibited. If you received this e-mail in error,
please return the e-mail to the sender, delete it from your computer, and
destroy any printed copy of it.
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v2 3/6] net/bnxt: modify VNIC accounting
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
@ 2021-01-03 3:46 ` Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
` (3 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-03 3:46 UTC (permalink / raw)
To: dev; +Cc: Kalesh AP
[-- Attachment #1: Type: text/plain, Size: 6649 bytes --]
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Modify VNIC accounting when enabling RFS on newer chips.
Unlike legacy chips, newer chips don't need additional VNIC resources
for ntuple filter. Fix the code accordingly so that we don't reserve
and allocate additional VNICs on newer chips.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 3 +++
drivers/net/bnxt/bnxt_ethdev.c | 18 ++++++++++++++----
drivers/net/bnxt/bnxt_flow.c | 14 ++++++++++++--
drivers/net/bnxt/bnxt_hwrm.c | 32 ++++++++++++++++++++++++++++++++
drivers/net/bnxt/bnxt_hwrm.h | 5 +++--
5 files changed, 64 insertions(+), 8 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 14f52b2c4..276d807c7 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -643,6 +643,9 @@ struct bnxt {
#define BNXT_FLAG_DFLT_MAC_SET BIT(26)
#define BNXT_FLAG_TRUFLOW_EN BIT(27)
#define BNXT_FLAG_GFID_ENABLE BIT(28)
+#define BNXT_FLAG_RFS_NEEDS_VNIC BIT(29)
+#define BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2 BIT(30)
+#define BNXT_RFS_NEEDS_VNIC(bp) ((bp)->flags & BNXT_FLAG_RFS_NEEDS_VNIC)
#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
#define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 02ab87bba..8ca4fb151 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -748,11 +748,17 @@ static int bnxt_init_chip(struct bnxt *bp)
goto err_out;
}
+ /* default vnic 0 */
+ rc = bnxt_setup_one_vnic(bp, 0);
+ if (rc)
+ goto err_out;
/* VNIC configuration */
- for (i = 0; i < bp->nr_vnics; i++) {
- rc = bnxt_setup_one_vnic(bp, i);
- if (rc)
- goto err_out;
+ if (BNXT_RFS_NEEDS_VNIC(bp)) {
+ for (i = 1; i < bp->nr_vnics; i++) {
+ rc = bnxt_setup_one_vnic(bp, i);
+ if (rc)
+ goto err_out;
+ }
}
rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
@@ -4698,6 +4704,10 @@ static int bnxt_init_fw(struct bnxt *bp)
if (rc)
return rc;
+ rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
+ if (rc)
+ return rc;
+
bnxt_hwrm_port_mac_qcfg(bp);
bnxt_hwrm_parent_pf_qcfg(bp);
diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c
index 127d51c45..07d359edf 100644
--- a/drivers/net/bnxt/bnxt_flow.c
+++ b/drivers/net/bnxt/bnxt_flow.c
@@ -1056,6 +1056,13 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev,
}
PMD_DRV_LOG(DEBUG, "Queue index %d\n", act_q->index);
+ if (use_ntuple && !BNXT_RFS_NEEDS_VNIC(bp)) {
+ filter->flags =
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX;
+ filter->dst_id = act_q->index;
+ goto skip_vnic_alloc;
+ }
+
vnic_id = attr->group;
if (!vnic_id) {
PMD_DRV_LOG(DEBUG, "Group id is 0\n");
@@ -1127,7 +1134,7 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev,
PMD_DRV_LOG(DEBUG,
"Setting vnic ff_idx %d\n", vnic->ff_pool_idx);
filter->dst_id = vnic->fw_vnic_id;
-
+skip_vnic_alloc:
/* For ntuple filter, create the L2 filter with default VNIC.
* The user specified redirect queue will be set while creating
* the ntuple filter in hardware.
@@ -1808,7 +1815,10 @@ bnxt_flow_create(struct rte_eth_dev *dev,
}
}
- vnic = find_matching_vnic(bp, filter);
+ if (BNXT_RFS_NEEDS_VNIC(bp))
+ vnic = find_matching_vnic(bp, filter);
+ else
+ vnic = BNXT_GET_DEFAULT_VNIC(bp);
done:
if (!ret || update_flow) {
flow->filter = filter;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 350fe2f97..56e2e33a9 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -5834,3 +5834,35 @@ int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
rep_bp->vf_id);
return rc;
}
+
+int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
+{
+ struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
+ bp->hwrm_cmd_resp_addr;
+ struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
+ uint32_t flags = 0;
+ int rc = 0;
+
+ if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
+ return 0;
+
+ if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
+ PMD_DRV_LOG(DEBUG,
+ "Not a PF or trusted VF. Command not supported\n");
+ return 0;
+ }
+
+ HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+
+ HWRM_CHECK_RESULT();
+ flags = rte_le_to_cpu_32(resp->flags);
+ HWRM_UNLOCK();
+
+ if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
+ bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
+ else
+ bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
+
+ return rc;
+}
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index 4b3290773..7deea29ca 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -55,8 +55,8 @@ struct hwrm_func_qstats_output;
#define HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK \
HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK
-#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN \
-HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED
+#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED \
+ HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED
#define HWRM_SPEC_CODE_1_8_4 0x10804
#define HWRM_SPEC_CODE_1_9_0 0x10900
@@ -300,4 +300,5 @@ int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
uint16_t *first_vf_id);
int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep);
int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep);
+int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp);
#endif
--
2.21.1 (Apple Git-122.3)
--
This electronic communication and the information and any files transmitted
with it, or attached to it, are confidential and are intended solely for
the use of the individual or entity to whom it is addressed and may contain
information that is confidential, legally privileged, protected by privacy
laws, or otherwise restricted from disclosure to anyone else. If you are
not the intended recipient or the person responsible for delivering the
e-mail to the intended recipient, you are hereby notified that any use,
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this e-mail is strictly prohibited. If you received this e-mail in error,
please return the e-mail to the sender, delete it from your computer, and
destroy any printed copy of it.
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v2 4/6] net/bnxt: add LRO support for SR2 chip
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
` (2 preceding siblings ...)
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
@ 2021-01-03 3:46 ` Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 5/6] net/bnxt: modify context memory allocation code Ajit Khaparde
` (2 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-03 3:46 UTC (permalink / raw)
To: dev; +Cc: Kalesh AP
[-- Attachment #1: Type: text/plain, Size: 5715 bytes --]
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Add the new chip specific TPA v2 logic to bnxt_tpa_start() to fully support
TPA on the new chip.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_rxr.c | 72 +++++++++++++++++++++++++++++++------
drivers/net/bnxt/bnxt_rxr.h | 12 ++++++-
2 files changed, 72 insertions(+), 12 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index 14901f1b9..af3f9b936 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -134,6 +134,53 @@ struct rte_mbuf *bnxt_consume_rx_buf(struct bnxt_rx_ring_info *rxr,
return mbuf;
}
+static void bnxt_tpa_get_metadata(struct bnxt *bp,
+ struct bnxt_tpa_info *tpa_info,
+ struct rx_tpa_start_cmpl *tpa_start,
+ struct rx_tpa_start_cmpl_hi *tpa_start1)
+{
+ tpa_info->cfa_code_valid = 0;
+ tpa_info->vlan_valid = 0;
+ tpa_info->hash_valid = 0;
+ tpa_info->l4_csum_valid = 0;
+
+ if (likely(tpa_start->flags_type &
+ rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
+ tpa_info->hash_valid = 1;
+ tpa_info->rss_hash = rte_le_to_cpu_32(tpa_start->rss_hash);
+ }
+
+ if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
+ struct rx_tpa_start_v2_cmpl *v2_tpa_start = (void *)tpa_start;
+ struct rx_tpa_start_v2_cmpl_hi *v2_tpa_start1 =
+ (void *)tpa_start1;
+
+ if (v2_tpa_start->agg_id &
+ RX_TPA_START_V2_CMPL_METADATA1_VALID) {
+ tpa_info->vlan_valid = 1;
+ tpa_info->vlan =
+ rte_le_to_cpu_16(v2_tpa_start1->metadata0);
+ }
+
+ if (v2_tpa_start1->flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK)
+ tpa_info->l4_csum_valid = 1;
+
+ return;
+ }
+
+ tpa_info->cfa_code_valid = 1;
+ tpa_info->cfa_code = rte_le_to_cpu_16(tpa_start1->cfa_code);
+ if (tpa_start1->flags2 &
+ rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
+ tpa_info->vlan_valid = 1;
+ tpa_info->vlan = rte_le_to_cpu_32(tpa_start1->metadata);
+ }
+
+ if (likely(tpa_start1->flags2 &
+ rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
+ tpa_info->l4_csum_valid = 1;
+}
+
static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
struct rx_tpa_start_cmpl *tpa_start,
struct rx_tpa_start_cmpl_hi *tpa_start1)
@@ -164,21 +211,23 @@ static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
mbuf->data_len = mbuf->pkt_len;
mbuf->port = rxq->port_id;
mbuf->ol_flags = PKT_RX_LRO;
- if (likely(tpa_start->flags_type &
- rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
- mbuf->hash.rss = rte_le_to_cpu_32(tpa_start->rss_hash);
+
+ bnxt_tpa_get_metadata(rxq->bp, tpa_info, tpa_start, tpa_start1);
+
+ if (likely(tpa_info->hash_valid)) {
+ mbuf->hash.rss = tpa_info->rss_hash;
mbuf->ol_flags |= PKT_RX_RSS_HASH;
- } else {
- mbuf->hash.fdir.id = rte_le_to_cpu_16(tpa_start1->cfa_code);
+ } else if (tpa_info->cfa_code_valid) {
+ mbuf->hash.fdir.id = tpa_info->cfa_code;
mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
}
- if (tpa_start1->flags2 &
- rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
- mbuf->vlan_tci = rte_le_to_cpu_32(tpa_start1->metadata);
+
+ if (tpa_info->vlan_valid) {
+ mbuf->vlan_tci = tpa_info->vlan;
mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
}
- if (likely(tpa_start1->flags2 &
- rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
+
+ if (likely(tpa_info->l4_csum_valid))
mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
/* recycle next mbuf */
@@ -751,7 +800,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
cpr->cp_ring_struct->ring_mask,
cpr->valid);
- if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START) {
+ if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START ||
+ cmp_type == RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2) {
bnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp,
(struct rx_tpa_start_cmpl_hi *)rxcmp1);
rc = -EINVAL; /* Continue w/o new mbuf */
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index b2942030a..78814edbb 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -50,6 +50,14 @@ struct bnxt_tpa_info {
uint16_t len;
uint32_t agg_count;
struct rx_tpa_v2_abuf_cmpl agg_arr[TPA_MAX_NUM_SEGS];
+
+ uint32_t rss_hash;
+ uint32_t vlan;
+ uint16_t cfa_code;
+ uint8_t hash_valid:1;
+ uint8_t vlan_valid:1;
+ uint8_t cfa_code_valid:1;
+ uint8_t l4_csum_valid:1;
};
struct bnxt_rx_ring_info {
@@ -122,4 +130,6 @@ bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)
#define BNXT_PTYPE_TBL_DIM 128
extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM];
-#endif
+
+#define RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK (0x1 << 14)
+#endif /* _BNXT_RXR_H_ */
--
2.21.1 (Apple Git-122.3)
--
This electronic communication and the information and any files transmitted
with it, or attached to it, are confidential and are intended solely for
the use of the individual or entity to whom it is addressed and may contain
information that is confidential, legally privileged, protected by privacy
laws, or otherwise restricted from disclosure to anyone else. If you are
not the intended recipient or the person responsible for delivering the
e-mail to the intended recipient, you are hereby notified that any use,
copying, distributing, dissemination, forwarding, printing, or copying of
this e-mail is strictly prohibited. If you received this e-mail in error,
please return the e-mail to the sender, delete it from your computer, and
destroy any printed copy of it.
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v2 5/6] net/bnxt: modify context memory allocation code
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
` (3 preceding siblings ...)
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
@ 2021-01-03 3:46 ` Ajit Khaparde
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-03 3:46 UTC (permalink / raw)
To: dev; +Cc: Kalesh AP
[-- Attachment #1: Type: text/plain, Size: 4930 bytes --]
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Newer devices like SR2 may have chip backing store and do not require
host backed memory allocation.
In these cases, HWRM_FUNC_BACKING_STORE_QCAPS will return a zero entry
size to indicate contexts for which the host should not allocate backing
store.
Selectively allocate context memory based on device capabilities and
only enable backing store for the appropriate contexts.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 60 ++++++++++++++++++++--------------
drivers/net/bnxt/bnxt_hwrm.c | 3 ++
2 files changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 8ca4fb151..e11751cc1 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -4212,39 +4212,49 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)
ctx_pg = &ctx->qp_mem;
ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
- mem_size = ctx->qp_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
- if (rc)
- return rc;
+ if (ctx->qp_entry_size) {
+ mem_size = ctx->qp_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
+ if (rc)
+ return rc;
+ }
ctx_pg = &ctx->srq_mem;
ctx_pg->entries = ctx->srq_max_l2_entries;
- mem_size = ctx->srq_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
- if (rc)
- return rc;
+ if (ctx->srq_entry_size) {
+ mem_size = ctx->srq_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
+ if (rc)
+ return rc;
+ }
ctx_pg = &ctx->cq_mem;
ctx_pg->entries = ctx->cq_max_l2_entries;
- mem_size = ctx->cq_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
- if (rc)
- return rc;
+ if (ctx->cq_entry_size) {
+ mem_size = ctx->cq_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
+ if (rc)
+ return rc;
+ }
ctx_pg = &ctx->vnic_mem;
ctx_pg->entries = ctx->vnic_max_vnic_entries +
ctx->vnic_max_ring_table_entries;
- mem_size = ctx->vnic_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
- if (rc)
- return rc;
+ if (ctx->vnic_entry_size) {
+ mem_size = ctx->vnic_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
+ if (rc)
+ return rc;
+ }
ctx_pg = &ctx->stat_mem;
ctx_pg->entries = ctx->stat_max_entries;
- mem_size = ctx->stat_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
- if (rc)
- return rc;
+ if (ctx->stat_entry_size) {
+ mem_size = ctx->stat_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
+ if (rc)
+ return rc;
+ }
min = ctx->tqm_min_entries_per_ring;
@@ -4260,10 +4270,12 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)
for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
ctx_pg = ctx->tqm_mem[i];
ctx_pg->entries = i ? entries : entries_sp;
- mem_size = ctx->tqm_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
- if (rc)
- return rc;
+ if (ctx->tqm_entry_size) {
+ mem_size = ctx->tqm_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
+ if (rc)
+ return rc;
+ }
ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
}
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 56e2e33a9..6d54b1656 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -64,6 +64,9 @@ static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
uint8_t *pg_attr,
uint64_t *pg_dir)
{
+ if (rmem->nr_pages == 0)
+ return;
+
if (rmem->nr_pages > 1) {
*pg_attr = 1;
*pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
--
2.21.1 (Apple Git-122.3)
--
This electronic communication and the information and any files transmitted
with it, or attached to it, are confidential and are intended solely for
the use of the individual or entity to whom it is addressed and may contain
information that is confidential, legally privileged, protected by privacy
laws, or otherwise restricted from disclosure to anyone else. If you are
not the intended recipient or the person responsible for delivering the
e-mail to the intended recipient, you are hereby notified that any use,
copying, distributing, dissemination, forwarding, printing, or copying of
this e-mail is strictly prohibited. If you received this e-mail in error,
please return the e-mail to the sender, delete it from your computer, and
destroy any printed copy of it.
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v2 6/6] net/bnxt: add Rx logic for 58818 chips
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
` (4 preceding siblings ...)
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 5/6] net/bnxt: modify context memory allocation code Ajit Khaparde
@ 2021-01-03 3:46 ` Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-03 3:46 UTC (permalink / raw)
To: dev; +Cc: Kalesh AP
[-- Attachment #1: Type: text/plain, Size: 11360 bytes --]
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
1. On the new 58818 chips, the RX completion is largely the same except
for the new completion opcode and the stripped VLAN format and checksum
status. Added bnxt_parse_csum_v2(), bnxt_parse_pkt_type_v2() and
bnxt_rx_vlan_v2() to support the new RX completion logic.
2. Disable vector mode RX/TX for 58818 chips for now.
3. The cfa_code format on 58818 chips is different than legacy chips.
So skip cfa_code parsing logic on 58818 chips for now.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 15 ++-
drivers/net/bnxt/bnxt_rxr.c | 24 +++--
drivers/net/bnxt/bnxt_rxr.h | 191 +++++++++++++++++++++++++++++++++
3 files changed, 221 insertions(+), 9 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index e11751cc1..ef6b611be 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -1159,6 +1159,12 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = eth_dev->data->dev_private;
+ /* Disable vector mode RX for Stingray2 for now */
+ if (BNXT_CHIP_SR2(bp)) {
+ bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
+ return bnxt_recv_pkts;
+ }
+
#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
#ifndef RTE_LIBRTE_IEEE1588
/*
@@ -1199,12 +1205,17 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev)
}
static eth_tx_burst_t
-bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
+bnxt_transmit_function(struct rte_eth_dev *eth_dev)
{
+ struct bnxt *bp = eth_dev->data->dev_private;
+
+ /* Disable vector mode TX for Stingray2 for now */
+ if (BNXT_CHIP_SR2(bp))
+ return bnxt_xmit_pkts;
+
#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
#ifndef RTE_LIBRTE_IEEE1588
uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
- struct bnxt *bp = eth_dev->data->dev_private;
/*
* Vector mode transmit can be enabled only if not using scatter rx
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index af3f9b936..a195bf118 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -814,7 +814,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
return -EBUSY;
*rx_pkt = mbuf;
goto next_rx;
- } else if (cmp_type != 0x11) {
+ } else if ((cmp_type != CMPL_BASE_TYPE_RX_L2) &&
+ (cmp_type != CMPL_BASE_TYPE_RX_L2_V2)) {
rc = -EINVAL;
goto next_rx;
}
@@ -838,8 +839,6 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
mbuf->data_len = mbuf->pkt_len;
mbuf->port = rxq->port_id;
- bnxt_set_ol_flags(rxr, rxcmp, rxcmp1, mbuf);
-
#ifdef RTE_LIBRTE_IEEE1588
if (unlikely((rte_le_to_cpu_16(rxcmp->flags_type) &
RX_PKT_CMPL_FLAGS_MASK) ==
@@ -849,17 +848,28 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
}
#endif
+ if (cmp_type == CMPL_BASE_TYPE_RX_L2_V2) {
+ bnxt_parse_csum_v2(mbuf, rxcmp1);
+ bnxt_parse_pkt_type_v2(mbuf, rxcmp, rxcmp1);
+ bnxt_rx_vlan_v2(mbuf, rxcmp, rxcmp1);
+ /* TODO Add support for cfa_code parsing */
+ goto reuse_rx_mbuf;
+ }
+
+ bnxt_set_ol_flags(rxr, rxcmp, rxcmp1, mbuf);
+
+ mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
+
if (BNXT_TRUFLOW_EN(bp))
mark_id = bnxt_ulp_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf,
&vfr_flag);
else
bnxt_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf);
+reuse_rx_mbuf:
if (agg_buf)
bnxt_rx_pages(rxq, mbuf, &tmp_raw_cons, agg_buf, NULL);
- mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
-
#ifdef BNXT_DEBUG
if (rxcmp1->errors_v2 & RX_CMP_L2_ERRORS) {
/* Re-install the mbuf back to the rx ring */
@@ -972,8 +982,8 @@ uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
cpr->cp_ring_struct->ring_mask,
cpr->valid);
- /* TODO: Avoid magic numbers... */
- if ((CMP_TYPE(rxcmp) & 0x30) == 0x10) {
+ if ((CMP_TYPE(rxcmp) >= CMPL_BASE_TYPE_RX_TPA_START_V2) &&
+ (CMP_TYPE(rxcmp) <= RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG)) {
rc = bnxt_rx_pkt(&rx_pkts[nb_rx_pkts], rxq, &raw_cons);
if (!rc)
nb_rx_pkts++;
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index 78814edbb..9cc5197a7 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -131,5 +131,196 @@ bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)
#define BNXT_PTYPE_TBL_DIM 128
extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM];
+/* Stingray2 specific code for RX completion parsing */
+#define RX_CMP_VLAN_VALID(rxcmp) \
+ (((struct rx_pkt_v2_cmpl *)rxcmp)->metadata1_payload_offset & \
+ RX_PKT_V2_CMPL_METADATA1_VALID)
+
+#define RX_CMP_METADATA0_VID(rxcmp1) \
+ ((((struct rx_pkt_v2_cmpl_hi *)rxcmp1)->metadata0) & \
+ (RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK | \
+ RX_PKT_V2_CMPL_HI_METADATA0_DE | \
+ RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK))
+
+static inline void bnxt_rx_vlan_v2(struct rte_mbuf *mbuf,
+ struct rx_pkt_cmpl *rxcmp,
+ struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ if (RX_CMP_VLAN_VALID(rxcmp)) {
+ mbuf->vlan_tci = RX_CMP_METADATA0_VID(rxcmp1);
+ mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
+ }
+}
+
+#define RX_CMP_FLAGS2_CS_ALL_OK_MODE_MASK (0x1 << 3)
+#define RX_CMP_FLAGS2_CS_OK_HDR_CNT_MASK (0x7 << 10)
+#define RX_CMP_FLAGS2_IP_CSUM_ALL_OK_MASK (0x1 << 13)
#define RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK (0x1 << 14)
+
+#define RX_CMP_V2_CS_OK_HDR_CNT(flags) \
+ (((flags) & RX_CMP_FLAGS2_CS_OK_HDR_CNT_MASK) >> \
+ RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT)
+
+#define RX_CMP_V2_CS_ALL_OK_MODE(flags) \
+ (((flags) & RX_CMP_FLAGS2_CS_ALL_OK_MODE_MASK))
+
+#define RX_CMP_FLAGS2_L3_CS_OK_MASK (0x7 << 10)
+#define RX_CMP_FLAGS2_L4_CS_OK_MASK (0x38 << 10)
+#define RX_CMP_FLAGS2_L3_CS_OK_SFT 10
+#define RX_CMP_FLAGS2_L4_CS_OK_SFT 13
+
+#define RX_CMP_V2_L4_CS_OK(flags2) \
+ (((flags2) & RX_CMP_FLAGS2_L4_CS_OK_MASK) >> \
+ RX_CMP_FLAGS2_L4_CS_OK_SFT)
+
+#define RX_CMP_V2_L3_CS_OK(flags2) \
+ (((flags2) & RX_CMP_FLAGS2_L3_CS_OK_MASK) >> \
+ RX_CMP_FLAGS2_L3_CS_OK_SFT)
+
+#define RX_CMP_V2_L4_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR)
+
+#define RX_CMP_V2_L3_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR)
+
+#define RX_CMP_V2_T_IP_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR)
+
+#define RX_CMP_V2_T_L4_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR)
+
+#define RX_CMP_V2_OT_L4_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR)
+
+static inline void bnxt_parse_csum_v2(struct rte_mbuf *mbuf,
+ struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ struct rx_pkt_v2_cmpl_hi *v2_cmp =
+ (struct rx_pkt_v2_cmpl_hi *)(rxcmp1);
+ uint16_t error_v2 = rte_le_to_cpu_16(v2_cmp->errors_v2);
+ uint32_t flags2 = rte_le_to_cpu_32(v2_cmp->flags2);
+ uint32_t hdr_cnt = 0, t_pkt = 0;
+
+ if (RX_CMP_V2_CS_ALL_OK_MODE(flags2)) {
+ hdr_cnt = RX_CMP_V2_CS_OK_HDR_CNT(flags2);
+ if (hdr_cnt > 1)
+ t_pkt = 1;
+
+ if (unlikely(RX_CMP_V2_L4_CS_ERR(error_v2)))
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
+ else if (flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK)
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
+ else
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
+
+ if (unlikely(RX_CMP_V2_L3_CS_ERR(error_v2)))
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
+ else if (flags2 & RX_CMP_FLAGS2_IP_CSUM_ALL_OK_MASK)
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
+ else
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
+ } else {
+ hdr_cnt = RX_CMP_V2_L4_CS_OK(flags2);
+ if (hdr_cnt > 1)
+ t_pkt = 1;
+
+ if (RX_CMP_V2_L4_CS_OK(flags2))
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
+ else if (RX_CMP_V2_L4_CS_ERR(error_v2))
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
+ else
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
+
+ if (RX_CMP_V2_L3_CS_OK(flags2))
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
+ else if (RX_CMP_V2_L3_CS_ERR(error_v2))
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
+ else
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
+ }
+
+ if (t_pkt) {
+ if (unlikely(RX_CMP_V2_OT_L4_CS_ERR(error_v2) ||
+ RX_CMP_V2_T_L4_CS_ERR(error_v2)))
+ mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
+ else
+ mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
+
+ if (unlikely(RX_CMP_V2_T_IP_CS_ERR(error_v2)))
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
+ }
+}
+
+static inline void
+bnxt_parse_pkt_type_v2(struct rte_mbuf *mbuf,
+ struct rx_pkt_cmpl *rxcmp,
+ struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ struct rx_pkt_v2_cmpl *v2_cmp =
+ (struct rx_pkt_v2_cmpl *)(rxcmp);
+ struct rx_pkt_v2_cmpl_hi *v2_cmp1 =
+ (struct rx_pkt_v2_cmpl_hi *)(rxcmp1);
+ uint16_t flags_type = v2_cmp->flags_type &
+ rte_cpu_to_le_32(RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK);
+ uint32_t flags2 = rte_le_to_cpu_32(v2_cmp1->flags2);
+ uint32_t l3, pkt_type = 0, vlan = 0;
+ uint32_t ip6 = 0, t_pkt = 0;
+ uint32_t hdr_cnt, csum_count;
+
+ if (RX_CMP_V2_CS_ALL_OK_MODE(flags2)) {
+ hdr_cnt = RX_CMP_V2_CS_OK_HDR_CNT(flags2);
+ if (hdr_cnt > 1)
+ t_pkt = 1;
+ } else {
+ csum_count = RX_CMP_V2_L4_CS_OK(flags2);
+ if (csum_count > 1)
+ t_pkt = 1;
+ }
+
+ vlan = !!RX_CMP_VLAN_VALID(rxcmp);
+ pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
+
+ ip6 = !!(flags2 & RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE);
+
+ if (!t_pkt && !ip6)
+ l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
+ else if (!t_pkt && ip6)
+ l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
+ else if (t_pkt && !ip6)
+ l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
+ else
+ l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
+
+ switch (flags_type) {
+ case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP):
+ if (!t_pkt)
+ pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
+ break;
+ case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP):
+ if (!t_pkt)
+ pkt_type |= l3 | RTE_PTYPE_L4_TCP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
+ break;
+ case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP):
+ if (!t_pkt)
+ pkt_type |= l3 | RTE_PTYPE_L4_UDP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
+ break;
+ case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_IP):
+ pkt_type |= l3;
+ break;
+ }
+
+ mbuf->packet_type = pkt_type;
+}
+
#endif /* _BNXT_RXR_H_ */
--
2.21.1 (Apple Git-122.3)
--
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
` (5 preceding siblings ...)
2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
@ 2021-01-08 5:12 ` Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
` (6 more replies)
6 siblings, 7 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-08 5:12 UTC (permalink / raw)
To: dev
Add support for 58818/Stingray2 chip.
The new chip Stingray 2 belongs to the P5 generation.
Some changes in the PMD are required to support this new chip.
This patchset adds the necessary changes.
Please apply.
v1->v2: rebased to latest dpdk-next-net-brcm tree.
v2->v3: rebased to latest code base.
Kalesh AP (6):
net/bnxt: add support for 58818 chip family
net/bnxt: add new RX checksum mode
net/bnxt: modify VNIC accounting
net/bnxt: add LRO support for SR2 chip
net/bnxt: modify context memory allocation
net/bnxt: add Rx logic for 58818 chips
doc/guides/rel_notes/release_21_02.rst | 6 +
drivers/net/bnxt/bnxt.h | 19 +++
drivers/net/bnxt/bnxt_cpr.h | 7 +-
drivers/net/bnxt/bnxt_ethdev.c | 102 +++++++++----
drivers/net/bnxt/bnxt_flow.c | 14 +-
drivers/net/bnxt/bnxt_hwrm.c | 49 ++++++
drivers/net/bnxt/bnxt_hwrm.h | 5 +-
drivers/net/bnxt/bnxt_ring.c | 19 ++-
drivers/net/bnxt/bnxt_rxr.c | 96 +++++++++---
drivers/net/bnxt/bnxt_rxr.h | 203 ++++++++++++++++++++++++-
10 files changed, 462 insertions(+), 58 deletions(-)
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v3 1/6] net/bnxt: add support for 58818 chip family
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
@ 2021-01-08 5:12 ` Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
` (5 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-08 5:12 UTC (permalink / raw)
To: dev; +Cc: Kalesh AP
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
The new chip (Stingray 2) is part of the P5 chip family with a number
of changes:
1. Implement the epoch doorbell bit for 58818 chip. With the new doorbell
infrastructure and the unbounded index logic, now set the epoch
doorbell bit to support proper doorbell operation on the new chip.
Toggle epoch bit of all rings when it's wrapped to support doorbell
overflow checking.
2. Get the legacy doorbell size from firmware. Legacy doorbell support has
been removed in Stingray 2. So, the fast path doorbell pages start from
the base of the BAR. Drivers need to use legacy_l2_db_space_size_kb
field in the hwrm_func_qcfg_output response to get the legacy doorbell
page offset from the BAR.
3. Set VALID doorbell bit on 58818 chip family. This class of chip has
a valid doorbell bit added and it needs to be set.
4. Use "chip_num" returned by firmware. The "chip_num" field in the
HWRM_VER_GET output returns the chip number. Use this value to identify
chip category for 58818 chip family.
5. Added device ids for Stingray2 PF/VF devices.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
doc/guides/rel_notes/release_21_02.rst | 6 ++++++
drivers/net/bnxt/bnxt.h | 15 +++++++++++++++
drivers/net/bnxt/bnxt_cpr.h | 7 ++++++-
drivers/net/bnxt/bnxt_ethdev.c | 9 +++++++++
drivers/net/bnxt/bnxt_hwrm.c | 6 ++++++
drivers/net/bnxt/bnxt_ring.c | 19 +++++++++++++++----
6 files changed, 57 insertions(+), 5 deletions(-)
diff --git a/doc/guides/rel_notes/release_21_02.rst b/doc/guides/rel_notes/release_21_02.rst
index 706cbf8f0..b1bb2d867 100644
--- a/doc/guides/rel_notes/release_21_02.rst
+++ b/doc/guides/rel_notes/release_21_02.rst
@@ -55,6 +55,12 @@ New Features
Also, make sure to start the actual text at the margin.
=======================================================
+* **Updated Broadcom bnxt driver.**
+
+ Updated the Broadcom bnxt driver with fixes and improvements, including:
+
+ * Added support for Stingray2 device.
+
Removed Items
-------------
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 8374e9fad..0d3998f20 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -66,6 +66,10 @@
#define BROADCOM_DEV_ID_58804 0xd804
#define BROADCOM_DEV_ID_58808 0x16f0
#define BROADCOM_DEV_ID_58802_VF 0xd800
+#define BROADCOM_DEV_ID_58812 0xd812
+#define BROADCOM_DEV_ID_58814 0xd814
+#define BROADCOM_DEV_ID_58818 0xd818
+#define BROADCOM_DEV_ID_58818_VF 0xd82e
#define BROADCOM_DEV_957508_N2100 0x5208
#define IS_BNXT_DEV_957508_N2100(bp) \
@@ -367,14 +371,20 @@ struct bnxt_coal {
};
/* 64-bit doorbell */
+#define DBR_EPOCH_MASK 0x01000000UL
+#define DBR_EPOCH_SFT 24
#define DBR_XID_SFT 32
#define DBR_PATH_L2 (0x1ULL << 56)
+#define DBR_VALID (0x1ULL << 58)
#define DBR_TYPE_SQ (0x0ULL << 60)
#define DBR_TYPE_SRQ (0x2ULL << 60)
#define DBR_TYPE_CQ (0x4ULL << 60)
#define DBR_TYPE_NQ (0xaULL << 60)
#define DBR_TYPE_NQ_ARM (0xbULL << 60)
+#define DB_PF_OFFSET 0x10000
+#define DB_VF_OFFSET 0x4000
+
#define BNXT_RSS_TBL_SIZE_P5 512U
#define BNXT_RSS_ENTRIES_PER_CTX_P5 64
#define BNXT_MAX_RSS_CTXTS_P5 \
@@ -601,6 +611,7 @@ struct bnxt {
struct rte_eth_dev *eth_dev;
struct rte_pci_device *pdev;
void *doorbell_base;
+ int legacy_db_size;
uint32_t flags;
#define BNXT_FLAG_REGISTERED BIT(0)
@@ -649,6 +660,10 @@ struct bnxt {
#define BNXT_TRUFLOW_EN(bp) ((bp)->flags & BNXT_FLAG_TRUFLOW_EN)
#define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
+ uint16_t chip_num;
+#define CHIP_NUM_58818 0xd818
+#define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818)
+
uint32_t fw_cap;
#define BNXT_FW_CAP_HOT_RESET BIT(0)
#define BNXT_FW_CAP_IF_CHANGE BIT(1)
diff --git a/drivers/net/bnxt/bnxt_cpr.h b/drivers/net/bnxt/bnxt_cpr.h
index a763f6006..30635fcc1 100644
--- a/drivers/net/bnxt/bnxt_cpr.h
+++ b/drivers/net/bnxt/bnxt_cpr.h
@@ -81,9 +81,14 @@ struct bnxt_db_info {
};
bool db_64;
uint32_t db_ring_mask;
+ uint32_t db_epoch_mask;
+ uint32_t db_epoch_shift;
};
-#define DB_RING_IDX(db, idx) ((idx) & (db)->db_ring_mask)
+#define DB_EPOCH(db, idx) (((idx) & (db)->db_epoch_mask) << \
+ ((db)->db_epoch_shift))
+#define DB_RING_IDX(db, idx) (((idx) & (db)->db_ring_mask) | \
+ DB_EPOCH(db, idx))
struct bnxt_ring;
struct bnxt_cp_ring_info {
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 0788d263d..02ab87bba 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -80,6 +80,10 @@ static const struct rte_pci_id bnxt_pci_id_map[] = {
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
{ .vendor_id = 0, /* sentinel */ },
};
@@ -3979,6 +3983,7 @@ static bool bnxt_vf_pciid(uint16_t device_id)
case BROADCOM_DEV_ID_58802_VF:
case BROADCOM_DEV_ID_57500_VF1:
case BROADCOM_DEV_ID_57500_VF2:
+ case BROADCOM_DEV_ID_58818_VF:
/* FALLTHROUGH */
return true;
default:
@@ -4001,6 +4006,10 @@ static bool bnxt_p5_device(uint16_t device_id)
case BROADCOM_DEV_ID_57502_MF2:
case BROADCOM_DEV_ID_57500_VF1:
case BROADCOM_DEV_ID_57500_VF2:
+ case BROADCOM_DEV_ID_58812:
+ case BROADCOM_DEV_ID_58814:
+ case BROADCOM_DEV_ID_58818:
+ case BROADCOM_DEV_ID_58818_VF:
/* FALLTHROUGH */
return true;
default:
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 73647fba8..36c229de1 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1129,6 +1129,9 @@ int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
PMD_DRV_LOG(ERR, "Unsupported request length\n");
rc = -EINVAL;
}
+
+ bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
+
bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
@@ -3207,6 +3210,9 @@ int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
break;
}
+ bp->legacy_db_size =
+ rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
+
HWRM_UNLOCK();
return rc;
diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c
index adddf9bc4..75b541bdc 100644
--- a/drivers/net/bnxt/bnxt_ring.c
+++ b/drivers/net/bnxt/bnxt_ring.c
@@ -346,10 +346,7 @@ static void bnxt_set_db(struct bnxt *bp,
uint32_t ring_mask)
{
if (BNXT_CHIP_P5(bp)) {
- if (BNXT_PF(bp))
- db->doorbell = (char *)bp->doorbell_base + 0x10000;
- else
- db->doorbell = (char *)bp->doorbell_base + 0x4000;
+ int db_offset = DB_PF_OFFSET;
switch (ring_type) {
case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
@@ -365,6 +362,14 @@ static void bnxt_set_db(struct bnxt *bp,
db->db_key64 = DBR_PATH_L2;
break;
}
+ if (BNXT_CHIP_SR2(bp)) {
+ db->db_key64 |= DBR_VALID;
+ db_offset = bp->legacy_db_size;
+ } else if (BNXT_VF(bp)) {
+ db_offset = DB_VF_OFFSET;
+ }
+
+ db->doorbell = (char *)bp->doorbell_base + db_offset;
db->db_key64 |= (uint64_t)fid << DBR_XID_SFT;
db->db_64 = true;
} else {
@@ -383,6 +388,12 @@ static void bnxt_set_db(struct bnxt *bp,
db->db_64 = false;
}
db->db_ring_mask = ring_mask;
+
+ if (BNXT_CHIP_SR2(bp)) {
+ db->db_epoch_mask = db->db_ring_mask + 1;
+ db->db_epoch_shift = DBR_EPOCH_SFT -
+ rte_log2_u32(db->db_epoch_mask);
+ }
}
static int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index,
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v3 2/6] net/bnxt: add new RX checksum mode
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
@ 2021-01-08 5:12 ` Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
` (4 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-08 5:12 UTC (permalink / raw)
To: dev; +Cc: Kalesh AP
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
The 58818 chips support two different checksum modes.
Host driver has to register with FW which checksum mode it
prefers to use. DPDK driver want to use "cs_all_ok_mode=1".
FW advertises the support of the different checksum modes
on per VNIC basis in the HWRM_VNIC_QCAPS response.
Driver should use HWRM_VNIC_CFG to configure the needed
checksum mode.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 1 +
drivers/net/bnxt/bnxt_hwrm.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 0d3998f20..14f52b2c4 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -679,6 +679,7 @@ struct bnxt {
uint32_t vnic_cap_flags;
#define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0)
#define BNXT_VNIC_CAP_OUTER_RSS BIT(1)
+#define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2)
unsigned int rx_nr_rings;
unsigned int rx_cp_nr_rings;
unsigned int rx_num_qs_per_vnic;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 36c229de1..350fe2f97 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -860,6 +860,9 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
+ if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
+ bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
+
bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
HWRM_UNLOCK();
@@ -1961,6 +1964,11 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
+ if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
+ enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
+ req.rx_csum_v2_mode =
+ HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
+ }
goto config_mru;
}
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v3 3/6] net/bnxt: modify VNIC accounting
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
@ 2021-01-08 5:12 ` Ajit Khaparde
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
` (3 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-08 5:12 UTC (permalink / raw)
To: dev; +Cc: Kalesh AP
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Modify VNIC accounting when enabling RFS on newer chips.
Unlike legacy chips, newer chips don't need additional VNIC resources
for ntuple filter. Fix the code accordingly so that we don't reserve
and allocate additional VNICs on newer chips.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 3 +++
drivers/net/bnxt/bnxt_ethdev.c | 18 ++++++++++++++----
drivers/net/bnxt/bnxt_flow.c | 14 ++++++++++++--
drivers/net/bnxt/bnxt_hwrm.c | 32 ++++++++++++++++++++++++++++++++
drivers/net/bnxt/bnxt_hwrm.h | 5 +++--
5 files changed, 64 insertions(+), 8 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 14f52b2c4..276d807c7 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -643,6 +643,9 @@ struct bnxt {
#define BNXT_FLAG_DFLT_MAC_SET BIT(26)
#define BNXT_FLAG_TRUFLOW_EN BIT(27)
#define BNXT_FLAG_GFID_ENABLE BIT(28)
+#define BNXT_FLAG_RFS_NEEDS_VNIC BIT(29)
+#define BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2 BIT(30)
+#define BNXT_RFS_NEEDS_VNIC(bp) ((bp)->flags & BNXT_FLAG_RFS_NEEDS_VNIC)
#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
#define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 02ab87bba..8ca4fb151 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -748,11 +748,17 @@ static int bnxt_init_chip(struct bnxt *bp)
goto err_out;
}
+ /* default vnic 0 */
+ rc = bnxt_setup_one_vnic(bp, 0);
+ if (rc)
+ goto err_out;
/* VNIC configuration */
- for (i = 0; i < bp->nr_vnics; i++) {
- rc = bnxt_setup_one_vnic(bp, i);
- if (rc)
- goto err_out;
+ if (BNXT_RFS_NEEDS_VNIC(bp)) {
+ for (i = 1; i < bp->nr_vnics; i++) {
+ rc = bnxt_setup_one_vnic(bp, i);
+ if (rc)
+ goto err_out;
+ }
}
rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
@@ -4698,6 +4704,10 @@ static int bnxt_init_fw(struct bnxt *bp)
if (rc)
return rc;
+ rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
+ if (rc)
+ return rc;
+
bnxt_hwrm_port_mac_qcfg(bp);
bnxt_hwrm_parent_pf_qcfg(bp);
diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c
index 127d51c45..07d359edf 100644
--- a/drivers/net/bnxt/bnxt_flow.c
+++ b/drivers/net/bnxt/bnxt_flow.c
@@ -1056,6 +1056,13 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev,
}
PMD_DRV_LOG(DEBUG, "Queue index %d\n", act_q->index);
+ if (use_ntuple && !BNXT_RFS_NEEDS_VNIC(bp)) {
+ filter->flags =
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX;
+ filter->dst_id = act_q->index;
+ goto skip_vnic_alloc;
+ }
+
vnic_id = attr->group;
if (!vnic_id) {
PMD_DRV_LOG(DEBUG, "Group id is 0\n");
@@ -1127,7 +1134,7 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev,
PMD_DRV_LOG(DEBUG,
"Setting vnic ff_idx %d\n", vnic->ff_pool_idx);
filter->dst_id = vnic->fw_vnic_id;
-
+skip_vnic_alloc:
/* For ntuple filter, create the L2 filter with default VNIC.
* The user specified redirect queue will be set while creating
* the ntuple filter in hardware.
@@ -1808,7 +1815,10 @@ bnxt_flow_create(struct rte_eth_dev *dev,
}
}
- vnic = find_matching_vnic(bp, filter);
+ if (BNXT_RFS_NEEDS_VNIC(bp))
+ vnic = find_matching_vnic(bp, filter);
+ else
+ vnic = BNXT_GET_DEFAULT_VNIC(bp);
done:
if (!ret || update_flow) {
flow->filter = filter;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 350fe2f97..56e2e33a9 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -5834,3 +5834,35 @@ int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
rep_bp->vf_id);
return rc;
}
+
+int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
+{
+ struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
+ bp->hwrm_cmd_resp_addr;
+ struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
+ uint32_t flags = 0;
+ int rc = 0;
+
+ if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
+ return 0;
+
+ if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
+ PMD_DRV_LOG(DEBUG,
+ "Not a PF or trusted VF. Command not supported\n");
+ return 0;
+ }
+
+ HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+
+ HWRM_CHECK_RESULT();
+ flags = rte_le_to_cpu_32(resp->flags);
+ HWRM_UNLOCK();
+
+ if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
+ bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
+ else
+ bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
+
+ return rc;
+}
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index 4b3290773..7deea29ca 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -55,8 +55,8 @@ struct hwrm_func_qstats_output;
#define HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK \
HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK
-#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN \
-HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED
+#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED \
+ HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED
#define HWRM_SPEC_CODE_1_8_4 0x10804
#define HWRM_SPEC_CODE_1_9_0 0x10900
@@ -300,4 +300,5 @@ int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
uint16_t *first_vf_id);
int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep);
int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep);
+int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp);
#endif
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v3 4/6] net/bnxt: add LRO support for SR2 chip
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
` (2 preceding siblings ...)
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
@ 2021-01-08 5:12 ` Ajit Khaparde
2021-01-08 5:13 ` [dpdk-dev] [PATCH v3 5/6] net/bnxt: modify context memory allocation Ajit Khaparde
` (2 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-08 5:12 UTC (permalink / raw)
To: dev; +Cc: Kalesh AP
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Add the new chip specific TPA v2 logic to bnxt_tpa_start() to fully support
TPA on the new chip.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_rxr.c | 72 +++++++++++++++++++++++++++++++------
drivers/net/bnxt/bnxt_rxr.h | 12 ++++++-
2 files changed, 72 insertions(+), 12 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index 14901f1b9..af3f9b936 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -134,6 +134,53 @@ struct rte_mbuf *bnxt_consume_rx_buf(struct bnxt_rx_ring_info *rxr,
return mbuf;
}
+static void bnxt_tpa_get_metadata(struct bnxt *bp,
+ struct bnxt_tpa_info *tpa_info,
+ struct rx_tpa_start_cmpl *tpa_start,
+ struct rx_tpa_start_cmpl_hi *tpa_start1)
+{
+ tpa_info->cfa_code_valid = 0;
+ tpa_info->vlan_valid = 0;
+ tpa_info->hash_valid = 0;
+ tpa_info->l4_csum_valid = 0;
+
+ if (likely(tpa_start->flags_type &
+ rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
+ tpa_info->hash_valid = 1;
+ tpa_info->rss_hash = rte_le_to_cpu_32(tpa_start->rss_hash);
+ }
+
+ if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
+ struct rx_tpa_start_v2_cmpl *v2_tpa_start = (void *)tpa_start;
+ struct rx_tpa_start_v2_cmpl_hi *v2_tpa_start1 =
+ (void *)tpa_start1;
+
+ if (v2_tpa_start->agg_id &
+ RX_TPA_START_V2_CMPL_METADATA1_VALID) {
+ tpa_info->vlan_valid = 1;
+ tpa_info->vlan =
+ rte_le_to_cpu_16(v2_tpa_start1->metadata0);
+ }
+
+ if (v2_tpa_start1->flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK)
+ tpa_info->l4_csum_valid = 1;
+
+ return;
+ }
+
+ tpa_info->cfa_code_valid = 1;
+ tpa_info->cfa_code = rte_le_to_cpu_16(tpa_start1->cfa_code);
+ if (tpa_start1->flags2 &
+ rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
+ tpa_info->vlan_valid = 1;
+ tpa_info->vlan = rte_le_to_cpu_32(tpa_start1->metadata);
+ }
+
+ if (likely(tpa_start1->flags2 &
+ rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
+ tpa_info->l4_csum_valid = 1;
+}
+
static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
struct rx_tpa_start_cmpl *tpa_start,
struct rx_tpa_start_cmpl_hi *tpa_start1)
@@ -164,21 +211,23 @@ static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
mbuf->data_len = mbuf->pkt_len;
mbuf->port = rxq->port_id;
mbuf->ol_flags = PKT_RX_LRO;
- if (likely(tpa_start->flags_type &
- rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
- mbuf->hash.rss = rte_le_to_cpu_32(tpa_start->rss_hash);
+
+ bnxt_tpa_get_metadata(rxq->bp, tpa_info, tpa_start, tpa_start1);
+
+ if (likely(tpa_info->hash_valid)) {
+ mbuf->hash.rss = tpa_info->rss_hash;
mbuf->ol_flags |= PKT_RX_RSS_HASH;
- } else {
- mbuf->hash.fdir.id = rte_le_to_cpu_16(tpa_start1->cfa_code);
+ } else if (tpa_info->cfa_code_valid) {
+ mbuf->hash.fdir.id = tpa_info->cfa_code;
mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
}
- if (tpa_start1->flags2 &
- rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
- mbuf->vlan_tci = rte_le_to_cpu_32(tpa_start1->metadata);
+
+ if (tpa_info->vlan_valid) {
+ mbuf->vlan_tci = tpa_info->vlan;
mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
}
- if (likely(tpa_start1->flags2 &
- rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
+
+ if (likely(tpa_info->l4_csum_valid))
mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
/* recycle next mbuf */
@@ -751,7 +800,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
cpr->cp_ring_struct->ring_mask,
cpr->valid);
- if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START) {
+ if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START ||
+ cmp_type == RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2) {
bnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp,
(struct rx_tpa_start_cmpl_hi *)rxcmp1);
rc = -EINVAL; /* Continue w/o new mbuf */
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index b2942030a..78814edbb 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -50,6 +50,14 @@ struct bnxt_tpa_info {
uint16_t len;
uint32_t agg_count;
struct rx_tpa_v2_abuf_cmpl agg_arr[TPA_MAX_NUM_SEGS];
+
+ uint32_t rss_hash;
+ uint32_t vlan;
+ uint16_t cfa_code;
+ uint8_t hash_valid:1;
+ uint8_t vlan_valid:1;
+ uint8_t cfa_code_valid:1;
+ uint8_t l4_csum_valid:1;
};
struct bnxt_rx_ring_info {
@@ -122,4 +130,6 @@ bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)
#define BNXT_PTYPE_TBL_DIM 128
extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM];
-#endif
+
+#define RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK (0x1 << 14)
+#endif /* _BNXT_RXR_H_ */
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v3 5/6] net/bnxt: modify context memory allocation
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
` (3 preceding siblings ...)
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
@ 2021-01-08 5:13 ` Ajit Khaparde
2021-01-08 5:13 ` [dpdk-dev] [PATCH v3 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-08 5:13 UTC (permalink / raw)
To: dev; +Cc: Kalesh AP
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Newer devices like SR2 may have chip backing store and do not require
host backed memory allocation.
In these cases, HWRM_FUNC_BACKING_STORE_QCAPS will return a zero entry
size to indicate contexts for which the host should not allocate backing
store.
Selectively allocate context memory based on device capabilities and
only enable backing store for the appropriate contexts
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 60 ++++++++++++++++++++--------------
drivers/net/bnxt/bnxt_hwrm.c | 3 ++
2 files changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 8ca4fb151..e11751cc1 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -4212,39 +4212,49 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)
ctx_pg = &ctx->qp_mem;
ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
- mem_size = ctx->qp_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
- if (rc)
- return rc;
+ if (ctx->qp_entry_size) {
+ mem_size = ctx->qp_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
+ if (rc)
+ return rc;
+ }
ctx_pg = &ctx->srq_mem;
ctx_pg->entries = ctx->srq_max_l2_entries;
- mem_size = ctx->srq_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
- if (rc)
- return rc;
+ if (ctx->srq_entry_size) {
+ mem_size = ctx->srq_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
+ if (rc)
+ return rc;
+ }
ctx_pg = &ctx->cq_mem;
ctx_pg->entries = ctx->cq_max_l2_entries;
- mem_size = ctx->cq_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
- if (rc)
- return rc;
+ if (ctx->cq_entry_size) {
+ mem_size = ctx->cq_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
+ if (rc)
+ return rc;
+ }
ctx_pg = &ctx->vnic_mem;
ctx_pg->entries = ctx->vnic_max_vnic_entries +
ctx->vnic_max_ring_table_entries;
- mem_size = ctx->vnic_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
- if (rc)
- return rc;
+ if (ctx->vnic_entry_size) {
+ mem_size = ctx->vnic_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
+ if (rc)
+ return rc;
+ }
ctx_pg = &ctx->stat_mem;
ctx_pg->entries = ctx->stat_max_entries;
- mem_size = ctx->stat_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
- if (rc)
- return rc;
+ if (ctx->stat_entry_size) {
+ mem_size = ctx->stat_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
+ if (rc)
+ return rc;
+ }
min = ctx->tqm_min_entries_per_ring;
@@ -4260,10 +4270,12 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)
for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
ctx_pg = ctx->tqm_mem[i];
ctx_pg->entries = i ? entries : entries_sp;
- mem_size = ctx->tqm_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
- if (rc)
- return rc;
+ if (ctx->tqm_entry_size) {
+ mem_size = ctx->tqm_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
+ if (rc)
+ return rc;
+ }
ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
}
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 56e2e33a9..6d54b1656 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -64,6 +64,9 @@ static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
uint8_t *pg_attr,
uint64_t *pg_dir)
{
+ if (rmem->nr_pages == 0)
+ return;
+
if (rmem->nr_pages > 1) {
*pg_attr = 1;
*pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v3 6/6] net/bnxt: add Rx logic for 58818 chips
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
` (4 preceding siblings ...)
2021-01-08 5:13 ` [dpdk-dev] [PATCH v3 5/6] net/bnxt: modify context memory allocation Ajit Khaparde
@ 2021-01-08 5:13 ` Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-08 5:13 UTC (permalink / raw)
To: dev; +Cc: Kalesh AP
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
1. On the new 58818 chips, the RX completion is largely the same except
for the new completion opcode and the stripped VLAN format and checksum
status. Added bnxt_parse_csum_v2(), bnxt_parse_pkt_type_v2() and
bnxt_rx_vlan_v2() to support the new RX completion logic.
2. Disable vector mode RX/TX for 58818 chips for now.
3. The cfa_code format on 58818 chips is different than legacy chips.
So skip cfa_code parsing logic on 58818 chips for now.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 15 ++-
drivers/net/bnxt/bnxt_rxr.c | 24 +++--
drivers/net/bnxt/bnxt_rxr.h | 191 +++++++++++++++++++++++++++++++++
3 files changed, 221 insertions(+), 9 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index e11751cc1..ef6b611be 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -1159,6 +1159,12 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = eth_dev->data->dev_private;
+ /* Disable vector mode RX for Stingray2 for now */
+ if (BNXT_CHIP_SR2(bp)) {
+ bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
+ return bnxt_recv_pkts;
+ }
+
#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
#ifndef RTE_LIBRTE_IEEE1588
/*
@@ -1199,12 +1205,17 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev)
}
static eth_tx_burst_t
-bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
+bnxt_transmit_function(struct rte_eth_dev *eth_dev)
{
+ struct bnxt *bp = eth_dev->data->dev_private;
+
+ /* Disable vector mode TX for Stingray2 for now */
+ if (BNXT_CHIP_SR2(bp))
+ return bnxt_xmit_pkts;
+
#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
#ifndef RTE_LIBRTE_IEEE1588
uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
- struct bnxt *bp = eth_dev->data->dev_private;
/*
* Vector mode transmit can be enabled only if not using scatter rx
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index af3f9b936..a195bf118 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -814,7 +814,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
return -EBUSY;
*rx_pkt = mbuf;
goto next_rx;
- } else if (cmp_type != 0x11) {
+ } else if ((cmp_type != CMPL_BASE_TYPE_RX_L2) &&
+ (cmp_type != CMPL_BASE_TYPE_RX_L2_V2)) {
rc = -EINVAL;
goto next_rx;
}
@@ -838,8 +839,6 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
mbuf->data_len = mbuf->pkt_len;
mbuf->port = rxq->port_id;
- bnxt_set_ol_flags(rxr, rxcmp, rxcmp1, mbuf);
-
#ifdef RTE_LIBRTE_IEEE1588
if (unlikely((rte_le_to_cpu_16(rxcmp->flags_type) &
RX_PKT_CMPL_FLAGS_MASK) ==
@@ -849,17 +848,28 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
}
#endif
+ if (cmp_type == CMPL_BASE_TYPE_RX_L2_V2) {
+ bnxt_parse_csum_v2(mbuf, rxcmp1);
+ bnxt_parse_pkt_type_v2(mbuf, rxcmp, rxcmp1);
+ bnxt_rx_vlan_v2(mbuf, rxcmp, rxcmp1);
+ /* TODO Add support for cfa_code parsing */
+ goto reuse_rx_mbuf;
+ }
+
+ bnxt_set_ol_flags(rxr, rxcmp, rxcmp1, mbuf);
+
+ mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
+
if (BNXT_TRUFLOW_EN(bp))
mark_id = bnxt_ulp_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf,
&vfr_flag);
else
bnxt_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf);
+reuse_rx_mbuf:
if (agg_buf)
bnxt_rx_pages(rxq, mbuf, &tmp_raw_cons, agg_buf, NULL);
- mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
-
#ifdef BNXT_DEBUG
if (rxcmp1->errors_v2 & RX_CMP_L2_ERRORS) {
/* Re-install the mbuf back to the rx ring */
@@ -972,8 +982,8 @@ uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
cpr->cp_ring_struct->ring_mask,
cpr->valid);
- /* TODO: Avoid magic numbers... */
- if ((CMP_TYPE(rxcmp) & 0x30) == 0x10) {
+ if ((CMP_TYPE(rxcmp) >= CMPL_BASE_TYPE_RX_TPA_START_V2) &&
+ (CMP_TYPE(rxcmp) <= RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG)) {
rc = bnxt_rx_pkt(&rx_pkts[nb_rx_pkts], rxq, &raw_cons);
if (!rc)
nb_rx_pkts++;
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index 78814edbb..9cc5197a7 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -131,5 +131,196 @@ bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)
#define BNXT_PTYPE_TBL_DIM 128
extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM];
+/* Stingray2 specific code for RX completion parsing */
+#define RX_CMP_VLAN_VALID(rxcmp) \
+ (((struct rx_pkt_v2_cmpl *)rxcmp)->metadata1_payload_offset & \
+ RX_PKT_V2_CMPL_METADATA1_VALID)
+
+#define RX_CMP_METADATA0_VID(rxcmp1) \
+ ((((struct rx_pkt_v2_cmpl_hi *)rxcmp1)->metadata0) & \
+ (RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK | \
+ RX_PKT_V2_CMPL_HI_METADATA0_DE | \
+ RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK))
+
+static inline void bnxt_rx_vlan_v2(struct rte_mbuf *mbuf,
+ struct rx_pkt_cmpl *rxcmp,
+ struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ if (RX_CMP_VLAN_VALID(rxcmp)) {
+ mbuf->vlan_tci = RX_CMP_METADATA0_VID(rxcmp1);
+ mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
+ }
+}
+
+#define RX_CMP_FLAGS2_CS_ALL_OK_MODE_MASK (0x1 << 3)
+#define RX_CMP_FLAGS2_CS_OK_HDR_CNT_MASK (0x7 << 10)
+#define RX_CMP_FLAGS2_IP_CSUM_ALL_OK_MASK (0x1 << 13)
#define RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK (0x1 << 14)
+
+#define RX_CMP_V2_CS_OK_HDR_CNT(flags) \
+ (((flags) & RX_CMP_FLAGS2_CS_OK_HDR_CNT_MASK) >> \
+ RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT)
+
+#define RX_CMP_V2_CS_ALL_OK_MODE(flags) \
+ (((flags) & RX_CMP_FLAGS2_CS_ALL_OK_MODE_MASK))
+
+#define RX_CMP_FLAGS2_L3_CS_OK_MASK (0x7 << 10)
+#define RX_CMP_FLAGS2_L4_CS_OK_MASK (0x38 << 10)
+#define RX_CMP_FLAGS2_L3_CS_OK_SFT 10
+#define RX_CMP_FLAGS2_L4_CS_OK_SFT 13
+
+#define RX_CMP_V2_L4_CS_OK(flags2) \
+ (((flags2) & RX_CMP_FLAGS2_L4_CS_OK_MASK) >> \
+ RX_CMP_FLAGS2_L4_CS_OK_SFT)
+
+#define RX_CMP_V2_L3_CS_OK(flags2) \
+ (((flags2) & RX_CMP_FLAGS2_L3_CS_OK_MASK) >> \
+ RX_CMP_FLAGS2_L3_CS_OK_SFT)
+
+#define RX_CMP_V2_L4_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR)
+
+#define RX_CMP_V2_L3_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR)
+
+#define RX_CMP_V2_T_IP_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR)
+
+#define RX_CMP_V2_T_L4_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR)
+
+#define RX_CMP_V2_OT_L4_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR)
+
+static inline void bnxt_parse_csum_v2(struct rte_mbuf *mbuf,
+ struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ struct rx_pkt_v2_cmpl_hi *v2_cmp =
+ (struct rx_pkt_v2_cmpl_hi *)(rxcmp1);
+ uint16_t error_v2 = rte_le_to_cpu_16(v2_cmp->errors_v2);
+ uint32_t flags2 = rte_le_to_cpu_32(v2_cmp->flags2);
+ uint32_t hdr_cnt = 0, t_pkt = 0;
+
+ if (RX_CMP_V2_CS_ALL_OK_MODE(flags2)) {
+ hdr_cnt = RX_CMP_V2_CS_OK_HDR_CNT(flags2);
+ if (hdr_cnt > 1)
+ t_pkt = 1;
+
+ if (unlikely(RX_CMP_V2_L4_CS_ERR(error_v2)))
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
+ else if (flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK)
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
+ else
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
+
+ if (unlikely(RX_CMP_V2_L3_CS_ERR(error_v2)))
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
+ else if (flags2 & RX_CMP_FLAGS2_IP_CSUM_ALL_OK_MASK)
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
+ else
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
+ } else {
+ hdr_cnt = RX_CMP_V2_L4_CS_OK(flags2);
+ if (hdr_cnt > 1)
+ t_pkt = 1;
+
+ if (RX_CMP_V2_L4_CS_OK(flags2))
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
+ else if (RX_CMP_V2_L4_CS_ERR(error_v2))
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
+ else
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
+
+ if (RX_CMP_V2_L3_CS_OK(flags2))
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
+ else if (RX_CMP_V2_L3_CS_ERR(error_v2))
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
+ else
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
+ }
+
+ if (t_pkt) {
+ if (unlikely(RX_CMP_V2_OT_L4_CS_ERR(error_v2) ||
+ RX_CMP_V2_T_L4_CS_ERR(error_v2)))
+ mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
+ else
+ mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
+
+ if (unlikely(RX_CMP_V2_T_IP_CS_ERR(error_v2)))
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
+ }
+}
+
+static inline void
+bnxt_parse_pkt_type_v2(struct rte_mbuf *mbuf,
+ struct rx_pkt_cmpl *rxcmp,
+ struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ struct rx_pkt_v2_cmpl *v2_cmp =
+ (struct rx_pkt_v2_cmpl *)(rxcmp);
+ struct rx_pkt_v2_cmpl_hi *v2_cmp1 =
+ (struct rx_pkt_v2_cmpl_hi *)(rxcmp1);
+ uint16_t flags_type = v2_cmp->flags_type &
+ rte_cpu_to_le_32(RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK);
+ uint32_t flags2 = rte_le_to_cpu_32(v2_cmp1->flags2);
+ uint32_t l3, pkt_type = 0, vlan = 0;
+ uint32_t ip6 = 0, t_pkt = 0;
+ uint32_t hdr_cnt, csum_count;
+
+ if (RX_CMP_V2_CS_ALL_OK_MODE(flags2)) {
+ hdr_cnt = RX_CMP_V2_CS_OK_HDR_CNT(flags2);
+ if (hdr_cnt > 1)
+ t_pkt = 1;
+ } else {
+ csum_count = RX_CMP_V2_L4_CS_OK(flags2);
+ if (csum_count > 1)
+ t_pkt = 1;
+ }
+
+ vlan = !!RX_CMP_VLAN_VALID(rxcmp);
+ pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
+
+ ip6 = !!(flags2 & RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE);
+
+ if (!t_pkt && !ip6)
+ l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
+ else if (!t_pkt && ip6)
+ l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
+ else if (t_pkt && !ip6)
+ l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
+ else
+ l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
+
+ switch (flags_type) {
+ case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP):
+ if (!t_pkt)
+ pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
+ break;
+ case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP):
+ if (!t_pkt)
+ pkt_type |= l3 | RTE_PTYPE_L4_TCP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
+ break;
+ case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP):
+ if (!t_pkt)
+ pkt_type |= l3 | RTE_PTYPE_L4_UDP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
+ break;
+ case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_IP):
+ pkt_type |= l3;
+ break;
+ }
+
+ mbuf->packet_type = pkt_type;
+}
+
#endif /* _BNXT_RXR_H_ */
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2
2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
` (5 preceding siblings ...)
2021-01-08 5:13 ` [dpdk-dev] [PATCH v3 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
@ 2021-01-11 17:43 ` Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
` (6 more replies)
6 siblings, 7 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-11 17:43 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
Add support for 58818/Stingray2 chip.
The new chip Stingray 2 belongs to the P5 generation.
Some changes in the PMD are required to support this new chip.
This patchset adds the necessary changes.
Please apply.
v1->v2: rebased to latest dpdk-next-net-brcm tree.
v2->v3: rebased to latest code base.
v3->v4: rebase to latest dpdk-next-net code.
Kalesh AP (6):
net/bnxt: add support for 58818 chip family
net/bnxt: add new RX checksum mode
net/bnxt: modify VNIC accounting
net/bnxt: add LRO support for SR2 chip
net/bnxt: modify context memory allocation
net/bnxt: add Rx logic for 58818 chips
doc/guides/rel_notes/release_21_02.rst | 6 +
drivers/net/bnxt/bnxt.h | 19 +++
drivers/net/bnxt/bnxt_cpr.h | 7 +-
drivers/net/bnxt/bnxt_ethdev.c | 102 +++++++++----
drivers/net/bnxt/bnxt_flow.c | 14 +-
drivers/net/bnxt/bnxt_hwrm.c | 49 ++++++
drivers/net/bnxt/bnxt_hwrm.h | 5 +-
drivers/net/bnxt/bnxt_ring.c | 19 ++-
drivers/net/bnxt/bnxt_rxr.c | 96 +++++++++---
drivers/net/bnxt/bnxt_rxr.h | 203 ++++++++++++++++++++++++-
10 files changed, 462 insertions(+), 58 deletions(-)
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v4 1/6] net/bnxt: add support for 58818 chip family
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
@ 2021-01-11 17:43 ` Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
` (5 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-11 17:43 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Kalesh AP
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
The new chip (Stingray 2) is part of the P5 chip family with a number
of changes:
1. Implement the epoch doorbell bit for 58818 chip. With the new doorbell
infrastructure and the unbounded index logic, now set the epoch
doorbell bit to support proper doorbell operation on the new chip.
Toggle epoch bit of all rings when it's wrapped to support doorbell
overflow checking.
2. Get the legacy doorbell size from firmware. Legacy doorbell support has
been removed in Stingray 2. So, the fast path doorbell pages start from
the base of the BAR. Drivers need to use legacy_l2_db_space_size_kb
field in the hwrm_func_qcfg_output response to get the legacy doorbell
page offset from the BAR.
3. Set VALID doorbell bit on 58818 chip family. This class of chip has
a valid doorbell bit added and it needs to be set.
4. Use "chip_num" returned by firmware. The "chip_num" field in the
HWRM_VER_GET output returns the chip number. Use this value to identify
chip category for 58818 chip family.
5. Added device ids for Stingray2 PF/VF devices.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
doc/guides/rel_notes/release_21_02.rst | 6 ++++++
drivers/net/bnxt/bnxt.h | 15 +++++++++++++++
drivers/net/bnxt/bnxt_cpr.h | 7 ++++++-
drivers/net/bnxt/bnxt_ethdev.c | 9 +++++++++
drivers/net/bnxt/bnxt_hwrm.c | 6 ++++++
drivers/net/bnxt/bnxt_ring.c | 19 +++++++++++++++----
6 files changed, 57 insertions(+), 5 deletions(-)
diff --git a/doc/guides/rel_notes/release_21_02.rst b/doc/guides/rel_notes/release_21_02.rst
index 706cbf8f0..b1bb2d867 100644
--- a/doc/guides/rel_notes/release_21_02.rst
+++ b/doc/guides/rel_notes/release_21_02.rst
@@ -55,6 +55,12 @@ New Features
Also, make sure to start the actual text at the margin.
=======================================================
+* **Updated Broadcom bnxt driver.**
+
+ Updated the Broadcom bnxt driver with fixes and improvements, including:
+
+ * Added support for Stingray2 device.
+
Removed Items
-------------
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 8374e9fad..0d3998f20 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -66,6 +66,10 @@
#define BROADCOM_DEV_ID_58804 0xd804
#define BROADCOM_DEV_ID_58808 0x16f0
#define BROADCOM_DEV_ID_58802_VF 0xd800
+#define BROADCOM_DEV_ID_58812 0xd812
+#define BROADCOM_DEV_ID_58814 0xd814
+#define BROADCOM_DEV_ID_58818 0xd818
+#define BROADCOM_DEV_ID_58818_VF 0xd82e
#define BROADCOM_DEV_957508_N2100 0x5208
#define IS_BNXT_DEV_957508_N2100(bp) \
@@ -367,14 +371,20 @@ struct bnxt_coal {
};
/* 64-bit doorbell */
+#define DBR_EPOCH_MASK 0x01000000UL
+#define DBR_EPOCH_SFT 24
#define DBR_XID_SFT 32
#define DBR_PATH_L2 (0x1ULL << 56)
+#define DBR_VALID (0x1ULL << 58)
#define DBR_TYPE_SQ (0x0ULL << 60)
#define DBR_TYPE_SRQ (0x2ULL << 60)
#define DBR_TYPE_CQ (0x4ULL << 60)
#define DBR_TYPE_NQ (0xaULL << 60)
#define DBR_TYPE_NQ_ARM (0xbULL << 60)
+#define DB_PF_OFFSET 0x10000
+#define DB_VF_OFFSET 0x4000
+
#define BNXT_RSS_TBL_SIZE_P5 512U
#define BNXT_RSS_ENTRIES_PER_CTX_P5 64
#define BNXT_MAX_RSS_CTXTS_P5 \
@@ -601,6 +611,7 @@ struct bnxt {
struct rte_eth_dev *eth_dev;
struct rte_pci_device *pdev;
void *doorbell_base;
+ int legacy_db_size;
uint32_t flags;
#define BNXT_FLAG_REGISTERED BIT(0)
@@ -649,6 +660,10 @@ struct bnxt {
#define BNXT_TRUFLOW_EN(bp) ((bp)->flags & BNXT_FLAG_TRUFLOW_EN)
#define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
+ uint16_t chip_num;
+#define CHIP_NUM_58818 0xd818
+#define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818)
+
uint32_t fw_cap;
#define BNXT_FW_CAP_HOT_RESET BIT(0)
#define BNXT_FW_CAP_IF_CHANGE BIT(1)
diff --git a/drivers/net/bnxt/bnxt_cpr.h b/drivers/net/bnxt/bnxt_cpr.h
index a763f6006..30635fcc1 100644
--- a/drivers/net/bnxt/bnxt_cpr.h
+++ b/drivers/net/bnxt/bnxt_cpr.h
@@ -81,9 +81,14 @@ struct bnxt_db_info {
};
bool db_64;
uint32_t db_ring_mask;
+ uint32_t db_epoch_mask;
+ uint32_t db_epoch_shift;
};
-#define DB_RING_IDX(db, idx) ((idx) & (db)->db_ring_mask)
+#define DB_EPOCH(db, idx) (((idx) & (db)->db_epoch_mask) << \
+ ((db)->db_epoch_shift))
+#define DB_RING_IDX(db, idx) (((idx) & (db)->db_ring_mask) | \
+ DB_EPOCH(db, idx))
struct bnxt_ring;
struct bnxt_cp_ring_info {
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 0788d263d..02ab87bba 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -80,6 +80,10 @@ static const struct rte_pci_id bnxt_pci_id_map[] = {
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
{ .vendor_id = 0, /* sentinel */ },
};
@@ -3979,6 +3983,7 @@ static bool bnxt_vf_pciid(uint16_t device_id)
case BROADCOM_DEV_ID_58802_VF:
case BROADCOM_DEV_ID_57500_VF1:
case BROADCOM_DEV_ID_57500_VF2:
+ case BROADCOM_DEV_ID_58818_VF:
/* FALLTHROUGH */
return true;
default:
@@ -4001,6 +4006,10 @@ static bool bnxt_p5_device(uint16_t device_id)
case BROADCOM_DEV_ID_57502_MF2:
case BROADCOM_DEV_ID_57500_VF1:
case BROADCOM_DEV_ID_57500_VF2:
+ case BROADCOM_DEV_ID_58812:
+ case BROADCOM_DEV_ID_58814:
+ case BROADCOM_DEV_ID_58818:
+ case BROADCOM_DEV_ID_58818_VF:
/* FALLTHROUGH */
return true;
default:
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 73647fba8..36c229de1 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1129,6 +1129,9 @@ int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
PMD_DRV_LOG(ERR, "Unsupported request length\n");
rc = -EINVAL;
}
+
+ bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
+
bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
@@ -3207,6 +3210,9 @@ int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
break;
}
+ bp->legacy_db_size =
+ rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
+
HWRM_UNLOCK();
return rc;
diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c
index adddf9bc4..75b541bdc 100644
--- a/drivers/net/bnxt/bnxt_ring.c
+++ b/drivers/net/bnxt/bnxt_ring.c
@@ -346,10 +346,7 @@ static void bnxt_set_db(struct bnxt *bp,
uint32_t ring_mask)
{
if (BNXT_CHIP_P5(bp)) {
- if (BNXT_PF(bp))
- db->doorbell = (char *)bp->doorbell_base + 0x10000;
- else
- db->doorbell = (char *)bp->doorbell_base + 0x4000;
+ int db_offset = DB_PF_OFFSET;
switch (ring_type) {
case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
@@ -365,6 +362,14 @@ static void bnxt_set_db(struct bnxt *bp,
db->db_key64 = DBR_PATH_L2;
break;
}
+ if (BNXT_CHIP_SR2(bp)) {
+ db->db_key64 |= DBR_VALID;
+ db_offset = bp->legacy_db_size;
+ } else if (BNXT_VF(bp)) {
+ db_offset = DB_VF_OFFSET;
+ }
+
+ db->doorbell = (char *)bp->doorbell_base + db_offset;
db->db_key64 |= (uint64_t)fid << DBR_XID_SFT;
db->db_64 = true;
} else {
@@ -383,6 +388,12 @@ static void bnxt_set_db(struct bnxt *bp,
db->db_64 = false;
}
db->db_ring_mask = ring_mask;
+
+ if (BNXT_CHIP_SR2(bp)) {
+ db->db_epoch_mask = db->db_ring_mask + 1;
+ db->db_epoch_shift = DBR_EPOCH_SFT -
+ rte_log2_u32(db->db_epoch_mask);
+ }
}
static int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index,
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v4 2/6] net/bnxt: add new RX checksum mode
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
@ 2021-01-11 17:43 ` Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
` (4 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-11 17:43 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Kalesh AP
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
The 58818 chips support two different checksum modes.
Host driver has to register with FW which checksum mode it
prefers to use. DPDK driver want to use "cs_all_ok_mode=1".
FW advertises the support of the different checksum modes
on per VNIC basis in the HWRM_VNIC_QCAPS response.
Driver should use HWRM_VNIC_CFG to configure the needed
checksum mode.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 1 +
drivers/net/bnxt/bnxt_hwrm.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 0d3998f20..14f52b2c4 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -679,6 +679,7 @@ struct bnxt {
uint32_t vnic_cap_flags;
#define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0)
#define BNXT_VNIC_CAP_OUTER_RSS BIT(1)
+#define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2)
unsigned int rx_nr_rings;
unsigned int rx_cp_nr_rings;
unsigned int rx_num_qs_per_vnic;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 36c229de1..350fe2f97 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -860,6 +860,9 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
+ if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
+ bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
+
bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
HWRM_UNLOCK();
@@ -1961,6 +1964,11 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
+ if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
+ enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
+ req.rx_csum_v2_mode =
+ HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
+ }
goto config_mru;
}
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v4 3/6] net/bnxt: modify VNIC accounting
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
@ 2021-01-11 17:43 ` Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
` (3 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-11 17:43 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Kalesh AP
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Modify VNIC accounting when enabling RFS on newer chips.
Unlike legacy chips, newer chips don't need additional VNIC resources
for ntuple filter. Fix the code accordingly so that we don't reserve
and allocate additional VNICs on newer chips.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 3 +++
drivers/net/bnxt/bnxt_ethdev.c | 18 ++++++++++++++----
drivers/net/bnxt/bnxt_flow.c | 14 ++++++++++++--
drivers/net/bnxt/bnxt_hwrm.c | 32 ++++++++++++++++++++++++++++++++
drivers/net/bnxt/bnxt_hwrm.h | 5 +++--
5 files changed, 64 insertions(+), 8 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 14f52b2c4..276d807c7 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -643,6 +643,9 @@ struct bnxt {
#define BNXT_FLAG_DFLT_MAC_SET BIT(26)
#define BNXT_FLAG_TRUFLOW_EN BIT(27)
#define BNXT_FLAG_GFID_ENABLE BIT(28)
+#define BNXT_FLAG_RFS_NEEDS_VNIC BIT(29)
+#define BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2 BIT(30)
+#define BNXT_RFS_NEEDS_VNIC(bp) ((bp)->flags & BNXT_FLAG_RFS_NEEDS_VNIC)
#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
#define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 02ab87bba..8ca4fb151 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -748,11 +748,17 @@ static int bnxt_init_chip(struct bnxt *bp)
goto err_out;
}
+ /* default vnic 0 */
+ rc = bnxt_setup_one_vnic(bp, 0);
+ if (rc)
+ goto err_out;
/* VNIC configuration */
- for (i = 0; i < bp->nr_vnics; i++) {
- rc = bnxt_setup_one_vnic(bp, i);
- if (rc)
- goto err_out;
+ if (BNXT_RFS_NEEDS_VNIC(bp)) {
+ for (i = 1; i < bp->nr_vnics; i++) {
+ rc = bnxt_setup_one_vnic(bp, i);
+ if (rc)
+ goto err_out;
+ }
}
rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
@@ -4698,6 +4704,10 @@ static int bnxt_init_fw(struct bnxt *bp)
if (rc)
return rc;
+ rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
+ if (rc)
+ return rc;
+
bnxt_hwrm_port_mac_qcfg(bp);
bnxt_hwrm_parent_pf_qcfg(bp);
diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c
index 127d51c45..07d359edf 100644
--- a/drivers/net/bnxt/bnxt_flow.c
+++ b/drivers/net/bnxt/bnxt_flow.c
@@ -1056,6 +1056,13 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev,
}
PMD_DRV_LOG(DEBUG, "Queue index %d\n", act_q->index);
+ if (use_ntuple && !BNXT_RFS_NEEDS_VNIC(bp)) {
+ filter->flags =
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX;
+ filter->dst_id = act_q->index;
+ goto skip_vnic_alloc;
+ }
+
vnic_id = attr->group;
if (!vnic_id) {
PMD_DRV_LOG(DEBUG, "Group id is 0\n");
@@ -1127,7 +1134,7 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev,
PMD_DRV_LOG(DEBUG,
"Setting vnic ff_idx %d\n", vnic->ff_pool_idx);
filter->dst_id = vnic->fw_vnic_id;
-
+skip_vnic_alloc:
/* For ntuple filter, create the L2 filter with default VNIC.
* The user specified redirect queue will be set while creating
* the ntuple filter in hardware.
@@ -1808,7 +1815,10 @@ bnxt_flow_create(struct rte_eth_dev *dev,
}
}
- vnic = find_matching_vnic(bp, filter);
+ if (BNXT_RFS_NEEDS_VNIC(bp))
+ vnic = find_matching_vnic(bp, filter);
+ else
+ vnic = BNXT_GET_DEFAULT_VNIC(bp);
done:
if (!ret || update_flow) {
flow->filter = filter;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 350fe2f97..56e2e33a9 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -5834,3 +5834,35 @@ int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
rep_bp->vf_id);
return rc;
}
+
+int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
+{
+ struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
+ bp->hwrm_cmd_resp_addr;
+ struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
+ uint32_t flags = 0;
+ int rc = 0;
+
+ if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
+ return 0;
+
+ if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
+ PMD_DRV_LOG(DEBUG,
+ "Not a PF or trusted VF. Command not supported\n");
+ return 0;
+ }
+
+ HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+
+ HWRM_CHECK_RESULT();
+ flags = rte_le_to_cpu_32(resp->flags);
+ HWRM_UNLOCK();
+
+ if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
+ bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
+ else
+ bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
+
+ return rc;
+}
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index 4b3290773..7deea29ca 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -55,8 +55,8 @@ struct hwrm_func_qstats_output;
#define HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK \
HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK
-#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN \
-HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED
+#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED \
+ HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED
#define HWRM_SPEC_CODE_1_8_4 0x10804
#define HWRM_SPEC_CODE_1_9_0 0x10900
@@ -300,4 +300,5 @@ int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
uint16_t *first_vf_id);
int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep);
int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep);
+int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp);
#endif
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v4 4/6] net/bnxt: add LRO support for SR2 chip
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
` (2 preceding siblings ...)
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
@ 2021-01-11 17:43 ` Ajit Khaparde
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 5/6] net/bnxt: modify context memory allocation Ajit Khaparde
` (2 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-11 17:43 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Kalesh AP
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Add the new chip specific TPA v2 logic to bnxt_tpa_start() to fully support
TPA on the new chip.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_rxr.c | 72 +++++++++++++++++++++++++++++++------
drivers/net/bnxt/bnxt_rxr.h | 12 ++++++-
2 files changed, 72 insertions(+), 12 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index 14901f1b9..af3f9b936 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -134,6 +134,53 @@ struct rte_mbuf *bnxt_consume_rx_buf(struct bnxt_rx_ring_info *rxr,
return mbuf;
}
+static void bnxt_tpa_get_metadata(struct bnxt *bp,
+ struct bnxt_tpa_info *tpa_info,
+ struct rx_tpa_start_cmpl *tpa_start,
+ struct rx_tpa_start_cmpl_hi *tpa_start1)
+{
+ tpa_info->cfa_code_valid = 0;
+ tpa_info->vlan_valid = 0;
+ tpa_info->hash_valid = 0;
+ tpa_info->l4_csum_valid = 0;
+
+ if (likely(tpa_start->flags_type &
+ rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
+ tpa_info->hash_valid = 1;
+ tpa_info->rss_hash = rte_le_to_cpu_32(tpa_start->rss_hash);
+ }
+
+ if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
+ struct rx_tpa_start_v2_cmpl *v2_tpa_start = (void *)tpa_start;
+ struct rx_tpa_start_v2_cmpl_hi *v2_tpa_start1 =
+ (void *)tpa_start1;
+
+ if (v2_tpa_start->agg_id &
+ RX_TPA_START_V2_CMPL_METADATA1_VALID) {
+ tpa_info->vlan_valid = 1;
+ tpa_info->vlan =
+ rte_le_to_cpu_16(v2_tpa_start1->metadata0);
+ }
+
+ if (v2_tpa_start1->flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK)
+ tpa_info->l4_csum_valid = 1;
+
+ return;
+ }
+
+ tpa_info->cfa_code_valid = 1;
+ tpa_info->cfa_code = rte_le_to_cpu_16(tpa_start1->cfa_code);
+ if (tpa_start1->flags2 &
+ rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
+ tpa_info->vlan_valid = 1;
+ tpa_info->vlan = rte_le_to_cpu_32(tpa_start1->metadata);
+ }
+
+ if (likely(tpa_start1->flags2 &
+ rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
+ tpa_info->l4_csum_valid = 1;
+}
+
static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
struct rx_tpa_start_cmpl *tpa_start,
struct rx_tpa_start_cmpl_hi *tpa_start1)
@@ -164,21 +211,23 @@ static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
mbuf->data_len = mbuf->pkt_len;
mbuf->port = rxq->port_id;
mbuf->ol_flags = PKT_RX_LRO;
- if (likely(tpa_start->flags_type &
- rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
- mbuf->hash.rss = rte_le_to_cpu_32(tpa_start->rss_hash);
+
+ bnxt_tpa_get_metadata(rxq->bp, tpa_info, tpa_start, tpa_start1);
+
+ if (likely(tpa_info->hash_valid)) {
+ mbuf->hash.rss = tpa_info->rss_hash;
mbuf->ol_flags |= PKT_RX_RSS_HASH;
- } else {
- mbuf->hash.fdir.id = rte_le_to_cpu_16(tpa_start1->cfa_code);
+ } else if (tpa_info->cfa_code_valid) {
+ mbuf->hash.fdir.id = tpa_info->cfa_code;
mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
}
- if (tpa_start1->flags2 &
- rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
- mbuf->vlan_tci = rte_le_to_cpu_32(tpa_start1->metadata);
+
+ if (tpa_info->vlan_valid) {
+ mbuf->vlan_tci = tpa_info->vlan;
mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
}
- if (likely(tpa_start1->flags2 &
- rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
+
+ if (likely(tpa_info->l4_csum_valid))
mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
/* recycle next mbuf */
@@ -751,7 +800,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
cpr->cp_ring_struct->ring_mask,
cpr->valid);
- if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START) {
+ if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START ||
+ cmp_type == RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2) {
bnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp,
(struct rx_tpa_start_cmpl_hi *)rxcmp1);
rc = -EINVAL; /* Continue w/o new mbuf */
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index b2942030a..78814edbb 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -50,6 +50,14 @@ struct bnxt_tpa_info {
uint16_t len;
uint32_t agg_count;
struct rx_tpa_v2_abuf_cmpl agg_arr[TPA_MAX_NUM_SEGS];
+
+ uint32_t rss_hash;
+ uint32_t vlan;
+ uint16_t cfa_code;
+ uint8_t hash_valid:1;
+ uint8_t vlan_valid:1;
+ uint8_t cfa_code_valid:1;
+ uint8_t l4_csum_valid:1;
};
struct bnxt_rx_ring_info {
@@ -122,4 +130,6 @@ bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)
#define BNXT_PTYPE_TBL_DIM 128
extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM];
-#endif
+
+#define RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK (0x1 << 14)
+#endif /* _BNXT_RXR_H_ */
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v4 5/6] net/bnxt: modify context memory allocation
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
` (3 preceding siblings ...)
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
@ 2021-01-11 17:43 ` Ajit Khaparde
2021-01-11 17:44 ` [dpdk-dev] [PATCH v4 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-12 3:39 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-11 17:43 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Kalesh AP
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Newer devices like SR2 may have chip backing store and do not require
host backed memory allocation.
In these cases, HWRM_FUNC_BACKING_STORE_QCAPS will return a zero entry
size to indicate contexts for which the host should not allocate backing
store.
Selectively allocate context memory based on device capabilities and
only enable backing store for the appropriate contexts
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 60 ++++++++++++++++++++--------------
drivers/net/bnxt/bnxt_hwrm.c | 3 ++
2 files changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 8ca4fb151..e11751cc1 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -4212,39 +4212,49 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)
ctx_pg = &ctx->qp_mem;
ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
- mem_size = ctx->qp_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
- if (rc)
- return rc;
+ if (ctx->qp_entry_size) {
+ mem_size = ctx->qp_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
+ if (rc)
+ return rc;
+ }
ctx_pg = &ctx->srq_mem;
ctx_pg->entries = ctx->srq_max_l2_entries;
- mem_size = ctx->srq_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
- if (rc)
- return rc;
+ if (ctx->srq_entry_size) {
+ mem_size = ctx->srq_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
+ if (rc)
+ return rc;
+ }
ctx_pg = &ctx->cq_mem;
ctx_pg->entries = ctx->cq_max_l2_entries;
- mem_size = ctx->cq_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
- if (rc)
- return rc;
+ if (ctx->cq_entry_size) {
+ mem_size = ctx->cq_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
+ if (rc)
+ return rc;
+ }
ctx_pg = &ctx->vnic_mem;
ctx_pg->entries = ctx->vnic_max_vnic_entries +
ctx->vnic_max_ring_table_entries;
- mem_size = ctx->vnic_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
- if (rc)
- return rc;
+ if (ctx->vnic_entry_size) {
+ mem_size = ctx->vnic_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
+ if (rc)
+ return rc;
+ }
ctx_pg = &ctx->stat_mem;
ctx_pg->entries = ctx->stat_max_entries;
- mem_size = ctx->stat_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
- if (rc)
- return rc;
+ if (ctx->stat_entry_size) {
+ mem_size = ctx->stat_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
+ if (rc)
+ return rc;
+ }
min = ctx->tqm_min_entries_per_ring;
@@ -4260,10 +4270,12 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)
for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
ctx_pg = ctx->tqm_mem[i];
ctx_pg->entries = i ? entries : entries_sp;
- mem_size = ctx->tqm_entry_size * ctx_pg->entries;
- rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
- if (rc)
- return rc;
+ if (ctx->tqm_entry_size) {
+ mem_size = ctx->tqm_entry_size * ctx_pg->entries;
+ rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
+ if (rc)
+ return rc;
+ }
ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
}
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 56e2e33a9..6d54b1656 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -64,6 +64,9 @@ static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
uint8_t *pg_attr,
uint64_t *pg_dir)
{
+ if (rmem->nr_pages == 0)
+ return;
+
if (rmem->nr_pages > 1) {
*pg_attr = 1;
*pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply related [flat|nested] 29+ messages in thread* [dpdk-dev] [PATCH v4 6/6] net/bnxt: add Rx logic for 58818 chips
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
` (4 preceding siblings ...)
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 5/6] net/bnxt: modify context memory allocation Ajit Khaparde
@ 2021-01-11 17:44 ` Ajit Khaparde
2021-01-12 3:39 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-11 17:44 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Kalesh AP
From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
1. On the new 58818 chips, the RX completion is largely the same except
for the new completion opcode and the stripped VLAN format and checksum
status. Added bnxt_parse_csum_v2(), bnxt_parse_pkt_type_v2() and
bnxt_rx_vlan_v2() to support the new RX completion logic.
2. Disable vector mode RX/TX for 58818 chips for now.
3. The cfa_code format on 58818 chips is different than legacy chips.
So skip cfa_code parsing logic on 58818 chips for now.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 15 ++-
drivers/net/bnxt/bnxt_rxr.c | 24 +++--
drivers/net/bnxt/bnxt_rxr.h | 191 +++++++++++++++++++++++++++++++++
3 files changed, 221 insertions(+), 9 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index e11751cc1..ef6b611be 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -1159,6 +1159,12 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = eth_dev->data->dev_private;
+ /* Disable vector mode RX for Stingray2 for now */
+ if (BNXT_CHIP_SR2(bp)) {
+ bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
+ return bnxt_recv_pkts;
+ }
+
#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
#ifndef RTE_LIBRTE_IEEE1588
/*
@@ -1199,12 +1205,17 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev)
}
static eth_tx_burst_t
-bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
+bnxt_transmit_function(struct rte_eth_dev *eth_dev)
{
+ struct bnxt *bp = eth_dev->data->dev_private;
+
+ /* Disable vector mode TX for Stingray2 for now */
+ if (BNXT_CHIP_SR2(bp))
+ return bnxt_xmit_pkts;
+
#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
#ifndef RTE_LIBRTE_IEEE1588
uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
- struct bnxt *bp = eth_dev->data->dev_private;
/*
* Vector mode transmit can be enabled only if not using scatter rx
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index af3f9b936..a195bf118 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -814,7 +814,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
return -EBUSY;
*rx_pkt = mbuf;
goto next_rx;
- } else if (cmp_type != 0x11) {
+ } else if ((cmp_type != CMPL_BASE_TYPE_RX_L2) &&
+ (cmp_type != CMPL_BASE_TYPE_RX_L2_V2)) {
rc = -EINVAL;
goto next_rx;
}
@@ -838,8 +839,6 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
mbuf->data_len = mbuf->pkt_len;
mbuf->port = rxq->port_id;
- bnxt_set_ol_flags(rxr, rxcmp, rxcmp1, mbuf);
-
#ifdef RTE_LIBRTE_IEEE1588
if (unlikely((rte_le_to_cpu_16(rxcmp->flags_type) &
RX_PKT_CMPL_FLAGS_MASK) ==
@@ -849,17 +848,28 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
}
#endif
+ if (cmp_type == CMPL_BASE_TYPE_RX_L2_V2) {
+ bnxt_parse_csum_v2(mbuf, rxcmp1);
+ bnxt_parse_pkt_type_v2(mbuf, rxcmp, rxcmp1);
+ bnxt_rx_vlan_v2(mbuf, rxcmp, rxcmp1);
+ /* TODO Add support for cfa_code parsing */
+ goto reuse_rx_mbuf;
+ }
+
+ bnxt_set_ol_flags(rxr, rxcmp, rxcmp1, mbuf);
+
+ mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
+
if (BNXT_TRUFLOW_EN(bp))
mark_id = bnxt_ulp_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf,
&vfr_flag);
else
bnxt_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf);
+reuse_rx_mbuf:
if (agg_buf)
bnxt_rx_pages(rxq, mbuf, &tmp_raw_cons, agg_buf, NULL);
- mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
-
#ifdef BNXT_DEBUG
if (rxcmp1->errors_v2 & RX_CMP_L2_ERRORS) {
/* Re-install the mbuf back to the rx ring */
@@ -972,8 +982,8 @@ uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
cpr->cp_ring_struct->ring_mask,
cpr->valid);
- /* TODO: Avoid magic numbers... */
- if ((CMP_TYPE(rxcmp) & 0x30) == 0x10) {
+ if ((CMP_TYPE(rxcmp) >= CMPL_BASE_TYPE_RX_TPA_START_V2) &&
+ (CMP_TYPE(rxcmp) <= RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG)) {
rc = bnxt_rx_pkt(&rx_pkts[nb_rx_pkts], rxq, &raw_cons);
if (!rc)
nb_rx_pkts++;
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index 78814edbb..9cc5197a7 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -131,5 +131,196 @@ bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)
#define BNXT_PTYPE_TBL_DIM 128
extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM];
+/* Stingray2 specific code for RX completion parsing */
+#define RX_CMP_VLAN_VALID(rxcmp) \
+ (((struct rx_pkt_v2_cmpl *)rxcmp)->metadata1_payload_offset & \
+ RX_PKT_V2_CMPL_METADATA1_VALID)
+
+#define RX_CMP_METADATA0_VID(rxcmp1) \
+ ((((struct rx_pkt_v2_cmpl_hi *)rxcmp1)->metadata0) & \
+ (RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK | \
+ RX_PKT_V2_CMPL_HI_METADATA0_DE | \
+ RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK))
+
+static inline void bnxt_rx_vlan_v2(struct rte_mbuf *mbuf,
+ struct rx_pkt_cmpl *rxcmp,
+ struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ if (RX_CMP_VLAN_VALID(rxcmp)) {
+ mbuf->vlan_tci = RX_CMP_METADATA0_VID(rxcmp1);
+ mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
+ }
+}
+
+#define RX_CMP_FLAGS2_CS_ALL_OK_MODE_MASK (0x1 << 3)
+#define RX_CMP_FLAGS2_CS_OK_HDR_CNT_MASK (0x7 << 10)
+#define RX_CMP_FLAGS2_IP_CSUM_ALL_OK_MASK (0x1 << 13)
#define RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK (0x1 << 14)
+
+#define RX_CMP_V2_CS_OK_HDR_CNT(flags) \
+ (((flags) & RX_CMP_FLAGS2_CS_OK_HDR_CNT_MASK) >> \
+ RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT)
+
+#define RX_CMP_V2_CS_ALL_OK_MODE(flags) \
+ (((flags) & RX_CMP_FLAGS2_CS_ALL_OK_MODE_MASK))
+
+#define RX_CMP_FLAGS2_L3_CS_OK_MASK (0x7 << 10)
+#define RX_CMP_FLAGS2_L4_CS_OK_MASK (0x38 << 10)
+#define RX_CMP_FLAGS2_L3_CS_OK_SFT 10
+#define RX_CMP_FLAGS2_L4_CS_OK_SFT 13
+
+#define RX_CMP_V2_L4_CS_OK(flags2) \
+ (((flags2) & RX_CMP_FLAGS2_L4_CS_OK_MASK) >> \
+ RX_CMP_FLAGS2_L4_CS_OK_SFT)
+
+#define RX_CMP_V2_L3_CS_OK(flags2) \
+ (((flags2) & RX_CMP_FLAGS2_L3_CS_OK_MASK) >> \
+ RX_CMP_FLAGS2_L3_CS_OK_SFT)
+
+#define RX_CMP_V2_L4_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR)
+
+#define RX_CMP_V2_L3_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR)
+
+#define RX_CMP_V2_T_IP_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR)
+
+#define RX_CMP_V2_T_L4_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR)
+
+#define RX_CMP_V2_OT_L4_CS_ERR(err) \
+ (((err) & RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK) == \
+ RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR)
+
+static inline void bnxt_parse_csum_v2(struct rte_mbuf *mbuf,
+ struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ struct rx_pkt_v2_cmpl_hi *v2_cmp =
+ (struct rx_pkt_v2_cmpl_hi *)(rxcmp1);
+ uint16_t error_v2 = rte_le_to_cpu_16(v2_cmp->errors_v2);
+ uint32_t flags2 = rte_le_to_cpu_32(v2_cmp->flags2);
+ uint32_t hdr_cnt = 0, t_pkt = 0;
+
+ if (RX_CMP_V2_CS_ALL_OK_MODE(flags2)) {
+ hdr_cnt = RX_CMP_V2_CS_OK_HDR_CNT(flags2);
+ if (hdr_cnt > 1)
+ t_pkt = 1;
+
+ if (unlikely(RX_CMP_V2_L4_CS_ERR(error_v2)))
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
+ else if (flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK)
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
+ else
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
+
+ if (unlikely(RX_CMP_V2_L3_CS_ERR(error_v2)))
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
+ else if (flags2 & RX_CMP_FLAGS2_IP_CSUM_ALL_OK_MASK)
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
+ else
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
+ } else {
+ hdr_cnt = RX_CMP_V2_L4_CS_OK(flags2);
+ if (hdr_cnt > 1)
+ t_pkt = 1;
+
+ if (RX_CMP_V2_L4_CS_OK(flags2))
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
+ else if (RX_CMP_V2_L4_CS_ERR(error_v2))
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
+ else
+ mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
+
+ if (RX_CMP_V2_L3_CS_OK(flags2))
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
+ else if (RX_CMP_V2_L3_CS_ERR(error_v2))
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
+ else
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
+ }
+
+ if (t_pkt) {
+ if (unlikely(RX_CMP_V2_OT_L4_CS_ERR(error_v2) ||
+ RX_CMP_V2_T_L4_CS_ERR(error_v2)))
+ mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
+ else
+ mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
+
+ if (unlikely(RX_CMP_V2_T_IP_CS_ERR(error_v2)))
+ mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
+ }
+}
+
+static inline void
+bnxt_parse_pkt_type_v2(struct rte_mbuf *mbuf,
+ struct rx_pkt_cmpl *rxcmp,
+ struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ struct rx_pkt_v2_cmpl *v2_cmp =
+ (struct rx_pkt_v2_cmpl *)(rxcmp);
+ struct rx_pkt_v2_cmpl_hi *v2_cmp1 =
+ (struct rx_pkt_v2_cmpl_hi *)(rxcmp1);
+ uint16_t flags_type = v2_cmp->flags_type &
+ rte_cpu_to_le_32(RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK);
+ uint32_t flags2 = rte_le_to_cpu_32(v2_cmp1->flags2);
+ uint32_t l3, pkt_type = 0, vlan = 0;
+ uint32_t ip6 = 0, t_pkt = 0;
+ uint32_t hdr_cnt, csum_count;
+
+ if (RX_CMP_V2_CS_ALL_OK_MODE(flags2)) {
+ hdr_cnt = RX_CMP_V2_CS_OK_HDR_CNT(flags2);
+ if (hdr_cnt > 1)
+ t_pkt = 1;
+ } else {
+ csum_count = RX_CMP_V2_L4_CS_OK(flags2);
+ if (csum_count > 1)
+ t_pkt = 1;
+ }
+
+ vlan = !!RX_CMP_VLAN_VALID(rxcmp);
+ pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
+
+ ip6 = !!(flags2 & RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE);
+
+ if (!t_pkt && !ip6)
+ l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
+ else if (!t_pkt && ip6)
+ l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
+ else if (t_pkt && !ip6)
+ l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
+ else
+ l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
+
+ switch (flags_type) {
+ case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP):
+ if (!t_pkt)
+ pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
+ break;
+ case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP):
+ if (!t_pkt)
+ pkt_type |= l3 | RTE_PTYPE_L4_TCP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
+ break;
+ case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP):
+ if (!t_pkt)
+ pkt_type |= l3 | RTE_PTYPE_L4_UDP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
+ break;
+ case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_IP):
+ pkt_type |= l3;
+ break;
+ }
+
+ mbuf->packet_type = pkt_type;
+}
+
#endif /* _BNXT_RXR_H_ */
--
2.21.1 (Apple Git-122.3)
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2
2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
` (5 preceding siblings ...)
2021-01-11 17:44 ` [dpdk-dev] [PATCH v4 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
@ 2021-01-12 3:39 ` Ajit Khaparde
6 siblings, 0 replies; 29+ messages in thread
From: Ajit Khaparde @ 2021-01-12 3:39 UTC (permalink / raw)
To: dev; +Cc: Ferruh Yigit
On Mon, Jan 11, 2021 at 9:44 AM Ajit Khaparde <ajitkhaparde@gmail.com> wrote:
>
> Add support for 58818/Stingray2 chip.
> The new chip Stingray 2 belongs to the P5 generation.
> Some changes in the PMD are required to support this new chip.
> This patchset adds the necessary changes.
> Please apply.
>
> v1->v2: rebased to latest dpdk-next-net-brcm tree.
> v2->v3: rebased to latest code base.
> v3->v4: rebase to latest dpdk-next-net code.
Patchset applied to dpdk-next-net-brcm. Thanks
>
> Kalesh AP (6):
> net/bnxt: add support for 58818 chip family
> net/bnxt: add new RX checksum mode
> net/bnxt: modify VNIC accounting
> net/bnxt: add LRO support for SR2 chip
> net/bnxt: modify context memory allocation
> net/bnxt: add Rx logic for 58818 chips
>
> doc/guides/rel_notes/release_21_02.rst | 6 +
> drivers/net/bnxt/bnxt.h | 19 +++
> drivers/net/bnxt/bnxt_cpr.h | 7 +-
> drivers/net/bnxt/bnxt_ethdev.c | 102 +++++++++----
> drivers/net/bnxt/bnxt_flow.c | 14 +-
> drivers/net/bnxt/bnxt_hwrm.c | 49 ++++++
> drivers/net/bnxt/bnxt_hwrm.h | 5 +-
> drivers/net/bnxt/bnxt_ring.c | 19 ++-
> drivers/net/bnxt/bnxt_rxr.c | 96 +++++++++---
> drivers/net/bnxt/bnxt_rxr.h | 203 ++++++++++++++++++++++++-
> 10 files changed, 462 insertions(+), 58 deletions(-)
>
> --
> 2.21.1 (Apple Git-122.3)
>
--
Ajit Khaparde
^ permalink raw reply [flat|nested] 29+ messages in thread