[PATCH 00/21] DC Patches January 08, 2021

[PATCH 00/21] DC Patches January 08, 2021

[Rodrigo Siqueira]

Happy new year, this is the first code promotion of the year; for this
reason, most of the changes are related to fixes.

This DC patchset brings improvements in multiple areas. In summary, we have:
* Multiple fixes and code refactoring.
* Updates on HUBP operations

Best Regards

Aric Cyr (2):
  drm/amd/display: 3.2.117
  drm/amd/display: 3.2.118

Bhawanpreet Lakha (1):
  drm/amd/display: enable HUBP blank behaviour

Charlene Liu (1):
  drm/amd/display: change SMU repsonse timeout to 2s

Chiawen Huang (1):
  drm/amd/display: removed unnecessary check when dpp clock increasing

Jacky Liao (1):
  drm/amd/display: Fix assert being hit with GAMCOR memory shut down

Jun Lei (1):
  drm/amd/display: implement T12 compliance

Lewis Huang (1):
  drm/amd/display: Separate fec debug flag and monitor patch

Li, Roman (1):
  drm/amd/display: disable dcn10 pipe split by default

Mike Hsieh (1):
  drm/amd/display: Remove unused P010 debug flag

Nikola Cornij (1):
  drm/amd/display: Add a missing DCN3.01 API mapping

Qingqing Zhuo (1):
  drm/amd/display: NULL pointer hang

Raymond Yang (1):
  drm/amd/display: fix seamless boot stream adding algorithm

Stylon Wang (1):
  drm/amd/display: Revert patch causing black screen

Wesley Chalmers (6):
  drm/amd/display: Initialize stack variable
  drm/amd/display: HUBP_IN_BLANK for DCN30
  drm/amd/display: Remove HUBP_DISABLE from default
  drm/amd/display: Unblank hubp based on plane visibility
  drm/amd/display: New path for enabling DPG
  drm/amd/display: New sequence for HUBP blank

Yu-ting Shen (1):
  drm/amd/display: doesn't reprogram AMD OUI

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  1 -
 .../gpu/drm/amd/display/dc/basics/dc_common.c | 20 ++++--
 .../gpu/drm/amd/display/dc/basics/dc_common.h |  4 +-
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  |  3 +-
 .../display/dc/clk_mgr/dcn301/dcn301_smu.c    |  2 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 12 ++++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 31 ++++++--
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 49 +++++++++----
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 28 +++++---
 drivers/gpu/drm/amd/display/dc/dc.h           |  3 +-
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  3 +
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  8 +++
 drivers/gpu/drm/amd/display/dc/dc_stream.h    | 11 +++
 .../display/dc/dce110/dce110_hw_sequencer.c   | 31 ++++++++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |  2 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 36 ++++++++--
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  5 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |  1 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  |  2 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 11 +++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |  1 +
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |  4 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 22 ++++--
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 12 +++-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |  1 +
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |  1 +
 .../drm/amd/display/dc/dcn30/dcn30_dpp_cm.c   |  7 --
 .../gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h |  1 +
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    | 70 ++++++++++++++++++-
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.h    |  4 ++
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |  2 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c |  1 +
 .../drm/amd/display/dc/dcn301/dcn301_init.c   |  1 +
 .../amd/display/dc/dcn301/dcn301_resource.c   |  1 +
 .../dc/dml/dcn30/display_mode_vba_30.c        |  2 +-
 .../gpu/drm/amd/display/dc/inc/core_types.h   |  1 +
 .../amd/display/dc/inc/hw/timing_generator.h  |  1 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  5 ++
 38 files changed, 332 insertions(+), 68 deletions(-)

-- 
2.25.1

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[PATCH 01/21] drm/amd/display: 3.2.117

[Rodrigo Siqueira]

From: Aric Cyr <aric.cyr@amd.com>

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 90fdddb72e3b..38a962bc28f2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -42,7 +42,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.116"
+#define DC_VER "3.2.117"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.25.1

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[PATCH 02/21] drm/amd/display: NULL pointer hang

[Rodrigo Siqueira]

From: Qingqing Zhuo <qingqing.zhuo@amd.com>

[Why]
In dc_link_dp_set_test_pattern, we assume all pipes have a stream, which
can cause null pointer dereference.

[How]
Add a null pointer check before accessing stream.

Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 2fc12239b22c..1bd1a0935290 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3992,7 +3992,7 @@ bool dc_link_dp_set_test_pattern(
 	unsigned int cust_pattern_size)
 {
 	struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
-	struct pipe_ctx *pipe_ctx = &pipes[0];
+	struct pipe_ctx *pipe_ctx = NULL;
 	unsigned int lane;
 	unsigned int i;
 	unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
@@ -4002,12 +4002,18 @@ bool dc_link_dp_set_test_pattern(
 	memset(&training_pattern, 0, sizeof(training_pattern));
 
 	for (i = 0; i < MAX_PIPES; i++) {
+		if (pipes[i].stream == NULL)
+			continue;
+
 		if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
 			pipe_ctx = &pipes[i];
 			break;
 		}
 	}
 
+	if (pipe_ctx == NULL)
+		return false;
+
 	/* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
 	if (link->test_pattern_enabled && test_pattern ==
 			DP_TEST_PATTERN_VIDEO_MODE) {
-- 
2.25.1

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[PATCH 03/21] drm/amd/display: Initialize stack variable

[Rodrigo Siqueira]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
The stack variable "val" is potentially unpopulate it, so initialize it
with the value 0xf (indicating an invalid mux)

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index a46cb20596fe..b096011acb49 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -470,7 +470,7 @@ void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)
 unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)
 {
 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
-	uint32_t val;
+	uint32_t val = 0xf;
 
 	if (opp_id < MAX_OPP && REG(MUX[opp_id]))
 		REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);
-- 
2.25.1

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[PATCH 04/21] drm/amd/display: Separate fec debug flag and monitor patch

[Rodrigo Siqueira]

From: Lewis Huang <Lewis.Huang@amd.com>

[Why]
Driver apply the monitor patch into global debug flag.  When apply
monitor patch, fec feature will always disable.

[How]
Separate fec debug flag and monitor patch

Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 20 +++++++++++++++----
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  4 ++--
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  1 +
 3 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index f4a2088ab179..59ef1eacc6e1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1065,9 +1065,6 @@ static bool dc_link_detect_helper(struct dc_link *link,
 			break;
 		}
 
-		if (link->local_sink->edid_caps.panel_patch.disable_fec)
-			link->ctx->dc->debug.disable_fec = true;
-
 		// Check if edid is the same
 		if ((prev_sink) &&
 		    (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
@@ -3635,7 +3632,7 @@ uint32_t dc_link_bandwidth_kbps(
 	link_bw_kbps *= 8;   /* 8 bits per byte*/
 	link_bw_kbps *= link_setting->lane_count;
 
-	if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec) {
+	if (dc_link_should_enable_fec(link)) {
 		/* Account for FEC overhead.
 		 * We have to do it based on caps,
 		 * and not based on FEC being set ready,
@@ -3687,3 +3684,18 @@ bool dc_link_is_fec_supported(const struct dc_link *link)
 			!IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
 }
 
+bool dc_link_should_enable_fec(const struct dc_link *link)
+{
+	bool is_fec_disable = false;
+	bool ret = false;
+
+	if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
+			link->local_sink &&
+			link->local_sink->edid_caps.panel_patch.disable_fec)
+		is_fec_disable = true;
+
+	if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
+		ret = true;
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 1bd1a0935290..3cd84dcb266b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -4345,7 +4345,7 @@ void dp_set_fec_ready(struct dc_link *link, bool ready)
 	struct link_encoder *link_enc = link->link_enc;
 	uint8_t fec_config = 0;
 
-	if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
+	if (!dc_link_should_enable_fec(link))
 		return;
 
 	if (link_enc->funcs->fec_set_ready &&
@@ -4380,7 +4380,7 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
 {
 	struct link_encoder *link_enc = link->link_enc;
 
-	if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
+	if (!dc_link_should_enable_fec(link))
 		return;
 
 	if (link_enc->funcs->fec_set_enable &&
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 6d9a60c9dcc0..d8d659b2bc34 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -369,5 +369,6 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
 	const struct dc_crtc_timing *timing);
 
 bool dc_link_is_fec_supported(const struct dc_link *link);
+bool dc_link_should_enable_fec(const struct dc_link *link);
 
 #endif /* DC_LINK_H_ */
-- 
2.25.1

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[PATCH 05/21] drm/amd/display: HUBP_IN_BLANK for DCN30

[Rodrigo Siqueira]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
Shift/mask for HUBP_IN_BLANK is currently missing.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
index 5fa150f34c60..705fbfc37502 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
@@ -62,6 +62,7 @@
 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
 	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
 	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
 	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
-- 
2.25.1

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[PATCH 06/21] drm/amd/display: Remove HUBP_DISABLE from default

[Rodrigo Siqueira]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
HW team plans to rename HUBP_DISABLE to HUBP_SOFT_RESET in future HW
revisions. Those future revisions should not inherit the HUBP_DISABLE
name.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |  2 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 22 ++++++++++++++-----
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index a9a6ed7f4f99..80794fed6e20 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -450,7 +450,6 @@
 
 #define DCN_HUBP_REG_FIELD_BASE_LIST(type) \
 	type HUBP_BLANK_EN;\
-	type HUBP_DISABLE;\
 	type HUBP_TTU_DISABLE;\
 	type HUBP_NO_OUTSTANDING_REQ;\
 	type HUBP_VTG_SEL;\
@@ -644,6 +643,7 @@
 
 #define DCN_HUBP_REG_FIELD_LIST(type) \
 	DCN_HUBP_REG_FIELD_BASE_LIST(type);\
+	type HUBP_DISABLE;\
 	type ALPHA_PLANE_EN
 
 struct dcn_mi_registers {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index f501c02c244b..98ec1f9171b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -161,7 +161,7 @@
 	DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\
 	uint32_t DCN_DMDATA_VM_CNTL
 
-#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type) \
 	DCN_HUBP_REG_FIELD_BASE_LIST(type); \
 	type DMDATA_ADDRESS_HIGH;\
 	type DMDATA_MODE;\
@@ -186,8 +186,12 @@
 	type SURFACE_TRIPLE_BUFFER_ENABLE;\
 	type VMID
 
-#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \
-	DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\
+#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+	DCN2_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type); \
+	type HUBP_DISABLE
+
+#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type) \
+	DCN2_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type);\
 	type REFCYC_PER_VM_GROUP_FLIP;\
 	type REFCYC_PER_VM_REQ_FLIP;\
 	type REFCYC_PER_VM_GROUP_VBLANK;\
@@ -196,8 +200,12 @@
 	type REFCYC_PER_META_CHUNK_FLIP_C; \
 	type VM_GROUP_SIZE
 
-#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \
-	DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\
+#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+	DCN21_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type);\
+	type HUBP_DISABLE
+
+#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type) \
+	DCN21_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type);\
 	type PRIMARY_SURFACE_DCC_IND_BLK;\
 	type SECONDARY_SURFACE_DCC_IND_BLK;\
 	type PRIMARY_SURFACE_DCC_IND_BLK_C;\
@@ -216,6 +224,10 @@
 	type ROW_TTU_MODE; \
 	type NUM_PKRS
 
+#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+	DCN30_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type);\
+	type HUBP_DISABLE
+
 struct dcn_hubp2_registers {
 	DCN30_HUBP_REG_COMMON_VARIABLE_LIST;
 };
-- 
2.25.1

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[PATCH 07/21] drm/amd/display: Unblank hubp based on plane visibility

[Rodrigo Siqueira]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
DCN10 uses plane visibility to determine when to unblank HUBP; there is
no reason DCN20+ should not do the same.

[HOW]
In addition to changing the check in HWSEQ, we must change
is_pipe_tree_visible so that it checks ODM pipe topologies as well as
MPC. Since we're now checking both ODM and MPC topologies, the helper
function names have been changed to reference "parent" and "child"
instead of "top" and "bottom".

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../gpu/drm/amd/display/dc/basics/dc_common.c | 20 +++++++++++++------
 .../gpu/drm/amd/display/dc/basics/dc_common.h |  4 ++--
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  2 +-
 3 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/dc_common.c b/drivers/gpu/drm/amd/display/dc/basics/dc_common.c
index b2fc4f8e6482..ad04ef98e652 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/dc_common.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/dc_common.c
@@ -49,20 +49,24 @@ bool is_rgb_cspace(enum dc_color_space output_color_space)
 	}
 }
 
-bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+bool is_child_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
 {
 	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
 		return true;
-	if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
+	if (pipe_ctx->bottom_pipe && is_child_pipe_tree_visible(pipe_ctx->bottom_pipe))
+		return true;
+	if (pipe_ctx->next_odm_pipe && is_child_pipe_tree_visible(pipe_ctx->next_odm_pipe))
 		return true;
 	return false;
 }
 
-bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+bool is_parent_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
 {
 	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
 		return true;
-	if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
+	if (pipe_ctx->top_pipe && is_parent_pipe_tree_visible(pipe_ctx->top_pipe))
+		return true;
+	if (pipe_ctx->prev_odm_pipe && is_parent_pipe_tree_visible(pipe_ctx->prev_odm_pipe))
 		return true;
 	return false;
 }
@@ -71,9 +75,13 @@ bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
 {
 	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
 		return true;
-	if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
+	if (pipe_ctx->top_pipe && is_parent_pipe_tree_visible(pipe_ctx->top_pipe))
+		return true;
+	if (pipe_ctx->bottom_pipe && is_child_pipe_tree_visible(pipe_ctx->bottom_pipe))
+		return true;
+	if (pipe_ctx->prev_odm_pipe && is_parent_pipe_tree_visible(pipe_ctx->prev_odm_pipe))
 		return true;
-	if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
+	if (pipe_ctx->next_odm_pipe && is_child_pipe_tree_visible(pipe_ctx->next_odm_pipe))
 		return true;
 	return false;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/basics/dc_common.h b/drivers/gpu/drm/amd/display/dc/basics/dc_common.h
index 7c0cbf47e8ce..b061497480b8 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/dc_common.h
+++ b/drivers/gpu/drm/amd/display/dc/basics/dc_common.h
@@ -30,9 +30,9 @@
 
 bool is_rgb_cspace(enum dc_color_space output_color_space);
 
-bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
+bool is_child_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
 
-bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
+bool is_parent_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
 
 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index cb822df21b7c..6470f5c7dfea 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1570,7 +1570,7 @@ static void dcn20_update_dchubp_dpp(
 
 
 
-	if (pipe_ctx->update_flags.bits.enable)
+	if (is_pipe_tree_visible(pipe_ctx))
 		hubp->funcs->set_blank(hubp, false);
 }
 
-- 
2.25.1

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[PATCH 08/21] drm/amd/display: New path for enabling DPG

[Rodrigo Siqueira]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
We want to make enabling test pattern a part of the stream update code
path. This change is the first step towards that goal.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 12 ++++++++++++
 drivers/gpu/drm/amd/display/dc/dc_stream.h | 11 +++++++++++
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8f1cadb823c7..7801b44cfaec 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2265,6 +2265,9 @@ static void copy_stream_update_to_stream(struct dc *dc,
 
 	if (update->dither_option)
 		stream->dither_option = *update->dither_option;
+
+	if (update->pending_test_pattern)
+		stream->test_pattern = *update->pending_test_pattern;
 	/* update current stream with writeback info */
 	if (update->wb_update) {
 		int i;
@@ -2361,6 +2364,15 @@ static void commit_planes_do_stream_update(struct dc *dc,
 				}
 			}
 
+			if (stream_update->pending_test_pattern) {
+				dc_link_dp_set_test_pattern(stream->link,
+					stream->test_pattern.type,
+					stream->test_pattern.color_space,
+					stream->test_pattern.p_link_settings,
+					stream->test_pattern.p_custom_pattern,
+					stream->test_pattern.cust_pattern_size);
+			}
+
 			/* Full fe update*/
 			if (update_type == UPDATE_TYPE_FAST)
 				continue;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index b7910976b81a..80b67b860091 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -130,6 +130,14 @@ union stream_update_flags {
 	uint32_t raw;
 };
 
+struct test_pattern {
+	enum dp_test_pattern type;
+	enum dp_test_pattern_color_space color_space;
+	struct link_training_settings const *p_link_settings;
+	unsigned char const *p_custom_pattern;
+	unsigned int cust_pattern_size;
+};
+
 struct dc_stream_state {
 	// sink is deprecated, new code should not reference
 	// this pointer
@@ -227,6 +235,8 @@ struct dc_stream_state {
 
 	uint32_t stream_id;
 	bool is_dsc_enabled;
+
+	struct test_pattern test_pattern;
 	union stream_update_flags update_flags;
 };
 
@@ -261,6 +271,7 @@ struct dc_stream_update {
 	struct dc_dsc_config *dsc_config;
 	struct dc_transfer_func *func_shaper;
 	struct dc_3dlut *lut3d_func;
+	struct test_pattern *pending_test_pattern;
 };
 
 bool dc_is_stream_unchanged(
-- 
2.25.1

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[PATCH 09/21] drm/amd/display: removed unnecessary check when dpp clock increasing

[Rodrigo Siqueira]

From: Chiawen Huang <chiawen.huang@amd.com>

[Why]
When switching single pipe to split pipe, the bandwidth check is just
for first pipe.  The 2nd pipe with abnormal(or zero) dpp clock when pipe
ready and unlock leads the garbage on display.

[How]
Removed external increasing dpp clock check, the internal function
already loops all of pipes to check whether update dpp clock.

Signed-off-by: Chiawen Huang <chiawen.huang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index f2114bc910bf..ec9dc265cde0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -257,8 +257,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
 			if (update_dppclk || update_dispclk)
 				dcn20_update_clocks_update_dentist(clk_mgr);
 			// always update dtos unless clock is lowered and not safe to lower
-			if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
-				dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 		}
 	}
 
-- 
2.25.1

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[PATCH 10/21] drm/amd/display: doesn't reprogram AMD OUI

[Rodrigo Siqueira]

From: Yu-ting Shen <Yu-ting.Shen@amd.com>

[Why]
1. the corrected timing to write DPCD 300h AMD signature is before
link training.
2. and VBIOS will writes correctted AMD signature by after AGESA 1.0.0,
so driver doesn't need to write DPCD 300h again to switch config.
3. there are some OLED panel will clean backlight level to 0 once
receive DPCD 300h, so we will see flicker issue at that time.

[How]
read DPCD 300h signature before write it to avoid reprogram again, if
AMD signature was writed corrected by VBIOS, driver will not reprogram
it again.

Signed-off-by: Yu-ting Shen <Yu-ting.Shen@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 37 +++++++++++++------
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  3 ++
 2 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 3cd84dcb266b..b2d859f32d54 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -4407,24 +4407,39 @@ void dpcd_set_source_specific_data(struct dc_link *link)
 {
 	if (!link->dc->vendor_signature.is_valid) {
 		enum dc_status result_write_min_hblank = DC_NOT_SUPPORTED;
-		struct dpcd_amd_signature amd_signature;
-		amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
-		amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
-		amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
-		amd_signature.device_id_byte1 =
+		struct dpcd_amd_signature amd_signature = {0};
+		struct dpcd_amd_device_id amd_device_id = {0};
+
+		amd_device_id.device_id_byte1 =
 				(uint8_t)(link->ctx->asic_id.chip_id);
-		amd_signature.device_id_byte2 =
+		amd_device_id.device_id_byte2 =
 				(uint8_t)(link->ctx->asic_id.chip_id >> 8);
-		memset(&amd_signature.zero, 0, 4);
-		amd_signature.dce_version =
+		amd_device_id.dce_version =
 				(uint8_t)(link->ctx->dce_version);
-		amd_signature.dal_version_byte1 = 0x0; // needed? where to get?
-		amd_signature.dal_version_byte2 = 0x0; // needed? where to get?
+		amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
+		amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
 
-		core_link_write_dpcd(link, DP_SOURCE_OUI,
+		core_link_read_dpcd(link, DP_SOURCE_OUI,
 				(uint8_t *)(&amd_signature),
 				sizeof(amd_signature));
 
+		if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
+			(amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
+			(amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
+
+			amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
+			amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
+			amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
+
+			core_link_write_dpcd(link, DP_SOURCE_OUI,
+				(uint8_t *)(&amd_signature),
+				sizeof(amd_signature));
+		}
+
+		core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
+				(uint8_t *)(&amd_device_id),
+				sizeof(amd_device_id));
+
 		if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
 			link->dc->caps.min_horizontal_blanking_period != 0) {
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 80a2191a3115..cc6fb838420e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -451,6 +451,9 @@ struct dpcd_amd_signature {
 	uint8_t AMD_IEEE_TxSignature_byte1;
 	uint8_t AMD_IEEE_TxSignature_byte2;
 	uint8_t AMD_IEEE_TxSignature_byte3;
+};
+
+struct dpcd_amd_device_id {
 	uint8_t device_id_byte1;
 	uint8_t device_id_byte2;
 	uint8_t zero[4];
-- 
2.25.1

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[PATCH 11/21] drm/amd/display: Remove unused P010 debug flag

[Rodrigo Siqueira]

From: Mike Hsieh <chun-wei.hsieh@amd.com>

Signed-off-by: Mike Hsieh <chun-wei.hsieh@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 38a962bc28f2..3737fb9802a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -484,7 +484,6 @@ struct dc_debug_options {
 	bool performance_trace;
 	bool az_endpoint_mute_only;
 	bool always_use_regamma;
-	bool p010_mpo_support;
 	bool recovery_enabled;
 	bool avoid_vbios_exec_table;
 	bool scl_reset_length10;
-- 
2.25.1

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[PATCH 12/21] drm/amd/display: implement T12 compliance

[Rodrigo Siqueira]

From: Jun Lei <jun.lei@amd.com>

[why]
When OS reboots, and panel is turned off, T12 may not be maintained.
T12 is defined as the interval between VDDC off (occurs at shutdown) and
the next VDDC on (occurs when eDP is POST-ed)

[how]
DC already tracks panel power off time.  Add a DC interface which DM can
call during shutdown.  Ideally this should be as late as possible during
the shutdown sequence so the extra delay is minimal.

Signed-off-by: Jun Lei <jun.lei@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 11 +++++++
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  7 +++++
 .../display/dc/dce110/dce110_hw_sequencer.c   | 31 +++++++++++++++++++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  2 ++
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |  1 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  1 +
 6 files changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 59ef1eacc6e1..4f58a5c43548 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -203,6 +203,17 @@ static bool program_hpd_filter(const struct dc_link *link)
 	return result;
 }
 
+bool dc_link_wait_for_t12(struct dc_link *link)
+{
+	if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
+		link->dc->hwss.edp_wait_for_T12(link);
+
+		return true;
+	}
+
+	return false;
+}
+
 /**
  * dc_link_detect_sink() - Determine if there is a sink connected
  *
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index d8d659b2bc34..d5d8f0ad9233 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -259,6 +259,13 @@ enum dc_status dc_link_reallocate_mst_payload(struct dc_link *link);
 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
 		union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss);
 
+/*
+ * On eDP links this function call will stall until T12 has elapsed.
+ * If the panel is not in power off state, this function will return
+ * immediately.
+ */
+bool dc_link_wait_for_t12(struct dc_link *link);
+
 enum dc_status read_hpd_rx_irq_data(
 	struct dc_link *link,
 	union hpd_irq_data *irq_data);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 4c230f1de9a3..3e9abb1b8e14 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -921,6 +921,37 @@ void dce110_edp_power_control(
 	}
 }
 
+void dce110_edp_wait_for_T12(
+		struct dc_link *link)
+{
+	struct dc_context *ctx = link->ctx;
+
+	if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
+			!= CONNECTOR_ID_EDP) {
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+
+	if (!link->panel_cntl)
+		return;
+
+	if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&
+			link->link_trace.time_stamp.edp_poweroff != 0) {
+		unsigned int t12_duration = 500; // Default T12 as per spec
+		unsigned long long current_ts = dm_get_timestamp(ctx);
+		unsigned long long time_since_edp_poweroff_ms =
+				div64_u64(dm_get_elapse_time_in_ns(
+						ctx,
+						current_ts,
+						link->link_trace.time_stamp.edp_poweroff), 1000000);
+
+		t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12
+
+		if (time_since_edp_poweroff_ms < t12_duration)
+			msleep(t12_duration - time_since_edp_poweroff_ms);
+	}
+}
+
 /*todo: cloned in stream enc, fix*/
 /*
  * @brief
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index e5691e499023..dee8ad1ebaa4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -163,6 +163,8 @@ void dcn10_wait_for_mpcc_disconnect(
 void dce110_edp_backlight_control(
 		struct dc_link *link,
 		bool enable);
+void dce110_edp_wait_for_T12(
+		struct dc_link *link);
 void dce110_edp_power_control(
 		struct dc_link *link,
 		bool power_up);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index 87c74aa84406..c4c14e9c1309 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -71,6 +71,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
 	.edp_backlight_control = dce110_edp_backlight_control,
 	.edp_power_control = dce110_edp_power_control,
 	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+	.edp_wait_for_T12 = dce110_edp_wait_for_T12,
 	.set_cursor_position = dcn10_set_cursor_position,
 	.set_cursor_attribute = dcn10_set_cursor_attribute,
 	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 7b12ffcdd4ec..7a19ff5d4214 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -54,6 +54,7 @@ struct hw_sequencer_funcs {
 	/* Embedded Display Related */
 	void (*edp_power_control)(struct dc_link *link, bool enable);
 	void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
+	void (*edp_wait_for_T12)(struct dc_link *link);
 
 	/* Pipe Programming Related */
 	void (*init_hw)(struct dc *dc);
-- 
2.25.1

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[PATCH 13/21] drm/amd/display: fix seamless boot stream adding algorithm

[Rodrigo Siqueira]

From: Raymond Yang <rayyang@amd.com>

[Why]
Seamless boot stream has hw resource assigned, already.  'add' is
actually rebuild the assignment.

[How]
Swap seamless boot stream to pipe 0 (if needed) to ensure pipe_ctx
matches

Signed-off-by: Raymond Yang <rayyang@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 28 +++++++++++++------
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 07c22556480b..3e9ab047301e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2075,6 +2075,20 @@ static int acquire_resource_from_hw_enabled_state(
 	return -1;
 }
 
+static void mark_seamless_boot_stream(
+		const struct dc  *dc,
+		struct dc_stream_state *stream)
+{
+	struct dc_bios *dcb = dc->ctx->dc_bios;
+
+	/* TODO: Check Linux */
+	if (dc->config.allow_seamless_boot_optimization &&
+			!dcb->funcs->is_accelerated_mode(dcb)) {
+		if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
+			stream->apply_seamless_boot_optimization = true;
+	}
+}
+
 enum dc_status resource_map_pool_resources(
 		const struct dc  *dc,
 		struct dc_state *context,
@@ -2085,22 +2099,20 @@ enum dc_status resource_map_pool_resources(
 	struct dc_context *dc_ctx = dc->ctx;
 	struct pipe_ctx *pipe_ctx = NULL;
 	int pipe_idx = -1;
-	struct dc_bios *dcb = dc->ctx->dc_bios;
 
 	calculate_phy_pix_clks(stream);
 
-	/* TODO: Check Linux */
-	if (dc->config.allow_seamless_boot_optimization &&
-			!dcb->funcs->is_accelerated_mode(dcb)) {
-		if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
-			stream->apply_seamless_boot_optimization = true;
-	}
+	mark_seamless_boot_stream(dc, stream);
 
-	if (stream->apply_seamless_boot_optimization)
+	if (stream->apply_seamless_boot_optimization) {
 		pipe_idx = acquire_resource_from_hw_enabled_state(
 				&context->res_ctx,
 				pool,
 				stream);
+		if (pipe_idx < 0)
+			/* hw resource was assigned to other stream */
+			stream->apply_seamless_boot_optimization = false;
+	}
 
 	if (pipe_idx < 0)
 		/* acquire new resources */
-- 
2.25.1

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[PATCH 14/21] drm/amd/display: Fix assert being hit with GAMCOR memory shut down

[Rodrigo Siqueira]

From: Jacky Liao <ziyu.liao@amd.com>

[Why]
A call to BREAK_TO_DEBUGGER is triggered when powering down memory

[How]
Remove the check for GAMCOR_MEM_PWR_STATE when powering off the memory

Signed-off-by: Jacky Liao <ziyu.liao@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c
index 9da66e491116..33985401f25c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c
@@ -133,7 +133,6 @@ static void dpp3_power_on_gamcor_lut(
 		struct dpp *dpp_base,
 	bool power_on)
 {
-	uint32_t power_status;
 	struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 
 	if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
@@ -143,12 +142,6 @@ static void dpp3_power_on_gamcor_lut(
 	} else
 		REG_SET(CM_MEM_PWR_CTRL, 0,
 				GAMCOR_MEM_PWR_DIS, power_on == true ? 0:1);
-
-	REG_GET(CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, &power_status);
-	if (power_status != 0)
-		BREAK_TO_DEBUGGER();
-
-
 }
 
 void dpp3_program_cm_dealpha(
-- 
2.25.1

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[PATCH 15/21] drm/amd/display: New sequence for HUBP blank

[Rodrigo Siqueira]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
DCN30 has a bug where blanking HUBP blocks pstate allow unless
HUBP_DISABLE is toggled afterwards.

[HOW]
Create a HW sequence for blanking HUBP.
1. Wait for enter VBLANK
2. Set HUBP_BLANK
3. Make sure HUBP_IN_BLANK = 1
4. Toggle HUBP_DISABLE on and off to perform soft reset

All existing calls to hubp->funcs->set_blank should be replaced with
this new sequence.
In wait_for_mpcc_disconnect, only blank the pipe being disconnected, and
leave all other pipes unmodified.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 36 +++++++++++---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  3 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |  1 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  2 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |  1 +
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |  1 +
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    | 47 +++++++++++++++++++
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.h    |  4 ++
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |  1 +
 .../drm/amd/display/dc/dcn301/dcn301_init.c   |  1 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  4 ++
 11 files changed, 93 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index cfc130e2d6fd..add86d4086e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2624,7 +2624,7 @@ static void dcn10_update_dchubp_dpp(
 	hws->funcs.update_plane_addr(dc, pipe_ctx);
 
 	if (is_pipe_tree_visible(pipe_ctx))
-		hubp->funcs->set_blank(hubp, false);
+		dc->hwss.set_hubp_blank(dc, pipe_ctx, false);
 }
 
 void dcn10_blank_pixel_data(
@@ -3135,13 +3135,16 @@ void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
 	return;
 }
 
-static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
+static struct pipe_ctx *get_pipe_ctx_by_hubp_inst(struct dc_state *context, int mpcc_inst)
 {
 	int i;
 
-	for (i = 0; i < res_pool->pipe_count; i++) {
-		if (res_pool->hubps[i]->inst == mpcc_inst)
-			return res_pool->hubps[i];
+	for (i = 0; i < MAX_PIPES; i++) {
+		if (context->res_ctx.pipe_ctx[i].plane_res.hubp
+				&& context->res_ctx.pipe_ctx[i].plane_res.hubp->inst == mpcc_inst) {
+			return &context->res_ctx.pipe_ctx[i];
+		}
+
 	}
 	ASSERT(false);
 	return NULL;
@@ -3164,11 +3167,23 @@ void dcn10_wait_for_mpcc_disconnect(
 
 	for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
 		if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
-			struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
+			struct pipe_ctx *restore_bottom_pipe;
+			struct pipe_ctx *restore_top_pipe;
+			struct pipe_ctx *inst_pipe_ctx = get_pipe_ctx_by_hubp_inst(dc->current_state, mpcc_inst);
 
+			ASSERT(inst_pipe_ctx);
 			res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
 			pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
-			hubp->funcs->set_blank(hubp, true);
+			/*
+			 * Set top and bottom pipes NULL, as we don't want
+			 * to blank those pipes when disconnecting from MPCC
+			 */
+			restore_bottom_pipe = inst_pipe_ctx->bottom_pipe;
+			restore_top_pipe = inst_pipe_ctx->top_pipe;
+			inst_pipe_ctx->top_pipe = inst_pipe_ctx->bottom_pipe = NULL;
+			dc->hwss.set_hubp_blank(dc, inst_pipe_ctx, true);
+			inst_pipe_ctx->top_pipe = restore_top_pipe;
+			inst_pipe_ctx->bottom_pipe = restore_bottom_pipe;
 		}
 	}
 
@@ -3721,3 +3736,10 @@ void dcn10_get_clock(struct dc *dc,
 				dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
 
 }
+
+void dcn10_set_hubp_blank(const struct dc *dc,
+				struct pipe_ctx *pipe_ctx,
+				bool blank_enable)
+{
+	pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, blank_enable);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index dee8ad1ebaa4..89e6dfb63da0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -204,5 +204,8 @@ void dcn10_wait_for_pending_cleared(struct dc *dc,
 		struct dc_state *context);
 void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
 void dcn10_verify_allow_pstate_change_high(struct dc *dc);
+void dcn10_set_hubp_blank(const struct dc *dc,
+				struct pipe_ctx *pipe_ctx,
+				bool blank_enable);
 
 #endif /* __DC_HWSS_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
index 254300b06b43..2f1b802e66a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
@@ -79,6 +79,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
 	.set_backlight_level = dce110_set_backlight_level,
 	.set_abm_immediate_disable = dce110_set_abm_immediate_disable,
 	.set_pipe = dce110_set_pipe,
+	.set_hubp_blank = dcn10_set_hubp_blank,
 };
 
 static const struct hwseq_private_funcs dcn10_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 6470f5c7dfea..b74f79575cdf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1571,7 +1571,7 @@ static void dcn20_update_dchubp_dpp(
 
 
 	if (is_pipe_tree_visible(pipe_ctx))
-		hubp->funcs->set_blank(hubp, false);
+		dc->hwss.set_hubp_blank(dc, pipe_ctx, false);
 }
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index de9dcbeea150..51a4166e9750 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -94,6 +94,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
 	.optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,
 #endif
 	.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
+	.set_hubp_blank = dcn10_set_hubp_blank,
 };
 
 static const struct hwseq_private_funcs dcn20_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index 074e2713257f..0597391b2171 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -99,6 +99,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
 #endif
 	.is_abm_supported = dcn21_is_abm_supported,
 	.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
+	.set_hubp_blank = dcn10_set_hubp_blank,
 };
 
 static const struct hwseq_private_funcs dcn21_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index b83c13d3d8b7..7f26c9444933 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -836,6 +836,53 @@ void dcn30_hardware_release(struct dc *dc)
 				dc->res_pool->hubbub, true, true);
 }
 
+void dcn30_set_hubp_blank(const struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		bool blank_enable)
+{
+	struct pipe_ctx *mpcc_pipe;
+	struct pipe_ctx *odm_pipe;
+
+	if (blank_enable) {
+		struct plane_resource *plane_res = &pipe_ctx->plane_res;
+		struct stream_resource *stream_res = &pipe_ctx->stream_res;
+
+		/* Wait for enter vblank */
+		stream_res->tg->funcs->wait_for_state(stream_res->tg, CRTC_STATE_VBLANK);
+
+		/* Blank HUBP to allow p-state during blank on all timings */
+		pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true);
+		/* Confirm hubp in blank */
+		ASSERT(plane_res->hubp->funcs->hubp_in_blank(plane_res->hubp));
+		/* Toggle HUBP_DISABLE */
+		plane_res->hubp->funcs->hubp_soft_reset(plane_res->hubp, true);
+		plane_res->hubp->funcs->hubp_soft_reset(plane_res->hubp, false);
+		for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) {
+			mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);
+			/* Confirm hubp in blank */
+			ASSERT(mpcc_pipe->plane_res.hubp->funcs->hubp_in_blank(mpcc_pipe->plane_res.hubp));
+			/* Toggle HUBP_DISABLE */
+			mpcc_pipe->plane_res.hubp->funcs->hubp_soft_reset(mpcc_pipe->plane_res.hubp, true);
+			mpcc_pipe->plane_res.hubp->funcs->hubp_soft_reset(mpcc_pipe->plane_res.hubp, false);
+
+		}
+		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+			odm_pipe->plane_res.hubp->funcs->set_blank(odm_pipe->plane_res.hubp, true);
+			/* Confirm hubp in blank */
+			ASSERT(odm_pipe->plane_res.hubp->funcs->hubp_in_blank(odm_pipe->plane_res.hubp));
+			/* Toggle HUBP_DISABLE */
+			odm_pipe->plane_res.hubp->funcs->hubp_soft_reset(odm_pipe->plane_res.hubp, true);
+			odm_pipe->plane_res.hubp->funcs->hubp_soft_reset(odm_pipe->plane_res.hubp, false);
+		}
+	} else {
+		pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false);
+		for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
+			mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, false);
+		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+			odm_pipe->plane_res.hubp->funcs->set_blank(odm_pipe->plane_res.hubp, false);
+	}
+}
+
 void dcn30_set_disp_pattern_generator(const struct dc *dc,
 		struct pipe_ctx *pipe_ctx,
 		enum controller_dp_test_pattern test_pattern,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
index bfc97e2ece61..1103f6356e90 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
@@ -79,4 +79,8 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
 		const struct tg_color *solid_color,
 		int width, int height, int offset);
 
+void dcn30_set_hubp_blank(const struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		bool blank_enable);
+
 #endif /* __DC_HWSS_DCN30_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index c4c14e9c1309..204444fead97 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -98,6 +98,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
 	.hardware_release = dcn30_hardware_release,
 	.set_pipe = dcn21_set_pipe,
 	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
+	.set_hubp_blank = dcn30_set_hubp_blank,
 };
 
 static const struct hwseq_private_funcs dcn30_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
index bdad72140cbc..b8bf6d61005b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
@@ -98,6 +98,7 @@ static const struct hw_sequencer_funcs dcn301_funcs = {
 	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
 	.set_pipe = dcn21_set_pipe,
 	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
+	.set_hubp_blank = dcn30_set_hubp_blank,
 };
 
 static const struct hwseq_private_funcs dcn301_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 7a19ff5d4214..48378beb71c0 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -230,6 +230,10 @@ struct hw_sequencer_funcs {
 			enum dc_color_depth color_depth,
 			const struct tg_color *solid_color,
 			int width, int height, int offset);
+
+	void (*set_hubp_blank)(const struct dc *dc,
+			struct pipe_ctx *pipe_ctx,
+			bool blank_enable);
 };
 
 void color_space_to_black_color(
-- 
2.25.1

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[PATCH 16/21] drm/amd/display: enable HUBP blank behaviour

[Rodrigo Siqueira]

From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

- Reverts "drm/amd/display: Revert HUBP blank behaviour for now"
- Hubp blank will fail if the pipe is locked (this is the case on
linux), so add a check to make sure pipe isn't locked, if it is then
defer the blank to post_unlock.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 11 +++++++++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |  1 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  8 +++++++
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    | 23 +++++++++++++++++--
 .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c |  1 +
 .../dc/dml/dcn30/display_mode_vba_30.c        |  2 +-
 .../gpu/drm/amd/display/dc/inc/core_types.h   |  1 +
 .../amd/display/dc/inc/hw/timing_generator.h  |  1 +
 8 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index f033397a84e9..6138f4887de7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -659,6 +659,16 @@ void optc1_unlock(struct timing_generator *optc)
 			OTG_MASTER_UPDATE_LOCK, 0);
 }
 
+bool optc1_is_locked(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+	uint32_t locked;
+
+	REG_GET(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, &locked);
+
+	return (locked == 1);
+}
+
 void optc1_get_position(struct timing_generator *optc,
 		struct crtc_position *position)
 {
@@ -1513,6 +1523,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = {
 		.enable_crtc_reset = optc1_enable_crtc_reset,
 		.disable_reset_trigger = optc1_disable_reset_trigger,
 		.lock = optc1_lock,
+		.is_locked = optc1_is_locked,
 		.unlock = optc1_unlock,
 		.enable_optc_clock = optc1_enable_optc_clock,
 		.set_drr = optc1_set_drr,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index b12bd9aae52f..b222c67973d4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -638,6 +638,7 @@ void optc1_set_blank(struct timing_generator *optc,
 		bool enable_blanking);
 
 bool optc1_is_blanked(struct timing_generator *optc);
+bool optc1_is_locked(struct timing_generator *optc);
 
 void optc1_program_blank_color(
 		struct timing_generator *optc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index b74f79575cdf..18653c423c96 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1765,6 +1765,14 @@ void dcn20_post_unlock_program_front_end(
 		}
 	}
 
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe->vtp_locked) {
+			dc->hwss.set_hubp_blank(dc, pipe, true);
+			pipe->vtp_locked = false;
+		}
+	}
 	/* WA to apply WM setting*/
 	if (hwseq->wa.DEGVIDCN21)
 		dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 7f26c9444933..e5cc8f8c363f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -891,6 +891,25 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
 		const struct tg_color *solid_color,
 		int width, int height, int offset)
 {
-	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
-			color_space, color_depth, solid_color, width, height, offset);
+	struct stream_resource *stream_res = &pipe_ctx->stream_res;
+
+	if (test_pattern != CONTROLLER_DP_TEST_PATTERN_VIDEOMODE) {
+		pipe_ctx->vtp_locked = false;
+		/* turning on DPG */
+		stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space,
+				color_depth, solid_color, width, height, offset);
+
+		/* Defer hubp blank if tg is locked */
+		if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg)) {
+			if (stream_res->tg->funcs->is_locked(stream_res->tg))
+				pipe_ctx->vtp_locked = true;
+			else
+				dc->hwss.set_hubp_blank(dc, pipe_ctx, true);
+		}
+	} else {
+		dc->hwss.set_hubp_blank(dc, pipe_ctx, false);
+		/* turning off DPG */
+		stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space,
+				color_depth, solid_color, width, height, offset);
+	}
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index 3ba3991ee612..8980c90b2277 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -309,6 +309,7 @@ static struct timing_generator_funcs dcn30_tg_funcs = {
 		.enable_crtc_reset = optc1_enable_crtc_reset,
 		.disable_reset_trigger = optc1_disable_reset_trigger,
 		.lock = optc3_lock,
+		.is_locked = optc1_is_locked,
 		.unlock = optc1_unlock,
 		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
 		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 319dec59bcd1..1fe3fb14afd4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -5558,7 +5558,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
 		}
 	}
 
-	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0 && PrefetchMode == 0) {
+	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
 		*DRAMClockChangeSupport = dm_dram_clock_change_vactive;
 	} else if (((mode_lib->vba.SynchronizedVBlank == true || mode_lib->vba.TotalNumberOfActiveOTG == 1 || SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0)) {
 		*DRAMClockChangeSupport = dm_dram_clock_change_vblank;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 2d77eac66cb0..8efa1b80546d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -333,6 +333,7 @@ struct pipe_ctx {
 	union pipe_update_flags update_flags;
 	struct dwbc *dwbc;
 	struct mcif_wb *mcif_wb;
+	bool vtp_locked;
 };
 
 struct resource_context {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index f7632fe25976..754832d216fd 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -190,6 +190,7 @@ struct timing_generator_funcs {
 	void (*set_blank)(struct timing_generator *tg,
 					bool enable_blanking);
 	bool (*is_blanked)(struct timing_generator *tg);
+	bool (*is_locked)(struct timing_generator *tg);
 	void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color);
 	void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color);
 	void (*set_colors)(struct timing_generator *tg,
-- 
2.25.1

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[PATCH 17/21] drm/amd/display: Add a missing DCN3.01 API mapping

[Rodrigo Siqueira]

From: Nikola Cornij <nikola.cornij@amd.com>

[why]
Required for DSC MST

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Zhan Liu <Zhan.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 4825c5c1c6ed..35f5bf08ae96 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1731,6 +1731,7 @@ static struct resource_funcs dcn301_res_pool_funcs = {
 	.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
 	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
 	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
+	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
 	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
 	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
-- 
2.25.1

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[PATCH 18/21] drm/amd/display: 3.2.118

[Rodrigo Siqueira]

From: Aric Cyr <aric.cyr@amd.com>

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 3737fb9802a4..f3ba02cc85d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -42,7 +42,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.117"
+#define DC_VER "3.2.118"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.25.1

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[PATCH 19/21] drm/amd/display: Revert patch causing black screen

[Rodrigo Siqueira]

From: Stylon Wang <stylon.wang@amd.com>

[Why]
Previous patch is causing black screen from S3 hotplug.

[How]
Revert patch until correct solution is developed.
This reverts 2b09ac8145dc.

Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 228b5e51c41e..3c1552667a2a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2386,7 +2386,6 @@ void amdgpu_dm_update_connector_after_detect(
 			drm_connector_update_edid_property(connector,
 							   aconnector->edid);
 			aconnector->num_modes = drm_add_edid_modes(connector, aconnector->edid);
-			drm_connector_list_update(connector);
 
 			if (aconnector->dc_link->aux_mode)
 				drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
-- 
2.25.1

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[PATCH 20/21] drm/amd/display: disable dcn10 pipe split by default

[Rodrigo Siqueira]

From: "Li, Roman" <Roman.Li@amd.com>

[Why]
The initial purpose of dcn10 pipe split is to support some high
bandwidth mode which requires dispclk greater than max dispclk. By
initial bring up power measurement data, it showed power consumption is
less with pipe split for dcn block. This could be reason for enable pipe
split by default. By battery life measurement of some Chromebooks,
result shows battery life is longer with pipe split disabled.

[How]
Disable pipe split by default. Pipe split could be still enabled when
required dispclk is greater than max dispclk.

Signed-off-by: hersen wu <hersenxs.wu@amd.com<mailto:hersenxs.wu@amd.com>>
Reviewed-by: Roman Li <Roman.Li@amd.com<mailto:Roman.Li@amd.com>>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 36745193c391..90e912fef2b3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -608,8 +608,8 @@ static const struct dc_debug_options debug_defaults_drv = {
 		.disable_pplib_clock_request = false,
 		.disable_pplib_wm_range = false,
 		.pplib_wm_report_mode = WM_REPORT_DEFAULT,
-		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
-		.force_single_disp_pipe_split = true,
+		.pipe_split_policy = MPC_SPLIT_AVOID,
+		.force_single_disp_pipe_split = false,
 		.disable_dcc = DCC_ENABLE,
 		.voltage_align_fclk = true,
 		.disable_stereo_support = true,
-- 
2.25.1

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[PATCH 21/21] drm/amd/display: change SMU repsonse timeout to 2s

[Rodrigo Siqueira]

From: Charlene Liu <Charlene.Liu@amd.com>

[why]
driver has sent PMFW VBIOSSMC_MSG_SetDisplayIdleOptimizations while SMU
still processing a previous VBIOSSMC_MSG_SetHardMinDcfclkByFreq message.

[how]
same as RN, change the time out to2s.

Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
index cfa8e02cf103..68942bbc7472 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
@@ -103,7 +103,7 @@ int dcn301_smu_send_msg_with_param(
 	/* Trigger the message transaction by writing the message ID */
 	REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
 
-	result = dcn301_smu_wait_for_response(clk_mgr, 10, 1000);
+	result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000);
 
 	ASSERT(result == VBIOSSMC_Result_OK);
 
-- 
2.25.1

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Re: [PATCH 00/21] DC Patches January 08, 2021

[Rodrigo Siqueira]

[-- Attachment #1.1: Type: text/plain, Size: 4218 bytes --]

+Daniel

On 01/08, Rodrigo Siqueira wrote:
> Happy new year, this is the first code promotion of the year; for this
> reason, most of the changes are related to fixes.
> 
> This DC patchset brings improvements in multiple areas. In summary, we have:
> * Multiple fixes and code refactoring.
> * Updates on HUBP operations
> 
> Best Regards
> 
> Aric Cyr (2):
>   drm/amd/display: 3.2.117
>   drm/amd/display: 3.2.118
> 
> Bhawanpreet Lakha (1):
>   drm/amd/display: enable HUBP blank behaviour
> 
> Charlene Liu (1):
>   drm/amd/display: change SMU repsonse timeout to 2s
> 
> Chiawen Huang (1):
>   drm/amd/display: removed unnecessary check when dpp clock increasing
> 
> Jacky Liao (1):
>   drm/amd/display: Fix assert being hit with GAMCOR memory shut down
> 
> Jun Lei (1):
>   drm/amd/display: implement T12 compliance
> 
> Lewis Huang (1):
>   drm/amd/display: Separate fec debug flag and monitor patch
> 
> Li, Roman (1):
>   drm/amd/display: disable dcn10 pipe split by default
> 
> Mike Hsieh (1):
>   drm/amd/display: Remove unused P010 debug flag
> 
> Nikola Cornij (1):
>   drm/amd/display: Add a missing DCN3.01 API mapping
> 
> Qingqing Zhuo (1):
>   drm/amd/display: NULL pointer hang
> 
> Raymond Yang (1):
>   drm/amd/display: fix seamless boot stream adding algorithm
> 
> Stylon Wang (1):
>   drm/amd/display: Revert patch causing black screen
> 
> Wesley Chalmers (6):
>   drm/amd/display: Initialize stack variable
>   drm/amd/display: HUBP_IN_BLANK for DCN30
>   drm/amd/display: Remove HUBP_DISABLE from default
>   drm/amd/display: Unblank hubp based on plane visibility
>   drm/amd/display: New path for enabling DPG
>   drm/amd/display: New sequence for HUBP blank
> 
> Yu-ting Shen (1):
>   drm/amd/display: doesn't reprogram AMD OUI
> 
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  1 -
>  .../gpu/drm/amd/display/dc/basics/dc_common.c | 20 ++++--
>  .../gpu/drm/amd/display/dc/basics/dc_common.h |  4 +-
>  .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  |  3 +-
>  .../display/dc/clk_mgr/dcn301/dcn301_smu.c    |  2 +-
>  drivers/gpu/drm/amd/display/dc/core/dc.c      | 12 ++++
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 31 ++++++--
>  .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 49 +++++++++----
>  .../gpu/drm/amd/display/dc/core/dc_resource.c | 28 +++++---
>  drivers/gpu/drm/amd/display/dc/dc.h           |  3 +-
>  drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  3 +
>  drivers/gpu/drm/amd/display/dc/dc_link.h      |  8 +++
>  drivers/gpu/drm/amd/display/dc/dc_stream.h    | 11 +++
>  .../display/dc/dce110/dce110_hw_sequencer.c   | 31 ++++++++
>  .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |  2 +-
>  .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 36 ++++++++--
>  .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  5 ++
>  .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |  1 +
>  .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  |  2 +-
>  .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 11 +++
>  .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |  1 +
>  .../drm/amd/display/dc/dcn10/dcn10_resource.c |  4 +-
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 22 ++++--
>  .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 12 +++-
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |  1 +
>  .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |  1 +
>  .../drm/amd/display/dc/dcn30/dcn30_dpp_cm.c   |  7 --
>  .../gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h |  1 +
>  .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    | 70 ++++++++++++++++++-
>  .../drm/amd/display/dc/dcn30/dcn30_hwseq.h    |  4 ++
>  .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |  2 +
>  .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c |  1 +
>  .../drm/amd/display/dc/dcn301/dcn301_init.c   |  1 +
>  .../amd/display/dc/dcn301/dcn301_resource.c   |  1 +
>  .../dc/dml/dcn30/display_mode_vba_30.c        |  2 +-
>  .../gpu/drm/amd/display/dc/inc/core_types.h   |  1 +
>  .../amd/display/dc/inc/hw/timing_generator.h  |  1 +
>  .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  5 ++
>  38 files changed, 332 insertions(+), 68 deletions(-)
> 
> -- 
> 2.25.1
> 

-- 
Rodrigo Siqueira
https://siqueira.tech

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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RE: [PATCH 00/21] DC Patches January 08, 2021

[Wheeler, Daniel]

[AMD Public Use]

Hi all,

Ran the promotion test this week on Navi14 and a Renoir laptop (HP Envy 360 with Ryzen 5 4500U). Tested the laptop with it's internal 1080p display and externally with USB-C to DP and HDMI to 2x 4k60 displays and 1x 1440p 144hz display. Also tested using an MST hub with 2x 4k30. I found nothing causing any visual impact, and did notice that this promotion did fix some previous bugs that I had seen.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>

Thank you,

Dan Wheeler
Technologist  |  AMD
SW Display

-----Original Message-----
From: Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com> 
Sent: Friday, January 8, 2021 5:12 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Zhuo, Qingqing <Qingqing.Zhuo@amd.com>; Brol, Eryk <Eryk.Brol@amd.com>; R, Bindu <Bindu.R@amd.com>; Li, Roman <Roman.Li@amd.com>; Wheeler, Daniel <Daniel.Wheeler@amd.com>
Subject: Re: [PATCH 00/21] DC Patches January 08, 2021

+Daniel

On 01/08, Rodrigo Siqueira wrote:
> Happy new year, this is the first code promotion of the year; for this 
> reason, most of the changes are related to fixes.
> 
> This DC patchset brings improvements in multiple areas. In summary, we have:
> * Multiple fixes and code refactoring.
> * Updates on HUBP operations
> 
> Best Regards
> 
> Aric Cyr (2):
>   drm/amd/display: 3.2.117
>   drm/amd/display: 3.2.118
> 
> Bhawanpreet Lakha (1):
>   drm/amd/display: enable HUBP blank behaviour
> 
> Charlene Liu (1):
>   drm/amd/display: change SMU repsonse timeout to 2s
> 
> Chiawen Huang (1):
>   drm/amd/display: removed unnecessary check when dpp clock increasing
> 
> Jacky Liao (1):
>   drm/amd/display: Fix assert being hit with GAMCOR memory shut down
> 
> Jun Lei (1):
>   drm/amd/display: implement T12 compliance
> 
> Lewis Huang (1):
>   drm/amd/display: Separate fec debug flag and monitor patch
> 
> Li, Roman (1):
>   drm/amd/display: disable dcn10 pipe split by default
> 
> Mike Hsieh (1):
>   drm/amd/display: Remove unused P010 debug flag
> 
> Nikola Cornij (1):
>   drm/amd/display: Add a missing DCN3.01 API mapping
> 
> Qingqing Zhuo (1):
>   drm/amd/display: NULL pointer hang
> 
> Raymond Yang (1):
>   drm/amd/display: fix seamless boot stream adding algorithm
> 
> Stylon Wang (1):
>   drm/amd/display: Revert patch causing black screen
> 
> Wesley Chalmers (6):
>   drm/amd/display: Initialize stack variable
>   drm/amd/display: HUBP_IN_BLANK for DCN30
>   drm/amd/display: Remove HUBP_DISABLE from default
>   drm/amd/display: Unblank hubp based on plane visibility
>   drm/amd/display: New path for enabling DPG
>   drm/amd/display: New sequence for HUBP blank
> 
> Yu-ting Shen (1):
>   drm/amd/display: doesn't reprogram AMD OUI
> 
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  1 -  
> .../gpu/drm/amd/display/dc/basics/dc_common.c | 20 ++++--  
> .../gpu/drm/amd/display/dc/basics/dc_common.h |  4 +-  
> .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  |  3 +-
>  .../display/dc/clk_mgr/dcn301/dcn301_smu.c    |  2 +-
>  drivers/gpu/drm/amd/display/dc/core/dc.c      | 12 ++++
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 31 ++++++--  
> .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 49 +++++++++----  
> .../gpu/drm/amd/display/dc/core/dc_resource.c | 28 +++++---
>  drivers/gpu/drm/amd/display/dc/dc.h           |  3 +-
>  drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  3 +
>  drivers/gpu/drm/amd/display/dc/dc_link.h      |  8 +++
>  drivers/gpu/drm/amd/display/dc/dc_stream.h    | 11 +++
>  .../display/dc/dce110/dce110_hw_sequencer.c   | 31 ++++++++
>  .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |  2 +-  
> .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 36 ++++++++--  
> .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  5 ++  
> .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |  1 +  
> .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  |  2 +-  
> .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 11 +++  
> .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |  1 +  
> .../drm/amd/display/dc/dcn10/dcn10_resource.c |  4 +-  
> .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 22 ++++--
>  .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 12 +++-
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |  1 +  
> .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |  1 +
>  .../drm/amd/display/dc/dcn30/dcn30_dpp_cm.c   |  7 --
>  .../gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h |  1 +
>  .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    | 70 ++++++++++++++++++-
>  .../drm/amd/display/dc/dcn30/dcn30_hwseq.h    |  4 ++
>  .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |  2 +  
> .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c |  1 +
>  .../drm/amd/display/dc/dcn301/dcn301_init.c   |  1 +
>  .../amd/display/dc/dcn301/dcn301_resource.c   |  1 +
>  .../dc/dml/dcn30/display_mode_vba_30.c        |  2 +-
>  .../gpu/drm/amd/display/dc/inc/core_types.h   |  1 +
>  .../amd/display/dc/inc/hw/timing_generator.h  |  1 +  
> .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  5 ++
>  38 files changed, 332 insertions(+), 68 deletions(-)
> 
> --
> 2.25.1
> 

-- 
Rodrigo Siqueira
https://siqueira.tech
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Re: [PATCH 06/21] drm/amd/display: Remove HUBP_DISABLE from default

[Rodrigo Siqueira]

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Hi,

After a discussion, we decided to drop this patch from the weekly
promotion. Please, don't apply this change to amd-staging-drm-next.

Thanks

On 01/08, Rodrigo Siqueira wrote:
> From: Wesley Chalmers <Wesley.Chalmers@amd.com>
> 
> [WHY]
> HW team plans to rename HUBP_DISABLE to HUBP_SOFT_RESET in future HW
> revisions. Those future revisions should not inherit the HUBP_DISABLE
> name.
> 
> Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
>  .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |  2 +-
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 22 ++++++++++++++-----
>  2 files changed, 18 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
> index a9a6ed7f4f99..80794fed6e20 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
> @@ -450,7 +450,6 @@
>  
>  #define DCN_HUBP_REG_FIELD_BASE_LIST(type) \
>  	type HUBP_BLANK_EN;\
> -	type HUBP_DISABLE;\
>  	type HUBP_TTU_DISABLE;\
>  	type HUBP_NO_OUTSTANDING_REQ;\
>  	type HUBP_VTG_SEL;\
> @@ -644,6 +643,7 @@
>  
>  #define DCN_HUBP_REG_FIELD_LIST(type) \
>  	DCN_HUBP_REG_FIELD_BASE_LIST(type);\
> +	type HUBP_DISABLE;\
>  	type ALPHA_PLANE_EN
>  
>  struct dcn_mi_registers {
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
> index f501c02c244b..98ec1f9171b6 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
> @@ -161,7 +161,7 @@
>  	DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\
>  	uint32_t DCN_DMDATA_VM_CNTL
>  
> -#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
> +#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type) \
>  	DCN_HUBP_REG_FIELD_BASE_LIST(type); \
>  	type DMDATA_ADDRESS_HIGH;\
>  	type DMDATA_MODE;\
> @@ -186,8 +186,12 @@
>  	type SURFACE_TRIPLE_BUFFER_ENABLE;\
>  	type VMID
>  
> -#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \
> -	DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\
> +#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
> +	DCN2_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type); \
> +	type HUBP_DISABLE
> +
> +#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type) \
> +	DCN2_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type);\
>  	type REFCYC_PER_VM_GROUP_FLIP;\
>  	type REFCYC_PER_VM_REQ_FLIP;\
>  	type REFCYC_PER_VM_GROUP_VBLANK;\
> @@ -196,8 +200,12 @@
>  	type REFCYC_PER_META_CHUNK_FLIP_C; \
>  	type VM_GROUP_SIZE
>  
> -#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \
> -	DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\
> +#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \
> +	DCN21_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type);\
> +	type HUBP_DISABLE
> +
> +#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type) \
> +	DCN21_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type);\
>  	type PRIMARY_SURFACE_DCC_IND_BLK;\
>  	type SECONDARY_SURFACE_DCC_IND_BLK;\
>  	type PRIMARY_SURFACE_DCC_IND_BLK_C;\
> @@ -216,6 +224,10 @@
>  	type ROW_TTU_MODE; \
>  	type NUM_PKRS
>  
> +#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \
> +	DCN30_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type);\
> +	type HUBP_DISABLE
> +
>  struct dcn_hubp2_registers {
>  	DCN30_HUBP_REG_COMMON_VARIABLE_LIST;
>  };
> -- 
> 2.25.1
> 

-- 
Rodrigo Siqueira
https://siqueira.tech

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