* [PATCH v7 0/6] RISC-V Pointer Masking implementation
@ 2021-01-10 18:51 ` Alexey Baturo
0 siblings, 0 replies; 27+ messages in thread
From: Alexey Baturo @ 2021-01-10 18:51 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv
Hi folks,
Sorry it took me almost 3 month to provide the reply and fixes: it was a really busy EOY.
This series contains fixed @Alistair suggestion on enabling J-ext.
As for @Richard comments:
- Indeed I've missed appending review-by to the approved commits. Now I've restored them except for the fourth commit. @Richard could you please tell if you think it's still ok to commit it as is, or should I support masking mem ops for RVV first?
- These patches don't have any support for load/store masking for RVV and RVH extensions, so no support for special load/store for Hypervisor in particular.
If this patch series would be accepted, I think my further attention would be to:
- Support pm for memory operations for RVV
- Add proper csr and support pm for memory operations for Hypervisor mode
- Support address wrapping on unaligned accesses as @Richard mentioned previously
Thanks!
Alexey Baturo (5):
[RISCV_PM] Add J-extension into RISC-V
[RISCV_PM] Support CSRs required for RISC-V PM extension except for
the ones required for hypervisor mode
[RISCV_PM] Print new PM CSRs in QEMU logs
[RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
instructions
[RISCV_PM] Allow experimental J-ext to be turned on
Anatoly Parshintsev (1):
[RISCV_PM] Implement address masking functions required for RISC-V
Pointer Masking extension
target/riscv/cpu.c | 30 +++
target/riscv/cpu.h | 33 +++
target/riscv/cpu_bits.h | 66 ++++++
target/riscv/csr.c | 271 ++++++++++++++++++++++++
target/riscv/insn_trans/trans_rva.c.inc | 3 +
target/riscv/insn_trans/trans_rvd.c.inc | 2 +
target/riscv/insn_trans/trans_rvf.c.inc | 2 +
target/riscv/insn_trans/trans_rvi.c.inc | 2 +
target/riscv/translate.c | 44 ++++
9 files changed, 453 insertions(+)
--
2.20.1
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH v7 1/6] [RISCV_PM] Add J-extension into RISC-V
2021-01-10 18:51 ` Alexey Baturo
@ 2021-01-10 18:51 ` Alexey Baturo
-1 siblings, 0 replies; 27+ messages in thread
From: Alexey Baturo @ 2021-01-10 18:51 UTC (permalink / raw)
Cc: baturo.alexey, qemu-riscv, sagark, kbastian, richard.henderson,
qemu-devel, space.monkey.delivers, Alistair.Francis,
kupokupokupopo, palmer
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6339e84819..d152842e37 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -72,6 +72,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVJ RV('J')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -285,6 +286,7 @@ struct RISCVCPU {
bool ext_s;
bool ext_u;
bool ext_h;
+ bool ext_j;
bool ext_v;
bool ext_counters;
bool ext_ifencei;
--
2.20.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v7 1/6] [RISCV_PM] Add J-extension into RISC-V
@ 2021-01-10 18:51 ` Alexey Baturo
0 siblings, 0 replies; 27+ messages in thread
From: Alexey Baturo @ 2021-01-10 18:51 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6339e84819..d152842e37 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -72,6 +72,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVJ RV('J')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -285,6 +286,7 @@ struct RISCVCPU {
bool ext_s;
bool ext_u;
bool ext_h;
+ bool ext_j;
bool ext_v;
bool ext_counters;
bool ext_ifencei;
--
2.20.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v7 1/6] [RISCV_PM] Add J-extension into RISC-V
2021-01-10 18:51 ` Alexey Baturo
(?)
@ 2021-01-15 22:08 ` Alistair Francis
-1 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2021-01-15 22:08 UTC (permalink / raw)
To: Alexey Baturo
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, qemu-devel@nongnu.org Developers,
space.monkey.delivers, Alistair Francis, kupokupokupopo,
Palmer Dabbelt
On Sun, Jan 10, 2021 at 10:51 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 6339e84819..d152842e37 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -72,6 +72,7 @@
> #define RVS RV('S')
> #define RVU RV('U')
> #define RVH RV('H')
> +#define RVJ RV('J')
>
> /* S extension denotes that Supervisor mode exists, however it is possible
> to have a core that support S mode but does not have an MMU and there
> @@ -285,6 +286,7 @@ struct RISCVCPU {
> bool ext_s;
> bool ext_u;
> bool ext_h;
> + bool ext_j;
> bool ext_v;
> bool ext_counters;
> bool ext_ifencei;
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v7 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the ones required for hypervisor mode
2021-01-10 18:51 ` Alexey Baturo
@ 2021-01-10 18:51 ` Alexey Baturo
-1 siblings, 0 replies; 27+ messages in thread
From: Alexey Baturo @ 2021-01-10 18:51 UTC (permalink / raw)
Cc: baturo.alexey, qemu-riscv, sagark, kbastian, richard.henderson,
qemu-devel, space.monkey.delivers, Alistair.Francis,
kupokupokupopo, palmer
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 12 ++
target/riscv/cpu_bits.h | 66 ++++++++++
target/riscv/csr.c | 271 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 352 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8227d7aea9..d50f09b757 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -472,6 +472,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
+ if (cpu->cfg.ext_j) {
+ env->mmte |= PM_EXT_INITIAL;
+ }
if (cpu->cfg.ext_v) {
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d152842e37..37ea7f7802 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -234,6 +234,18 @@ struct CPURISCVState {
/* True if in debugger mode. */
bool debugger;
+
+ /*
+ * CSRs for PM
+ * TODO: move these csr to appropriate groups
+ */
+ target_ulong mmte;
+ target_ulong mpmmask;
+ target_ulong mpmbase;
+ target_ulong spmmask;
+ target_ulong spmbase;
+ target_ulong upmmask;
+ target_ulong upmbase;
#endif
float_status fp_status;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index b41e8836c3..c92d0896aa 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -354,6 +354,21 @@
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
+/* Custom user register */
+#define CSR_UMTE 0x8c0
+#define CSR_UPMMASK 0x8c1
+#define CSR_UPMBASE 0x8c2
+
+/* Custom machine register */
+#define CSR_MMTE 0x7c0
+#define CSR_MPMMASK 0x7c1
+#define CSR_MPMBASE 0x7c2
+
+/* Custom supervisor register */
+#define CSR_SMTE 0x9c0
+#define CSR_SPMMASK 0x9c1
+#define CSR_SPMBASE 0x9c2
+
/* Legacy Machine Protection and Translation (priv v1.9.1) */
#define CSR_MBASE 0x380
#define CSR_MBOUND 0x381
@@ -590,4 +605,55 @@
#define MIE_UTIE (1 << IRQ_U_TIMER)
#define MIE_SSIE (1 << IRQ_S_SOFT)
#define MIE_USIE (1 << IRQ_U_SOFT)
+
+/* general mte CSR bits*/
+#define PM_ENABLE 0x00000001ULL
+#define PM_CURRENT 0x00000002ULL
+#define PM_XS_MASK 0x00000003ULL
+
+/* PM XS bits values */
+#define PM_EXT_DISABLE 0x00000000ULL
+#define PM_EXT_INITIAL 0x00000001ULL
+#define PM_EXT_CLEAN 0x00000002ULL
+#define PM_EXT_DIRTY 0x00000003ULL
+
+/* offsets for every pair of control bits per each priv level */
+#define XS_OFFSET 0ULL
+#define U_OFFSET 2ULL
+#define S_OFFSET 4ULL
+#define M_OFFSET 6ULL
+
+#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
+#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
+#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
+#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
+#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
+#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
+
+/* mmte CSR bits */
+#define MMTE_PM_XS_BITS PM_XS_BITS
+#define MMTE_U_PM_ENABLE U_PM_ENABLE
+#define MMTE_U_PM_CURRENT U_PM_CURRENT
+#define MMTE_S_PM_ENABLE S_PM_ENABLE
+#define MMTE_S_PM_CURRENT S_PM_CURRENT
+#define MMTE_M_PM_ENABLE M_PM_ENABLE
+#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | \
+ MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | \
+ MMTE_M_PM_ENABLE | MMTE_PM_XS_BITS)
+
+/* smte CSR bits */
+#define SMTE_PM_XS_BITS PM_XS_BITS
+#define SMTE_U_PM_ENABLE U_PM_ENABLE
+#define SMTE_U_PM_CURRENT U_PM_CURRENT
+#define SMTE_S_PM_ENABLE S_PM_ENABLE
+#define SMTE_S_PM_CURRENT S_PM_CURRENT
+#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | \
+ SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | \
+ SMTE_PM_XS_BITS)
+
+/* umte CSR bits */
+#define UMTE_U_PM_ENABLE U_PM_ENABLE
+#define UMTE_U_PM_CURRENT U_PM_CURRENT
+#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT)
+
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 10ab82ed1f..28a3eaf18d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -192,6 +192,11 @@ static int hmode32(CPURISCVState *env, int csrno)
}
+static int umode(CPURISCVState *env, int csrno)
+{
+ return -!riscv_has_ext(env, RVU);
+}
+
static int pmp(CPURISCVState *env, int csrno)
{
return -!riscv_feature(env, RISCV_FEATURE_PMP);
@@ -1270,6 +1275,257 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+/*
+ * Functions to access Pointer Masking feature registers
+ * We have to check if current priv lvl could modify
+ * csr in given mode
+ */
+static int check_pm_current_disabled(CPURISCVState *env, int csrno)
+{
+ int csr_priv = get_field(csrno, 0xC00);
+ /*
+ * If priv lvls differ that means we're accessing csr from higher priv lvl,
+ * so allow the access
+ */
+ if (env->priv != csr_priv) {
+ return 0;
+ }
+ int cur_bit_pos;
+ switch (env->priv) {
+ case PRV_M:
+ /* m-mode is always allowed to modify registers, so allow */
+ return 0;
+ case PRV_S:
+ cur_bit_pos = S_PM_CURRENT;
+ break;
+ case PRV_U:
+ cur_bit_pos = U_PM_CURRENT;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ int pm_current = get_field(env->mmte, cur_bit_pos);
+ /* It's same priv lvl, so we allow to modify csr only if pm_current==1 */
+ return !pm_current;
+}
+
+static int read_mmte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ *val = 0;
+ return 0;
+ }
+ *val = env->mmte & MMTE_MASK;
+ return 0;
+}
+
+static int write_mmte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ target_ulong wpri_val = val & MMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "MMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ env->mmte = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_smte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ *val = 0;
+ return 0;
+ }
+ *val = env->mmte & SMTE_MASK;
+ return 0;
+}
+
+static int write_smte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ target_ulong wpri_val = val & SMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "SMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ target_ulong new_val = val | (env->mmte & ~SMTE_MASK);
+ write_mmte(env, csrno, new_val);
+ return 0;
+}
+
+static int read_umte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ *val = 0;
+ return 0;
+ }
+ *val = env->mmte & UMTE_MASK;
+ return 0;
+}
+
+static int write_umte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ target_ulong wpri_val = val & UMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "UMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ target_ulong new_val = val | (env->mmte & ~UMTE_MASK);
+ write_mmte(env, csrno, new_val);
+ return 0;
+}
+
+static int read_mpmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->mpmmask;
+ return 0;
+}
+
+static int write_mpmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ env->mpmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_spmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->spmmask;
+ return 0;
+}
+
+static int write_spmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->spmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_upmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->upmmask;
+ return 0;
+}
+
+static int write_upmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->upmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_mpmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->mpmbase;
+ return 0;
+}
+
+static int write_mpmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ env->mpmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_spmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->spmbase;
+ return 0;
+}
+
+static int write_spmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->spmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_upmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->upmbase;
+ return 0;
+}
+
+static int write_upmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->upmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
#endif
/*
@@ -1481,6 +1737,21 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
+ /* User Pointer Masking */
+ [CSR_UMTE] = { umode, read_umte, write_umte },
+ [CSR_UPMMASK] = { umode, read_upmmask, write_upmmask },
+ [CSR_UPMBASE] = { umode, read_upmbase, write_upmbase },
+
+ /* Machine Pointer Masking */
+ [CSR_MMTE] = { any, read_mmte, write_mmte },
+ [CSR_MPMMASK] = { any, read_mpmmask, write_mpmmask },
+ [CSR_MPMBASE] = { any, read_mpmbase, write_mpmbase },
+
+ /* Supervisor Pointer Masking */
+ [CSR_SMTE] = { smode, read_smte, write_smte },
+ [CSR_SPMMASK] = { smode, read_spmmask, write_spmmask },
+ [CSR_SPMBASE] = { smode, read_spmbase, write_spmbase },
+
/* Performance Counters */
[CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
[CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
--
2.20.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v7 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the ones required for hypervisor mode
@ 2021-01-10 18:51 ` Alexey Baturo
0 siblings, 0 replies; 27+ messages in thread
From: Alexey Baturo @ 2021-01-10 18:51 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 12 ++
target/riscv/cpu_bits.h | 66 ++++++++++
target/riscv/csr.c | 271 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 352 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8227d7aea9..d50f09b757 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -472,6 +472,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
+ if (cpu->cfg.ext_j) {
+ env->mmte |= PM_EXT_INITIAL;
+ }
if (cpu->cfg.ext_v) {
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d152842e37..37ea7f7802 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -234,6 +234,18 @@ struct CPURISCVState {
/* True if in debugger mode. */
bool debugger;
+
+ /*
+ * CSRs for PM
+ * TODO: move these csr to appropriate groups
+ */
+ target_ulong mmte;
+ target_ulong mpmmask;
+ target_ulong mpmbase;
+ target_ulong spmmask;
+ target_ulong spmbase;
+ target_ulong upmmask;
+ target_ulong upmbase;
#endif
float_status fp_status;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index b41e8836c3..c92d0896aa 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -354,6 +354,21 @@
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
+/* Custom user register */
+#define CSR_UMTE 0x8c0
+#define CSR_UPMMASK 0x8c1
+#define CSR_UPMBASE 0x8c2
+
+/* Custom machine register */
+#define CSR_MMTE 0x7c0
+#define CSR_MPMMASK 0x7c1
+#define CSR_MPMBASE 0x7c2
+
+/* Custom supervisor register */
+#define CSR_SMTE 0x9c0
+#define CSR_SPMMASK 0x9c1
+#define CSR_SPMBASE 0x9c2
+
/* Legacy Machine Protection and Translation (priv v1.9.1) */
#define CSR_MBASE 0x380
#define CSR_MBOUND 0x381
@@ -590,4 +605,55 @@
#define MIE_UTIE (1 << IRQ_U_TIMER)
#define MIE_SSIE (1 << IRQ_S_SOFT)
#define MIE_USIE (1 << IRQ_U_SOFT)
+
+/* general mte CSR bits*/
+#define PM_ENABLE 0x00000001ULL
+#define PM_CURRENT 0x00000002ULL
+#define PM_XS_MASK 0x00000003ULL
+
+/* PM XS bits values */
+#define PM_EXT_DISABLE 0x00000000ULL
+#define PM_EXT_INITIAL 0x00000001ULL
+#define PM_EXT_CLEAN 0x00000002ULL
+#define PM_EXT_DIRTY 0x00000003ULL
+
+/* offsets for every pair of control bits per each priv level */
+#define XS_OFFSET 0ULL
+#define U_OFFSET 2ULL
+#define S_OFFSET 4ULL
+#define M_OFFSET 6ULL
+
+#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
+#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
+#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
+#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
+#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
+#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
+
+/* mmte CSR bits */
+#define MMTE_PM_XS_BITS PM_XS_BITS
+#define MMTE_U_PM_ENABLE U_PM_ENABLE
+#define MMTE_U_PM_CURRENT U_PM_CURRENT
+#define MMTE_S_PM_ENABLE S_PM_ENABLE
+#define MMTE_S_PM_CURRENT S_PM_CURRENT
+#define MMTE_M_PM_ENABLE M_PM_ENABLE
+#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | \
+ MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | \
+ MMTE_M_PM_ENABLE | MMTE_PM_XS_BITS)
+
+/* smte CSR bits */
+#define SMTE_PM_XS_BITS PM_XS_BITS
+#define SMTE_U_PM_ENABLE U_PM_ENABLE
+#define SMTE_U_PM_CURRENT U_PM_CURRENT
+#define SMTE_S_PM_ENABLE S_PM_ENABLE
+#define SMTE_S_PM_CURRENT S_PM_CURRENT
+#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | \
+ SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | \
+ SMTE_PM_XS_BITS)
+
+/* umte CSR bits */
+#define UMTE_U_PM_ENABLE U_PM_ENABLE
+#define UMTE_U_PM_CURRENT U_PM_CURRENT
+#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT)
+
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 10ab82ed1f..28a3eaf18d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -192,6 +192,11 @@ static int hmode32(CPURISCVState *env, int csrno)
}
+static int umode(CPURISCVState *env, int csrno)
+{
+ return -!riscv_has_ext(env, RVU);
+}
+
static int pmp(CPURISCVState *env, int csrno)
{
return -!riscv_feature(env, RISCV_FEATURE_PMP);
@@ -1270,6 +1275,257 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+/*
+ * Functions to access Pointer Masking feature registers
+ * We have to check if current priv lvl could modify
+ * csr in given mode
+ */
+static int check_pm_current_disabled(CPURISCVState *env, int csrno)
+{
+ int csr_priv = get_field(csrno, 0xC00);
+ /*
+ * If priv lvls differ that means we're accessing csr from higher priv lvl,
+ * so allow the access
+ */
+ if (env->priv != csr_priv) {
+ return 0;
+ }
+ int cur_bit_pos;
+ switch (env->priv) {
+ case PRV_M:
+ /* m-mode is always allowed to modify registers, so allow */
+ return 0;
+ case PRV_S:
+ cur_bit_pos = S_PM_CURRENT;
+ break;
+ case PRV_U:
+ cur_bit_pos = U_PM_CURRENT;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ int pm_current = get_field(env->mmte, cur_bit_pos);
+ /* It's same priv lvl, so we allow to modify csr only if pm_current==1 */
+ return !pm_current;
+}
+
+static int read_mmte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ *val = 0;
+ return 0;
+ }
+ *val = env->mmte & MMTE_MASK;
+ return 0;
+}
+
+static int write_mmte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ target_ulong wpri_val = val & MMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "MMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ env->mmte = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_smte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ *val = 0;
+ return 0;
+ }
+ *val = env->mmte & SMTE_MASK;
+ return 0;
+}
+
+static int write_smte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ target_ulong wpri_val = val & SMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "SMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ target_ulong new_val = val | (env->mmte & ~SMTE_MASK);
+ write_mmte(env, csrno, new_val);
+ return 0;
+}
+
+static int read_umte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ *val = 0;
+ return 0;
+ }
+ *val = env->mmte & UMTE_MASK;
+ return 0;
+}
+
+static int write_umte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ target_ulong wpri_val = val & UMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "UMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ target_ulong new_val = val | (env->mmte & ~UMTE_MASK);
+ write_mmte(env, csrno, new_val);
+ return 0;
+}
+
+static int read_mpmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->mpmmask;
+ return 0;
+}
+
+static int write_mpmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ env->mpmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_spmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->spmmask;
+ return 0;
+}
+
+static int write_spmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->spmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_upmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->upmmask;
+ return 0;
+}
+
+static int write_upmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->upmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_mpmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->mpmbase;
+ return 0;
+}
+
+static int write_mpmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ env->mpmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_spmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->spmbase;
+ return 0;
+}
+
+static int write_spmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->spmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_upmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->upmbase;
+ return 0;
+}
+
+static int write_upmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->upmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
#endif
/*
@@ -1481,6 +1737,21 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
+ /* User Pointer Masking */
+ [CSR_UMTE] = { umode, read_umte, write_umte },
+ [CSR_UPMMASK] = { umode, read_upmmask, write_upmmask },
+ [CSR_UPMBASE] = { umode, read_upmbase, write_upmbase },
+
+ /* Machine Pointer Masking */
+ [CSR_MMTE] = { any, read_mmte, write_mmte },
+ [CSR_MPMMASK] = { any, read_mpmmask, write_mpmmask },
+ [CSR_MPMBASE] = { any, read_mpmbase, write_mpmbase },
+
+ /* Supervisor Pointer Masking */
+ [CSR_SMTE] = { smode, read_smte, write_smte },
+ [CSR_SPMMASK] = { smode, read_spmmask, write_spmmask },
+ [CSR_SPMBASE] = { smode, read_spmbase, write_spmbase },
+
/* Performance Counters */
[CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
[CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
--
2.20.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v7 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the ones required for hypervisor mode
2021-01-10 18:51 ` Alexey Baturo
(?)
@ 2021-02-03 19:19 ` Alistair Francis
-1 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2021-02-03 19:19 UTC (permalink / raw)
To: Alexey Baturo
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, qemu-devel@nongnu.org Developers,
space.monkey.delivers, Alistair Francis, kupokupokupopo,
Palmer Dabbelt
On Sun, Jan 10, 2021 at 10:56 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
> ---
> target/riscv/cpu.c | 3 +
> target/riscv/cpu.h | 12 ++
> target/riscv/cpu_bits.h | 66 ++++++++++
> target/riscv/csr.c | 271 ++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 352 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8227d7aea9..d50f09b757 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -472,6 +472,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> if (cpu->cfg.ext_h) {
> target_misa |= RVH;
> }
> + if (cpu->cfg.ext_j) {
> + env->mmte |= PM_EXT_INITIAL;
> + }
> if (cpu->cfg.ext_v) {
> target_misa |= RVV;
> if (!is_power_of_2(cpu->cfg.vlen)) {
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d152842e37..37ea7f7802 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -234,6 +234,18 @@ struct CPURISCVState {
>
> /* True if in debugger mode. */
> bool debugger;
> +
> + /*
> + * CSRs for PM
> + * TODO: move these csr to appropriate groups
> + */
> + target_ulong mmte;
> + target_ulong mpmmask;
> + target_ulong mpmbase;
> + target_ulong spmmask;
> + target_ulong spmbase;
> + target_ulong upmmask;
> + target_ulong upmbase;
> #endif
>
> float_status fp_status;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index b41e8836c3..c92d0896aa 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -354,6 +354,21 @@
> #define CSR_MHPMCOUNTER30H 0xb9e
> #define CSR_MHPMCOUNTER31H 0xb9f
>
> +/* Custom user register */
> +#define CSR_UMTE 0x8c0
> +#define CSR_UPMMASK 0x8c1
> +#define CSR_UPMBASE 0x8c2
> +
> +/* Custom machine register */
> +#define CSR_MMTE 0x7c0
> +#define CSR_MPMMASK 0x7c1
> +#define CSR_MPMBASE 0x7c2
> +
> +/* Custom supervisor register */
> +#define CSR_SMTE 0x9c0
> +#define CSR_SPMMASK 0x9c1
> +#define CSR_SPMBASE 0x9c2
> +
> /* Legacy Machine Protection and Translation (priv v1.9.1) */
> #define CSR_MBASE 0x380
> #define CSR_MBOUND 0x381
> @@ -590,4 +605,55 @@
> #define MIE_UTIE (1 << IRQ_U_TIMER)
> #define MIE_SSIE (1 << IRQ_S_SOFT)
> #define MIE_USIE (1 << IRQ_U_SOFT)
> +
> +/* general mte CSR bits*/
> +#define PM_ENABLE 0x00000001ULL
> +#define PM_CURRENT 0x00000002ULL
> +#define PM_XS_MASK 0x00000003ULL
> +
> +/* PM XS bits values */
> +#define PM_EXT_DISABLE 0x00000000ULL
> +#define PM_EXT_INITIAL 0x00000001ULL
> +#define PM_EXT_CLEAN 0x00000002ULL
> +#define PM_EXT_DIRTY 0x00000003ULL
> +
> +/* offsets for every pair of control bits per each priv level */
> +#define XS_OFFSET 0ULL
> +#define U_OFFSET 2ULL
> +#define S_OFFSET 4ULL
> +#define M_OFFSET 6ULL
> +
> +#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
> +#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
> +#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
> +#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
> +#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
> +#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
> +
> +/* mmte CSR bits */
> +#define MMTE_PM_XS_BITS PM_XS_BITS
> +#define MMTE_U_PM_ENABLE U_PM_ENABLE
> +#define MMTE_U_PM_CURRENT U_PM_CURRENT
> +#define MMTE_S_PM_ENABLE S_PM_ENABLE
> +#define MMTE_S_PM_CURRENT S_PM_CURRENT
> +#define MMTE_M_PM_ENABLE M_PM_ENABLE
> +#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | \
> + MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | \
> + MMTE_M_PM_ENABLE | MMTE_PM_XS_BITS)
> +
> +/* smte CSR bits */
> +#define SMTE_PM_XS_BITS PM_XS_BITS
> +#define SMTE_U_PM_ENABLE U_PM_ENABLE
> +#define SMTE_U_PM_CURRENT U_PM_CURRENT
> +#define SMTE_S_PM_ENABLE S_PM_ENABLE
> +#define SMTE_S_PM_CURRENT S_PM_CURRENT
> +#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | \
> + SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | \
> + SMTE_PM_XS_BITS)
> +
> +/* umte CSR bits */
> +#define UMTE_U_PM_ENABLE U_PM_ENABLE
> +#define UMTE_U_PM_CURRENT U_PM_CURRENT
> +#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT)
> +
> #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 10ab82ed1f..28a3eaf18d 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -192,6 +192,11 @@ static int hmode32(CPURISCVState *env, int csrno)
>
> }
>
> +static int umode(CPURISCVState *env, int csrno)
> +{
> + return -!riscv_has_ext(env, RVU);
> +}
> +
> static int pmp(CPURISCVState *env, int csrno)
> {
> return -!riscv_feature(env, RISCV_FEATURE_PMP);
> @@ -1270,6 +1275,257 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
> return 0;
> }
>
> +/*
> + * Functions to access Pointer Masking feature registers
> + * We have to check if current priv lvl could modify
> + * csr in given mode
> + */
> +static int check_pm_current_disabled(CPURISCVState *env, int csrno)
> +{
> + int csr_priv = get_field(csrno, 0xC00);
> + /*
> + * If priv lvls differ that means we're accessing csr from higher priv lvl,
> + * so allow the access
> + */
> + if (env->priv != csr_priv) {
> + return 0;
> + }
> + int cur_bit_pos;
> + switch (env->priv) {
> + case PRV_M:
> + /* m-mode is always allowed to modify registers, so allow */
> + return 0;
> + case PRV_S:
> + cur_bit_pos = S_PM_CURRENT;
> + break;
> + case PRV_U:
> + cur_bit_pos = U_PM_CURRENT;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + int pm_current = get_field(env->mmte, cur_bit_pos);
> + /* It's same priv lvl, so we allow to modify csr only if pm_current==1 */
> + return !pm_current;
> +}
This check and `if (!riscv_has_ext(env, RVJ))` seems to be repeated a
lot. It's probably worth having an access function to do all of the
checking. See the `hmode()` function for what this would look like.
Alistair
> +
> +static int read_mmte(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + *val = 0;
> + return 0;
> + }
> + *val = env->mmte & MMTE_MASK;
> + return 0;
> +}
> +
> +static int write_mmte(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + target_ulong wpri_val = val & MMTE_MASK;
> + if (val != wpri_val) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "MMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
> + val, wpri_val);
> + }
> + env->mmte = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> +static int read_smte(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + *val = 0;
> + return 0;
> + }
> + *val = env->mmte & SMTE_MASK;
> + return 0;
> +}
> +
> +static int write_smte(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + target_ulong wpri_val = val & SMTE_MASK;
> + if (val != wpri_val) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "SMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
> + val, wpri_val);
> + }
> + if (check_pm_current_disabled(env, csrno)) {
> + return 0;
> + }
> + target_ulong new_val = val | (env->mmte & ~SMTE_MASK);
> + write_mmte(env, csrno, new_val);
> + return 0;
> +}
> +
> +static int read_umte(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + *val = 0;
> + return 0;
> + }
> + *val = env->mmte & UMTE_MASK;
> + return 0;
> +}
> +
> +static int write_umte(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + target_ulong wpri_val = val & UMTE_MASK;
> + if (val != wpri_val) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "UMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
> + val, wpri_val);
> + }
> + if (check_pm_current_disabled(env, csrno)) {
> + return 0;
> + }
> + target_ulong new_val = val | (env->mmte & ~UMTE_MASK);
> + write_mmte(env, csrno, new_val);
> + return 0;
> +}
> +
> +static int read_mpmmask(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + *val = env->mpmmask;
> + return 0;
> +}
> +
> +static int write_mpmmask(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + env->mpmmask = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> +static int read_spmmask(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + *val = env->spmmask;
> + return 0;
> +}
> +
> +static int write_spmmask(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + if (check_pm_current_disabled(env, csrno)) {
> + return 0;
> + }
> + env->spmmask = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> +static int read_upmmask(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + *val = env->upmmask;
> + return 0;
> +}
> +
> +static int write_upmmask(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + if (check_pm_current_disabled(env, csrno)) {
> + return 0;
> + }
> + env->upmmask = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> +static int read_mpmbase(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + *val = env->mpmbase;
> + return 0;
> +}
> +
> +static int write_mpmbase(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + env->mpmbase = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> +static int read_spmbase(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + *val = env->spmbase;
> + return 0;
> +}
> +
> +static int write_spmbase(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + if (check_pm_current_disabled(env, csrno)) {
> + return 0;
> + }
> + env->spmbase = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> +static int read_upmbase(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + *val = env->upmbase;
> + return 0;
> +}
> +
> +static int write_upmbase(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (!riscv_has_ext(env, RVJ)) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + if (check_pm_current_disabled(env, csrno)) {
> + return 0;
> + }
> + env->upmbase = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> #endif
>
> /*
> @@ -1481,6 +1737,21 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg },
> [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
>
> + /* User Pointer Masking */
> + [CSR_UMTE] = { umode, read_umte, write_umte },
> + [CSR_UPMMASK] = { umode, read_upmmask, write_upmmask },
> + [CSR_UPMBASE] = { umode, read_upmbase, write_upmbase },
> +
> + /* Machine Pointer Masking */
> + [CSR_MMTE] = { any, read_mmte, write_mmte },
> + [CSR_MPMMASK] = { any, read_mpmmask, write_mpmmask },
> + [CSR_MPMBASE] = { any, read_mpmbase, write_mpmbase },
> +
> + /* Supervisor Pointer Masking */
> + [CSR_SMTE] = { smode, read_smte, write_smte },
> + [CSR_SPMMASK] = { smode, read_spmmask, write_spmmask },
> + [CSR_SPMBASE] = { smode, read_spmbase, write_spmbase },
> +
> /* Performance Counters */
> [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
> [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v7 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
2021-01-10 18:51 ` Alexey Baturo
@ 2021-01-10 18:51 ` Alexey Baturo
-1 siblings, 0 replies; 27+ messages in thread
From: Alexey Baturo @ 2021-01-10 18:51 UTC (permalink / raw)
Cc: baturo.alexey, qemu-riscv, sagark, kbastian, richard.henderson,
qemu-devel, space.monkey.delivers, Alistair.Francis,
kupokupokupopo, palmer
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d50f09b757..19398977d3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -287,6 +287,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
}
+ if (riscv_has_ext(env, RVJ)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte);
+ switch (env->priv) {
+ case PRV_U:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ",
+ env->upmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ",
+ env->upmmask);
+ break;
+ case PRV_S:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ",
+ env->spmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ",
+ env->spmmask);
+ break;
+ case PRV_M:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ",
+ env->mpmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ",
+ env->mpmmask);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
#endif
for (i = 0; i < 32; i++) {
--
2.20.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v7 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
@ 2021-01-10 18:51 ` Alexey Baturo
0 siblings, 0 replies; 27+ messages in thread
From: Alexey Baturo @ 2021-01-10 18:51 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d50f09b757..19398977d3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -287,6 +287,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
}
+ if (riscv_has_ext(env, RVJ)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte);
+ switch (env->priv) {
+ case PRV_U:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ",
+ env->upmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ",
+ env->upmmask);
+ break;
+ case PRV_S:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ",
+ env->spmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ",
+ env->spmmask);
+ break;
+ case PRV_M:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ",
+ env->mpmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ",
+ env->mpmmask);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
#endif
for (i = 0; i < 32; i++) {
--
2.20.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v7 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
2021-01-10 18:51 ` Alexey Baturo
(?)
@ 2021-01-15 22:09 ` Alistair Francis
-1 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2021-01-15 22:09 UTC (permalink / raw)
To: Alexey Baturo
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, qemu-devel@nongnu.org Developers,
space.monkey.delivers, Alistair Francis, kupokupokupopo,
Palmer Dabbelt
On Sun, Jan 10, 2021 at 10:57 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d50f09b757..19398977d3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -287,6 +287,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
> }
> + if (riscv_has_ext(env, RVJ)) {
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte);
> + switch (env->priv) {
> + case PRV_U:
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ",
> + env->upmbase);
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ",
> + env->upmmask);
> + break;
> + case PRV_S:
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ",
> + env->spmbase);
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ",
> + env->spmmask);
> + break;
> + case PRV_M:
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ",
> + env->mpmbase);
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ",
> + env->mpmmask);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + }
> #endif
>
> for (i = 0; i < 32; i++) {
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v7 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
2021-01-10 18:51 ` Alexey Baturo
@ 2021-01-10 18:51 ` Alexey Baturo
-1 siblings, 0 replies; 27+ messages in thread
From: Alexey Baturo @ 2021-01-10 18:51 UTC (permalink / raw)
Cc: baturo.alexey, qemu-riscv, sagark, kbastian, richard.henderson,
qemu-devel, space.monkey.delivers, Alistair.Francis,
kupokupokupopo, palmer
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
target/riscv/insn_trans/trans_rva.c.inc | 3 +++
target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
target/riscv/translate.c | 14 ++++++++++++++
5 files changed, 23 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index be8a9f06dd..5559e347ba 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -26,6 +26,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
if (a->rl) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
+ gen_pm_adjust_address(ctx, src1, src1);
tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
if (a->aq) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -46,6 +47,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
TCGLabel *l2 = gen_new_label();
gen_get_gpr(src1, a->rs1);
+ gen_pm_adjust_address(ctx, src1, src1);
tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
gen_get_gpr(src2, a->rs2);
@@ -91,6 +93,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
gen_get_gpr(src1, a->rs1);
gen_get_gpr(src2, a->rs2);
+ gen_pm_adjust_address(ctx, src1, src1);
(*func)(src2, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(a->rd, src2);
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 4f832637fa..935342f66d 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -25,6 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
@@ -40,6 +41,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index 3dfec8211d..04b3c3eb3d 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -30,6 +30,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
@@ -47,6 +48,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index d04ca0394c..bee7f6be46 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -141,6 +141,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
TCGv t1 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
gen_set_gpr(a->rd, t1);
@@ -180,6 +181,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
TCGv dat = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
gen_get_gpr(dat, a->rs2);
tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 554d52a4be..5da7330f33 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -102,6 +102,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
}
+/*
+ * Temp stub: generates address adjustment for PointerMasking
+ */
+static void gen_pm_adjust_address(DisasContext *s,
+ TCGv_i64 dst,
+ TCGv_i64 src)
+{
+ tcg_gen_mov_i64(dst, src);
+}
+
/*
* A narrow n-bit operation, where n < FLEN, checks that input operands
* are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
@@ -381,6 +391,7 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
TCGv t1 = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_addi_tl(t0, t0, imm);
+ gen_pm_adjust_address(ctx, t0, t0);
int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
if (memop < 0) {
@@ -401,6 +412,7 @@ static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
TCGv dat = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_addi_tl(t0, t0, imm);
+ gen_pm_adjust_address(ctx, t0, t0);
gen_get_gpr(dat, rs2);
int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
@@ -460,6 +472,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_addi_tl(t0, t0, imm);
+ gen_pm_adjust_address(ctx, t0, t0);
switch (opc) {
case OPC_RISC_FLW:
@@ -499,6 +512,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_addi_tl(t0, t0, imm);
+ gen_pm_adjust_address(ctx, t0, t0);
switch (opc) {
case OPC_RISC_FSW:
--
2.20.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v7 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
@ 2021-01-10 18:51 ` Alexey Baturo
0 siblings, 0 replies; 27+ messages in thread
From: Alexey Baturo @ 2021-01-10 18:51 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
target/riscv/insn_trans/trans_rva.c.inc | 3 +++
target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
target/riscv/translate.c | 14 ++++++++++++++
5 files changed, 23 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index be8a9f06dd..5559e347ba 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -26,6 +26,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
if (a->rl) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
+ gen_pm_adjust_address(ctx, src1, src1);
tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
if (a->aq) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -46,6 +47,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
TCGLabel *l2 = gen_new_label();
gen_get_gpr(src1, a->rs1);
+ gen_pm_adjust_address(ctx, src1, src1);
tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
gen_get_gpr(src2, a->rs2);
@@ -91,6 +93,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
gen_get_gpr(src1, a->rs1);
gen_get_gpr(src2, a->rs2);
+ gen_pm_adjust_address(ctx, src1, src1);
(*func)(src2, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(a->rd, src2);
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 4f832637fa..935342f66d 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -25,6 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
@@ -40,6 +41,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index 3dfec8211d..04b3c3eb3d 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -30,6 +30,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
@@ -47,6 +48,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index d04ca0394c..bee7f6be46 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -141,6 +141,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
TCGv t1 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
gen_set_gpr(a->rd, t1);
@@ -180,6 +181,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
TCGv dat = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
gen_get_gpr(dat, a->rs2);
tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 554d52a4be..5da7330f33 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -102,6 +102,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
}
+/*
+ * Temp stub: generates address adjustment for PointerMasking
+ */
+static void gen_pm_adjust_address(DisasContext *s,
+ TCGv_i64 dst,
+ TCGv_i64 src)
+{
+ tcg_gen_mov_i64(dst, src);
+}
+
/*
* A narrow n-bit operation, where n < FLEN, checks that input operands
* are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
@@ -381,6 +391,7 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
TCGv t1 = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_addi_tl(t0, t0, imm);
+ gen_pm_adjust_address(ctx, t0, t0);
int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
if (memop < 0) {
@@ -401,6 +412,7 @@ static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
TCGv dat = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_addi_tl(t0, t0, imm);
+ gen_pm_adjust_address(ctx, t0, t0);
gen_get_gpr(dat, rs2);
int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
@@ -460,6 +472,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_addi_tl(t0, t0, imm);
+ gen_pm_adjust_address(ctx, t0, t0);
switch (opc) {
case OPC_RISC_FLW:
@@ -499,6 +512,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_addi_tl(t0, t0, imm);
+ gen_pm_adjust_address(ctx, t0, t0);
switch (opc) {
case OPC_RISC_FSW:
--
2.20.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v7 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
2021-01-10 18:51 ` Alexey Baturo
@ 2021-01-21 19:42 ` Richard Henderson
-1 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2021-01-21 19:42 UTC (permalink / raw)
To: Alexey Baturo
Cc: qemu-riscv, sagark, kbastian, qemu-devel, space.monkey.delivers,
Alistair.Francis, kupokupokupopo, palmer
On 1/10/21 8:51 AM, Alexey Baturo wrote:
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
> ---
> target/riscv/insn_trans/trans_rva.c.inc | 3 +++
> target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
> target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
> target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
> target/riscv/translate.c | 14 ++++++++++++++
> 5 files changed, 23 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> +static void gen_pm_adjust_address(DisasContext *s,
> + TCGv_i64 dst,
> + TCGv_i64 src)
Don't bother aligning variables like this. That just leads to additional
changes when code is adjusted later.
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v7 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
@ 2021-01-21 19:42 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2021-01-21 19:42 UTC (permalink / raw)
To: Alexey Baturo
Cc: space.monkey.delivers, kupokupokupopo, palmer, Alistair.Francis,
sagark, kbastian, qemu-devel, qemu-riscv
On 1/10/21 8:51 AM, Alexey Baturo wrote:
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
> ---
> target/riscv/insn_trans/trans_rva.c.inc | 3 +++
> target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
> target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
> target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
> target/riscv/translate.c | 14 ++++++++++++++
> 5 files changed, 23 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> +static void gen_pm_adjust_address(DisasContext *s,
> + TCGv_i64 dst,
> + TCGv_i64 src)
Don't bother aligning variables like this. That just leads to additional
changes when code is adjusted later.
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v7 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
2021-01-10 18:51 ` Alexey Baturo
(?)
(?)
@ 2021-02-03 19:20 ` Alistair Francis
-1 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2021-02-03 19:20 UTC (permalink / raw)
To: Alexey Baturo
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, qemu-devel@nongnu.org Developers,
space.monkey.delivers, Alistair Francis, kupokupokupopo,
Palmer Dabbelt
On Sun, Jan 10, 2021 at 10:51 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rva.c.inc | 3 +++
> target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
> target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
> target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
> target/riscv/translate.c | 14 ++++++++++++++
> 5 files changed, 23 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
> index be8a9f06dd..5559e347ba 100644
> --- a/target/riscv/insn_trans/trans_rva.c.inc
> +++ b/target/riscv/insn_trans/trans_rva.c.inc
> @@ -26,6 +26,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
> if (a->rl) {
> tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
> }
> + gen_pm_adjust_address(ctx, src1, src1);
> tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
> if (a->aq) {
> tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
> @@ -46,6 +47,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
> TCGLabel *l2 = gen_new_label();
>
> gen_get_gpr(src1, a->rs1);
> + gen_pm_adjust_address(ctx, src1, src1);
> tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
>
> gen_get_gpr(src2, a->rs2);
> @@ -91,6 +93,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
> gen_get_gpr(src1, a->rs1);
> gen_get_gpr(src2, a->rs2);
>
> + gen_pm_adjust_address(ctx, src1, src1);
> (*func)(src2, src1, src2, ctx->mem_idx, mop);
>
> gen_set_gpr(a->rd, src2);
> diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
> index 4f832637fa..935342f66d 100644
> --- a/target/riscv/insn_trans/trans_rvd.c.inc
> +++ b/target/riscv/insn_trans/trans_rvd.c.inc
> @@ -25,6 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
> TCGv t0 = tcg_temp_new();
> gen_get_gpr(t0, a->rs1);
> tcg_gen_addi_tl(t0, t0, a->imm);
> + gen_pm_adjust_address(ctx, t0, t0);
>
> tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
>
> @@ -40,6 +41,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
> TCGv t0 = tcg_temp_new();
> gen_get_gpr(t0, a->rs1);
> tcg_gen_addi_tl(t0, t0, a->imm);
> + gen_pm_adjust_address(ctx, t0, t0);
>
> tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
>
> diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
> index 3dfec8211d..04b3c3eb3d 100644
> --- a/target/riscv/insn_trans/trans_rvf.c.inc
> +++ b/target/riscv/insn_trans/trans_rvf.c.inc
> @@ -30,6 +30,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
> TCGv t0 = tcg_temp_new();
> gen_get_gpr(t0, a->rs1);
> tcg_gen_addi_tl(t0, t0, a->imm);
> + gen_pm_adjust_address(ctx, t0, t0);
>
> tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
> gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
> @@ -47,6 +48,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
> gen_get_gpr(t0, a->rs1);
>
> tcg_gen_addi_tl(t0, t0, a->imm);
> + gen_pm_adjust_address(ctx, t0, t0);
>
> tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index d04ca0394c..bee7f6be46 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -141,6 +141,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
> TCGv t1 = tcg_temp_new();
> gen_get_gpr(t0, a->rs1);
> tcg_gen_addi_tl(t0, t0, a->imm);
> + gen_pm_adjust_address(ctx, t0, t0);
>
> tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
> gen_set_gpr(a->rd, t1);
> @@ -180,6 +181,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
> TCGv dat = tcg_temp_new();
> gen_get_gpr(t0, a->rs1);
> tcg_gen_addi_tl(t0, t0, a->imm);
> + gen_pm_adjust_address(ctx, t0, t0);
> gen_get_gpr(dat, a->rs2);
>
> tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 554d52a4be..5da7330f33 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -102,6 +102,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
> tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
> }
>
> +/*
> + * Temp stub: generates address adjustment for PointerMasking
> + */
> +static void gen_pm_adjust_address(DisasContext *s,
> + TCGv_i64 dst,
> + TCGv_i64 src)
> +{
> + tcg_gen_mov_i64(dst, src);
> +}
> +
> /*
> * A narrow n-bit operation, where n < FLEN, checks that input operands
> * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
> @@ -381,6 +391,7 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
> TCGv t1 = tcg_temp_new();
> gen_get_gpr(t0, rs1);
> tcg_gen_addi_tl(t0, t0, imm);
> + gen_pm_adjust_address(ctx, t0, t0);
> int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
>
> if (memop < 0) {
> @@ -401,6 +412,7 @@ static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
> TCGv dat = tcg_temp_new();
> gen_get_gpr(t0, rs1);
> tcg_gen_addi_tl(t0, t0, imm);
> + gen_pm_adjust_address(ctx, t0, t0);
> gen_get_gpr(dat, rs2);
> int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
>
> @@ -460,6 +472,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
> t0 = tcg_temp_new();
> gen_get_gpr(t0, rs1);
> tcg_gen_addi_tl(t0, t0, imm);
> + gen_pm_adjust_address(ctx, t0, t0);
>
> switch (opc) {
> case OPC_RISC_FLW:
> @@ -499,6 +512,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
> t0 = tcg_temp_new();
> gen_get_gpr(t0, rs1);
> tcg_gen_addi_tl(t0, t0, imm);
> + gen_pm_adjust_address(ctx, t0, t0);
>
> switch (opc) {
> case OPC_RISC_FSW:
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v7 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
2021-01-10 18:51 ` Alexey Baturo
@ 2021-01-10 18:51 ` Alexey Baturo
-1 siblings, 0 replies; 27+ messages in thread
From: Alexey Baturo @ 2021-01-10 18:51 UTC (permalink / raw)
Cc: baturo.alexey, qemu-riscv, sagark, kbastian, richard.henderson,
qemu-devel, space.monkey.delivers, Alistair.Francis,
kupokupokupopo, palmer
From: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 19 +++++++++++++++++++
target/riscv/translate.c | 34 ++++++++++++++++++++++++++++++++--
2 files changed, 51 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 37ea7f7802..b3c63ca5ff 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -397,6 +397,7 @@ FIELD(TB_FLAGS, SEW, 5, 3)
FIELD(TB_FLAGS, VILL, 8, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 9, 1)
+FIELD(TB_FLAGS, PM_ENABLED, 10, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
@@ -454,6 +455,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
}
}
+ if (riscv_has_ext(env, RVJ)) {
+ int priv = cpu_mmu_index(env, false);
+ bool pm_enabled = false;
+ switch (priv) {
+ case PRV_U:
+ pm_enabled = env->mmte & U_PM_ENABLE;
+ break;
+ case PRV_S:
+ pm_enabled = env->mmte & S_PM_ENABLE;
+ break;
+ case PRV_M:
+ pm_enabled = env->mmte & M_PM_ENABLE;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
+ }
#endif
*pflags = flags;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5da7330f33..980604935d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
+/* globals for PM CSRs */
+static TCGv pm_mask[4];
+static TCGv pm_base[4];
#include "exec/gen-icount.h"
@@ -64,6 +67,10 @@ typedef struct DisasContext {
uint16_t vlen;
uint16_t mlen;
bool vl_eq_vlmax;
+ /* PointerMasking extension */
+ bool pm_enabled;
+ TCGv pm_mask;
+ TCGv pm_base;
} DisasContext;
#ifdef TARGET_RISCV64
@@ -103,13 +110,19 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
}
/*
- * Temp stub: generates address adjustment for PointerMasking
+ * Generates address adjustment for PointerMasking
*/
static void gen_pm_adjust_address(DisasContext *s,
TCGv_i64 dst,
TCGv_i64 src)
{
- tcg_gen_mov_i64(dst, src);
+ if (!s->pm_enabled) {
+ /* Load unmodified address */
+ tcg_gen_mov_i64(dst, src);
+ } else {
+ tcg_gen_andc_i64(dst, src, s->pm_mask);
+ tcg_gen_or_i64(dst, dst, s->pm_base);
+ }
}
/*
@@ -828,6 +841,10 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
+ ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
+ int priv = cpu_mmu_index(env, false);
+ ctx->pm_mask = pm_mask[priv];
+ ctx->pm_base = pm_base[priv];
}
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
@@ -947,4 +964,17 @@ void riscv_translate_init(void)
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
"load_val");
+ /* Assign PM CSRs to tcg globals */
+ pm_mask[PRV_U] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
+ pm_base[PRV_U] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
+ pm_mask[PRV_S] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
+ pm_base[PRV_S] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
+ pm_mask[PRV_M] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
+ pm_base[PRV_M] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
}
--
2.20.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v7 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
@ 2021-01-10 18:51 ` Alexey Baturo
0 siblings, 0 replies; 27+ messages in thread
From: Alexey Baturo @ 2021-01-10 18:51 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv
From: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 19 +++++++++++++++++++
target/riscv/translate.c | 34 ++++++++++++++++++++++++++++++++--
2 files changed, 51 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 37ea7f7802..b3c63ca5ff 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -397,6 +397,7 @@ FIELD(TB_FLAGS, SEW, 5, 3)
FIELD(TB_FLAGS, VILL, 8, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 9, 1)
+FIELD(TB_FLAGS, PM_ENABLED, 10, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
@@ -454,6 +455,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
}
}
+ if (riscv_has_ext(env, RVJ)) {
+ int priv = cpu_mmu_index(env, false);
+ bool pm_enabled = false;
+ switch (priv) {
+ case PRV_U:
+ pm_enabled = env->mmte & U_PM_ENABLE;
+ break;
+ case PRV_S:
+ pm_enabled = env->mmte & S_PM_ENABLE;
+ break;
+ case PRV_M:
+ pm_enabled = env->mmte & M_PM_ENABLE;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
+ }
#endif
*pflags = flags;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5da7330f33..980604935d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
+/* globals for PM CSRs */
+static TCGv pm_mask[4];
+static TCGv pm_base[4];
#include "exec/gen-icount.h"
@@ -64,6 +67,10 @@ typedef struct DisasContext {
uint16_t vlen;
uint16_t mlen;
bool vl_eq_vlmax;
+ /* PointerMasking extension */
+ bool pm_enabled;
+ TCGv pm_mask;
+ TCGv pm_base;
} DisasContext;
#ifdef TARGET_RISCV64
@@ -103,13 +110,19 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
}
/*
- * Temp stub: generates address adjustment for PointerMasking
+ * Generates address adjustment for PointerMasking
*/
static void gen_pm_adjust_address(DisasContext *s,
TCGv_i64 dst,
TCGv_i64 src)
{
- tcg_gen_mov_i64(dst, src);
+ if (!s->pm_enabled) {
+ /* Load unmodified address */
+ tcg_gen_mov_i64(dst, src);
+ } else {
+ tcg_gen_andc_i64(dst, src, s->pm_mask);
+ tcg_gen_or_i64(dst, dst, s->pm_base);
+ }
}
/*
@@ -828,6 +841,10 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
+ ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
+ int priv = cpu_mmu_index(env, false);
+ ctx->pm_mask = pm_mask[priv];
+ ctx->pm_base = pm_base[priv];
}
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
@@ -947,4 +964,17 @@ void riscv_translate_init(void)
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
"load_val");
+ /* Assign PM CSRs to tcg globals */
+ pm_mask[PRV_U] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
+ pm_base[PRV_U] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
+ pm_mask[PRV_S] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
+ pm_base[PRV_S] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
+ pm_mask[PRV_M] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
+ pm_base[PRV_M] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
}
--
2.20.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v7 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
2021-01-10 18:51 ` Alexey Baturo
(?)
@ 2021-02-03 19:27 ` Alistair Francis
-1 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2021-02-03 19:27 UTC (permalink / raw)
To: Alexey Baturo
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, qemu-devel@nongnu.org Developers,
space.monkey.delivers, Alistair Francis, kupokupokupopo,
Palmer Dabbelt
On Sun, Jan 10, 2021 at 10:53 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Anatoly Parshintsev <kupokupokupopo@gmail.com>
>
> Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/cpu.h | 19 +++++++++++++++++++
> target/riscv/translate.c | 34 ++++++++++++++++++++++++++++++++--
> 2 files changed, 51 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 37ea7f7802..b3c63ca5ff 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -397,6 +397,7 @@ FIELD(TB_FLAGS, SEW, 5, 3)
> FIELD(TB_FLAGS, VILL, 8, 1)
> /* Is a Hypervisor instruction load/store allowed? */
> FIELD(TB_FLAGS, HLSX, 9, 1)
> +FIELD(TB_FLAGS, PM_ENABLED, 10, 1)
Can you add a comment above this for what this is? PM could be lots of
different things.
>
> bool riscv_cpu_is_32bit(CPURISCVState *env);
>
> @@ -454,6 +455,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
> }
> }
> + if (riscv_has_ext(env, RVJ)) {
> + int priv = cpu_mmu_index(env, false);
> + bool pm_enabled = false;
> + switch (priv) {
> + case PRV_U:
> + pm_enabled = env->mmte & U_PM_ENABLE;
> + break;
> + case PRV_S:
> + pm_enabled = env->mmte & S_PM_ENABLE;
> + break;
> + case PRV_M:
> + pm_enabled = env->mmte & M_PM_ENABLE;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
> + }
> #endif
>
> *pflags = flags;
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 5da7330f33..980604935d 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
> static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
> static TCGv load_res;
> static TCGv load_val;
> +/* globals for PM CSRs */
> +static TCGv pm_mask[4];
> +static TCGv pm_base[4];
>
> #include "exec/gen-icount.h"
>
> @@ -64,6 +67,10 @@ typedef struct DisasContext {
> uint16_t vlen;
> uint16_t mlen;
> bool vl_eq_vlmax;
> + /* PointerMasking extension */
> + bool pm_enabled;
> + TCGv pm_mask;
> + TCGv pm_base;
> } DisasContext;
>
> #ifdef TARGET_RISCV64
> @@ -103,13 +110,19 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
> }
>
> /*
> - * Temp stub: generates address adjustment for PointerMasking
> + * Generates address adjustment for PointerMasking
> */
> static void gen_pm_adjust_address(DisasContext *s,
> TCGv_i64 dst,
> TCGv_i64 src)
> {
> - tcg_gen_mov_i64(dst, src);
> + if (!s->pm_enabled) {
> + /* Load unmodified address */
> + tcg_gen_mov_i64(dst, src);
> + } else {
> + tcg_gen_andc_i64(dst, src, s->pm_mask);
> + tcg_gen_or_i64(dst, dst, s->pm_base);
> + }
> }
>
> /*
> @@ -828,6 +841,10 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
> ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
> ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
> + ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
> + int priv = cpu_mmu_index(env, false);
Can you AND this with TB_FLAGS_PRIV_MMU_MASK?
Alistair
> + ctx->pm_mask = pm_mask[priv];
> + ctx->pm_base = pm_base[priv];
> }
>
> static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
> @@ -947,4 +964,17 @@ void riscv_translate_init(void)
> "load_res");
> load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
> "load_val");
> + /* Assign PM CSRs to tcg globals */
> + pm_mask[PRV_U] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
> + pm_base[PRV_U] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
> + pm_mask[PRV_S] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
> + pm_base[PRV_S] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
> + pm_mask[PRV_M] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
> + pm_base[PRV_M] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
> }
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v7 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
2021-01-10 18:51 ` Alexey Baturo
@ 2021-01-10 18:51 ` Alexey Baturo
-1 siblings, 0 replies; 27+ messages in thread
From: Alexey Baturo @ 2021-01-10 18:51 UTC (permalink / raw)
Cc: baturo.alexey, qemu-riscv, sagark, kbastian, richard.henderson,
qemu-devel, space.monkey.delivers, Alistair.Francis,
kupokupokupopo, palmer
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 19398977d3..234401c3c6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -499,6 +499,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
if (cpu->cfg.ext_j) {
env->mmte |= PM_EXT_INITIAL;
+ target_misa |= RVJ;
}
if (cpu->cfg.ext_v) {
target_misa |= RVV;
@@ -571,6 +572,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
--
2.20.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v7 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
@ 2021-01-10 18:51 ` Alexey Baturo
0 siblings, 0 replies; 27+ messages in thread
From: Alexey Baturo @ 2021-01-10 18:51 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 19398977d3..234401c3c6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -499,6 +499,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
if (cpu->cfg.ext_j) {
env->mmte |= PM_EXT_INITIAL;
+ target_misa |= RVJ;
}
if (cpu->cfg.ext_v) {
target_misa |= RVV;
@@ -571,6 +572,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
--
2.20.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v7 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
2021-01-10 18:51 ` Alexey Baturo
(?)
@ 2021-01-15 22:10 ` Alistair Francis
-1 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2021-01-15 22:10 UTC (permalink / raw)
To: Alexey Baturo
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, qemu-devel@nongnu.org Developers,
space.monkey.delivers, Alistair Francis, kupokupokupopo,
Palmer Dabbelt
On Sun, Jan 10, 2021 at 11:00 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 19398977d3..234401c3c6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -499,6 +499,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> }
> if (cpu->cfg.ext_j) {
> env->mmte |= PM_EXT_INITIAL;
> + target_misa |= RVJ;
> }
> if (cpu->cfg.ext_v) {
> target_misa |= RVV;
> @@ -571,6 +572,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
> /* This is experimental so mark with 'x-' */
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> + DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v7 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
2021-01-10 18:51 ` Alexey Baturo
@ 2021-01-21 19:45 ` Richard Henderson
-1 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2021-01-21 19:45 UTC (permalink / raw)
To: Alexey Baturo
Cc: qemu-riscv, sagark, kbastian, qemu-devel, space.monkey.delivers,
Alistair.Francis, kupokupokupopo, palmer
On 1/10/21 8:51 AM, Alexey Baturo wrote:
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v7 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
@ 2021-01-21 19:45 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2021-01-21 19:45 UTC (permalink / raw)
To: Alexey Baturo
Cc: space.monkey.delivers, kupokupokupopo, palmer, Alistair.Francis,
sagark, kbastian, qemu-devel, qemu-riscv
On 1/10/21 8:51 AM, Alexey Baturo wrote:
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v7 0/6] RISC-V Pointer Masking implementation
2021-01-10 18:51 ` Alexey Baturo
` (6 preceding siblings ...)
(?)
@ 2021-02-03 19:22 ` Alistair Francis
2021-02-15 20:52 ` Alexey Baturo
-1 siblings, 1 reply; 27+ messages in thread
From: Alistair Francis @ 2021-02-03 19:22 UTC (permalink / raw)
To: Alexey Baturo
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, qemu-devel@nongnu.org Developers,
space.monkey.delivers, Alistair Francis, kupokupokupopo,
Palmer Dabbelt
On Sun, Jan 10, 2021 at 10:54 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Hi folks,
>
> Sorry it took me almost 3 month to provide the reply and fixes: it was a really busy EOY.
> This series contains fixed @Alistair suggestion on enabling J-ext.
>
> As for @Richard comments:
> - Indeed I've missed appending review-by to the approved commits. Now I've restored them except for the fourth commit. @Richard could you please tell if you think it's still ok to commit it as is, or should I support masking mem ops for RVV first?
> - These patches don't have any support for load/store masking for RVV and RVH extensions, so no support for special load/store for Hypervisor in particular.
>
> If this patch series would be accepted, I think my further attention would be to:
> - Support pm for memory operations for RVV
> - Add proper csr and support pm for memory operations for Hypervisor mode
> - Support address wrapping on unaligned accesses as @Richard mentioned previously
Overall this looks fine.
Unfortunately it doesn't look like there is a release of the pointer
masking spec. Until there is a release (a draft release counts) we
can't accept it. We need a version to point to so that we can say "we
support v0.1 of the RISC-V pointer masking spec". Otherwise we are
chasing a moving target and users don't know what version we do/don't
support.
Do you know the current state of the spec?
Alistair
>
> Thanks!
>
> Alexey Baturo (5):
> [RISCV_PM] Add J-extension into RISC-V
> [RISCV_PM] Support CSRs required for RISC-V PM extension except for
> the ones required for hypervisor mode
> [RISCV_PM] Print new PM CSRs in QEMU logs
> [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
> instructions
> [RISCV_PM] Allow experimental J-ext to be turned on
>
> Anatoly Parshintsev (1):
> [RISCV_PM] Implement address masking functions required for RISC-V
> Pointer Masking extension
>
> target/riscv/cpu.c | 30 +++
> target/riscv/cpu.h | 33 +++
> target/riscv/cpu_bits.h | 66 ++++++
> target/riscv/csr.c | 271 ++++++++++++++++++++++++
> target/riscv/insn_trans/trans_rva.c.inc | 3 +
> target/riscv/insn_trans/trans_rvd.c.inc | 2 +
> target/riscv/insn_trans/trans_rvf.c.inc | 2 +
> target/riscv/insn_trans/trans_rvi.c.inc | 2 +
> target/riscv/translate.c | 44 ++++
> 9 files changed, 453 insertions(+)
>
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v7 0/6] RISC-V Pointer Masking implementation
2021-02-03 19:22 ` [PATCH v7 0/6] RISC-V Pointer Masking implementation Alistair Francis
@ 2021-02-15 20:52 ` Alexey Baturo
2021-02-16 0:01 ` Alistair Francis
0 siblings, 1 reply; 27+ messages in thread
From: Alexey Baturo @ 2021-02-15 20:52 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, qemu-devel@nongnu.org Developers,
space.monkey.delivers, Alistair Francis, Dave Smith,
Palmer Dabbelt
[-- Attachment #1: Type: text/plain, Size: 3367 bytes --]
Hi Alistair,
Sorry for the late reply.
>Do you know the current state of the spec?
As far as I can tell, the spec for PointerMasking is quite frozen: it has
not been updated for quite some time, but some of the clarifications have
not been included in the actual spec.
I'll ask the J workgroup if they could do draft release v0.1, while I'll
address the fixed you proposed in this patch series.
Meanwhile could you please tell, if it's ok to push several series of
patches to claim the support of i.e. v0.1 or it's mandatory to push all the
patches at once?
Thanks!
ср, 3 февр. 2021 г. в 22:22, Alistair Francis <alistair23@gmail.com>:
> On Sun, Jan 10, 2021 at 10:54 AM Alexey Baturo <baturo.alexey@gmail.com>
> wrote:
> >
> > Hi folks,
> >
> > Sorry it took me almost 3 month to provide the reply and fixes: it was a
> really busy EOY.
> > This series contains fixed @Alistair suggestion on enabling J-ext.
> >
> > As for @Richard comments:
> > - Indeed I've missed appending review-by to the approved commits. Now
> I've restored them except for the fourth commit. @Richard could you please
> tell if you think it's still ok to commit it as is, or should I support
> masking mem ops for RVV first?
> > - These patches don't have any support for load/store masking for RVV
> and RVH extensions, so no support for special load/store for Hypervisor in
> particular.
> >
> > If this patch series would be accepted, I think my further attention
> would be to:
> > - Support pm for memory operations for RVV
> > - Add proper csr and support pm for memory operations for Hypervisor mode
> > - Support address wrapping on unaligned accesses as @Richard mentioned
> previously
>
> Overall this looks fine.
>
> Unfortunately it doesn't look like there is a release of the pointer
> masking spec. Until there is a release (a draft release counts) we
> can't accept it. We need a version to point to so that we can say "we
> support v0.1 of the RISC-V pointer masking spec". Otherwise we are
> chasing a moving target and users don't know what version we do/don't
> support.
>
> Do you know the current state of the spec?
>
> Alistair
>
> >
> > Thanks!
> >
> > Alexey Baturo (5):
> > [RISCV_PM] Add J-extension into RISC-V
> > [RISCV_PM] Support CSRs required for RISC-V PM extension except for
> > the ones required for hypervisor mode
> > [RISCV_PM] Print new PM CSRs in QEMU logs
> > [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
> > instructions
> > [RISCV_PM] Allow experimental J-ext to be turned on
> >
> > Anatoly Parshintsev (1):
> > [RISCV_PM] Implement address masking functions required for RISC-V
> > Pointer Masking extension
> >
> > target/riscv/cpu.c | 30 +++
> > target/riscv/cpu.h | 33 +++
> > target/riscv/cpu_bits.h | 66 ++++++
> > target/riscv/csr.c | 271 ++++++++++++++++++++++++
> > target/riscv/insn_trans/trans_rva.c.inc | 3 +
> > target/riscv/insn_trans/trans_rvd.c.inc | 2 +
> > target/riscv/insn_trans/trans_rvf.c.inc | 2 +
> > target/riscv/insn_trans/trans_rvi.c.inc | 2 +
> > target/riscv/translate.c | 44 ++++
> > 9 files changed, 453 insertions(+)
> >
> > --
> > 2.20.1
> >
> >
>
[-- Attachment #2: Type: text/html, Size: 4182 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v7 0/6] RISC-V Pointer Masking implementation
2021-02-15 20:52 ` Alexey Baturo
@ 2021-02-16 0:01 ` Alistair Francis
0 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2021-02-16 0:01 UTC (permalink / raw)
To: Alexey Baturo
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, qemu-devel@nongnu.org Developers,
space.monkey.delivers, Alistair Francis, Dave Smith,
Palmer Dabbelt
On Mon, Feb 15, 2021 at 12:52 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Hi Alistair,
>
> Sorry for the late reply.
>
> >Do you know the current state of the spec?
> As far as I can tell, the spec for PointerMasking is quite frozen: it has not been updated for quite some time, but some of the clarifications have not been included in the actual spec.
> I'll ask the J workgroup if they could do draft release v0.1, while I'll address the fixed you proposed in this patch series.
> Meanwhile could you please tell, if it's ok to push several series of patches to claim the support of i.e. v0.1 or it's mandatory to push all the patches at once?
You can post multiple patches on the list, but I wouldn't claim to
support v0.1 until there is a v0.1 to claim.
For actual changes being merged we can only claim to support v0.1 when
there is a v0.1 and it is supported. We can push the patches in
stages, for example we can merge some tidy ups before merging the full
support, but we can't allow a user to enable support (or advertise it)
until it's fully supported.
Alistair
>
> Thanks!
>
> ср, 3 февр. 2021 г. в 22:22, Alistair Francis <alistair23@gmail.com>:
>>
>> On Sun, Jan 10, 2021 at 10:54 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>> >
>> > Hi folks,
>> >
>> > Sorry it took me almost 3 month to provide the reply and fixes: it was a really busy EOY.
>> > This series contains fixed @Alistair suggestion on enabling J-ext.
>> >
>> > As for @Richard comments:
>> > - Indeed I've missed appending review-by to the approved commits. Now I've restored them except for the fourth commit. @Richard could you please tell if you think it's still ok to commit it as is, or should I support masking mem ops for RVV first?
>> > - These patches don't have any support for load/store masking for RVV and RVH extensions, so no support for special load/store for Hypervisor in particular.
>> >
>> > If this patch series would be accepted, I think my further attention would be to:
>> > - Support pm for memory operations for RVV
>> > - Add proper csr and support pm for memory operations for Hypervisor mode
>> > - Support address wrapping on unaligned accesses as @Richard mentioned previously
>>
>> Overall this looks fine.
>>
>> Unfortunately it doesn't look like there is a release of the pointer
>> masking spec. Until there is a release (a draft release counts) we
>> can't accept it. We need a version to point to so that we can say "we
>> support v0.1 of the RISC-V pointer masking spec". Otherwise we are
>> chasing a moving target and users don't know what version we do/don't
>> support.
>>
>> Do you know the current state of the spec?
>>
>> Alistair
>>
>> >
>> > Thanks!
>> >
>> > Alexey Baturo (5):
>> > [RISCV_PM] Add J-extension into RISC-V
>> > [RISCV_PM] Support CSRs required for RISC-V PM extension except for
>> > the ones required for hypervisor mode
>> > [RISCV_PM] Print new PM CSRs in QEMU logs
>> > [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
>> > instructions
>> > [RISCV_PM] Allow experimental J-ext to be turned on
>> >
>> > Anatoly Parshintsev (1):
>> > [RISCV_PM] Implement address masking functions required for RISC-V
>> > Pointer Masking extension
>> >
>> > target/riscv/cpu.c | 30 +++
>> > target/riscv/cpu.h | 33 +++
>> > target/riscv/cpu_bits.h | 66 ++++++
>> > target/riscv/csr.c | 271 ++++++++++++++++++++++++
>> > target/riscv/insn_trans/trans_rva.c.inc | 3 +
>> > target/riscv/insn_trans/trans_rvd.c.inc | 2 +
>> > target/riscv/insn_trans/trans_rvf.c.inc | 2 +
>> > target/riscv/insn_trans/trans_rvi.c.inc | 2 +
>> > target/riscv/translate.c | 44 ++++
>> > 9 files changed, 453 insertions(+)
>> >
>> > --
>> > 2.20.1
>> >
>> >
^ permalink raw reply [flat|nested] 27+ messages in thread