* Re: [Intel-gfx] [PATCH v7 3/3] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
@ 2021-01-15 15:08 kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2021-01-15 15:08 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 6996 bytes --]
CC: kbuild-all(a)lists.01.org
In-Reply-To: <20210114201314.783648-4-imre.deak@intel.com>
References: <20210114201314.783648-4-imre.deak@intel.com>
TO: Imre Deak <imre.deak@intel.com>
TO: intel-gfx(a)lists.freedesktop.org
CC: Nanley G Chery <nanley.g.chery@intel.com>
CC: Rafael Antognolli <rafael.antognolli@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
CC: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
CC: Ville Syrjala <ville.syrjala@intel.com>
CC: Shashank Sharma <shashank.sharma@intel.com>
Hi Imre,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20210115]
[cannot apply to linus/master v5.11-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Imre-Deak/drm-i915-gen12-Add-display-render-clear-color-decompression-support/20210115-113136
base: git://anongit.freedesktop.org/drm-intel for-linux-next
:::::: branch date: 12 hours ago
:::::: commit date: 12 hours ago
config: x86_64-randconfig-m001-20210115 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
New smatch warnings:
drivers/gpu/drm/i915/display/intel_display.c:15299 intel_atomic_prepare_plane_clear_colors() warn: taking sizeof binop
Old smatch warnings:
drivers/gpu/drm/i915/gem/i915_gem_object.h:127 __i915_gem_object_lock() error: we previously assumed 'ww' could be null (see line 119)
drivers/gpu/drm/i915/display/intel_display.c:5740 skl_update_scaler_plane() error: we previously assumed 'fb' could be null (see line 5724)
vim +15299 drivers/gpu/drm/i915/display/intel_display.c
8d52e447807b35 drivers/gpu/drm/i915/intel_display.c Chris Wilson 2018-06-23 15272
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15273 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15274 {
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15275 struct drm_device *dev = state->base.dev;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15276 struct drm_i915_private *i915 = to_i915(dev);
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15277 struct intel_plane *plane;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15278 struct intel_plane_state *plane_state;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15279 int i;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15280
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15281 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15282 struct drm_framebuffer *fb = plane_state->hw.fb;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15283 struct drm_i915_gem_object *obj;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15284 int ret;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15285
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15286 if (!fb ||
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15287 fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15288 continue;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15289
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15290 obj = intel_fb_obj(fb);
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15291 /*
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15292 * The layout of the fast clear color value expected by HW:
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15293 * - 4 x 4 bytes per-channel value (in surface type specific float/int format)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15294 * - 8 bytes native color value used by the display (converted/written by GPU during
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15295 * a fast clear operation using the above per-channel values)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15296 */
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15297 ret = i915_gem_object_read_from_page(obj,
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15298 fb->offsets[2] + 16,
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 @15299 sizeof(&plane_state->ccval),
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15300 &plane_state->ccval);
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15301 /*
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15302 * The obj is pinned and synced against GPU writes already, so
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15303 * the above can't normally fail.
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15304 */
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15305 drm_WARN_ON(&i915->drm, ret);
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15306 }
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15307 }
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15308
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 34082 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH v7 3/3] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
2021-01-19 8:29 ` Dan Carpenter
@ 2021-01-19 14:20 ` Imre Deak
-1 siblings, 0 replies; 7+ messages in thread
From: Imre Deak @ 2021-01-19 14:20 UTC (permalink / raw)
To: Dan Carpenter
Cc: Nanley G Chery, Rafael Antognolli, kbuild, Chris Wilson,
Dhinakaran Pandiyan, kbuild-all, Shashank Sharma, intel-gfx,
Ville Syrjala
Hi Dan,
On Tue, Jan 19, 2021 at 11:29:37AM +0300, Dan Carpenter wrote:
> Hi Imre,
>
> url: https://github.com/0day-ci/linux/commits/Imre-Deak/drm-i915-gen12-Add-display-render-clear-color-decompression-support/20210115-113136
> ...
> d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15296 */
> d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15297 ret = i915_gem_object_read_from_page(obj,
> d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15298 fb->offsets[2] + 16,
> d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 @15299 sizeof(&plane_state->ccval),
> d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15300 &plane_state->ccval);
>
> This is a bug in Smatch and it's quite complicated to fix... But the
> sizeof() is still probably wrong. It should be the size of the u64
> instead of the address.
Yes, thanks for the note, I typoed the sizeof(). It's fixed in:
https://patchwork.freedesktop.org/patch/414552/?series=85877&rev=4
--Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH v7 3/3] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
@ 2021-01-19 14:20 ` Imre Deak
0 siblings, 0 replies; 7+ messages in thread
From: Imre Deak @ 2021-01-19 14:20 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 1234 bytes --]
Hi Dan,
On Tue, Jan 19, 2021 at 11:29:37AM +0300, Dan Carpenter wrote:
> Hi Imre,
>
> url: https://github.com/0day-ci/linux/commits/Imre-Deak/drm-i915-gen12-Add-display-render-clear-color-decompression-support/20210115-113136
> ...
> d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15296 */
> d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15297 ret = i915_gem_object_read_from_page(obj,
> d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15298 fb->offsets[2] + 16,
> d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 @15299 sizeof(&plane_state->ccval),
> d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15300 &plane_state->ccval);
>
> This is a bug in Smatch and it's quite complicated to fix... But the
> sizeof() is still probably wrong. It should be the size of the u64
> instead of the address.
Yes, thanks for the note, I typoed the sizeof(). It's fixed in:
https://patchwork.freedesktop.org/patch/414552/?series=85877&rev=4
--Imre
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH v7 3/3] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
2021-01-14 20:13 ` [Intel-gfx] [PATCH v7 3/3] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Imre Deak
2021-01-19 8:29 ` Dan Carpenter
@ 2021-01-19 8:29 ` Dan Carpenter
0 siblings, 0 replies; 7+ messages in thread
From: Dan Carpenter @ 2021-01-19 8:29 UTC (permalink / raw)
To: kbuild, Imre Deak, intel-gfx
Cc: Nanley G Chery, Rafael Antognolli, Chris Wilson,
Dhinakaran Pandiyan, kbuild-all, Shashank Sharma, Ville Syrjala
[-- Attachment #1: Type: text/plain, Size: 5600 bytes --]
Hi Imre,
url: https://github.com/0day-ci/linux/commits/Imre-Deak/drm-i915-gen12-Add-display-render-clear-color-decompression-support/20210115-113136
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-m001-20210115 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
New smatch warnings:
drivers/gpu/drm/i915/display/intel_display.c:15299 intel_atomic_prepare_plane_clear_colors() warn: taking sizeof binop
vim +15299 drivers/gpu/drm/i915/display/intel_display.c
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15273 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15274 {
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15275 struct drm_device *dev = state->base.dev;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15276 struct drm_i915_private *i915 = to_i915(dev);
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15277 struct intel_plane *plane;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15278 struct intel_plane_state *plane_state;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15279 int i;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15280
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15281 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15282 struct drm_framebuffer *fb = plane_state->hw.fb;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15283 struct drm_i915_gem_object *obj;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15284 int ret;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15285
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15286 if (!fb ||
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15287 fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15288 continue;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15289
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15290 obj = intel_fb_obj(fb);
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15291 /*
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15292 * The layout of the fast clear color value expected by HW:
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15293 * - 4 x 4 bytes per-channel value (in surface type specific float/int format)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15294 * - 8 bytes native color value used by the display (converted/written by GPU during
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15295 * a fast clear operation using the above per-channel values)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15296 */
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15297 ret = i915_gem_object_read_from_page(obj,
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15298 fb->offsets[2] + 16,
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 @15299 sizeof(&plane_state->ccval),
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15300 &plane_state->ccval);
This is a bug in Smatch and it's quite complicated to fix... But the
sizeof() is still probably wrong. It should be the size of the u64
instead of the address.
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15301 /*
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15302 * The obj is pinned and synced against GPU writes already, so
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15303 * the above can't normally fail.
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15304 */
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15305 drm_WARN_ON(&i915->drm, ret);
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15306 }
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15307 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
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[-- Attachment #3: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH v7 3/3] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
@ 2021-01-19 8:29 ` Dan Carpenter
0 siblings, 0 replies; 7+ messages in thread
From: Dan Carpenter @ 2021-01-19 8:29 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 5662 bytes --]
Hi Imre,
url: https://github.com/0day-ci/linux/commits/Imre-Deak/drm-i915-gen12-Add-display-render-clear-color-decompression-support/20210115-113136
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-m001-20210115 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
New smatch warnings:
drivers/gpu/drm/i915/display/intel_display.c:15299 intel_atomic_prepare_plane_clear_colors() warn: taking sizeof binop
vim +15299 drivers/gpu/drm/i915/display/intel_display.c
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15273 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15274 {
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15275 struct drm_device *dev = state->base.dev;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15276 struct drm_i915_private *i915 = to_i915(dev);
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15277 struct intel_plane *plane;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15278 struct intel_plane_state *plane_state;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15279 int i;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15280
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15281 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15282 struct drm_framebuffer *fb = plane_state->hw.fb;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15283 struct drm_i915_gem_object *obj;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15284 int ret;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15285
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15286 if (!fb ||
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15287 fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15288 continue;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15289
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15290 obj = intel_fb_obj(fb);
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15291 /*
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15292 * The layout of the fast clear color value expected by HW:
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15293 * - 4 x 4 bytes per-channel value (in surface type specific float/int format)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15294 * - 8 bytes native color value used by the display (converted/written by GPU during
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15295 * a fast clear operation using the above per-channel values)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15296 */
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15297 ret = i915_gem_object_read_from_page(obj,
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15298 fb->offsets[2] + 16,
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 @15299 sizeof(&plane_state->ccval),
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15300 &plane_state->ccval);
This is a bug in Smatch and it's quite complicated to fix... But the
sizeof() is still probably wrong. It should be the size of the u64
instead of the address.
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15301 /*
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15302 * The obj is pinned and synced against GPU writes already, so
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15303 * the above can't normally fail.
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15304 */
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15305 drm_WARN_ON(&i915->drm, ret);
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15306 }
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15307 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 34082 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH v7 3/3] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
@ 2021-01-19 8:29 ` Dan Carpenter
0 siblings, 0 replies; 7+ messages in thread
From: Dan Carpenter @ 2021-01-19 8:29 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 5662 bytes --]
Hi Imre,
url: https://github.com/0day-ci/linux/commits/Imre-Deak/drm-i915-gen12-Add-display-render-clear-color-decompression-support/20210115-113136
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-m001-20210115 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
New smatch warnings:
drivers/gpu/drm/i915/display/intel_display.c:15299 intel_atomic_prepare_plane_clear_colors() warn: taking sizeof binop
vim +15299 drivers/gpu/drm/i915/display/intel_display.c
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15273 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15274 {
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15275 struct drm_device *dev = state->base.dev;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15276 struct drm_i915_private *i915 = to_i915(dev);
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15277 struct intel_plane *plane;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15278 struct intel_plane_state *plane_state;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15279 int i;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15280
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15281 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15282 struct drm_framebuffer *fb = plane_state->hw.fb;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15283 struct drm_i915_gem_object *obj;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15284 int ret;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15285
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15286 if (!fb ||
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15287 fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15288 continue;
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15289
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15290 obj = intel_fb_obj(fb);
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15291 /*
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15292 * The layout of the fast clear color value expected by HW:
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15293 * - 4 x 4 bytes per-channel value (in surface type specific float/int format)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15294 * - 8 bytes native color value used by the display (converted/written by GPU during
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15295 * a fast clear operation using the above per-channel values)
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15296 */
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15297 ret = i915_gem_object_read_from_page(obj,
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15298 fb->offsets[2] + 16,
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 @15299 sizeof(&plane_state->ccval),
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15300 &plane_state->ccval);
This is a bug in Smatch and it's quite complicated to fix... But the
sizeof() is still probably wrong. It should be the size of the u64
instead of the address.
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15301 /*
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15302 * The obj is pinned and synced against GPU writes already, so
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15303 * the above can't normally fail.
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15304 */
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15305 drm_WARN_ON(&i915->drm, ret);
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15306 }
d5de4516a9de74 drivers/gpu/drm/i915/display/intel_display.c Radhakrishna Sripada 2021-01-14 15307 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 34082 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] [PATCH v7 3/3] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
2021-01-14 20:13 [Intel-gfx] [PATCH v7 0/3] drm/i915/gen12: Add display render clear color decompression support Imre Deak
@ 2021-01-14 20:13 ` Imre Deak
2021-01-19 8:29 ` Dan Carpenter
0 siblings, 1 reply; 7+ messages in thread
From: Imre Deak @ 2021-01-14 20:13 UTC (permalink / raw)
To: intel-gfx
Cc: Nanley G Chery, Rafael Antognolli, Chris Wilson,
Dhinakaran Pandiyan, Ville Syrjala, Shashank Sharma
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.
v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
v5: Fix typos and wrap comments(Matt)
v6:
- Use format block descriptors to get the subsampling calculations for
the CCS surface right.
- Use helpers to convert between main and CCS surfaces.
- Prevent coordinate checks for the CC surface.
- Simplify reading CC value from surface map, add description of CC val
layout.
- Remove redundant ccval variable from skl_program_plane().
v7:
- Move the CC value readout after syncing against any GPU write on the
FB obj (Nanley, Chris)
- Make sure the CC value readout works on platforms w/o struct pages
(dGFX) and other non-coherent platforms wrt. CPU reads (none atm).
(Chris)
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjala <ville.syrjala@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com> (v5)
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 101 +++++++++++++++++-
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_sprite.c | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 9 ++
4 files changed, 117 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 66990e48c0d4..f1b4ae451fa9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -58,6 +58,8 @@
#include "display/intel_tv.h"
#include "display/intel_vdsc.h"
+#include "gem/i915_gem_object.h"
+
#include "gt/intel_rps.h"
#include "i915_drv.h"
@@ -1906,8 +1908,8 @@ static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
static bool is_gen12_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
-
}
static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
@@ -1915,6 +1917,12 @@ static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
}
+static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
+{
+ return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
+ plane == 2;
+}
+
static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
{
if (is_ccs_modifier(fb->modifier))
@@ -1936,6 +1944,9 @@ static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
ccs_plane < fb->format->num_planes / 2);
+ if (is_gen12_ccs_cc_plane(fb, ccs_plane))
+ return 0;
+
return ccs_plane - fb->format->num_planes / 2;
}
@@ -1986,6 +1997,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
fallthrough;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
if (is_ccs_plane(fb, color_plane))
return 64;
@@ -2142,6 +2154,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
return intel_tile_row_size(fb, color_plane);
fallthrough;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2546,6 +2559,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
default:
@@ -2624,6 +2638,25 @@ static const struct drm_format_info gen12_ccs_formats[] = {
.hsub = 2, .vsub = 2, .is_yuv = true },
};
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * to pass Clear Color information in plane 2 with 64 bits of data.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2652,6 +2685,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return lookup_format_info(gen12_ccs_cc_formats,
+ ARRAY_SIZE(gen12_ccs_cc_formats),
+ cmd->pixel_format);
default:
return NULL;
}
@@ -2660,6 +2697,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
@@ -2878,7 +2916,7 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
int ccs_x, ccs_y;
int main_x, main_y;
- if (!is_ccs_plane(fb, ccs_plane))
+ if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane))
return 0;
intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
@@ -3005,6 +3043,18 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int x, y;
int ret;
+ /*
+ * Plane 2 of Render Compression with Clear Color fb modifier
+ * is consumed by the driver and not passed to DE. Skip the
+ * arithmetic related to alignment and offset calculation.
+ */
+ if (is_gen12_ccs_cc_plane(fb, i)) {
+ if (IS_ALIGNED(fb->offsets[i], PAGE_SIZE))
+ continue;
+ else
+ return -EINVAL;
+ }
+
cpp = fb->format->cpp[i];
intel_fb_plane_dims(&width, &height, fb, i);
@@ -3946,7 +3996,8 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
int hsub, vsub;
int x, y;
- if (!is_ccs_plane(fb, ccs_plane))
+ if (!is_ccs_plane(fb, ccs_plane) ||
+ is_gen12_ccs_cc_plane(fb, ccs_plane))
continue;
intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
@@ -4186,6 +4237,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return PLANE_CTL_TILED_Y |
@@ -15218,6 +15270,42 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
intel_atomic_helper_free_state(i915);
}
+static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct intel_plane *plane;
+ struct intel_plane_state *plane_state;
+ int i;
+
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ struct drm_framebuffer *fb = plane_state->hw.fb;
+ struct drm_i915_gem_object *obj;
+ int ret;
+
+ if (!fb ||
+ fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ continue;
+
+ obj = intel_fb_obj(fb);
+ /*
+ * The layout of the fast clear color value expected by HW:
+ * - 4 x 4 bytes per-channel value (in surface type specific float/int format)
+ * - 8 bytes native color value used by the display (converted/written by GPU during
+ * a fast clear operation using the above per-channel values)
+ */
+ ret = i915_gem_object_read_from_page(obj,
+ fb->offsets[2] + 16,
+ sizeof(&plane_state->ccval),
+ &plane_state->ccval);
+ /*
+ * The obj is pinned and synced against GPU writes already, so
+ * the above can't normally fail.
+ */
+ drm_WARN_ON(&i915->drm, ret);
+ }
+}
+
static void intel_atomic_commit_tail(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
@@ -15235,6 +15323,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
+ intel_atomic_prepare_plane_clear_colors(state);
+
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (intel_crtc_needs_modeset(new_crtc_state) ||
@@ -15662,7 +15752,8 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct intel_plane_state *old_plane_state =
intel_atomic_get_old_plane_state(state, plane);
- struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
+ struct drm_framebuffer *fb = new_plane_state->hw.fb;
+ struct drm_i915_gem_object *obj = intel_fb_obj(fb);
struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
int ret;
@@ -16540,7 +16631,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
- if (is_gen12_ccs_plane(fb, i)) {
+ if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
if (fb->pitches[i] != ccs_aux_stride) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 585bb1edea04..d64f327a28a6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -620,6 +620,9 @@ struct intel_plane_state {
struct drm_intel_sprite_colorkey ckey;
struct drm_rect psr2_sel_fetch_area;
+
+ /* Clear Color Value */
+ u64 ccval;
};
struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index cf3589fd0ddb..3efb346e071a 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -867,6 +867,10 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ intel_uncore_write64_fw(&dev_priv->uncore,
+ PLANE_CC_VAL(pipe, plane_id), plane_state->ccval);
+
skl_write_plane_wm(plane, crtc_state);
intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
@@ -2366,7 +2370,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
drm_dbg_kms(&dev_priv->drm,
"Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
@@ -2856,6 +2861,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2864,6 +2870,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -3054,6 +3061,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
break;
default:
return false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 249a81575b9d..8b9bbc6bacb1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7070,6 +7070,8 @@ enum {
#define _PLANE_KEYMAX_1_A 0x701a0
#define _PLANE_KEYMAX_2_A 0x702a0
#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
+#define _PLANE_CC_VAL_1_A 0x701b4
+#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_AUX_DIST_1_A 0x701c0
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_OFFSET_1_A 0x701c4
@@ -7111,6 +7113,13 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
+#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+
/* Input CSC Register Definitions */
#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
--
2.25.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-01-19 14:20 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-15 15:08 [Intel-gfx] [PATCH v7 3/3] drm/i915/tgl: Add Clear Color support for TGL Render Decompression kernel test robot
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2021-01-14 20:13 [Intel-gfx] [PATCH v7 0/3] drm/i915/gen12: Add display render clear color decompression support Imre Deak
2021-01-14 20:13 ` [Intel-gfx] [PATCH v7 3/3] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Imre Deak
2021-01-19 8:29 ` Dan Carpenter
2021-01-19 8:29 ` Dan Carpenter
2021-01-19 8:29 ` Dan Carpenter
2021-01-19 14:20 ` Imre Deak
2021-01-19 14:20 ` Imre Deak
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