* [Intel-gfx] [RFC-v19 01/13] drm/i915/pxp: Introduce Intel PXP component
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
@ 2021-01-06 23:12 ` Huang, Sean Z
2021-01-07 15:28 ` Vivi, Rodrigo
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
` (17 subsequent siblings)
18 siblings, 1 reply; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-06 23:12 UTC (permalink / raw)
To: Intel-gfx
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (a.k.a default session or
arbitrary session). So Mesa can allocate the protected buffer,
which is encrypted with the leverage of the arbitrary hardware
session.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Kconfig | 22 +++++++++++++++
drivers/gpu/drm/i915/Makefile | 5 ++++
drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 29 ++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 25 +++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 25 +++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 23 ++++++++++++++++
9 files changed, 152 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..594775c11e19 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,28 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ select INTEL_MEI
+ select INTEL_MEI_ME
+ select INTEL_MEI_TXE
+ select INTEL_MEI_PXP
+ default y
+ help
+ This option selects INTEL_MEI_ME if it isn't already selected to
+ enabled full PXP Services on Intel platforms.
+
+ PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
+ that helps to establish the hardware protected session and manage
+ the status of the alive software session, as well as its life cycle.
+
+ This patch series is to allow the kernel space to create and
+ manage a single hardware session (a.k.a default session or
+ arbitrary session). So Mesa can allocate the protected buffer,
+ which is encrypted with the leverage of the arbitrary hardware
+ session.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4074d8cb0d6e..cbf2f0594b4d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -259,6 +259,11 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index d8e1ab412634..336ad7deae06 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -18,6 +18,7 @@
#include "intel_uncore.h"
#include "intel_pm.h"
#include "shmem_utils.h"
+#include "pxp/intel_pxp.h"
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
@@ -584,6 +585,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ intel_pxp_init(>->pxp);
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -607,6 +610,8 @@ void intel_gt_driver_remove(struct intel_gt *gt)
{
__intel_gt_disable(gt);
+ intel_pxp_fini(>->pxp);
+
intel_uc_driver_remove(>->uc);
intel_engines_release(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index a83d3e18254d..c4760e2722fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -23,6 +23,7 @@
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_types.h"
struct drm_i915_private;
struct i915_ggtt;
@@ -145,6 +146,8 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
+
+ struct intel_pxp pxp;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index 000000000000..9bc3c7e30654
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+
+void intel_pxp_init(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ if (INTEL_GEN(gt->i915) < 12)
+ return;
+
+ intel_pxp_ctx_init(&pxp->ctx);
+
+ drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
+}
+
+void intel_pxp_fini(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ if (INTEL_GEN(gt->i915) < 12)
+ return;
+
+ intel_pxp_ctx_fini(&pxp->ctx);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
new file mode 100644
index 000000000000..f47bc6bea34f
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_H__
+#define __INTEL_PXP_H__
+
+#include "intel_pxp_types.h"
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_init(struct intel_pxp *pxp);
+void intel_pxp_fini(struct intel_pxp *pxp);
+#else
+static inline void intel_pxp_init(struct intel_pxp *pxp)
+{
+ return 0;
+}
+
+static inline void intel_pxp_fini(struct intel_pxp *pxp)
+{
+}
+#endif
+
+#endif /* __INTEL_PXP_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
new file mode 100644
index 000000000000..2be6bf2f0d0f
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_context.h"
+
+/**
+ * intel_pxp_ctx_init - To init a pxp context.
+ * @ctx: pointer to ctx structure.
+ */
+void intel_pxp_ctx_init(struct pxp_context *ctx)
+{
+ mutex_init(&ctx->mutex);
+ ctx->inited = true;
+}
+
+/**
+ * intel_pxp_ctx_fini - To finish the pxp context.
+ * @ctx: pointer to ctx structure.
+ */
+void intel_pxp_ctx_fini(struct pxp_context *ctx)
+{
+ ctx->inited = false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
new file mode 100644
index 000000000000..f51021c33d45
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_CONTEXT_H__
+#define __INTEL_PXP_CONTEXT_H__
+
+#include <linux/mutex.h>
+#include "intel_pxp_types.h"
+
+void intel_pxp_ctx_init(struct pxp_context *ctx);
+void intel_pxp_ctx_fini(struct pxp_context *ctx);
+
+#endif /* __INTEL_PXP_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
new file mode 100644
index 000000000000..f9b40ea98b1b
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_TYPES_H__
+#define __INTEL_PXP_TYPES_H__
+
+#include <linux/mutex.h>
+
+/* struct pxp_context - Represents combined view of driver and logical HW states. */
+struct pxp_context {
+ /** @mutex: mutex to protect the pxp context */
+ struct mutex mutex;
+
+ bool inited;
+};
+
+struct intel_pxp {
+ struct pxp_context ctx;
+};
+
+#endif /* __INTEL_PXP_TYPES_H__ */
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 01/13] drm/i915/pxp: Introduce Intel PXP component
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
@ 2021-01-07 15:28 ` Vivi, Rodrigo
2021-01-11 22:06 ` Huang, Sean Z
0 siblings, 1 reply; 55+ messages in thread
From: Vivi, Rodrigo @ 2021-01-07 15:28 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> that helps to establish the hardware protected session and manage
> the status of the alive software session, as well as its life cycle.
>
> This patch series is to allow the kernel space to create and
> manage a single hardware session (a.k.a default session or
> arbitrary session). So Mesa can allocate the protected buffer,
> which is encrypted with the leverage of the arbitrary hardware
> session.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Kconfig | 22 +++++++++++++++
> drivers/gpu/drm/i915/Makefile | 5 ++++
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 29
> ++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 25 +++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 25 +++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 23 ++++++++++++++++
> 9 files changed, 152 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>
> diff --git a/drivers/gpu/drm/i915/Kconfig
> b/drivers/gpu/drm/i915/Kconfig
> index 1e1cb245fca7..594775c11e19 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -130,6 +130,28 @@ config DRM_I915_GVT_KVMGT
> Choose this option if you want to enable KVMGT support for
> Intel GVT-g.
>
> +config DRM_I915_PXP
> + bool "Enable Intel PXP support for Intel Gen12+ platform"
> + depends on DRM_I915
> + select INTEL_MEI
> + select INTEL_MEI_ME
> + select INTEL_MEI_TXE
> + select INTEL_MEI_PXP
I'm afraid you haven't addressed any of the Chris' comments from V4.
I saw you marked as "done", but I'm seeing everything back here.
So I'm not sure what's going on here.
> + default y
> + help
> + This option selects INTEL_MEI_ME if it isn't already
> selected to
> + enabled full PXP Services on Intel platforms.
> +
> + PXP (Protected Xe Path) is an i915 componment, available on
> GEN12+,
> + that helps to establish the hardware protected session and
> manage
> + the status of the alive software session, as well as its
> life cycle.
> +
> + This patch series is to allow the kernel space to create
> and
> + manage a single hardware session (a.k.a default session or
> + arbitrary session). So Mesa can allocate the protected
> buffer,
> + which is encrypted with the leverage of the arbitrary
> hardware
> + session.
> +
> menu "drm/i915 Debugging"
> depends on DRM_I915
> depends on EXPERT
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile
> index 4074d8cb0d6e..cbf2f0594b4d 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -259,6 +259,11 @@ i915-y += \
>
> i915-y += i915_perf.o
>
> +# Protected execution platform (PXP) support
> +i915-$(CONFIG_DRM_I915_PXP) += \
> + pxp/intel_pxp.o \
> + pxp/intel_pxp_context.o
> +
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> i915-$(CONFIG_DRM_I915_SELFTEST) += \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index d8e1ab412634..336ad7deae06 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -18,6 +18,7 @@
> #include "intel_uncore.h"
> #include "intel_pm.h"
> #include "shmem_utils.h"
> +#include "pxp/intel_pxp.h"
>
> void intel_gt_init_early(struct intel_gt *gt, struct
> drm_i915_private *i915)
> {
> @@ -584,6 +585,8 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_gt;
>
> + intel_pxp_init(>->pxp);
> +
> goto out_fw;
> err_gt:
> __intel_gt_disable(gt);
> @@ -607,6 +610,8 @@ void intel_gt_driver_remove(struct intel_gt *gt)
> {
> __intel_gt_disable(gt);
>
> + intel_pxp_fini(>->pxp);
> +
> intel_uc_driver_remove(>->uc);
>
> intel_engines_release(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index a83d3e18254d..c4760e2722fd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp_types.h"
>
> struct drm_i915_private;
> struct i915_ggtt;
> @@ -145,6 +146,8 @@ struct intel_gt {
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
> } info;
> +
> + struct intel_pxp pxp;
> };
>
> enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> new file mode 100644
> index 000000000000..9bc3c7e30654
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_context.h"
> +
> +void intel_pxp_init(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = container_of(pxp, struct intel_gt,
> pxp);
> +
> + if (INTEL_GEN(gt->i915) < 12)
> + return;
> +
> + intel_pxp_ctx_init(&pxp->ctx);
> +
> + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected
> content support initialized\n");
> +}
> +
> +void intel_pxp_fini(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = container_of(pxp, struct intel_gt,
> pxp);
> +
> + if (INTEL_GEN(gt->i915) < 12)
> + return;
> +
> + intel_pxp_ctx_fini(&pxp->ctx);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> new file mode 100644
> index 000000000000..f47bc6bea34f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_H__
> +#define __INTEL_PXP_H__
> +
> +#include "intel_pxp_types.h"
> +
> +#ifdef CONFIG_DRM_I915_PXP
> +void intel_pxp_init(struct intel_pxp *pxp);
> +void intel_pxp_fini(struct intel_pxp *pxp);
> +#else
> +static inline void intel_pxp_init(struct intel_pxp *pxp)
> +{
> + return 0;
> +}
> +
> +static inline void intel_pxp_fini(struct intel_pxp *pxp)
> +{
> +}
> +#endif
> +
> +#endif /* __INTEL_PXP_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> new file mode 100644
> index 000000000000..2be6bf2f0d0f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp_context.h"
> +
> +/**
> + * intel_pxp_ctx_init - To init a pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_init(struct pxp_context *ctx)
> +{
> + mutex_init(&ctx->mutex);
> + ctx->inited = true;
> +}
> +
> +/**
> + * intel_pxp_ctx_fini - To finish the pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_fini(struct pxp_context *ctx)
> +{
> + ctx->inited = false;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> new file mode 100644
> index 000000000000..f51021c33d45
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CONTEXT_H__
> +#define __INTEL_PXP_CONTEXT_H__
> +
> +#include <linux/mutex.h>
> +#include "intel_pxp_types.h"
> +
> +void intel_pxp_ctx_init(struct pxp_context *ctx);
> +void intel_pxp_ctx_fini(struct pxp_context *ctx);
> +
> +#endif /* __INTEL_PXP_CONTEXT_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> new file mode 100644
> index 000000000000..f9b40ea98b1b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_TYPES_H__
> +#define __INTEL_PXP_TYPES_H__
> +
> +#include <linux/mutex.h>
> +
> +/* struct pxp_context - Represents combined view of driver and
> logical HW states. */
> +struct pxp_context {
> + /** @mutex: mutex to protect the pxp context */
> + struct mutex mutex;
> +
> + bool inited;
> +};
> +
> +struct intel_pxp {
> + struct pxp_context ctx;
> +};
> +
> +#endif /* __INTEL_PXP_TYPES_H__ */
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^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 01/13] drm/i915/pxp: Introduce Intel PXP component
2021-01-07 15:28 ` Vivi, Rodrigo
@ 2021-01-11 22:06 ` Huang, Sean Z
0 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-11 22:06 UTC (permalink / raw)
To: Vivi, Rodrigo, Intel-gfx
Hi Rodrigo,
Regarding to Chris comment in v4:
>> +config DRM_I915_PXP
>> + bool "Enable Intel PXP support for Intel Gen12+ platform"
>> + depends on DRM_I915
>> + select INTEL_MEI_PXP
>
>Doesn't exist.
>
>Kconfig dependency resolution is not recursive; you probably will need a
>depends on INTEL_MEI
Since select INTEL_MEI_PXP isn't recursive so I have add "select INTEL_MEI" accordingly based on Chris suggestion.
In the rev20, I removed the term "Mesa" from the help description, modification as below:
This patch series is to allow the kernel space to create and
manage a single hardware session (a.k.a default session or
- arbitrary session). So Mesa can allocate the protected buffer,
+ arbitrary session). So user space can allocate the protected buffer,
which is encrypted with the leverage of the arbitrary hardware
session.
Best regards,
Sean
-----Original Message-----
From: Vivi, Rodrigo <rodrigo.vivi@intel.com>
Sent: Thursday, January 7, 2021 7:29 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v19 01/13] drm/i915/pxp: Introduce Intel PXP component
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> that helps to establish the hardware protected session and manage the
> status of the alive software session, as well as its life cycle.
>
> This patch series is to allow the kernel space to create and manage a
> single hardware session (a.k.a default session or arbitrary session).
> So Mesa can allocate the protected buffer, which is encrypted with the
> leverage of the arbitrary hardware session.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Kconfig | 22 +++++++++++++++
> drivers/gpu/drm/i915/Makefile | 5 ++++
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 29
> ++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 25 +++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 25 +++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 23 ++++++++++++++++
> 9 files changed, 152 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>
> diff --git a/drivers/gpu/drm/i915/Kconfig
> b/drivers/gpu/drm/i915/Kconfig index 1e1cb245fca7..594775c11e19 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -130,6 +130,28 @@ config DRM_I915_GVT_KVMGT
> Choose this option if you want to enable KVMGT support for
> Intel GVT-g.
>
> +config DRM_I915_PXP
> + bool "Enable Intel PXP support for Intel Gen12+ platform"
> + depends on DRM_I915
> + select INTEL_MEI
> + select INTEL_MEI_ME
> + select INTEL_MEI_TXE
> + select INTEL_MEI_PXP
I'm afraid you haven't addressed any of the Chris' comments from V4.
I saw you marked as "done", but I'm seeing everything back here.
So I'm not sure what's going on here.
> + default y
> + help
> + This option selects INTEL_MEI_ME if it isn't already
> selected to
> + enabled full PXP Services on Intel platforms.
> +
> + PXP (Protected Xe Path) is an i915 componment, available on
> GEN12+,
> + that helps to establish the hardware protected session and
> manage
> + the status of the alive software session, as well as its
> life cycle.
> +
> + This patch series is to allow the kernel space to create
> and
> + manage a single hardware session (a.k.a default session or
> + arbitrary session). So Mesa can allocate the protected
> buffer,
> + which is encrypted with the leverage of the arbitrary
> hardware
> + session.
> +
> menu "drm/i915 Debugging"
> depends on DRM_I915
> depends on EXPERT
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile index 4074d8cb0d6e..cbf2f0594b4d
> 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -259,6 +259,11 @@ i915-y += \
>
> i915-y += i915_perf.o
>
> +# Protected execution platform (PXP) support
> +i915-$(CONFIG_DRM_I915_PXP) += \
> + pxp/intel_pxp.o \
> + pxp/intel_pxp_context.o
> +
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> i915-$(CONFIG_DRM_I915_SELFTEST) += \ diff --git
> a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index d8e1ab412634..336ad7deae06 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -18,6 +18,7 @@
> #include "intel_uncore.h"
> #include "intel_pm.h"
> #include "shmem_utils.h"
> +#include "pxp/intel_pxp.h"
>
> void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private
> *i915) { @@ -584,6 +585,8 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_gt;
>
> + intel_pxp_init(>->pxp);
> +
> goto out_fw;
> err_gt:
> __intel_gt_disable(gt);
> @@ -607,6 +610,8 @@ void intel_gt_driver_remove(struct intel_gt *gt)
> {
> __intel_gt_disable(gt);
>
> + intel_pxp_fini(>->pxp);
> +
> intel_uc_driver_remove(>->uc);
>
> intel_engines_release(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index a83d3e18254d..c4760e2722fd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp_types.h"
>
> struct drm_i915_private;
> struct i915_ggtt;
> @@ -145,6 +146,8 @@ struct intel_gt {
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
> } info;
> +
> + struct intel_pxp pxp;
> };
>
> enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> new file mode 100644
> index 000000000000..9bc3c7e30654
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_context.h"
> +
> +void intel_pxp_init(struct intel_pxp *pxp) {
> + struct intel_gt *gt = container_of(pxp, struct intel_gt,
> pxp);
> +
> + if (INTEL_GEN(gt->i915) < 12)
> + return;
> +
> + intel_pxp_ctx_init(&pxp->ctx);
> +
> + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected
> content support initialized\n");
> +}
> +
> +void intel_pxp_fini(struct intel_pxp *pxp) {
> + struct intel_gt *gt = container_of(pxp, struct intel_gt,
> pxp);
> +
> + if (INTEL_GEN(gt->i915) < 12)
> + return;
> +
> + intel_pxp_ctx_fini(&pxp->ctx); }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> new file mode 100644
> index 000000000000..f47bc6bea34f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_H__
> +#define __INTEL_PXP_H__
> +
> +#include "intel_pxp_types.h"
> +
> +#ifdef CONFIG_DRM_I915_PXP
> +void intel_pxp_init(struct intel_pxp *pxp); void
> +intel_pxp_fini(struct intel_pxp *pxp); #else static inline void
> +intel_pxp_init(struct intel_pxp *pxp) {
> + return 0;
> +}
> +
> +static inline void intel_pxp_fini(struct intel_pxp *pxp) { } #endif
> +
> +#endif /* __INTEL_PXP_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> new file mode 100644
> index 000000000000..2be6bf2f0d0f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp_context.h"
> +
> +/**
> + * intel_pxp_ctx_init - To init a pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_init(struct pxp_context *ctx) {
> + mutex_init(&ctx->mutex);
> + ctx->inited = true;
> +}
> +
> +/**
> + * intel_pxp_ctx_fini - To finish the pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_fini(struct pxp_context *ctx) {
> + ctx->inited = false;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> new file mode 100644
> index 000000000000..f51021c33d45
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CONTEXT_H__
> +#define __INTEL_PXP_CONTEXT_H__
> +
> +#include <linux/mutex.h>
> +#include "intel_pxp_types.h"
> +
> +void intel_pxp_ctx_init(struct pxp_context *ctx); void
> +intel_pxp_ctx_fini(struct pxp_context *ctx);
> +
> +#endif /* __INTEL_PXP_CONTEXT_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> new file mode 100644
> index 000000000000..f9b40ea98b1b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_TYPES_H__
> +#define __INTEL_PXP_TYPES_H__
> +
> +#include <linux/mutex.h>
> +
> +/* struct pxp_context - Represents combined view of driver and
> logical HW states. */
> +struct pxp_context {
> + /** @mutex: mutex to protect the pxp context */
> + struct mutex mutex;
> +
> + bool inited;
> +};
> +
> +struct intel_pxp {
> + struct pxp_context ctx;
> +};
> +
> +#endif /* __INTEL_PXP_TYPES_H__ */
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^ permalink raw reply [flat|nested] 55+ messages in thread
* [Intel-gfx] [RFC-v19 02/13] drm/i915/pxp: set KCR reg init during the boot time
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
@ 2021-01-06 23:12 ` Huang, Sean Z
2021-01-07 15:31 ` Vivi, Rodrigo
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 03/13] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
` (16 subsequent siblings)
18 siblings, 1 reply; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-06 23:12 UTC (permalink / raw)
To: Intel-gfx
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 9bc3c7e30654..f566a4fda044 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,12 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+/* KCR register definitions */
+#define KCR_INIT _MMIO(0x320f0)
+#define KCR_INIT_MASK_SHIFT (16)
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT))
+
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -15,6 +21,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_ctx_init(&pxp->ctx);
+ intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 02/13] drm/i915/pxp: set KCR reg init during the boot time
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
@ 2021-01-07 15:31 ` Vivi, Rodrigo
2021-01-08 11:30 ` Joonas Lahtinen
0 siblings, 1 reply; 55+ messages in thread
From: Vivi, Rodrigo @ 2021-01-07 15:31 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> Set the KCR init during the boot time, which is
> required by hardware, to allow us doing further
> protection operation such as sending commands to
> GPU or TEE.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 9bc3c7e30654..f566a4fda044 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,12 @@
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
>
> +/* KCR register definitions */
please define this in i915_reg.h
> +#define KCR_INIT _MMIO(0x320f0)
> +#define KCR_INIT_MASK_SHIFT (16)
mask or shift?
> +/* Setting KCR Init bit is required after system boot */
> +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
> KCR_INIT_MASK_SHIFT))
Also, use only bit definitions here and leave the mask and/or shift
only when calling the write function.
>
> +
> void intel_pxp_init(struct intel_pxp *pxp)
> {
> struct intel_gt *gt = container_of(pxp, struct intel_gt,
> pxp);
> @@ -15,6 +21,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
>
> intel_pxp_ctx_init(&pxp->ctx);
>
> + intel_uncore_write(gt->uncore, KCR_INIT,
> KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
> +
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected
> content support initialized\n");
> }
>
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^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 02/13] drm/i915/pxp: set KCR reg init during the boot time
2021-01-07 15:31 ` Vivi, Rodrigo
@ 2021-01-08 11:30 ` Joonas Lahtinen
2021-01-11 21:38 ` Huang, Sean Z
0 siblings, 1 reply; 55+ messages in thread
From: Joonas Lahtinen @ 2021-01-08 11:30 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx, Vivi, Rodrigo
Quoting Vivi, Rodrigo (2021-01-07 17:31:36)
> On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> > Set the KCR init during the boot time, which is
> > required by hardware, to allow us doing further
> > protection operation such as sending commands to
> > GPU or TEE.
> >
> > Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> > ---
> > drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > index 9bc3c7e30654..f566a4fda044 100644
> > --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > @@ -6,6 +6,12 @@
> > #include "intel_pxp.h"
> > #include "intel_pxp_context.h"
> >
> > +/* KCR register definitions */
>
> please define this in i915_reg.h
Generally the trend on the GT side is to contain in a .c file if there are
no shared users like these. So they should be at this spot, yet the rest
of the review comments apply.
The spurious comments should be dropped and like Rodrigo pointed out, we
should be using the appropriate macros for a masked writes, not baking in
the #define.
Regards, Joonas
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^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [Intel-gfx] [RFC-v19 02/13] drm/i915/pxp: set KCR reg init during the boot time
2021-01-08 11:30 ` Joonas Lahtinen
@ 2021-01-11 21:38 ` Huang, Sean Z
2021-01-12 11:27 ` Vivi, Rodrigo
0 siblings, 1 reply; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-11 21:38 UTC (permalink / raw)
To: Joonas Lahtinen, Intel-gfx, Vivi, Rodrigo
Hello,
I see, based on Joonas and Rodrigo's feedback.
I made the modification as below, I will still keep the macro in this .c instead of i915_reg.h, and this change will be reflected in rev20.
/* KCR register definitions */
#define KCR_INIT _MMIO(0x320f0)
-#define KCR_INIT_MASK_SHIFT (16)
+
/* Setting KCR Init bit is required after system boot */
-#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT))
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << 16))
Best regards,
Sean
-----Original Message-----
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Sent: Friday, January 8, 2021 3:31 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>
Subject: Re: [Intel-gfx] [RFC-v19 02/13] drm/i915/pxp: set KCR reg init during the boot time
Quoting Vivi, Rodrigo (2021-01-07 17:31:36)
> On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> > Set the KCR init during the boot time, which is required by
> > hardware, to allow us doing further protection operation such as
> > sending commands to GPU or TEE.
> >
> > Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> > ---
> > drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > index 9bc3c7e30654..f566a4fda044 100644
> > --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > @@ -6,6 +6,12 @@
> > #include "intel_pxp.h"
> > #include "intel_pxp_context.h"
> >
> > +/* KCR register definitions */
>
> please define this in i915_reg.h
Generally the trend on the GT side is to contain in a .c file if there are no shared users like these. So they should be at this spot, yet the rest of the review comments apply.
The spurious comments should be dropped and like Rodrigo pointed out, we should be using the appropriate macros for a masked writes, not baking in the #define.
Regards, Joonas
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [Intel-gfx] [RFC-v19 02/13] drm/i915/pxp: set KCR reg init during the boot time
2021-01-11 21:38 ` Huang, Sean Z
@ 2021-01-12 11:27 ` Vivi, Rodrigo
2021-01-12 15:36 ` Jani Nikula
0 siblings, 1 reply; 55+ messages in thread
From: Vivi, Rodrigo @ 2021-01-12 11:27 UTC (permalink / raw)
To: joonas.lahtinen, Huang, Sean Z, Intel-gfx
On Mon, 2021-01-11 at 21:38 +0000, Huang, Sean Z wrote:
> Hello,
>
> I see, based on Joonas and Rodrigo's feedback.
>
> I made the modification as below, I will still keep the macro in this
> .c instead of i915_reg.h, and this change will be reflected in rev20.
>
> /* KCR register definitions */
> #define KCR_INIT _MMIO(0x320f0)
> -#define KCR_INIT_MASK_SHIFT (16)
> +
> /* Setting KCR Init bit is required after system boot */
> -#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
> KCR_INIT_MASK_SHIFT))
> +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << 16))
This is not what I asked actually.
I asked to get the BIT(14) to be defined separated, shift defined as
well... and the | and actuall shift operations to be performed in the
code and not in the defines
>
> Best regards,
> Sean
>
> -----Original Message-----
> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Sent: Friday, January 8, 2021 3:31 AM
> To: Huang, Sean Z <sean.z.huang@intel.com>;
> Intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <
> rodrigo.vivi@intel.com>
> Subject: Re: [Intel-gfx] [RFC-v19 02/13] drm/i915/pxp: set KCR reg
> init during the boot time
>
> Quoting Vivi, Rodrigo (2021-01-07 17:31:36)
> > On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> > > Set the KCR init during the boot time, which is required by
> > > hardware, to allow us doing further protection operation such as
> > > sending commands to GPU or TEE.
> > >
> > > Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++
> > > 1 file changed, 8 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > > b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > > index 9bc3c7e30654..f566a4fda044 100644
> > > --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > > @@ -6,6 +6,12 @@
> > > #include "intel_pxp.h"
> > > #include "intel_pxp_context.h"
> > >
> > > +/* KCR register definitions */
> >
> > please define this in i915_reg.h
>
> Generally the trend on the GT side is to contain in a .c file if
> there are no shared users like these. So they should be at this spot,
> yet the rest of the review comments apply.
>
> The spurious comments should be dropped and like Rodrigo pointed out,
> we should be using the appropriate macros for a masked writes, not
> baking in the #define.
>
> Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [Intel-gfx] [RFC-v19 02/13] drm/i915/pxp: set KCR reg init during the boot time
2021-01-12 11:27 ` Vivi, Rodrigo
@ 2021-01-12 15:36 ` Jani Nikula
0 siblings, 0 replies; 55+ messages in thread
From: Jani Nikula @ 2021-01-12 15:36 UTC (permalink / raw)
To: Vivi, Rodrigo, joonas.lahtinen, Huang, Sean Z, Intel-gfx
On Tue, 12 Jan 2021, "Vivi, Rodrigo" <rodrigo.vivi@intel.com> wrote:
> On Mon, 2021-01-11 at 21:38 +0000, Huang, Sean Z wrote:
>> Hello,
>>
>> I see, based on Joonas and Rodrigo's feedback.
>>
>> I made the modification as below, I will still keep the macro in this
>> .c instead of i915_reg.h, and this change will be reflected in rev20.
>>
>> /* KCR register definitions */
>> #define KCR_INIT _MMIO(0x320f0)
>> -#define KCR_INIT_MASK_SHIFT (16)
Useless parenthesis.
>> +
>> /* Setting KCR Init bit is required after system boot */
>> -#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
>> KCR_INIT_MASK_SHIFT))
>> +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << 16))
BIT(14) << 16 is actually BIT(14+16), or BIT(30). The above is
pointless.
Also, you'll end up with problems by using BIT() instead of REG_BIT()
defined in i915_reg.h due to BIT() using unsigned long.
Also, read the big style comment near the top of i915_reg.h.
BR,
Jani.
>
> This is not what I asked actually.
>
> I asked to get the BIT(14) to be defined separated, shift defined as
> well... and the | and actuall shift operations to be performed in the
> code and not in the defines
>
>>
>> Best regards,
>> Sean
>>
>> -----Original Message-----
>> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Sent: Friday, January 8, 2021 3:31 AM
>> To: Huang, Sean Z <sean.z.huang@intel.com>;
>> Intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <
>> rodrigo.vivi@intel.com>
>> Subject: Re: [Intel-gfx] [RFC-v19 02/13] drm/i915/pxp: set KCR reg
>> init during the boot time
>>
>> Quoting Vivi, Rodrigo (2021-01-07 17:31:36)
>> > On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
>> > > Set the KCR init during the boot time, which is required by
>> > > hardware, to allow us doing further protection operation such as
>> > > sending commands to GPU or TEE.
>> > >
>> > > Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
>> > > ---
>> > > drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++
>> > > 1 file changed, 8 insertions(+)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
>> > > b/drivers/gpu/drm/i915/pxp/intel_pxp.c
>> > > index 9bc3c7e30654..f566a4fda044 100644
>> > > --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
>> > > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
>> > > @@ -6,6 +6,12 @@
>> > > #include "intel_pxp.h"
>> > > #include "intel_pxp_context.h"
>> > >
>> > > +/* KCR register definitions */
>> >
>> > please define this in i915_reg.h
>>
>> Generally the trend on the GT side is to contain in a .c file if
>> there are no shared users like these. So they should be at this spot,
>> yet the rest of the review comments apply.
>>
>> The spurious comments should be dropped and like Rodrigo pointed out,
>> we should be using the appropriate macros for a masked writes, not
>> baking in the #define.
>>
>> Regards, Joonas
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 55+ messages in thread
* [Intel-gfx] [RFC-v19 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
@ 2021-01-06 23:12 ` Huang, Sean Z
2021-01-07 15:36 ` Vivi, Rodrigo
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 04/13] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
` (15 subsequent siblings)
18 siblings, 1 reply; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-06 23:12 UTC (permalink / raw)
To: Intel-gfx
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(defualt) session.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 137 +++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45 ++++++++
8 files changed, 211 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index cbf2f0594b4d..5494c30cb54f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -262,7 +262,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
- pxp/intel_pxp_context.o
+ pxp/intel_pxp_context.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3e504247f2da..207d50226e64 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
mutex_init(&dev_priv->hdcp_comp_mutex);
+ mutex_init(&dev_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5e5bcef20e33..c2f47daef5a5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1209,6 +1209,12 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index f566a4fda044..c819f3791ee4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
/* KCR register definitions */
#define KCR_INIT _MMIO(0x320f0)
@@ -23,6 +24,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ intel_pxp_tee_component_init(pxp);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
}
@@ -33,5 +36,7 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (INTEL_GEN(gt->i915) < 12)
return;
+ intel_pxp_tee_component_fini(pxp);
+
intel_pxp_ctx_fini(&pxp->ctx);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index 000000000000..5a1ffcc703e2
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include <linux/component.h>
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
+ return -EINVAL;
+
+ lockdep_assert_held(&i915->pxp_tee_comp_mutex);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size, true);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in, msg_in_size);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to send TEE message\n");
+ return -EFAULT;
+ }
+
+ ret = pxp_tee_master->ops->receive(pxp_tee_master->tee_dev, msg_out, msg_out_buf_size);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed to receive TEE message\n");
+ return -EFAULT;
+ }
+
+ if (ret > msg_out_buf_size) {
+ drm_err(&i915->drm, "Failed to receive TEE message due to unexpected output size\n");
+ return -EFAULT;
+ }
+
+ *msg_out_size_ptr = ret;
+ ret = 0;
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE output message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_out, *msg_out_size_ptr, true);
+
+ return ret;
+}
+
+/**
+ * i915_pxp_tee_component_bind - bind funciton to pass the function pointers to pxp_tee
+ * @i915_kdev: pointer to i915 kernel device
+ * @tee_kdev: pointer to tee kernel device
+ * @data: pointer to pxp_tee_master containing the function pointers
+ *
+ * This bind function is called during the system boot or resume from system sleep.
+ *
+ * Return: return 0 if successful.
+ */
+static int i915_pxp_tee_component_bind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+ if (!i915 || !tee_kdev || !data)
+ return -EPERM;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_master = (struct i915_pxp_comp_master *)data;
+ i915->pxp_tee_master->tee_dev = tee_kdev;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ return 0;
+}
+
+static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+ if (!i915 || !tee_kdev || !data)
+ return;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_master = NULL;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+}
+
+static const struct component_ops i915_pxp_tee_component_ops = {
+ .bind = i915_pxp_tee_component_bind,
+ .unbind = i915_pxp_tee_component_unbind,
+};
+
+void intel_pxp_tee_component_init(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops,
+ I915_COMPONENT_PXP);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed at component add(%d)\n", ret);
+ return;
+ }
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_comp_added = true;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+}
+
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ if (!i915->pxp_tee_comp_added) {
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+ return;
+ }
+
+ i915->pxp_tee_comp_added = false;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
new file mode 100644
index 000000000000..4b5e3edb1d9b
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_TEE_H__
+#define __INTEL_PXP_TEE_H__
+
+#include "intel_pxp.h"
+
+void intel_pxp_tee_component_init(struct intel_pxp *pxp);
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_TEE_H__ */
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 55c3b123581b..c1e2a43d2d1e 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -29,6 +29,7 @@
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
+ I915_COMPONENT_PXP
};
/* MAX_PORT is the number of port
diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h
new file mode 100644
index 000000000000..3999e255e145
--- /dev/null
+++ b/include/drm/i915_pxp_tee_interface.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef _I915_PXP_TEE_INTERFACE_H_
+#define _I915_PXP_TEE_INTERFACE_H_
+
+#include <linux/mutex.h>
+#include <linux/device.h>
+
+/**
+ * struct i915_pxp_component_ops - ops for PXP services.
+ * @owner: Module providing the ops
+ * @send: sends data to PXP
+ * @receive: receives data from PXP
+ */
+struct i915_pxp_component_ops {
+ /**
+ * @owner: owner of the module provding the ops
+ */
+ struct module *owner;
+
+ int (*send)(struct device *dev, const void *message, size_t size);
+ int (*receive)(struct device *dev, void *buffer, size_t size);
+};
+
+/**
+ * struct i915_pxp_component_master - Used for communication between i915
+ * and TEE drivers for the PXP services
+ * @tee_dev: device that provide the PXP service from TEE Bus.
+ * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
+ */
+struct i915_pxp_comp_master {
+ struct device *tee_dev;
+ const struct i915_pxp_component_ops *ops;
+
+ /* To protect the above members. */
+ struct mutex mutex;
+};
+
+#endif /* _I915_TEE_PXP_INTERFACE_H_ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 03/13] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
@ 2021-01-07 15:36 ` Vivi, Rodrigo
2021-01-11 22:47 ` Huang, Sean Z
0 siblings, 1 reply; 55+ messages in thread
From: Vivi, Rodrigo @ 2021-01-07 15:36 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> Implement the funcs to create the TEE channel, so kernel can
> send the TEE commands directly to TEE for creating the arbitrary
> (defualt) session.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/i915_drv.c | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 137
> +++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
> include/drm/i915_component.h | 1 +
> include/drm/i915_pxp_tee_interface.h | 45 ++++++++
> 8 files changed, 211 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> create mode 100644 include/drm/i915_pxp_tee_interface.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile
> index cbf2f0594b4d..5494c30cb54f 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -262,7 +262,8 @@ i915-y += i915_perf.o
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> - pxp/intel_pxp_context.o
> + pxp/intel_pxp_context.o \
> + pxp/intel_pxp_tee.o
>
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 3e504247f2da..207d50226e64 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct
> drm_i915_private *dev_priv)
> mutex_init(&dev_priv->wm.wm_mutex);
> mutex_init(&dev_priv->pps_mutex);
> mutex_init(&dev_priv->hdcp_comp_mutex);
> + mutex_init(&dev_priv->pxp_tee_comp_mutex);
>
> i915_memcpy_init_early(dev_priv);
> intel_runtime_pm_init_early(&dev_priv->runtime_pm);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 5e5bcef20e33..c2f47daef5a5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1209,6 +1209,12 @@ struct drm_i915_private {
> /* Mutex to protect the above hdcp component related values.
> */
> struct mutex hdcp_comp_mutex;
>
> + struct i915_pxp_comp_master *pxp_tee_master;
> + bool pxp_tee_comp_added;
> +
> + /* Mutex to protect the above pxp_tee component related
> values. */
> + struct mutex pxp_tee_comp_mutex;
> +
> I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
>
> /*
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index f566a4fda044..c819f3791ee4 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -5,6 +5,7 @@
> #include "i915_drv.h"
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
> +#include "intel_pxp_tee.h"
>
> /* KCR register definitions */
> #define KCR_INIT _MMIO(0x320f0)
> @@ -23,6 +24,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
>
> intel_uncore_write(gt->uncore, KCR_INIT,
> KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
>
> + intel_pxp_tee_component_init(pxp);
> +
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected
> content support initialized\n");
> }
>
> @@ -33,5 +36,7 @@ void intel_pxp_fini(struct intel_pxp *pxp)
> if (INTEL_GEN(gt->i915) < 12)
> return;
>
> + intel_pxp_tee_component_fini(pxp);
> +
> intel_pxp_ctx_fini(&pxp->ctx);
> }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> new file mode 100644
> index 000000000000..5a1ffcc703e2
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -0,0 +1,137 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include <linux/component.h>
> +#include "drm/i915_pxp_tee_interface.h"
> +#include "drm/i915_component.h"
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_context.h"
> +#include "intel_pxp_tee.h"
> +
> +static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
> + void *msg_in, u32 msg_in_size,
> + void *msg_out, u32
> *msg_out_size_ptr,
> + u32 msg_out_buf_size)
> +{
> + int ret;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + struct drm_i915_private *i915 = gt->i915;
> + struct i915_pxp_comp_master *pxp_tee_master = i915-
> >pxp_tee_master;
> +
> + if (!pxp_tee_master || !msg_in || !msg_out ||
> !msg_out_size_ptr)
> + return -EINVAL;
> +
> + lockdep_assert_held(&i915->pxp_tee_comp_mutex);
> +
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> + print_hex_dump(KERN_DEBUG, "TEE input message
> binaries:",
> + DUMP_PREFIX_OFFSET, 4, 4, msg_in,
> msg_in_size, true);
why not use drm debug prints directly?
Also, this patch didn't address any of the concerns that Chris had
raised on v4.
> +
> + ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev,
> msg_in, msg_in_size);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to send TEE message\n");
> + return -EFAULT;
> + }
> +
> + ret = pxp_tee_master->ops->receive(pxp_tee_master->tee_dev,
> msg_out, msg_out_buf_size);
> + if (ret < 0) {
> + drm_err(&i915->drm, "Failed to receive TEE
> message\n");
> + return -EFAULT;
> + }
> +
> + if (ret > msg_out_buf_size) {
> + drm_err(&i915->drm, "Failed to receive TEE message
> due to unexpected output size\n");
> + return -EFAULT;
> + }
> +
> + *msg_out_size_ptr = ret;
> + ret = 0;
> +
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> + print_hex_dump(KERN_DEBUG, "TEE output message
> binaries:",
> + DUMP_PREFIX_OFFSET, 4, 4, msg_out,
> *msg_out_size_ptr, true);
> +
> + return ret;
> +}
> +
> +/**
> + * i915_pxp_tee_component_bind - bind funciton to pass the function
> pointers to pxp_tee
> + * @i915_kdev: pointer to i915 kernel device
> + * @tee_kdev: pointer to tee kernel device
> + * @data: pointer to pxp_tee_master containing the function pointers
> + *
> + * This bind function is called during the system boot or resume
> from system sleep.
> + *
> + * Return: return 0 if successful.
> + */
> +static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> + struct device *tee_kdev, void
> *data)
> +{
> + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> +
> + if (!i915 || !tee_kdev || !data)
> + return -EPERM;
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + i915->pxp_tee_master = (struct i915_pxp_comp_master *)data;
> + i915->pxp_tee_master->tee_dev = tee_kdev;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +
> + return 0;
> +}
> +
> +static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
> + struct device *tee_kdev,
> void *data)
> +{
> + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> +
> + if (!i915 || !tee_kdev || !data)
> + return;
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + i915->pxp_tee_master = NULL;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +}
> +
> +static const struct component_ops i915_pxp_tee_component_ops = {
> + .bind = i915_pxp_tee_component_bind,
> + .unbind = i915_pxp_tee_component_unbind,
> +};
> +
> +void intel_pxp_tee_component_init(struct intel_pxp *pxp)
> +{
> + int ret;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + struct drm_i915_private *i915 = gt->i915;
> +
> + ret = component_add_typed(i915->drm.dev,
> &i915_pxp_tee_component_ops,
> + I915_COMPONENT_PXP);
> + if (ret < 0) {
> + drm_err(&i915->drm, "Failed at component add(%d)\n",
> ret);
> + return;
> + }
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + i915->pxp_tee_comp_added = true;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +}
> +
> +void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + struct drm_i915_private *i915 = gt->i915;
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + if (!i915->pxp_tee_comp_added) {
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> + return;
> + }
> +
> + i915->pxp_tee_comp_added = false;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +
> + component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> new file mode 100644
> index 000000000000..4b5e3edb1d9b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_TEE_H__
> +#define __INTEL_PXP_TEE_H__
> +
> +#include "intel_pxp.h"
> +
> +void intel_pxp_tee_component_init(struct intel_pxp *pxp);
> +void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
> +
> +#endif /* __INTEL_PXP_TEE_H__ */
> diff --git a/include/drm/i915_component.h
> b/include/drm/i915_component.h
> index 55c3b123581b..c1e2a43d2d1e 100644
> --- a/include/drm/i915_component.h
> +++ b/include/drm/i915_component.h
> @@ -29,6 +29,7 @@
> enum i915_component_type {
> I915_COMPONENT_AUDIO = 1,
> I915_COMPONENT_HDCP,
> + I915_COMPONENT_PXP
> };
>
> /* MAX_PORT is the number of port
> diff --git a/include/drm/i915_pxp_tee_interface.h
> b/include/drm/i915_pxp_tee_interface.h
> new file mode 100644
> index 000000000000..3999e255e145
> --- /dev/null
> +++ b/include/drm/i915_pxp_tee_interface.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Authors:
> + * Vitaly Lubart <vitaly.lubart@intel.com>
> + */
> +
> +#ifndef _I915_PXP_TEE_INTERFACE_H_
> +#define _I915_PXP_TEE_INTERFACE_H_
> +
> +#include <linux/mutex.h>
> +#include <linux/device.h>
> +
> +/**
> + * struct i915_pxp_component_ops - ops for PXP services.
> + * @owner: Module providing the ops
> + * @send: sends data to PXP
> + * @receive: receives data from PXP
> + */
> +struct i915_pxp_component_ops {
> + /**
> + * @owner: owner of the module provding the ops
> + */
> + struct module *owner;
> +
> + int (*send)(struct device *dev, const void *message, size_t
> size);
> + int (*receive)(struct device *dev, void *buffer, size_t
> size);
> +};
> +
> +/**
> + * struct i915_pxp_component_master - Used for communication between
> i915
> + * and TEE drivers for the PXP services
> + * @tee_dev: device that provide the PXP service from TEE Bus.
> + * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
> + */
> +struct i915_pxp_comp_master {
> + struct device *tee_dev;
> + const struct i915_pxp_component_ops *ops;
> +
> + /* To protect the above members. */
> + struct mutex mutex;
> +};
> +
> +#endif /* _I915_TEE_PXP_INTERFACE_H_ */
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^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
2021-01-07 15:36 ` Vivi, Rodrigo
@ 2021-01-11 22:47 ` Huang, Sean Z
0 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-11 22:47 UTC (permalink / raw)
To: Vivi, Rodrigo, Intel-gfx
Hi Rodrigo,
I removed the debug print print_hex_dump() in this patch, this change will reflect at rev20.
Regarding to the Chris's question for mutex, actually what I'm doing the similar with the existing hdcp_comp_added and hdcp_comp_mutex in https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/i915/display/intel_hdcp.c#L2002
During the bind/unbind, we would need to protect pxp_tee_comp_added with pxp_tee_comp_mutex, to make sure no race condition between intel_pxp_tee_component_init() and intel_pxp_tee_component_fini().
So hopefully this mutex is acceptable. Thank you!
Best regards,
Sean
-----Original Message-----
From: Vivi, Rodrigo <rodrigo.vivi@intel.com>
Sent: Thursday, January 7, 2021 7:36 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v19 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> Implement the funcs to create the TEE channel, so kernel can send the
> TEE commands directly to TEE for creating the arbitrary
> (defualt) session.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/i915_drv.c | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 137
> +++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
> include/drm/i915_component.h | 1 +
> include/drm/i915_pxp_tee_interface.h | 45 ++++++++
> 8 files changed, 211 insertions(+), 1 deletion(-) create mode 100644
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> create mode 100644 include/drm/i915_pxp_tee_interface.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile index cbf2f0594b4d..5494c30cb54f
> 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -262,7 +262,8 @@ i915-y += i915_perf.o # Protected execution
> platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> - pxp/intel_pxp_context.o
> + pxp/intel_pxp_context.o \
> + pxp/intel_pxp_tee.o
>
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o diff --git
> a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 3e504247f2da..207d50226e64 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct
> drm_i915_private *dev_priv)
> mutex_init(&dev_priv->wm.wm_mutex);
> mutex_init(&dev_priv->pps_mutex);
> mutex_init(&dev_priv->hdcp_comp_mutex);
> + mutex_init(&dev_priv->pxp_tee_comp_mutex);
>
> i915_memcpy_init_early(dev_priv);
> intel_runtime_pm_init_early(&dev_priv->runtime_pm);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 5e5bcef20e33..c2f47daef5a5
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1209,6 +1209,12 @@ struct drm_i915_private {
> /* Mutex to protect the above hdcp component related values.
> */
> struct mutex hdcp_comp_mutex;
>
> + struct i915_pxp_comp_master *pxp_tee_master;
> + bool pxp_tee_comp_added;
> +
> + /* Mutex to protect the above pxp_tee component related
> values. */
> + struct mutex pxp_tee_comp_mutex;
> +
> I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
>
> /*
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index f566a4fda044..c819f3791ee4 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -5,6 +5,7 @@
> #include "i915_drv.h"
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
> +#include "intel_pxp_tee.h"
>
> /* KCR register definitions */
> #define KCR_INIT _MMIO(0x320f0)
> @@ -23,6 +24,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
>
> intel_uncore_write(gt->uncore, KCR_INIT,
> KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
>
> + intel_pxp_tee_component_init(pxp);
> +
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected
> content support initialized\n"); }
>
> @@ -33,5 +36,7 @@ void intel_pxp_fini(struct intel_pxp *pxp)
> if (INTEL_GEN(gt->i915) < 12)
> return;
>
> + intel_pxp_tee_component_fini(pxp);
> +
> intel_pxp_ctx_fini(&pxp->ctx); } diff --git
> a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> new file mode 100644
> index 000000000000..5a1ffcc703e2
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -0,0 +1,137 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include <linux/component.h>
> +#include "drm/i915_pxp_tee_interface.h"
> +#include "drm/i915_component.h"
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_context.h"
> +#include "intel_pxp_tee.h"
> +
> +static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
> + void *msg_in, u32 msg_in_size,
> + void *msg_out, u32
> *msg_out_size_ptr,
> + u32 msg_out_buf_size) {
> + int ret;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + struct drm_i915_private *i915 = gt->i915;
> + struct i915_pxp_comp_master *pxp_tee_master = i915-
> >pxp_tee_master;
> +
> + if (!pxp_tee_master || !msg_in || !msg_out ||
> !msg_out_size_ptr)
> + return -EINVAL;
> +
> + lockdep_assert_held(&i915->pxp_tee_comp_mutex);
> +
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> + print_hex_dump(KERN_DEBUG, "TEE input message
> binaries:",
> + DUMP_PREFIX_OFFSET, 4, 4, msg_in,
> msg_in_size, true);
why not use drm debug prints directly?
Also, this patch didn't address any of the concerns that Chris had raised on v4.
> +
> + ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev,
> msg_in, msg_in_size);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to send TEE message\n");
> + return -EFAULT;
> + }
> +
> + ret = pxp_tee_master->ops->receive(pxp_tee_master->tee_dev,
> msg_out, msg_out_buf_size);
> + if (ret < 0) {
> + drm_err(&i915->drm, "Failed to receive TEE
> message\n");
> + return -EFAULT;
> + }
> +
> + if (ret > msg_out_buf_size) {
> + drm_err(&i915->drm, "Failed to receive TEE message
> due to unexpected output size\n");
> + return -EFAULT;
> + }
> +
> + *msg_out_size_ptr = ret;
> + ret = 0;
> +
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> + print_hex_dump(KERN_DEBUG, "TEE output message
> binaries:",
> + DUMP_PREFIX_OFFSET, 4, 4, msg_out,
> *msg_out_size_ptr, true);
> +
> + return ret;
> +}
> +
> +/**
> + * i915_pxp_tee_component_bind - bind funciton to pass the function
> pointers to pxp_tee
> + * @i915_kdev: pointer to i915 kernel device
> + * @tee_kdev: pointer to tee kernel device
> + * @data: pointer to pxp_tee_master containing the function pointers
> + *
> + * This bind function is called during the system boot or resume
> from system sleep.
> + *
> + * Return: return 0 if successful.
> + */
> +static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> + struct device *tee_kdev, void
> *data)
> +{
> + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> +
> + if (!i915 || !tee_kdev || !data)
> + return -EPERM;
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + i915->pxp_tee_master = (struct i915_pxp_comp_master *)data;
> + i915->pxp_tee_master->tee_dev = tee_kdev;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +
> + return 0;
> +}
> +
> +static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
> + struct device *tee_kdev,
> void *data)
> +{
> + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> +
> + if (!i915 || !tee_kdev || !data)
> + return;
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + i915->pxp_tee_master = NULL;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +}
> +
> +static const struct component_ops i915_pxp_tee_component_ops = {
> + .bind = i915_pxp_tee_component_bind,
> + .unbind = i915_pxp_tee_component_unbind, };
> +
> +void intel_pxp_tee_component_init(struct intel_pxp *pxp) {
> + int ret;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + struct drm_i915_private *i915 = gt->i915;
> +
> + ret = component_add_typed(i915->drm.dev,
> &i915_pxp_tee_component_ops,
> + I915_COMPONENT_PXP);
> + if (ret < 0) {
> + drm_err(&i915->drm, "Failed at component add(%d)\n",
> ret);
> + return;
> + }
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + i915->pxp_tee_comp_added = true;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +}
> +
> +void intel_pxp_tee_component_fini(struct intel_pxp *pxp) {
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + struct drm_i915_private *i915 = gt->i915;
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + if (!i915->pxp_tee_comp_added) {
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> + return;
> + }
> +
> + i915->pxp_tee_comp_added = false;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +
> + component_del(i915->drm.dev, &i915_pxp_tee_component_ops); }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> new file mode 100644
> index 000000000000..4b5e3edb1d9b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_TEE_H__
> +#define __INTEL_PXP_TEE_H__
> +
> +#include "intel_pxp.h"
> +
> +void intel_pxp_tee_component_init(struct intel_pxp *pxp); void
> +intel_pxp_tee_component_fini(struct intel_pxp *pxp);
> +
> +#endif /* __INTEL_PXP_TEE_H__ */
> diff --git a/include/drm/i915_component.h
> b/include/drm/i915_component.h index 55c3b123581b..c1e2a43d2d1e 100644
> --- a/include/drm/i915_component.h
> +++ b/include/drm/i915_component.h
> @@ -29,6 +29,7 @@
> enum i915_component_type {
> I915_COMPONENT_AUDIO = 1,
> I915_COMPONENT_HDCP,
> + I915_COMPONENT_PXP
> };
>
> /* MAX_PORT is the number of port
> diff --git a/include/drm/i915_pxp_tee_interface.h
> b/include/drm/i915_pxp_tee_interface.h
> new file mode 100644
> index 000000000000..3999e255e145
> --- /dev/null
> +++ b/include/drm/i915_pxp_tee_interface.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Authors:
> + * Vitaly Lubart <vitaly.lubart@intel.com> */
> +
> +#ifndef _I915_PXP_TEE_INTERFACE_H_
> +#define _I915_PXP_TEE_INTERFACE_H_
> +
> +#include <linux/mutex.h>
> +#include <linux/device.h>
> +
> +/**
> + * struct i915_pxp_component_ops - ops for PXP services.
> + * @owner: Module providing the ops
> + * @send: sends data to PXP
> + * @receive: receives data from PXP
> + */
> +struct i915_pxp_component_ops {
> + /**
> + * @owner: owner of the module provding the ops
> + */
> + struct module *owner;
> +
> + int (*send)(struct device *dev, const void *message, size_t
> size);
> + int (*receive)(struct device *dev, void *buffer, size_t
> size);
> +};
> +
> +/**
> + * struct i915_pxp_component_master - Used for communication between
> i915
> + * and TEE drivers for the PXP services
> + * @tee_dev: device that provide the PXP service from TEE Bus.
> + * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
> + */
> +struct i915_pxp_comp_master {
> + struct device *tee_dev;
> + const struct i915_pxp_component_ops *ops;
> +
> + /* To protect the above members. */
> + struct mutex mutex;
> +};
> +
> +#endif /* _I915_TEE_PXP_INTERFACE_H_ */
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 55+ messages in thread
* [Intel-gfx] [RFC-v19 04/13] drm/i915/pxp: Create the arbitrary session after boot
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (2 preceding siblings ...)
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 03/13] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
@ 2021-01-06 23:12 ` Huang, Sean Z
2021-01-07 15:40 ` Vivi, Rodrigo
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 05/13] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
` (14 subsequent siblings)
18 siblings, 1 reply; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-06 23:12 UTC (permalink / raw)
To: Intel-gfx
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 131 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 16 +++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 73 +++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 26 ++++
9 files changed, 268 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5494c30cb54f..af9e87e4c63a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -262,6 +262,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_arb.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index c819f3791ee4..3868e8c697f9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_arb.h"
/* KCR register definitions */
#define KCR_INIT _MMIO(0x320f0)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index f47bc6bea34f..8fc91e900b16 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -8,6 +8,22 @@
#include "intel_pxp_types.h"
+enum pxp_session_types {
+ SESSION_TYPE_TYPE0 = 0,
+ SESSION_TYPE_TYPE1 = 1,
+
+ SESSION_TYPE_MAX
+};
+
+enum pxp_protection_modes {
+ PROTECTION_MODE_NONE = 0,
+ PROTECTION_MODE_LM = 2,
+ PROTECTION_MODE_HM = 3,
+ PROTECTION_MODE_SM = 6,
+
+ PROTECTION_MODE_ALL
+};
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
new file mode 100644
index 000000000000..640d7103c04d
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp_types.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
+
+/* Arbitrary session */
+#define ARB_SESSION_INDEX 0xf
+#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0
+
+bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp)
+{
+ u32 regval_sip = 0;
+ intel_wakeref_t wakeref;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
+ regval_sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+ }
+
+ return regval_sip & BIT(ARB_SESSION_INDEX);
+}
+
+/* wait hw session_in_play reg to match the current sw state */
+static int wait_arb_hw_sw_state(struct intel_pxp *pxp)
+{
+ const int max_retry = 10;
+ const int ms_delay = 10;
+ int retry = 0;
+ int ret;
+ struct pxp_protected_session *arb = &pxp->ctx.arb_session;
+
+ ret = -EINVAL;
+ for (retry = 0; retry < max_retry; retry++) {
+ if (intel_pxp_arb_session_is_in_play(pxp) ==
+ arb->is_in_play) {
+ ret = 0;
+ break;
+ }
+
+ msleep(ms_delay);
+ }
+
+ return ret;
+}
+
+static void arb_session_entry_init(struct intel_pxp *pxp)
+{
+ struct pxp_protected_session *arb = &pxp->ctx.arb_session;
+
+ arb->type = ARB_SESSION_TYPE;
+ arb->protection_mode = PROTECTION_MODE_HM;
+ arb->index = ARB_SESSION_INDEX;
+ arb->is_in_play = false;
+}
+
+static int intel_pxp_arb_reserve_session(struct intel_pxp *pxp)
+{
+ int ret;
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ arb_session_entry_init(pxp);
+ ret = wait_arb_hw_sw_state(pxp);
+
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_mark_session_in_play - To put an reserved protected session to "in_play" state
+ * @pxp: pointer to pxp struct.
+ *
+ * Return: status. 0 means update is successful.
+ */
+static int intel_pxp_arb_mark_session_in_play(struct intel_pxp *pxp)
+{
+ struct pxp_protected_session *arb = &pxp->ctx.arb_session;
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ if (arb->is_in_play)
+ return -EINVAL;
+
+ arb->is_in_play = true;
+ return 0;
+}
+
+int intel_pxp_arb_create_session(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ if (pxp->ctx.flag_display_hm_surface_keys) {
+ drm_err(>->i915->drm, "%s: arb session is alive so skipping the creation\n",
+ __func__);
+ return 0;
+ }
+
+ ret = intel_pxp_arb_reserve_session(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to reserve arb session\n");
+ return ret;
+ }
+
+ ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION_INDEX);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to send tee cmd for arb session creation\n");
+ return ret;
+ }
+
+ ret = intel_pxp_arb_mark_session_in_play(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to mark arb session status in play\n");
+ return ret;
+ }
+
+ pxp->ctx.flag_display_hm_surface_keys = true;
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
new file mode 100644
index 000000000000..2196153dd879
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_ARB_H__
+#define __INTEL_PXP_ARB_H__
+
+#include <linux/types.h>
+
+struct intel_pxp;
+
+int intel_pxp_arb_create_session(struct intel_pxp *pxp);
+bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_ARB_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
index f51021c33d45..bf2feb4aaf6d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -8,6 +8,7 @@
#include <linux/mutex.h>
#include "intel_pxp_types.h"
+#include "intel_pxp_arb.h"
void intel_pxp_ctx_init(struct pxp_context *ctx);
void intel_pxp_ctx_fini(struct pxp_context *ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 5a1ffcc703e2..41d8a31bbb75 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -10,6 +10,32 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_arb.h"
+
+#define PXP_TEE_APIVER 0x40002
+#define PXP_TEE_ARB_CMDID 0x1e
+#define PXP_TEE_ARB_PROTECTION_MODE 0x2
+
+/* PXP TEE message header */
+struct pxp_tee_cmd_header {
+ u32 api_version;
+ u32 command_id;
+ u32 status;
+ /* Length of the message (excluding the header) */
+ u32 buffer_len;
+} __packed;
+
+/* PXP TEE message input to create a arbitrary session */
+struct pxp_tee_create_arb_in {
+ struct pxp_tee_cmd_header header;
+ u32 protection_mode;
+ u32 session_id;
+} __packed;
+
+/* PXP TEE message output to create a arbitrary session */
+struct pxp_tee_create_arb_out {
+ struct pxp_tee_cmd_header header;
+} __packed;
static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
void *msg_in, u32 msg_in_size,
@@ -70,7 +96,9 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
static int i915_pxp_tee_component_bind(struct device *i915_kdev,
struct device *tee_kdev, void *data)
{
+ int ret = 0;
struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+ struct intel_pxp *pxp = &i915->gt.pxp;
if (!i915 || !tee_kdev || !data)
return -EPERM;
@@ -80,6 +108,19 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
i915->pxp_tee_master->tee_dev = tee_kdev;
mutex_unlock(&i915->pxp_tee_comp_mutex);
+ mutex_lock(&pxp->ctx.mutex);
+
+ /* Create arb session only if tee is ready, during system boot or sleep/resume */
+ if (!intel_pxp_arb_session_is_in_play(pxp))
+ ret = intel_pxp_arb_create_session(pxp);
+
+ mutex_unlock(&pxp->ctx.mutex);
+
+ if (ret) {
+ drm_err(&i915->drm, "Failed to create arb session ret=[%d]\n", ret);
+ return ret;
+ }
+
return 0;
}
@@ -135,3 +176,35 @@ void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
}
+
+int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
+ int arb_session_id)
+{
+ int ret;
+ u32 msg_out_size_received = 0;
+ struct pxp_tee_create_arb_in msg_in = {0};
+ struct pxp_tee_create_arb_out msg_out = {0};
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ msg_in.header.api_version = PXP_TEE_APIVER;
+ msg_in.header.command_id = PXP_TEE_ARB_CMDID;
+ msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header);
+ msg_in.protection_mode = PXP_TEE_ARB_PROTECTION_MODE;
+ msg_in.session_id = arb_session_id;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+
+ ret = intel_pxp_tee_io_message(pxp,
+ &msg_in,
+ sizeof(msg_in),
+ &msg_out, &msg_out_size_received,
+ sizeof(msg_out));
+
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ if (ret)
+ drm_err(&i915->drm, "Failed to send tee msg ret=[%d]\n", ret);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
index 4b5e3edb1d9b..c46f9033f709 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -11,4 +11,7 @@
void intel_pxp_tee_component_init(struct intel_pxp *pxp);
void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
+int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
+ int arb_session_id);
+
#endif /* __INTEL_PXP_TEE_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index f9b40ea98b1b..287ba1e0ed9d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -8,12 +8,38 @@
#include <linux/mutex.h>
+/**
+ * struct pxp_protected_session - structure to track all active sessions.
+ */
+struct pxp_protected_session {
+ /** @index: Numeric identifier for this protected session */
+ int index;
+ /** @type: Type of session */
+ int type;
+ /** @protection_mode: mode of protection requested */
+ int protection_mode;
+
+ /**
+ * @is_in_play: indicates whether the session has been established
+ * in the HW root of trust if this flag is false, it
+ * indicates an application has reserved this session,
+ * but has not * established the session in the
+ * hardware yet.
+ */
+ bool is_in_play;
+};
+
/* struct pxp_context - Represents combined view of driver and logical HW states. */
struct pxp_context {
/** @mutex: mutex to protect the pxp context */
struct mutex mutex;
bool inited;
+
+ struct pxp_protected_session arb_session;
+ u32 arb_session_pxp_tag;
+
+ bool flag_display_hm_surface_keys;
};
struct intel_pxp {
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 04/13] drm/i915/pxp: Create the arbitrary session after boot
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 04/13] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
@ 2021-01-07 15:40 ` Vivi, Rodrigo
2021-01-11 23:48 ` Huang, Sean Z
0 siblings, 1 reply; 55+ messages in thread
From: Vivi, Rodrigo @ 2021-01-07 15:40 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> Create the arbitrary session, with the fixed session id 0xf, after
> system boot, for the case that application allocates the protected
> buffer without establishing any protection session. Because the
> hardware requires at least one alive session for protected buffer
> creation. This arbitrary session needs to be re-created after
> teardown or power event because hardware encryption key won't be
> valid after such cases.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 131
> +++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 16 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 73 +++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 26 ++++
> 9 files changed, 268 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile
> index 5494c30cb54f..af9e87e4c63a 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -262,6 +262,7 @@ i915-y += i915_perf.o
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> + pxp/intel_pxp_arb.o \
> pxp/intel_pxp_context.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index c819f3791ee4..3868e8c697f9 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,7 @@
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
> #include "intel_pxp_tee.h"
> +#include "intel_pxp_arb.h"
>
> /* KCR register definitions */
> #define KCR_INIT _MMIO(0x320f0)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index f47bc6bea34f..8fc91e900b16 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -8,6 +8,22 @@
>
> #include "intel_pxp_types.h"
>
> +enum pxp_session_types {
> + SESSION_TYPE_TYPE0 = 0,
> + SESSION_TYPE_TYPE1 = 1,
> +
> + SESSION_TYPE_MAX
> +};
> +
> +enum pxp_protection_modes {
> + PROTECTION_MODE_NONE = 0,
> + PROTECTION_MODE_LM = 2,
> + PROTECTION_MODE_HM = 3,
> + PROTECTION_MODE_SM = 6,
> +
> + PROTECTION_MODE_ALL
> +};
> +
> #ifdef CONFIG_DRM_I915_PXP
> void intel_pxp_init(struct intel_pxp *pxp);
> void intel_pxp_fini(struct intel_pxp *pxp);
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> new file mode 100644
> index 000000000000..640d7103c04d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> @@ -0,0 +1,131 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "gt/intel_context.h"
> +#include "gt/intel_engine_pm.h"
> +
> +#include "intel_pxp_types.h"
> +#include "intel_pxp_arb.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_tee.h"
> +
> +#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-
> 31 */
> +
> +/* Arbitrary session */
> +#define ARB_SESSION_INDEX 0xf
> +#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0
All reg defines should be in i915_reg.h
> +
> +bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp)
> +{
> + u32 regval_sip = 0;
> + intel_wakeref_t wakeref;
> + struct intel_gt *gt = container_of(pxp, struct intel_gt,
> pxp);
> +
> + with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
> + regval_sip = intel_uncore_read(gt->uncore,
> GEN12_KCR_SIP);
> + }
> +
> + return regval_sip & BIT(ARB_SESSION_INDEX);
> +}
> +
> +/* wait hw session_in_play reg to match the current sw state */
> +static int wait_arb_hw_sw_state(struct intel_pxp *pxp)
> +{
> + const int max_retry = 10;
> + const int ms_delay = 10;
> + int retry = 0;
> + int ret;
> + struct pxp_protected_session *arb = &pxp->ctx.arb_session;
> +
> + ret = -EINVAL;
> + for (retry = 0; retry < max_retry; retry++) {
> + if (intel_pxp_arb_session_is_in_play(pxp) ==
> + arb->is_in_play) {
> + ret = 0;
> + break;
> + }
> +
> + msleep(ms_delay);
> + }
> +
> + return ret;
> +}
> +
> +static void arb_session_entry_init(struct intel_pxp *pxp)
> +{
> + struct pxp_protected_session *arb = &pxp->ctx.arb_session;
> +
> + arb->type = ARB_SESSION_TYPE;
> + arb->protection_mode = PROTECTION_MODE_HM;
> + arb->index = ARB_SESSION_INDEX;
> + arb->is_in_play = false;
> +}
> +
> +static int intel_pxp_arb_reserve_session(struct intel_pxp *pxp)
> +{
> + int ret;
> +
> + lockdep_assert_held(&pxp->ctx.mutex);
> +
> + arb_session_entry_init(pxp);
> + ret = wait_arb_hw_sw_state(pxp);
> +
> + return ret;
> +}
> +
> +/**
> + * intel_pxp_arb_mark_session_in_play - To put an reserved protected
> session to "in_play" state
> + * @pxp: pointer to pxp struct.
> + *
> + * Return: status. 0 means update is successful.
> + */
> +static int intel_pxp_arb_mark_session_in_play(struct intel_pxp *pxp)
> +{
> + struct pxp_protected_session *arb = &pxp->ctx.arb_session;
> +
> + lockdep_assert_held(&pxp->ctx.mutex);
> +
> + if (arb->is_in_play)
> + return -EINVAL;
> +
> + arb->is_in_play = true;
> + return 0;
> +}
> +
> +int intel_pxp_arb_create_session(struct intel_pxp *pxp)
> +{
> + int ret;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> +
> + lockdep_assert_held(&pxp->ctx.mutex);
> +
> + if (pxp->ctx.flag_display_hm_surface_keys) {
> + drm_err(>->i915->drm, "%s: arb session is alive so
> skipping the creation\n",
> + __func__);
> + return 0;
> + }
> +
> + ret = intel_pxp_arb_reserve_session(pxp);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to reserve arb
> session\n");
> + return ret;
> + }
> +
> + ret = intel_pxp_tee_cmd_create_arb_session(pxp,
> ARB_SESSION_INDEX);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to send tee cmd for
> arb session creation\n");
> + return ret;
> + }
> +
> + ret = intel_pxp_arb_mark_session_in_play(pxp);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to mark arb session
> status in play\n");
> + return ret;
> + }
> +
> + pxp->ctx.flag_display_hm_surface_keys = true;
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> new file mode 100644
> index 000000000000..2196153dd879
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_ARB_H__
> +#define __INTEL_PXP_ARB_H__
> +
> +#include <linux/types.h>
> +
> +struct intel_pxp;
> +
> +int intel_pxp_arb_create_session(struct intel_pxp *pxp);
> +bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp);
> +
> +#endif /* __INTEL_PXP_ARB_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> index f51021c33d45..bf2feb4aaf6d 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -8,6 +8,7 @@
>
> #include <linux/mutex.h>
> #include "intel_pxp_types.h"
> +#include "intel_pxp_arb.h"
>
> void intel_pxp_ctx_init(struct pxp_context *ctx);
> void intel_pxp_ctx_fini(struct pxp_context *ctx);
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> index 5a1ffcc703e2..41d8a31bbb75 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -10,6 +10,32 @@
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
> #include "intel_pxp_tee.h"
> +#include "intel_pxp_arb.h"
> +
> +#define PXP_TEE_APIVER 0x40002
> +#define PXP_TEE_ARB_CMDID 0x1e
> +#define PXP_TEE_ARB_PROTECTION_MODE 0x2
> +
> +/* PXP TEE message header */
> +struct pxp_tee_cmd_header {
> + u32 api_version;
> + u32 command_id;
> + u32 status;
> + /* Length of the message (excluding the header) */
> + u32 buffer_len;
> +} __packed;
> +
> +/* PXP TEE message input to create a arbitrary session */
> +struct pxp_tee_create_arb_in {
> + struct pxp_tee_cmd_header header;
> + u32 protection_mode;
> + u32 session_id;
> +} __packed;
> +
> +/* PXP TEE message output to create a arbitrary session */
> +struct pxp_tee_create_arb_out {
> + struct pxp_tee_cmd_header header;
> +} __packed;
>
> static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
> void *msg_in, u32 msg_in_size,
> @@ -70,7 +96,9 @@ static int intel_pxp_tee_io_message(struct
> intel_pxp *pxp,
> static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> struct device *tee_kdev, void
> *data)
> {
> + int ret = 0;
> struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> + struct intel_pxp *pxp = &i915->gt.pxp;
>
> if (!i915 || !tee_kdev || !data)
> return -EPERM;
> @@ -80,6 +108,19 @@ static int i915_pxp_tee_component_bind(struct
> device *i915_kdev,
> i915->pxp_tee_master->tee_dev = tee_kdev;
> mutex_unlock(&i915->pxp_tee_comp_mutex);
>
> + mutex_lock(&pxp->ctx.mutex);
> +
> + /* Create arb session only if tee is ready, during system
> boot or sleep/resume */
> + if (!intel_pxp_arb_session_is_in_play(pxp))
> + ret = intel_pxp_arb_create_session(pxp);
> +
> + mutex_unlock(&pxp->ctx.mutex);
> +
> + if (ret) {
> + drm_err(&i915->drm, "Failed to create arb session
> ret=[%d]\n", ret);
> + return ret;
> + }
> +
> return 0;
> }
>
> @@ -135,3 +176,35 @@ void intel_pxp_tee_component_fini(struct
> intel_pxp *pxp)
>
> component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
> }
> +
> +int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
> + int arb_session_id)
> +{
> + int ret;
> + u32 msg_out_size_received = 0;
> + struct pxp_tee_create_arb_in msg_in = {0};
> + struct pxp_tee_create_arb_out msg_out = {0};
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + struct drm_i915_private *i915 = gt->i915;
> +
> + msg_in.header.api_version = PXP_TEE_APIVER;
> + msg_in.header.command_id = PXP_TEE_ARB_CMDID;
> + msg_in.header.buffer_len = sizeof(msg_in) -
> sizeof(msg_in.header);
> + msg_in.protection_mode = PXP_TEE_ARB_PROTECTION_MODE;
> + msg_in.session_id = arb_session_id;
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> +
> + ret = intel_pxp_tee_io_message(pxp,
> + &msg_in,
> + sizeof(msg_in),
> + &msg_out,
> &msg_out_size_received,
> + sizeof(msg_out));
> +
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +
> + if (ret)
> + drm_err(&i915->drm, "Failed to send tee msg
> ret=[%d]\n", ret);
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> index 4b5e3edb1d9b..c46f9033f709 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> @@ -11,4 +11,7 @@
> void intel_pxp_tee_component_init(struct intel_pxp *pxp);
> void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
>
> +int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
> + int arb_session_id);
> +
> #endif /* __INTEL_PXP_TEE_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> index f9b40ea98b1b..287ba1e0ed9d 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -8,12 +8,38 @@
>
> #include <linux/mutex.h>
>
> +/**
> + * struct pxp_protected_session - structure to track all active
> sessions.
> + */
> +struct pxp_protected_session {
> + /** @index: Numeric identifier for this protected session */
> + int index;
> + /** @type: Type of session */
> + int type;
> + /** @protection_mode: mode of protection requested */
> + int protection_mode;
> +
> + /**
> + * @is_in_play: indicates whether the session has been
> established
> + * in the HW root of trust if this flag is
> false, it
> + * indicates an application has reserved this
> session,
> + * but has not * established the session in the
> + * hardware yet.
> + */
> + bool is_in_play;
> +};
> +
> /* struct pxp_context - Represents combined view of driver and
> logical HW states. */
> struct pxp_context {
> /** @mutex: mutex to protect the pxp context */
> struct mutex mutex;
>
> bool inited;
> +
> + struct pxp_protected_session arb_session;
> + u32 arb_session_pxp_tag;
> +
> + bool flag_display_hm_surface_keys;
> };
>
> struct intel_pxp {
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^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 04/13] drm/i915/pxp: Create the arbitrary session after boot
2021-01-07 15:40 ` Vivi, Rodrigo
@ 2021-01-11 23:48 ` Huang, Sean Z
0 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-11 23:48 UTC (permalink / raw)
To: Vivi, Rodrigo, Intel-gfx
Hi Rodrigo,
Quoted from Joonas at https://patchwork.freedesktop.org/patch/412397/?series=84620&rev=19
" Generally the trend on the GT side is to contain in a .c file if there are
no shared users like these. So they should be at this spot, yet the rest
of the review comments apply."
So I think the define GEN12_KCR_SIP should stay in intel_pxp_arb.c since it's no shared users.
But anyway please let me know if you insist to move it to i915_reg.h
Best regards,
Sean
-----Original Message-----
From: Vivi, Rodrigo <rodrigo.vivi@intel.com>
Sent: Thursday, January 7, 2021 7:40 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v19 04/13] drm/i915/pxp: Create the arbitrary session after boot
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> Create the arbitrary session, with the fixed session id 0xf, after
> system boot, for the case that application allocates the protected
> buffer without establishing any protection session. Because the
> hardware requires at least one alive session for protected buffer
> creation. This arbitrary session needs to be re-created after
> teardown or power event because hardware encryption key won't be valid
> after such cases.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 131
> +++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 16 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 73 +++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 26 ++++
> 9 files changed, 268 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile index 5494c30cb54f..af9e87e4c63a
> 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -262,6 +262,7 @@ i915-y += i915_perf.o # Protected execution
> platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> + pxp/intel_pxp_arb.o \
> pxp/intel_pxp_context.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index c819f3791ee4..3868e8c697f9 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,7 @@
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
> #include "intel_pxp_tee.h"
> +#include "intel_pxp_arb.h"
>
> /* KCR register definitions */
> #define KCR_INIT _MMIO(0x320f0)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index f47bc6bea34f..8fc91e900b16 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -8,6 +8,22 @@
>
> #include "intel_pxp_types.h"
>
> +enum pxp_session_types {
> + SESSION_TYPE_TYPE0 = 0,
> + SESSION_TYPE_TYPE1 = 1,
> +
> + SESSION_TYPE_MAX
> +};
> +
> +enum pxp_protection_modes {
> + PROTECTION_MODE_NONE = 0,
> + PROTECTION_MODE_LM = 2,
> + PROTECTION_MODE_HM = 3,
> + PROTECTION_MODE_SM = 6,
> +
> + PROTECTION_MODE_ALL
> +};
> +
> #ifdef CONFIG_DRM_I915_PXP
> void intel_pxp_init(struct intel_pxp *pxp); void
> intel_pxp_fini(struct intel_pxp *pxp); diff --git
> a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> new file mode 100644
> index 000000000000..640d7103c04d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> @@ -0,0 +1,131 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "gt/intel_context.h"
> +#include "gt/intel_engine_pm.h"
> +
> +#include "intel_pxp_types.h"
> +#include "intel_pxp_arb.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_tee.h"
> +
> +#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-
> 31 */
> +
> +/* Arbitrary session */
> +#define ARB_SESSION_INDEX 0xf
> +#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0
All reg defines should be in i915_reg.h
> +
> +bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp) {
> + u32 regval_sip = 0;
> + intel_wakeref_t wakeref;
> + struct intel_gt *gt = container_of(pxp, struct intel_gt,
> pxp);
> +
> + with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
> + regval_sip = intel_uncore_read(gt->uncore,
> GEN12_KCR_SIP);
> + }
> +
> + return regval_sip & BIT(ARB_SESSION_INDEX); }
> +
> +/* wait hw session_in_play reg to match the current sw state */
> +static int wait_arb_hw_sw_state(struct intel_pxp *pxp) {
> + const int max_retry = 10;
> + const int ms_delay = 10;
> + int retry = 0;
> + int ret;
> + struct pxp_protected_session *arb = &pxp->ctx.arb_session;
> +
> + ret = -EINVAL;
> + for (retry = 0; retry < max_retry; retry++) {
> + if (intel_pxp_arb_session_is_in_play(pxp) ==
> + arb->is_in_play) {
> + ret = 0;
> + break;
> + }
> +
> + msleep(ms_delay);
> + }
> +
> + return ret;
> +}
> +
> +static void arb_session_entry_init(struct intel_pxp *pxp) {
> + struct pxp_protected_session *arb = &pxp->ctx.arb_session;
> +
> + arb->type = ARB_SESSION_TYPE;
> + arb->protection_mode = PROTECTION_MODE_HM;
> + arb->index = ARB_SESSION_INDEX;
> + arb->is_in_play = false;
> +}
> +
> +static int intel_pxp_arb_reserve_session(struct intel_pxp *pxp) {
> + int ret;
> +
> + lockdep_assert_held(&pxp->ctx.mutex);
> +
> + arb_session_entry_init(pxp);
> + ret = wait_arb_hw_sw_state(pxp);
> +
> + return ret;
> +}
> +
> +/**
> + * intel_pxp_arb_mark_session_in_play - To put an reserved protected
> session to "in_play" state
> + * @pxp: pointer to pxp struct.
> + *
> + * Return: status. 0 means update is successful.
> + */
> +static int intel_pxp_arb_mark_session_in_play(struct intel_pxp *pxp)
> +{
> + struct pxp_protected_session *arb = &pxp->ctx.arb_session;
> +
> + lockdep_assert_held(&pxp->ctx.mutex);
> +
> + if (arb->is_in_play)
> + return -EINVAL;
> +
> + arb->is_in_play = true;
> + return 0;
> +}
> +
> +int intel_pxp_arb_create_session(struct intel_pxp *pxp) {
> + int ret;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> +
> + lockdep_assert_held(&pxp->ctx.mutex);
> +
> + if (pxp->ctx.flag_display_hm_surface_keys) {
> + drm_err(>->i915->drm, "%s: arb session is alive so
> skipping the creation\n",
> + __func__);
> + return 0;
> + }
> +
> + ret = intel_pxp_arb_reserve_session(pxp);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to reserve arb
> session\n");
> + return ret;
> + }
> +
> + ret = intel_pxp_tee_cmd_create_arb_session(pxp,
> ARB_SESSION_INDEX);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to send tee cmd for
> arb session creation\n");
> + return ret;
> + }
> +
> + ret = intel_pxp_arb_mark_session_in_play(pxp);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to mark arb session
> status in play\n");
> + return ret;
> + }
> +
> + pxp->ctx.flag_display_hm_surface_keys = true;
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> new file mode 100644
> index 000000000000..2196153dd879
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_ARB_H__
> +#define __INTEL_PXP_ARB_H__
> +
> +#include <linux/types.h>
> +
> +struct intel_pxp;
> +
> +int intel_pxp_arb_create_session(struct intel_pxp *pxp); bool
> +intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp);
> +
> +#endif /* __INTEL_PXP_ARB_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> index f51021c33d45..bf2feb4aaf6d 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -8,6 +8,7 @@
>
> #include <linux/mutex.h>
> #include "intel_pxp_types.h"
> +#include "intel_pxp_arb.h"
>
> void intel_pxp_ctx_init(struct pxp_context *ctx); void
> intel_pxp_ctx_fini(struct pxp_context *ctx); diff --git
> a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> index 5a1ffcc703e2..41d8a31bbb75 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -10,6 +10,32 @@
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
> #include "intel_pxp_tee.h"
> +#include "intel_pxp_arb.h"
> +
> +#define PXP_TEE_APIVER 0x40002
> +#define PXP_TEE_ARB_CMDID 0x1e
> +#define PXP_TEE_ARB_PROTECTION_MODE 0x2
> +
> +/* PXP TEE message header */
> +struct pxp_tee_cmd_header {
> + u32 api_version;
> + u32 command_id;
> + u32 status;
> + /* Length of the message (excluding the header) */
> + u32 buffer_len;
> +} __packed;
> +
> +/* PXP TEE message input to create a arbitrary session */ struct
> +pxp_tee_create_arb_in {
> + struct pxp_tee_cmd_header header;
> + u32 protection_mode;
> + u32 session_id;
> +} __packed;
> +
> +/* PXP TEE message output to create a arbitrary session */ struct
> +pxp_tee_create_arb_out {
> + struct pxp_tee_cmd_header header; } __packed;
>
> static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
> void *msg_in, u32 msg_in_size, @@
> -70,7 +96,9 @@ static int intel_pxp_tee_io_message(struct intel_pxp
> *pxp, static int i915_pxp_tee_component_bind(struct device
> *i915_kdev,
> struct device *tee_kdev, void
> *data)
> {
> + int ret = 0;
> struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> + struct intel_pxp *pxp = &i915->gt.pxp;
>
> if (!i915 || !tee_kdev || !data)
> return -EPERM;
> @@ -80,6 +108,19 @@ static int i915_pxp_tee_component_bind(struct
> device *i915_kdev,
> i915->pxp_tee_master->tee_dev = tee_kdev;
> mutex_unlock(&i915->pxp_tee_comp_mutex);
>
> + mutex_lock(&pxp->ctx.mutex);
> +
> + /* Create arb session only if tee is ready, during system
> boot or sleep/resume */
> + if (!intel_pxp_arb_session_is_in_play(pxp))
> + ret = intel_pxp_arb_create_session(pxp);
> +
> + mutex_unlock(&pxp->ctx.mutex);
> +
> + if (ret) {
> + drm_err(&i915->drm, "Failed to create arb session
> ret=[%d]\n", ret);
> + return ret;
> + }
> +
> return 0;
> }
>
> @@ -135,3 +176,35 @@ void intel_pxp_tee_component_fini(struct
> intel_pxp *pxp)
>
> component_del(i915->drm.dev, &i915_pxp_tee_component_ops); }
> +
> +int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
> + int arb_session_id) {
> + int ret;
> + u32 msg_out_size_received = 0;
> + struct pxp_tee_create_arb_in msg_in = {0};
> + struct pxp_tee_create_arb_out msg_out = {0};
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + struct drm_i915_private *i915 = gt->i915;
> +
> + msg_in.header.api_version = PXP_TEE_APIVER;
> + msg_in.header.command_id = PXP_TEE_ARB_CMDID;
> + msg_in.header.buffer_len = sizeof(msg_in) -
> sizeof(msg_in.header);
> + msg_in.protection_mode = PXP_TEE_ARB_PROTECTION_MODE;
> + msg_in.session_id = arb_session_id;
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> +
> + ret = intel_pxp_tee_io_message(pxp,
> + &msg_in,
> + sizeof(msg_in),
> + &msg_out,
> &msg_out_size_received,
> + sizeof(msg_out));
> +
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +
> + if (ret)
> + drm_err(&i915->drm, "Failed to send tee msg
> ret=[%d]\n", ret);
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> index 4b5e3edb1d9b..c46f9033f709 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> @@ -11,4 +11,7 @@
> void intel_pxp_tee_component_init(struct intel_pxp *pxp); void
> intel_pxp_tee_component_fini(struct intel_pxp *pxp);
>
> +int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
> + int arb_session_id);
> +
> #endif /* __INTEL_PXP_TEE_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> index f9b40ea98b1b..287ba1e0ed9d 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -8,12 +8,38 @@
>
> #include <linux/mutex.h>
>
> +/**
> + * struct pxp_protected_session - structure to track all active
> sessions.
> + */
> +struct pxp_protected_session {
> + /** @index: Numeric identifier for this protected session */
> + int index;
> + /** @type: Type of session */
> + int type;
> + /** @protection_mode: mode of protection requested */
> + int protection_mode;
> +
> + /**
> + * @is_in_play: indicates whether the session has been
> established
> + * in the HW root of trust if this flag is
> false, it
> + * indicates an application has reserved this
> session,
> + * but has not * established the session in the
> + * hardware yet.
> + */
> + bool is_in_play;
> +};
> +
> /* struct pxp_context - Represents combined view of driver and
> logical HW states. */ struct pxp_context {
> /** @mutex: mutex to protect the pxp context */
> struct mutex mutex;
>
> bool inited;
> +
> + struct pxp_protected_session arb_session;
> + u32 arb_session_pxp_tag;
> +
> + bool flag_display_hm_surface_keys;
> };
>
> struct intel_pxp {
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^ permalink raw reply [flat|nested] 55+ messages in thread
* [Intel-gfx] [RFC-v19 05/13] drm/i915/pxp: Func to send hardware session termination
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (3 preceding siblings ...)
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 04/13] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
@ 2021-01-06 23:12 ` Huang, Sean Z
2021-01-07 15:45 ` Vivi, Rodrigo
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
` (13 subsequent siblings)
18 siblings, 1 reply; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-06 23:12 UTC (permalink / raw)
To: Intel-gfx
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 13 ++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 158 +++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 4 +
5 files changed, 194 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index af9e87e4c63a..5599b92bea9b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -263,6 +263,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_arb.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 3868e8c697f9..2f63801748f8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -17,10 +17,23 @@
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ int i;
if (INTEL_GEN(gt->i915) < 12)
return;
+ /* Find the first VCS engine present */
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (HAS_ENGINE(gt, _VCS(i))) {
+ pxp->vcs_engine = gt->engine[_VCS(i)];
+ break;
+ }
+ }
+ if (!pxp->vcs_engine) {
+ drm_err(>->i915->drm, "Could not find a VCS engine\n");
+ return;
+ }
+
intel_pxp_ctx_init(&pxp->ctx);
intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index 000000000000..d9298cf5e1a7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_cmd.h"
+#include "i915_drv.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ u32 *cmd;
+
+ if (!ce || !ce->engine || !cmd_buf)
+ return ERR_PTR(-EINVAL);
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_err(>->i915->drm, "Failed to %s, invalid cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_err(>->i915->drm, "Failed to i915_gem_object_pin_map()\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
+ }
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_err(>->i915->drm, "Failed to i915_vma_instance()\n");
+ return batch;
+ }
+
+ return batch;
+}
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ bool is_engine_pm_get = false;
+ bool is_batch_vma_pin = false;
+ bool is_skip_req_on_err = false;
+ bool is_engine_get_pool = false;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ ce = pxp->vcs_engine->kernel_context;
+ if (!ce) {
+ drm_err(>->i915->drm, "VCS engine does not have context\n");
+ err = -EINVAL;
+ goto end;
+ }
+
+ if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
+ drm_err(>->i915->drm, "Failed to %s bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ intel_engine_pm_get(ce->engine);
+ is_engine_pm_get = true;
+
+ pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
+ if (IS_ERR(pool)) {
+ drm_err(>->i915->drm, "Failed to intel_engine_get_pool()\n");
+ err = PTR_ERR(pool);
+ goto end;
+ }
+ is_engine_get_pool = true;
+
+ batch = intel_pxp_cmd_get_batch(pxp, ce, pool, cmd, cmd_size_in_dw);
+ if (IS_ERR(batch)) {
+ drm_err(>->i915->drm, "Failed to intel_pxp_cmd_get_batch()\n");
+ err = PTR_ERR(batch);
+ goto end;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to i915_vma_pin()\n");
+ goto end;
+ }
+ is_batch_vma_pin = true;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ drm_err(>->i915->drm, "Failed to intel_context_create_request()\n");
+ err = PTR_ERR(rq);
+ goto end;
+ }
+ is_skip_req_on_err = true;
+
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to intel_engine_pool_mark_active()\n");
+ goto end;
+ }
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (!err)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to i915_request_await_object()\n");
+ goto end;
+ }
+
+ if (ce->engine->emit_init_breadcrumb) {
+ err = ce->engine->emit_init_breadcrumb(rq);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to emit_init_breadcrumb()\n");
+ goto end;
+ }
+ }
+
+ err = ce->engine->emit_bb_start(rq, batch->node.start,
+ batch->node.size, 0);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to emit_bb_start()\n");
+ goto end;
+ }
+
+ i915_request_add(rq);
+
+end:
+ if (unlikely(err) && is_skip_req_on_err)
+ i915_request_set_error_once(rq, err);
+
+ if (is_batch_vma_pin)
+ i915_vma_unpin(batch);
+
+ if (is_engine_get_pool)
+ intel_gt_buffer_pool_put(pool);
+
+ if (is_engine_pm_get)
+ intel_engine_pm_put(ce->engine);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
new file mode 100644
index 000000000000..d04463962421
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_CMD_H__
+#define __INTEL_PXP_CMD_H__
+
+#include "gt/intel_gt_buffer_pool.h"
+#include "intel_pxp.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw);
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw);
+#endif /* __INTEL_PXP_SM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index 287ba1e0ed9d..f3d9335aee5f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -8,6 +8,8 @@
#include <linux/mutex.h>
+struct intel_engine_cs;
+
/**
* struct pxp_protected_session - structure to track all active sessions.
*/
@@ -44,6 +46,8 @@ struct pxp_context {
struct intel_pxp {
struct pxp_context ctx;
+
+ struct intel_engine_cs *vcs_engine;
};
#endif /* __INTEL_PXP_TYPES_H__ */
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 05/13] drm/i915/pxp: Func to send hardware session termination
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 05/13] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
@ 2021-01-07 15:45 ` Vivi, Rodrigo
2021-01-12 18:53 ` Huang, Sean Z
0 siblings, 1 reply; 55+ messages in thread
From: Vivi, Rodrigo @ 2021-01-07 15:45 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> Implement the functions to allow PXP to send a GPU command, in
> order to terminate the hardware session, so hardware can recycle
> this session slot for the next usage.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 13 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 158
> +++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 4 +
> 5 files changed, 194 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile
> index af9e87e4c63a..5599b92bea9b 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -263,6 +263,7 @@ i915-y += i915_perf.o
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> pxp/intel_pxp_arb.o \
> + pxp/intel_pxp_cmd.o \
> pxp/intel_pxp_context.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 3868e8c697f9..2f63801748f8 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -17,10 +17,23 @@
> void intel_pxp_init(struct intel_pxp *pxp)
> {
> struct intel_gt *gt = container_of(pxp, struct intel_gt,
> pxp);
> + int i;
>
> if (INTEL_GEN(gt->i915) < 12)
> return;
>
> + /* Find the first VCS engine present */
> + for (i = 0; i < I915_MAX_VCS; i++) {
> + if (HAS_ENGINE(gt, _VCS(i))) {
> + pxp->vcs_engine = gt->engine[_VCS(i)];
> + break;
> + }
> + }
> + if (!pxp->vcs_engine) {
> + drm_err(>->i915->drm, "Could not find a VCS
> engine\n");
> + return;
> + }
> +
> intel_pxp_ctx_init(&pxp->ctx);
>
> intel_uncore_write(gt->uncore, KCR_INIT,
> KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> new file mode 100644
> index 000000000000..d9298cf5e1a7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> @@ -0,0 +1,158 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp_cmd.h"
> +#include "i915_drv.h"
> +#include "gt/intel_context.h"
> +#include "gt/intel_engine_pm.h"
> +
> +struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
> + struct intel_context *ce,
> + struct
> intel_gt_buffer_pool_node *pool,
> + u32 *cmd_buf, int
> cmd_size_in_dw)
> +{
> + struct i915_vma *batch = ERR_PTR(-EINVAL);
> + struct intel_gt *gt = container_of(pxp, struct intel_gt,
> pxp);
> + u32 *cmd;
> +
> + if (!ce || !ce->engine || !cmd_buf)
> + return ERR_PTR(-EINVAL);
> +
> + if (cmd_size_in_dw * 4 > PAGE_SIZE) {
> + drm_err(>->i915->drm, "Failed to %s, invalid
> cmd_size_id_dw=[%d]\n",
> + __func__, cmd_size_in_dw);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
> + if (IS_ERR(cmd)) {
> + drm_err(>->i915->drm, "Failed to
> i915_gem_object_pin_map()\n");
> + return ERR_PTR(-EINVAL);
> + }
> +
> + memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
> +
> + if (drm_debug_enabled(DRM_UT_DRIVER)) {
> + print_hex_dump(KERN_DEBUG, "cmd binaries:",
> + DUMP_PREFIX_OFFSET, 4, 4, cmd,
> cmd_size_in_dw * 4, true);
> + }
> +
> + i915_gem_object_unpin_map(pool->obj);
> +
> + batch = i915_vma_instance(pool->obj, ce->vm, NULL);
> + if (IS_ERR(batch)) {
> + drm_err(>->i915->drm, "Failed to
> i915_vma_instance()\n");
> + return batch;
> + }
> +
> + return batch;
> +}
> +
> +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int
> cmd_size_in_dw)
> +{
> + int err = -EINVAL;
> + struct i915_vma *batch;
> + struct i915_request *rq;
> + struct intel_context *ce = NULL;
> + bool is_engine_pm_get = false;
> + bool is_batch_vma_pin = false;
> + bool is_skip_req_on_err = false;
> + bool is_engine_get_pool = false;
I remember that I asked myself in some internal version to this to be
converted to gotos and I remember seeing the change. I'm not sure why
this also came back to the very original code.
Then Chris and Joonas also requested changes on older versions of this
patch. Not only limited to this. Please address all old requests.
> + struct intel_gt_buffer_pool_node *pool = NULL;
> + struct intel_gt *gt = container_of(pxp, struct intel_gt,
> pxp);
> +
> + ce = pxp->vcs_engine->kernel_context;
> + if (!ce) {
> + drm_err(>->i915->drm, "VCS engine does not have
> context\n");
> + err = -EINVAL;
> + goto end;
> + }
> +
> + if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
> + drm_err(>->i915->drm, "Failed to %s bad params\n",
> __func__);
> + return -EINVAL;
> + }
> +
> + intel_engine_pm_get(ce->engine);
> + is_engine_pm_get = true;
> +
> + pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
> + if (IS_ERR(pool)) {
> + drm_err(>->i915->drm, "Failed to
> intel_engine_get_pool()\n");
> + err = PTR_ERR(pool);
> + goto end;
> + }
> + is_engine_get_pool = true;
> +
> + batch = intel_pxp_cmd_get_batch(pxp, ce, pool, cmd,
> cmd_size_in_dw);
> + if (IS_ERR(batch)) {
> + drm_err(>->i915->drm, "Failed to
> intel_pxp_cmd_get_batch()\n");
> + err = PTR_ERR(batch);
> + goto end;
> + }
> +
> + err = i915_vma_pin(batch, 0, 0, PIN_USER);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to
> i915_vma_pin()\n");
> + goto end;
> + }
> + is_batch_vma_pin = true;
> +
> + rq = intel_context_create_request(ce);
> + if (IS_ERR(rq)) {
> + drm_err(>->i915->drm, "Failed to
> intel_context_create_request()\n");
> + err = PTR_ERR(rq);
> + goto end;
> + }
> + is_skip_req_on_err = true;
> +
> + err = intel_gt_buffer_pool_mark_active(pool, rq);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to
> intel_engine_pool_mark_active()\n");
> + goto end;
> + }
> +
> + i915_vma_lock(batch);
> + err = i915_request_await_object(rq, batch->obj, false);
> + if (!err)
> + err = i915_vma_move_to_active(batch, rq, 0);
> + i915_vma_unlock(batch);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to
> i915_request_await_object()\n");
> + goto end;
> + }
> +
> + if (ce->engine->emit_init_breadcrumb) {
> + err = ce->engine->emit_init_breadcrumb(rq);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to
> emit_init_breadcrumb()\n");
> + goto end;
> + }
> + }
> +
> + err = ce->engine->emit_bb_start(rq, batch->node.start,
> + batch->node.size, 0);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to
> emit_bb_start()\n");
> + goto end;
> + }
> +
> + i915_request_add(rq);
> +
> +end:
> + if (unlikely(err) && is_skip_req_on_err)
> + i915_request_set_error_once(rq, err);
> +
> + if (is_batch_vma_pin)
> + i915_vma_unpin(batch);
> +
> + if (is_engine_get_pool)
> + intel_gt_buffer_pool_put(pool);
> +
> + if (is_engine_pm_get)
> + intel_engine_pm_put(ce->engine);
> +
> + return err;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> new file mode 100644
> index 000000000000..d04463962421
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CMD_H__
> +#define __INTEL_PXP_CMD_H__
> +
> +#include "gt/intel_gt_buffer_pool.h"
> +#include "intel_pxp.h"
> +
> +struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
> + struct intel_context *ce,
> + struct
> intel_gt_buffer_pool_node *pool,
> + u32 *cmd_buf, int
> cmd_size_in_dw);
> +
> +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int
> cmd_size_in_dw);
> +#endif /* __INTEL_PXP_SM_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> index 287ba1e0ed9d..f3d9335aee5f 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -8,6 +8,8 @@
>
> #include <linux/mutex.h>
>
> +struct intel_engine_cs;
> +
> /**
> * struct pxp_protected_session - structure to track all active
> sessions.
> */
> @@ -44,6 +46,8 @@ struct pxp_context {
>
> struct intel_pxp {
> struct pxp_context ctx;
> +
> + struct intel_engine_cs *vcs_engine;
> };
>
> #endif /* __INTEL_PXP_TYPES_H__ */
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 05/13] drm/i915/pxp: Func to send hardware session termination
2021-01-07 15:45 ` Vivi, Rodrigo
@ 2021-01-12 18:53 ` Huang, Sean Z
0 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-12 18:53 UTC (permalink / raw)
To: Vivi, Rodrigo, Intel-gfx
Hi Rodrigo,
I made the modification as below according to Chris and your suggestion, will reflect at rev20. All my comments (// sean: ...) the won't be checked in.
This change can address part of the comment Chris provided. But please let me go through the remaining comments at rev19 first.
Best regards,
Sean
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
index d9298cf5e1a7..6898b8826302 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -34,11 +34,7 @@ struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
- if (drm_debug_enabled(DRM_UT_DRIVER)) { // sean: my original intension just to print out the hex command for debug. But let me remove this.
- print_hex_dump(KERN_DEBUG, "cmd binaries:",
- DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
- }
-
+ i915_gem_object_flush_map(pool->obj); // sean: we should flush map before unpin, thanks Chris's suggestion.
i915_gem_object_unpin_map(pool->obj);
batch = i915_vma_instance(pool->obj, ce->vm, NULL);
@@ -56,103 +52,73 @@ int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
struct i915_vma *batch;
struct i915_request *rq;
struct intel_context *ce = NULL;
- bool is_engine_pm_get = false; // sean: replace bool with goto label.
- bool is_batch_vma_pin = false;
- bool is_skip_req_on_err = false;
- bool is_engine_get_pool = false;
struct intel_gt_buffer_pool_node *pool = NULL;
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ int size = cmd_size_in_dw * 4;
ce = pxp->vcs_engine->kernel_context;
- if (!ce) {
- drm_err(>->i915->drm, "VCS engine does not have context\n");
- err = -EINVAL;
- goto end;
- }
+ if (!ce)
+ return -EINVAL;
- if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
- drm_err(>->i915->drm, "Failed to %s bad params\n", __func__);
+ if (!cmd || cmd_size_in_dw == 0)
return -EINVAL;
- }
intel_engine_pm_get(ce->engine);
- is_engine_pm_get = true;
- pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
+ size = round_up(size, PAGE_SIZE); // sean: I think this would be better to handle the allocation size.
+ pool = intel_gt_get_buffer_pool(gt, size);
if (IS_ERR(pool)) {
- drm_err(>->i915->drm, "Failed to intel_engine_get_pool()\n");
err = PTR_ERR(pool);
- goto end;
+ goto out_engine_pm_put;
}
- is_engine_get_pool = true;
batch = intel_pxp_cmd_get_batch(pxp, ce, pool, cmd, cmd_size_in_dw);
if (IS_ERR(batch)) {
- drm_err(>->i915->drm, "Failed to intel_pxp_cmd_get_batch()\n");
err = PTR_ERR(batch);
- goto end;
+ goto out_engine_pool_put;
}
err = i915_vma_pin(batch, 0, 0, PIN_USER);
- if (err) {
- drm_err(>->i915->drm, "Failed to i915_vma_pin()\n");
- goto end;
- }
- is_batch_vma_pin = true;
+ if (err)
+ goto out_engine_pool_put;
rq = intel_context_create_request(ce);
if (IS_ERR(rq)) {
- drm_err(>->i915->drm, "Failed to intel_context_create_request()\n");
err = PTR_ERR(rq);
- goto end;
+ goto out_vma_unpin;
}
- is_skip_req_on_err = true;
err = intel_gt_buffer_pool_mark_active(pool, rq);
- if (err) {
- drm_err(>->i915->drm, "Failed to intel_engine_pool_mark_active()\n");
- goto end;
- }
+ if (err)
+ goto out_vma_unpin;
i915_vma_lock(batch);
err = i915_request_await_object(rq, batch->obj, false);
if (!err)
err = i915_vma_move_to_active(batch, rq, 0);
i915_vma_unlock(batch);
- if (err) {
- drm_err(>->i915->drm, "Failed to i915_request_await_object()\n");
- goto end;
- }
+ if (err)
+ goto out_vma_unpin;
if (ce->engine->emit_init_breadcrumb) {
err = ce->engine->emit_init_breadcrumb(rq);
- if (err) {
- drm_err(>->i915->drm, "Failed to emit_init_breadcrumb()\n");
- goto end;
- }
+ if (err)
+ goto out_vma_unpin;
}
err = ce->engine->emit_bb_start(rq, batch->node.start,
- batch->node.size, 0);
- if (err) {
- drm_err(>->i915->drm, "Failed to emit_bb_start()\n");
- goto end;
- }
+ batch->node.size, 0);
+ if (err)
+ goto out_vma_unpin;
i915_request_add(rq);
-end:
- if (unlikely(err) && is_skip_req_on_err) // sean: I think we should not skip if there are further errors, thanks Chris pointed out this.
- i915_request_set_error_once(rq, err);
-
- if (is_batch_vma_pin)
- i915_vma_unpin(batch);
-
- if (is_engine_get_pool)
- intel_gt_buffer_pool_put(pool);
-
- if (is_engine_pm_get)
- intel_engine_pm_put(ce->engine);
+out_vma_unpin:
+ i915_vma_unpin(batch);
+out_engine_pool_put:
+ intel_gt_buffer_pool_put(pool);
+out_engine_pm_put:
+ intel_engine_pm_put(ce->engine);
return err;
}
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [Intel-gfx] [RFC-v19 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (4 preceding siblings ...)
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 05/13] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
@ 2021-01-06 23:12 ` Huang, Sean Z
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 07/13] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
` (12 subsequent siblings)
18 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-06 23:12 UTC (permalink / raw)
To: Intel-gfx
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 101 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 24 ++++-
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 -
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++
7 files changed, 139 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 9830342aa6f4..b92072554ab3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -14,6 +14,7 @@
#include "intel_lrc_reg.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -107,6 +108,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>->pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0023c023f472..1e8dfe435ca8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7944,6 +7944,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE 1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
@@ -7966,7 +7967,7 @@ enum {
#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
-#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
+#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
#define ENGINE1_MASK REG_GENMASK(31, 16)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 2f63801748f8..fa15e3ad2f92 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -14,6 +14,70 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT))
+static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>->irq_lock);
+
+ intel_uncore_write(gt->uncore, GEN11_CRYPTO_INTR_MASK, mask << 16);
+}
+
+static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
+{
+ int ret;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ pxp->ctx.global_state_attacked = true;
+
+ mutex_unlock(&pxp->ctx.mutex);
+
+ return ret;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ if (pxp->ctx.global_state_attacked) {
+ pxp->ctx.global_state_attacked = false;
+
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_arb_create_session(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to create arb session\n");
+ goto end;
+ }
+ }
+end:
+ mutex_unlock(&pxp->ctx.mutex);
+ return ret;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work);
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ u32 events = 0;
+
+ spin_lock_irq(>->irq_lock);
+ events = fetch_and_zero(&pxp->current_events);
+ spin_unlock_irq(>->irq_lock);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(pxp);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(pxp);
+
+ spin_lock_irq(>->irq_lock);
+ intel_pxp_write_irq_mask_reg(gt, 0);
+ spin_unlock_irq(>->irq_lock);
+}
+
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -40,6 +104,12 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_tee_component_init(pxp);
+ INIT_WORK(&pxp->irq_work, intel_pxp_irq_work);
+
+ pxp->handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
+ PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
+ PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
}
@@ -54,3 +124,34 @@ void intel_pxp_fini(struct intel_pxp *pxp)
intel_pxp_ctx_fini(&pxp->ctx);
}
+
+/**
+ * intel_pxp_irq_handler - Proxies KCR interrupts to PXP.
+ * @pxp: pointer to pxp struct
+ * @iir: GT interrupt vector associated with the interrupt
+ *
+ * Dispatches each vector element into an IRQ to PXP.
+ */
+void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
+{
+ struct drm_i915_private *i915;
+ const u32 events = iir & pxp->handled_irr;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (!gt || !gt->i915 || INTEL_GEN(i915) < 12)
+ return;
+
+ i915 = gt->i915;
+
+ lockdep_assert_held(>->irq_lock);
+
+ if (unlikely(!events)) {
+ drm_err(&i915->drm, "%s returned due to iir=[0x%04x]\n", __func__, iir);
+ return;
+ }
+
+ intel_pxp_write_irq_mask_reg(gt, pxp->handled_irr);
+
+ pxp->current_events |= events;
+ schedule_work(&pxp->irq_work);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 8fc91e900b16..cdaa6ce6fdca 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -6,8 +6,13 @@
#ifndef __INTEL_PXP_H__
#define __INTEL_PXP_H__
+#include <linux/workqueue.h>
#include "intel_pxp_types.h"
+#define PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED BIT(1)
+#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
+#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+
enum pxp_session_types {
SESSION_TYPE_TYPE0 = 0,
SESSION_TYPE_TYPE1 = 1,
@@ -25,14 +30,31 @@ enum pxp_protection_modes {
};
#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
+int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
+int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp);
+
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
#else
-static inline void intel_pxp_init(struct intel_pxp *pxp)
+static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
+{
+}
+
+static inline int i915_pxp_teardown_required_callback(struct intel_pxp *pxp)
+{
+ return 0;
+}
+
+static inline int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
{
return 0;
}
+static inline void intel_pxp_init(struct intel_pxp *pxp)
+{
+}
+
static inline void intel_pxp_fini(struct intel_pxp *pxp)
{
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
index 2be6bf2f0d0f..4e820258b7ae 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -11,7 +11,10 @@
*/
void intel_pxp_ctx_init(struct pxp_context *ctx)
{
+ ctx->global_state_attacked = false;
+
mutex_init(&ctx->mutex);
+
ctx->inited = true;
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
index bf2feb4aaf6d..f51021c33d45 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -8,7 +8,6 @@
#include <linux/mutex.h>
#include "intel_pxp_types.h"
-#include "intel_pxp_arb.h"
void intel_pxp_ctx_init(struct pxp_context *ctx);
void intel_pxp_ctx_fini(struct pxp_context *ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index f3d9335aee5f..0b140aaeb6ed 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -7,6 +7,7 @@
#define __INTEL_PXP_TYPES_H__
#include <linux/mutex.h>
+#include <linux/workqueue.h>
struct intel_engine_cs;
@@ -42,9 +43,14 @@ struct pxp_context {
u32 arb_session_pxp_tag;
bool flag_display_hm_surface_keys;
+ bool global_state_attacked;
};
struct intel_pxp {
+ struct work_struct irq_work;
+ u32 handled_irr;
+ u32 current_events;
+
struct pxp_context ctx;
struct intel_engine_cs *vcs_engine;
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v19 07/13] drm/i915/pxp: Destroy arb session upon teardown
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (5 preceding siblings ...)
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
@ 2021-01-06 23:12 ` Huang, Sean Z
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 08/13] drm/i915/pxp: Enable PXP power management Huang, Sean Z
` (11 subsequent siblings)
18 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-06 23:12 UTC (permalink / raw)
To: Intel-gfx
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 76 +++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 130 ++++++++++++++++++++++-
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 12 ++-
5 files changed, 212 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index fa15e3ad2f92..23d4cfc1fb1f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -28,6 +28,9 @@ static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
mutex_lock(&pxp->ctx.mutex);
pxp->ctx.global_state_attacked = true;
+ pxp->ctx.flag_display_hm_surface_keys = false;
+
+ ret = intel_pxp_arb_terminate_session(pxp);
mutex_unlock(&pxp->ctx.mutex);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
index 640d7103c04d..1d2ec8ffd7ad 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -10,6 +10,7 @@
#include "intel_pxp_arb.h"
#include "intel_pxp.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_cmd.h"
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
@@ -129,3 +130,78 @@ int intel_pxp_arb_create_session(struct intel_pxp *pxp)
return ret;
}
+
+static int intel_pxp_arb_session_with_global_termination(struct intel_pxp *pxp)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ /* Calculate how many bytes need to be alloc */
+ cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL, ARB_SESSION_TYPE, ARB_SESSION_INDEX);
+ cmd_size_in_dw += intel_pxp_cmd_add_inline_termination(NULL);
+ cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr, ARB_SESSION_TYPE, ARB_SESSION_INDEX);
+ cmd_ptr += intel_pxp_cmd_add_inline_termination(cmd_ptr);
+ cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr);
+
+ if (cmd_size_in_dw != (cmd_ptr - cmd)) {
+ ret = -EINVAL;
+ drm_err(>->i915->drm, "Failed to %s\n", __func__);
+ goto end;
+ }
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
+ }
+
+ ret = intel_pxp_cmd_submit(pxp, cmd, cmd_size_in_dw);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to intel_pxp_cmd_submit()\n");
+ goto end;
+ }
+
+end:
+ kfree(cmd);
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_terminate_session - Terminate the arb hw session and its entries.
+ * @pxp: pointer to pxp struct.
+ *
+ * This function is NOT intended to be called from the ioctl, and need to be protected by
+ * ctx.mutex to ensure no SIP change during the call.
+ *
+ * Return: status. 0 means terminate is successful.
+ */
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ struct pxp_protected_session *arb = &pxp->ctx.arb_session;
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ /* terminate the hw sessions */
+ ret = intel_pxp_arb_session_with_global_termination(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to intel_pxp_arb_session_with_global_termination\n");
+ return ret;
+ }
+
+ arb->is_in_play = false;
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
index 2196153dd879..42261ef33a03 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
@@ -11,6 +11,7 @@
struct intel_pxp;
int intel_pxp_arb_create_session(struct intel_pxp *pxp);
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp);
bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp);
#endif /* __INTEL_PXP_ARB_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
index d9298cf5e1a7..ae338ab2e629 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -5,13 +5,33 @@
#include "intel_pxp_cmd.h"
#include "i915_drv.h"
+#include "gt/intel_gpu_commands.h"
#include "gt/intel_context.h"
#include "gt/intel_engine_pm.h"
-struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
- struct intel_context *ce,
- struct intel_gt_buffer_pool_node *pool,
- u32 *cmd_buf, int cmd_size_in_dw)
+/* PXP GPU command definitions */
+
+/* MI_SET_APPID */
+#define MI_SET_APPID_TYPE1_APP BIT(7)
+#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
+
+/* MI_FLUSH_DW */
+#define MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE BIT(22)
+
+/* MI_WAIT */
+#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG BIT(9)
+#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG BIT(8)
+
+/* CRYPTO_KEY_EXCHANGE */
+#define CRYPTO_KEY_EXCHANGE ((0x3 << 29) | (0x01609 << 16))
+
+#define PXP_MAX_TYPE0_SESSIONS 16
+#define PXP_MAX_TYPE1_SESSIONS 6
+
+static struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
{
struct i915_vma *batch = ERR_PTR(-EINVAL);
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -50,7 +70,8 @@ struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
return batch;
}
-int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd,
+ int cmd_size_in_dw)
{
int err = -EINVAL;
struct i915_vma *batch;
@@ -156,3 +177,102 @@ int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
return err;
}
+
+int intel_pxp_cmd_add_prolog(struct intel_pxp *pxp, u32 *cmd,
+ int session_type,
+ int session_index)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_prolog = cmd;
+ const int cmd_prolog_size_in_dw = 10;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (!cmd)
+ return cmd_prolog_size_in_dw;
+
+ /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_FLUSH_DW - pxp off */
+ *cmd_prolog++ = MI_FLUSH_DW; /* DW0 */
+ *cmd_prolog++ = 0; /* DW1 */
+ *cmd_prolog++ = 0; /* DW2 */
+
+ /* MI_SET_APPID */
+ if (session_type == SESSION_TYPE_TYPE1) {
+ if (session_index >= PXP_MAX_TYPE1_SESSIONS) {
+ drm_err(>->i915->drm, "Failed to %s invalid session_index\n", __func__);
+ goto end;
+ }
+
+ *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_TYPE1_APP |
+ MI_SET_APPID_SESSION_ID(session_index));
+ } else {
+ if (session_index >= PXP_MAX_TYPE0_SESSIONS) {
+ drm_err(>->i915->drm, "Failed to %s invalid session_index\n", __func__);
+ goto end;
+ }
+
+ *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_SESSION_ID(session_index));
+ }
+
+ /* MFX_WAIT */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_FLUSH_DW - pxp on */
+ *cmd_prolog++ = (MI_FLUSH_DW | MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE); /* DW0 */
+ *cmd_prolog++ = 0; /* DW1 */
+ *cmd_prolog++ = 0; /* DW2 */
+
+ /* MFX_WAIT */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ increased_size_in_dw = (cmd_prolog - cmd);
+end:
+ return increased_size_in_dw;
+}
+
+int intel_pxp_cmd_add_epilog(u32 *cmd)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_epilog = cmd;
+ const int cmd_epilog_size_in_dw = 5;
+
+ if (!cmd)
+ return cmd_epilog_size_in_dw;
+
+ /* MI_FLUSH_DW - pxp off */
+ *cmd_epilog++ = MI_FLUSH_DW; /* DW0 */
+ *cmd_epilog++ = 0; /* DW1 */
+ *cmd_epilog++ = 0; /* DW2 */
+
+ /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
+ *cmd_epilog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_BATCH_BUFFER_END */
+ *cmd_epilog++ = MI_BATCH_BUFFER_END;
+
+ increased_size_in_dw = (cmd_epilog - cmd);
+ return increased_size_in_dw;
+}
+
+int intel_pxp_cmd_add_inline_termination(u32 *cmd)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_termin = cmd;
+ const int cmd_termin_size_in_dw = 2;
+
+ if (!cmd)
+ return cmd_termin_size_in_dw;
+
+ /* CRYPTO_KEY_EXCHANGE - session inline termination */
+ *cmd_termin++ = CRYPTO_KEY_EXCHANGE; /* DW0 */
+ *cmd_termin++ = 0; /* DW1 */
+
+ increased_size_in_dw = (cmd_termin - cmd);
+ return increased_size_in_dw;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
index d04463962421..087f260034c4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
@@ -9,10 +9,12 @@
#include "gt/intel_gt_buffer_pool.h"
#include "intel_pxp.h"
-struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
- struct intel_context *ce,
- struct intel_gt_buffer_pool_node *pool,
- u32 *cmd_buf, int cmd_size_in_dw);
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd,
+ int cmd_size_in_dw);
+int intel_pxp_cmd_add_prolog(struct intel_pxp *pxp, u32 *cmd,
+ int session_type,
+ int session_index);
+int intel_pxp_cmd_add_epilog(u32 *cmd);
+int intel_pxp_cmd_add_inline_termination(u32 *cmd);
-int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v19 08/13] drm/i915/pxp: Enable PXP power management
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (6 preceding siblings ...)
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 07/13] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
@ 2021-01-06 23:12 ` Huang, Sean Z
2021-01-07 15:52 ` Vivi, Rodrigo
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 09/13] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
` (10 subsequent siblings)
18 siblings, 1 reply; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-06 23:12 UTC (permalink / raw)
To: Intel-gfx
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++
drivers/gpu/drm/i915/i915_drv.c | 4 ++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 ++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 +++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 +
6 files changed, 106 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5599b92bea9b..7592fc8cbd89 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -265,6 +265,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_arb.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index c94e8ac884eb..ae0387e419a2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -20,6 +20,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -266,6 +267,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>->uc);
+ intel_pxp_pm_resume(>->pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -300,6 +303,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_pm_prepare_suspend(>->pxp);
intel_uc_suspend(>->uc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 207d50226e64..5923db004d9b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1338,6 +1340,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(&dev_priv->gt.pxp);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index 000000000000..ebe89262485c
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp_context.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+ if (!pxp->ctx.inited)
+ return;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ /* Disable PXP-IOCTLs */
+ pxp->ctx.global_state_in_suspend = true;
+
+ mutex_unlock(&pxp->ctx.mutex);
+}
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+ if (!pxp->ctx.inited)
+ return;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ if (pxp->ctx.global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ pxp->ctx.global_state_attacked = false;
+
+ pxp->ctx.flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(&pxp->ctx.mutex);
+}
+
+int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (!pxp->ctx.inited)
+ return 0;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (pxp->ctx.global_state_in_suspend) {
+ ret = intel_pxp_arb_terminate_session(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to terminate the arb session\n");
+ goto end;
+ }
+
+ pxp->ctx.global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(&pxp->ctx.mutex);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
new file mode 100644
index 000000000000..135bfb59aaf7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_PM_H__
+#define __INTEL_PXP_PM_H__
+
+#include "i915_drv.h"
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp);
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp);
+int intel_pxp_pm_resume(struct intel_pxp *pxp);
+#else
+static inline void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+}
+
+static inline void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+}
+
+static inline int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ return 0;
+}
+#endif
+
+#endif /* __INTEL_PXP_PM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index 0b140aaeb6ed..13d7b502b7f9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -44,6 +44,7 @@ struct pxp_context {
bool flag_display_hm_surface_keys;
bool global_state_attacked;
+ bool global_state_in_suspend;
};
struct intel_pxp {
--
2.17.1
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^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 08/13] drm/i915/pxp: Enable PXP power management
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 08/13] drm/i915/pxp: Enable PXP power management Huang, Sean Z
@ 2021-01-07 15:52 ` Vivi, Rodrigo
2021-01-12 19:14 ` Huang, Sean Z
0 siblings, 1 reply; 55+ messages in thread
From: Vivi, Rodrigo @ 2021-01-07 15:52 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> During the power event S3+ sleep/resume, hardware will lose all the
> encryption keys for every hardware session, even though the
> software session state was marked as alive after resume. So to
> handle such case, PXP should terminate all the hardware sessions
> and cleanup all the software states after the power cycle.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++
> drivers/gpu/drm/i915/i915_drv.c | 4 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65
> ++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 +++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 +
> 6 files changed, 106 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile
> index 5599b92bea9b..7592fc8cbd89 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -265,6 +265,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp_arb.o \
> pxp/intel_pxp_cmd.o \
> pxp/intel_pxp_context.o \
> + pxp/intel_pxp_pm.o \
> pxp/intel_pxp_tee.o
>
> # Post-mortem debug and GPU hang state capture
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index c94e8ac884eb..ae0387e419a2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -20,6 +20,7 @@
> #include "intel_rc6.h"
> #include "intel_rps.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp_pm.h"
>
> static void user_forcewake(struct intel_gt *gt, bool suspend)
> {
> @@ -266,6 +267,8 @@ int intel_gt_resume(struct intel_gt *gt)
>
> intel_uc_resume(>->uc);
>
> + intel_pxp_pm_resume(>->pxp);
> +
> user_forcewake(gt, false);
>
> out_fw:
> @@ -300,6 +303,7 @@ void intel_gt_suspend_prepare(struct intel_gt
> *gt)
> user_forcewake(gt, true);
> wait_for_suspend(gt);
>
> + intel_pxp_pm_prepare_suspend(>->pxp);
> intel_uc_suspend(>->uc);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 207d50226e64..5923db004d9b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -68,6 +68,8 @@
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_rc6.h"
>
> +#include "pxp/intel_pxp_pm.h"
> +
> #include "i915_debugfs.h"
> #include "i915_drv.h"
> #include "i915_ioc32.h"
> @@ -1338,6 +1340,8 @@ static int i915_drm_resume_early(struct
> drm_device *dev)
>
> intel_power_domains_resume(dev_priv);
>
> + intel_pxp_pm_resume_early(&dev_priv->gt.pxp);
> +
> enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>
> return ret;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> new file mode 100644
> index 000000000000..ebe89262485c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include "intel_pxp_context.h"
> +#include "intel_pxp_arb.h"
> +#include "intel_pxp_pm.h"
> +
> +void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
> +{
> + if (!pxp->ctx.inited)
> + return;
> +
> + mutex_lock(&pxp->ctx.mutex);
> +
> + /* Disable PXP-IOCTLs */
> + pxp->ctx.global_state_in_suspend = true;
> +
> + mutex_unlock(&pxp->ctx.mutex);
> +}
> +
> +void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
> +{
> + if (!pxp->ctx.inited)
> + return;
> +
> + mutex_lock(&pxp->ctx.mutex);
> +
> + if (pxp->ctx.global_state_in_suspend) {
> + /* reset the attacked flag even there was a pending
> */
> + pxp->ctx.global_state_attacked = false;
> +
> + pxp->ctx.flag_display_hm_surface_keys = false;
> + }
> +
> + mutex_unlock(&pxp->ctx.mutex);
> +}
> +
> +int intel_pxp_pm_resume(struct intel_pxp *pxp)
> +{
> + int ret = 0;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> +
> + if (!pxp->ctx.inited)
> + return 0;
> +
> + mutex_lock(&pxp->ctx.mutex);
> +
> + /* Re-enable PXP-IOCTLs */
> + if (pxp->ctx.global_state_in_suspend) {
> + ret = intel_pxp_arb_terminate_session(pxp);
I'm confused. I was expecting we terminate the session at suspend and
re-stablish at resume. But I'm missing or forgetting something
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to terminate
> the arb session\n");
> + goto end;
> + }
> +
> + pxp->ctx.global_state_in_suspend = false;
> + }
> +
> +end:
> + mutex_unlock(&pxp->ctx.mutex);
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> new file mode 100644
> index 000000000000..135bfb59aaf7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_PM_H__
> +#define __INTEL_PXP_PM_H__
> +
> +#include "i915_drv.h"
> +
> +#ifdef CONFIG_DRM_I915_PXP
> +void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp);
> +
> +void intel_pxp_pm_resume_early(struct intel_pxp *pxp);
> +int intel_pxp_pm_resume(struct intel_pxp *pxp);
> +#else
> +static inline void intel_pxp_pm_prepare_suspend(struct intel_pxp
> *pxp)
> +{
> +}
> +
> +static inline void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
> +{
> +}
> +
> +static inline int intel_pxp_pm_resume(struct intel_pxp *pxp)
> +{
> + return 0;
> +}
> +#endif
> +
> +#endif /* __INTEL_PXP_PM_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> index 0b140aaeb6ed..13d7b502b7f9 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -44,6 +44,7 @@ struct pxp_context {
>
> bool flag_display_hm_surface_keys;
> bool global_state_attacked;
> + bool global_state_in_suspend;
> };
>
> struct intel_pxp {
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^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 08/13] drm/i915/pxp: Enable PXP power management
2021-01-07 15:52 ` Vivi, Rodrigo
@ 2021-01-12 19:14 ` Huang, Sean Z
0 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-12 19:14 UTC (permalink / raw)
To: Vivi, Rodrigo, Intel-gfx
Hi Rodrigo,
According to our design we terminate the session after resume, and then re-create the session at i915_pxp_tee_component_bind() in intel_pxp_tee.c
We only can terminate the session after resume, instead of during the intel_pxp_pm_prepare_suspend() call, because there is a change that display is stilling rendering/playing-back the protected buffer, and protected surfaces turn corruption garbage if we terminate the session during the suspend().
Best regards,
Sean
-----Original Message-----
From: Vivi, Rodrigo <rodrigo.vivi@intel.com>
Sent: Thursday, January 7, 2021 9:53 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v19 08/13] drm/i915/pxp: Enable PXP power management
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> During the power event S3+ sleep/resume, hardware will lose all the
> encryption keys for every hardware session, even though the software
> session state was marked as alive after resume. So to handle such
> case, PXP should terminate all the hardware sessions and cleanup all
> the software states after the power cycle.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++
> drivers/gpu/drm/i915/i915_drv.c | 4 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65
> ++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 +++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 +
> 6 files changed, 106 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile index 5599b92bea9b..7592fc8cbd89
> 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -265,6 +265,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp_arb.o \
> pxp/intel_pxp_cmd.o \
> pxp/intel_pxp_context.o \
> + pxp/intel_pxp_pm.o \
> pxp/intel_pxp_tee.o
>
> # Post-mortem debug and GPU hang state capture diff --git
> a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index c94e8ac884eb..ae0387e419a2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -20,6 +20,7 @@
> #include "intel_rc6.h"
> #include "intel_rps.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp_pm.h"
>
> static void user_forcewake(struct intel_gt *gt, bool suspend) { @@
> -266,6 +267,8 @@ int intel_gt_resume(struct intel_gt *gt)
>
> intel_uc_resume(>->uc);
>
> + intel_pxp_pm_resume(>->pxp);
> +
> user_forcewake(gt, false);
>
> out_fw:
> @@ -300,6 +303,7 @@ void intel_gt_suspend_prepare(struct intel_gt
> *gt)
> user_forcewake(gt, true);
> wait_for_suspend(gt);
>
> + intel_pxp_pm_prepare_suspend(>->pxp);
> intel_uc_suspend(>->uc);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c index 207d50226e64..5923db004d9b
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -68,6 +68,8 @@
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_rc6.h"
>
> +#include "pxp/intel_pxp_pm.h"
> +
> #include "i915_debugfs.h"
> #include "i915_drv.h"
> #include "i915_ioc32.h"
> @@ -1338,6 +1340,8 @@ static int i915_drm_resume_early(struct
> drm_device *dev)
>
> intel_power_domains_resume(dev_priv);
>
> + intel_pxp_pm_resume_early(&dev_priv->gt.pxp);
> +
> enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>
> return ret;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> new file mode 100644
> index 000000000000..ebe89262485c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include "intel_pxp_context.h"
> +#include "intel_pxp_arb.h"
> +#include "intel_pxp_pm.h"
> +
> +void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp) {
> + if (!pxp->ctx.inited)
> + return;
> +
> + mutex_lock(&pxp->ctx.mutex);
> +
> + /* Disable PXP-IOCTLs */
> + pxp->ctx.global_state_in_suspend = true;
> +
> + mutex_unlock(&pxp->ctx.mutex); }
> +
> +void intel_pxp_pm_resume_early(struct intel_pxp *pxp) {
> + if (!pxp->ctx.inited)
> + return;
> +
> + mutex_lock(&pxp->ctx.mutex);
> +
> + if (pxp->ctx.global_state_in_suspend) {
> + /* reset the attacked flag even there was a pending
> */
> + pxp->ctx.global_state_attacked = false;
> +
> + pxp->ctx.flag_display_hm_surface_keys = false;
> + }
> +
> + mutex_unlock(&pxp->ctx.mutex); }
> +
> +int intel_pxp_pm_resume(struct intel_pxp *pxp) {
> + int ret = 0;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> +
> + if (!pxp->ctx.inited)
> + return 0;
> +
> + mutex_lock(&pxp->ctx.mutex);
> +
> + /* Re-enable PXP-IOCTLs */
> + if (pxp->ctx.global_state_in_suspend) {
> + ret = intel_pxp_arb_terminate_session(pxp);
I'm confused. I was expecting we terminate the session at suspend and re-stablish at resume. But I'm missing or forgetting something
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to terminate
> the arb session\n");
> + goto end;
> + }
> +
> + pxp->ctx.global_state_in_suspend = false;
> + }
> +
> +end:
> + mutex_unlock(&pxp->ctx.mutex);
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> new file mode 100644
> index 000000000000..135bfb59aaf7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_PM_H__
> +#define __INTEL_PXP_PM_H__
> +
> +#include "i915_drv.h"
> +
> +#ifdef CONFIG_DRM_I915_PXP
> +void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp);
> +
> +void intel_pxp_pm_resume_early(struct intel_pxp *pxp); int
> +intel_pxp_pm_resume(struct intel_pxp *pxp); #else static inline void
> +intel_pxp_pm_prepare_suspend(struct intel_pxp
> *pxp)
> +{
> +}
> +
> +static inline void intel_pxp_pm_resume_early(struct intel_pxp *pxp) {
> +}
> +
> +static inline int intel_pxp_pm_resume(struct intel_pxp *pxp) {
> + return 0;
> +}
> +#endif
> +
> +#endif /* __INTEL_PXP_PM_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> index 0b140aaeb6ed..13d7b502b7f9 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -44,6 +44,7 @@ struct pxp_context {
>
> bool flag_display_hm_surface_keys;
> bool global_state_attacked;
> + bool global_state_in_suspend;
> };
>
> struct intel_pxp {
_______________________________________________
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^ permalink raw reply [flat|nested] 55+ messages in thread
* [Intel-gfx] [RFC-v19 09/13] drm/i915/pxp: Expose session state for display protection flip
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (7 preceding siblings ...)
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 08/13] drm/i915/pxp: Enable PXP power management Huang, Sean Z
@ 2021-01-06 23:12 ` Huang, Sean Z
2021-01-07 15:54 ` Vivi, Rodrigo
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 10/13] mei: pxp: export pavp client to me client bus Huang, Sean Z
` (9 subsequent siblings)
18 siblings, 1 reply; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-06 23:12 UTC (permalink / raw)
To: Intel-gfx
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive. And Implement the funciton to set
the protected flag for gem context.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 21 +++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 18 ++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 23d4cfc1fb1f..a28a459532c2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -158,3 +158,24 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
pxp->current_events |= events;
schedule_work(&pxp->irq_work);
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ if (i915->gt.pxp.ctx.inited &&
+ i915->gt.pxp.ctx.flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
+
+int intel_pxp_gem_context_set_protected(struct drm_i915_private *i915,
+ unsigned long *user_flags,
+ u32 protected_bit)
+{
+ if (!user_flags || !protected_bit ||
+ !intel_pxp_arb_session_is_in_play(&i915->gt.pxp))
+ return -EINVAL;
+
+ set_bit(protected_bit, user_flags);
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index cdaa6ce6fdca..ff1c1c0e720c 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -29,6 +29,8 @@ enum pxp_protection_modes {
PROTECTION_MODE_ALL
};
+struct drm_i915_private;
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
@@ -36,6 +38,10 @@ int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp);
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
+int intel_pxp_gem_context_set_protected(struct drm_i915_private *i915,
+ unsigned long *user_flag,
+ u32 protected_bit);
#else
static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
{
@@ -58,6 +64,18 @@ static inline void intel_pxp_init(struct intel_pxp *pxp)
static inline void intel_pxp_fini(struct intel_pxp *pxp)
{
}
+
+static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ return false;
+}
+
+static inline int intel_pxp_gem_context_set_protected(struct drm_i915_private *i915,
+ unsigned long *user_flag,
+ u32 protected_bit)
+{
+ return 0;
+}
#endif
#endif /* __INTEL_PXP_H__ */
--
2.17.1
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^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 09/13] drm/i915/pxp: Expose session state for display protection flip
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 09/13] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
@ 2021-01-07 15:54 ` Vivi, Rodrigo
2021-01-18 8:23 ` Huang, Sean Z
0 siblings, 1 reply; 55+ messages in thread
From: Vivi, Rodrigo @ 2021-01-07 15:54 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> Implement the intel_pxp_gem_object_status() to allow i915 display
> querying the current PXP session state. In the design, display
> should not perform protection flip on the protected buffers if
> there is no PXP session alive. And Implement the funciton to set
> the protected flag for gem context.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 21 +++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 18 ++++++++++++++++++
> 2 files changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 23d4cfc1fb1f..a28a459532c2 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -158,3 +158,24 @@ void intel_pxp_irq_handler(struct intel_pxp
> *pxp, u16 iir)
> pxp->current_events |= events;
> schedule_work(&pxp->irq_work);
> }
> +
> +bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
> +{
> + if (i915->gt.pxp.ctx.inited &&
> + i915->gt.pxp.ctx.flag_display_hm_surface_keys)
> + return true;
> + else
> + return false;
> +}
> +
> +int intel_pxp_gem_context_set_protected(struct drm_i915_private
> *i915,
> + unsigned long *user_flags,
> + u32 protected_bit)
> +{
> + if (!user_flags || !protected_bit ||
> + !intel_pxp_arb_session_is_in_play(&i915->gt.pxp))
> + return -EINVAL;
> +
> + set_bit(protected_bit, user_flags);
This protected_bit should only be set during context creation and never
modified with set_context.
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index cdaa6ce6fdca..ff1c1c0e720c 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -29,6 +29,8 @@ enum pxp_protection_modes {
> PROTECTION_MODE_ALL
> };
>
> +struct drm_i915_private;
> +
> #ifdef CONFIG_DRM_I915_PXP
> void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
> int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
> @@ -36,6 +38,10 @@ int
> i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp);
>
> void intel_pxp_init(struct intel_pxp *pxp);
> void intel_pxp_fini(struct intel_pxp *pxp);
> +bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
> +int intel_pxp_gem_context_set_protected(struct drm_i915_private
> *i915,
> + unsigned long *user_flag,
> + u32 protected_bit);
> #else
> static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16
> iir)
> {
> @@ -58,6 +64,18 @@ static inline void intel_pxp_init(struct intel_pxp
> *pxp)
> static inline void intel_pxp_fini(struct intel_pxp *pxp)
> {
> }
> +
> +static inline bool intel_pxp_gem_object_status(struct
> drm_i915_private *i915)
> +{
> + return false;
> +}
> +
> +static inline int intel_pxp_gem_context_set_protected(struct
> drm_i915_private *i915,
> + unsigned long
> *user_flag,
> + u32
> protected_bit)
> +{
> + return 0;
> +}
> #endif
>
> #endif /* __INTEL_PXP_H__ */
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 09/13] drm/i915/pxp: Expose session state for display protection flip
2021-01-07 15:54 ` Vivi, Rodrigo
@ 2021-01-18 8:23 ` Huang, Sean Z
0 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-18 8:23 UTC (permalink / raw)
To: Vivi, Rodrigo, Intel-gfx
Hi Rodrigo,
Quoted from your feedback: "This protected_bit should only be set during context creation and never modified with set_context."
I have modified the code accordingly at rev21 https://patchwork.freedesktop.org/series/84620/#rev21
Best regards,
Sean
-----Original Message-----
From: Vivi, Rodrigo <rodrigo.vivi@intel.com>
Sent: Thursday, January 7, 2021 7:55 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v19 09/13] drm/i915/pxp: Expose session state for display protection flip
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> Implement the intel_pxp_gem_object_status() to allow i915 display
> querying the current PXP session state. In the design, display should
> not perform protection flip on the protected buffers if there is no
> PXP session alive. And Implement the funciton to set the protected
> flag for gem context.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 21 +++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 18 ++++++++++++++++++
> 2 files changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 23d4cfc1fb1f..a28a459532c2 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -158,3 +158,24 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp,
> u16 iir)
> pxp->current_events |= events;
> schedule_work(&pxp->irq_work); }
> +
> +bool intel_pxp_gem_object_status(struct drm_i915_private *i915) {
> + if (i915->gt.pxp.ctx.inited &&
> + i915->gt.pxp.ctx.flag_display_hm_surface_keys)
> + return true;
> + else
> + return false;
> +}
> +
> +int intel_pxp_gem_context_set_protected(struct drm_i915_private
> *i915,
> + unsigned long *user_flags,
> + u32 protected_bit) {
> + if (!user_flags || !protected_bit ||
> + !intel_pxp_arb_session_is_in_play(&i915->gt.pxp))
> + return -EINVAL;
> +
> + set_bit(protected_bit, user_flags);
This protected_bit should only be set during context creation and never modified with set_context.
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index cdaa6ce6fdca..ff1c1c0e720c 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -29,6 +29,8 @@ enum pxp_protection_modes {
> PROTECTION_MODE_ALL
> };
>
> +struct drm_i915_private;
> +
> #ifdef CONFIG_DRM_I915_PXP
> void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir); int
> i915_pxp_teardown_required_callback(struct intel_pxp *pxp); @@ -36,6
> +38,10 @@ int i915_pxp_global_terminate_complete_callback(struct
> intel_pxp *pxp);
>
> void intel_pxp_init(struct intel_pxp *pxp); void
> intel_pxp_fini(struct intel_pxp *pxp);
> +bool intel_pxp_gem_object_status(struct drm_i915_private *i915); int
> +intel_pxp_gem_context_set_protected(struct drm_i915_private
> *i915,
> + unsigned long *user_flag,
> + u32 protected_bit);
> #else
> static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16
> iir)
> {
> @@ -58,6 +64,18 @@ static inline void intel_pxp_init(struct intel_pxp
> *pxp)
> static inline void intel_pxp_fini(struct intel_pxp *pxp) { }
> +
> +static inline bool intel_pxp_gem_object_status(struct
> drm_i915_private *i915)
> +{
> + return false;
> +}
> +
> +static inline int intel_pxp_gem_context_set_protected(struct
> drm_i915_private *i915,
> + unsigned long
> *user_flag,
> + u32
> protected_bit)
> +{
> + return 0;
> +}
> #endif
>
> #endif /* __INTEL_PXP_H__ */
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 55+ messages in thread
* [Intel-gfx] [RFC-v19 10/13] mei: pxp: export pavp client to me client bus
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (8 preceding siblings ...)
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 09/13] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
@ 2021-01-06 23:12 ` Huang, Sean Z
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
` (8 subsequent siblings)
18 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-06 23:12 UTC (permalink / raw)
To: Intel-gfx; +Cc: Vitaly Lubart
From: Vitaly Lubart <vitaly.lubart@intel.com>
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +++++++++++++++++++++++++++++++++
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index 000000000000..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index 000000000000..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index 000000000000..5bd61fe445e3
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/uuid.h>
+#include <linux/mei_cl_bus.h>
+#include <linux/component.h>
+#include <drm/drm_connector.h>
+#include <drm/i915_component.h>
+#include <drm/i915_pxp_tee_interface.h>
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .receive = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = &mei_pxp_ops;
+ comp_master->tee_dev = dev;
+ ret = component_bind_all(dev, comp_master);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static void mei_component_master_unbind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+
+ dev_dbg(dev, "%s\n", __func__);
+ component_unbind_all(dev, comp_master);
+}
+
+static const struct component_master_ops mei_component_master_ops = {
+ .bind = mei_component_master_bind,
+ .unbind = mei_component_master_unbind,
+};
+
+/**
+ * mei_pxp_component_match - compare function for matching mei pxp.
+ *
+ * The function checks if the driver is i915, the subcomponent is PXP
+ * and the grand parent of pxp and the parent of i915 are the same
+ * PCH device.
+ *
+ * @dev: master device
+ * @subcomponent: subcomponent to match (I915_COMPONENT_PXP)
+ * @data: compare data (mei pxp device)
+ *
+ * Return:
+ * * 1 - if components match
+ * * 0 - otherwise
+ */
+static int mei_pxp_component_match(struct device *dev, int subcomponent,
+ void *data)
+{
+ struct device *base = data;
+
+ if (subcomponent != I915_COMPONENT_PXP)
+ return 0;
+
+ if (strcmp(dev->driver->name, "i915") == 0) {
+ base = base->parent;
+ if (!base)
+ return 0;
+
+ base = base->parent;
+ dev = dev->parent;
+ return (base && dev && dev == base);
+ }
+
+ return 0;
+}
+
+static int mei_pxp_probe(struct mei_cl_device *cldev,
+ const struct mei_cl_device_id *id)
+{
+ struct i915_pxp_comp_master *comp_master;
+ struct component_match *master_match;
+ int ret;
+
+ ret = mei_cldev_enable(cldev);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret);
+ goto enable_err_exit;
+ }
+
+ comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL);
+ if (!comp_master) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ master_match = NULL;
+ component_match_add_typed(&cldev->dev, &master_match,
+ mei_pxp_component_match, &cldev->dev);
+ if (IS_ERR_OR_NULL(master_match)) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ mei_cldev_set_drvdata(cldev, comp_master);
+ ret = component_master_add_with_match(&cldev->dev,
+ &mei_component_master_ops,
+ master_match);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "Master comp add failed %d\n", ret);
+ goto err_exit;
+ }
+
+ return 0;
+
+err_exit:
+ mei_cldev_set_drvdata(cldev, NULL);
+ kfree(comp_master);
+ mei_cldev_disable(cldev);
+enable_err_exit:
+ return ret;
+}
+
+static int mei_pxp_remove(struct mei_cl_device *cldev)
+{
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+
+ component_master_del(&cldev->dev, &mei_component_master_ops);
+ kfree(comp_master);
+ mei_cldev_set_drvdata(cldev, NULL);
+
+ return mei_cldev_disable(cldev);
+}
+
+/* fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 : PAVP GUID*/
+#define MEI_GUID_PXP GUID_INIT(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \
+ 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1)
+
+static struct mei_cl_device_id mei_pxp_tbl[] = {
+ { .uuid = MEI_GUID_PXP, .version = MEI_CL_VERSION_ANY },
+ { }
+};
+MODULE_DEVICE_TABLE(mei, mei_pxp_tbl);
+
+static struct mei_cl_driver mei_pxp_driver = {
+ .id_table = mei_pxp_tbl,
+ .name = KBUILD_MODNAME,
+ .probe = mei_pxp_probe,
+ .remove = mei_pxp_remove,
+};
+
+module_mei_cl_driver(mei_pxp_driver);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MEI PXP");
diff --git a/drivers/misc/mei/pxp/mei_pxp.h b/drivers/misc/mei/pxp/mei_pxp.h
new file mode 100644
index 000000000000..e7b15373fefd
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef __MEI_PXP_H__
+#define __MEI_PXP_H__
+
+/* me_pxp_status: Enumeration of all PXP Status Codes */
+enum me_pxp_status {
+ ME_PXP_STATUS_SUCCESS = 0x0000,
+
+};
+
+#endif /* __MEI_PXP_H__ */
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v19 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (9 preceding siblings ...)
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 10/13] mei: pxp: export pavp client to me client bus Huang, Sean Z
@ 2021-01-06 23:12 ` Huang, Sean Z
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 12/13] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
` (7 subsequent siblings)
18 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-06 23:12 UTC (permalink / raw)
To: Intel-gfx; +Cc: Joonas, Bommu Krishnaiah, Matthew
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com
Cc: Matthew Auld matthew.auld@intel.com
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 42 ++++++++++++++++++++++++++++-
include/uapi/drm/i915_drm.h | 47 +++++++++++++++++++++++++++++++++
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5923db004d9b..ca526923d9b3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1727,7 +1727,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 17a4636ee542..c53b13c02e59 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -53,6 +53,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "i915_user_extensions.h"
#include "intel_pm.h"
@@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
&args->size, &args->handle);
}
+struct create_ext {
+ struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext *ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(&ext.param, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ &ext_data);
+ if (ret)
+ return ret;
+
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 1987e2ea79a3..f9a1d26824b6 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -729,6 +730,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+ * Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ */
+ __u64 size;
+ /**
+ * Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ __u32 pad;
+#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
+#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
+ (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
+ __u64 extensions;
+
+};
+
struct drm_i915_gem_pread {
/** Handle for the object being read. */
__u32 handle;
@@ -1699,6 +1721,31 @@ struct drm_i915_gem_context_param {
__u64 value;
};
+struct drm_i915_gem_object_param {
+ /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
+ __u32 handle;
+
+ /* Data pointer size */
+ __u32 size;
+
+/*
+ * I915_OBJECT_PARAM:
+ *
+ * Select object namespace for the param.
+ */
+#define I915_OBJECT_PARAM (1ull<<32)
+
+ __u64 param;
+
+ /* Data value or pointer */
+ __u64 data;
+};
+
+struct drm_i915_gem_create_ext_setparam {
+ struct i915_user_extension base;
+ struct drm_i915_gem_object_param param;
+};
+
/**
* Context SSEU programming
*
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v19 12/13] drm/i915/pxp: User interface for Protected buffer
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (10 preceding siblings ...)
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
@ 2021-01-06 23:12 ` Huang, Sean Z
2021-01-07 15:58 ` Vivi, Rodrigo
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 13/13] drm/i915/pxp: Add plane decryption support Huang, Sean Z
` (6 subsequent siblings)
18 siblings, 1 reply; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-06 23:12 UTC (permalink / raw)
To: Intel-gfx; +Cc: Bommu Krishnaiah, Huang Sean Z, Kondapally Kalyan
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
Cc: Huang Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 19 +++++++++++++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 5 ++++
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5 ++++
drivers/gpu/drm/i915/i915_gem.c | 23 +++++++++++++++----
include/uapi/drm/i915_drm.h | 19 +++++++++++++++
6 files changed, 66 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 68f58762d5e3..00d7ca3071e7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -81,6 +81,8 @@
#include "i915_trace.h"
#include "i915_user_extensions.h"
+#include "pxp/intel_pxp.h"
+
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
static struct i915_global_gem_context {
@@ -2022,12 +2024,25 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ if (args->size)
+ ret = -EINVAL;
+ else if (args->value)
+ ret = intel_pxp_gem_context_set_protected(ctx->i915,
+ &ctx->user_flags,
+ UCONTEXT_PROTECTED);
+ break;
+
case I915_CONTEXT_PARAM_PRIORITY:
ret = set_priority(ctx, args);
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index b5c908f3f4f2..173154fdc311 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,11 @@ static inline void i915_gem_context_set_recoverable(struct i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
}
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context *ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 1449f54924e0..0917c9431c65 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -134,7 +134,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
-
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+ * @user_flags: small set of booleans set by the user
+ */
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c53b13c02e59..611a0b5ab51f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,7 +184,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
mem_type),
- &args->size, &args->handle);
+ &args->size, &args->handle, 0);
}
struct create_ext {
- struct drm_i915_private *i915;
+ struct drm_i915_private *i915;
+ unsigned long user_flags;
};
static int __create_setparam(struct drm_i915_gem_object_param *args,
@@ -273,6 +277,17 @@ static int __create_setparam(struct drm_i915_gem_object_param *args,
return -EINVAL;
}
+ switch (lower_32_bits(args->param)) {
+ case I915_PARAM_PROTECTED_CONTENT:
+ if (args->size) {
+ return -EINVAL;
+ } else if (args->data) {
+ ext_data->user_flags = args->data;
+ return 0;
+ }
+ break;
+ }
+
return -EINVAL;
}
@@ -318,7 +333,7 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
- &args->size, &args->handle);
+ &args->size, &args->handle, ext_data.user_flags);
}
static int
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index f9a1d26824b6..6822f11814fa 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1716,6 +1716,15 @@ struct drm_i915_gem_context_param {
* Default is 16 KiB.
*/
#define I915_CONTEXT_PARAM_RINGSIZE 0xc
+
+/*
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true (1) PAVP content protection is enabled.
+ * When enabled, the context is marked unrecoverable and may
+ * become invalid due to PAVP teardown event or other error.
+ */
+#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
/* Must be kept compact -- no holes and well documented */
__u64 value;
@@ -1735,6 +1744,16 @@ struct drm_i915_gem_object_param {
*/
#define I915_OBJECT_PARAM (1ull<<32)
+/*
+ * I915_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true (1) buffer contents is expected to be protected by
+ * PAVP encryption and requires decryption for scan out and processing.
+ * Protected buffers can only be used in PAVP protected contexts.
+ * A protected buffer may become invalid as a result of PAVP teardown.
+ */
+#define I915_PARAM_PROTECTED_CONTENT 0x1
+
__u64 param;
/* Data value or pointer */
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 12/13] drm/i915/pxp: User interface for Protected buffer
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 12/13] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
@ 2021-01-07 15:58 ` Vivi, Rodrigo
2021-01-18 8:29 ` Huang, Sean Z
0 siblings, 1 reply; 55+ messages in thread
From: Vivi, Rodrigo @ 2021-01-07 15:58 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx; +Cc: Kondapally, Kalyan, Bommu, Krishnaiah
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>
> This api allow user mode to create Protected buffer and context
> creation.
>
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
> Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
> Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
> Cc: Huang Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 19 +++++++++++++--
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 5 ++++
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 ++++
> drivers/gpu/drm/i915/i915_gem.c | 23 +++++++++++++++--
> --
> include/uapi/drm/i915_drm.h | 19 +++++++++++++++
> 6 files changed, 66 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 68f58762d5e3..00d7ca3071e7 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -81,6 +81,8 @@
> #include "i915_trace.h"
> #include "i915_user_extensions.h"
>
> +#include "pxp/intel_pxp.h"
> +
> #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
>
> static struct i915_global_gem_context {
> @@ -2022,12 +2024,25 @@ static int ctx_setparam(struct
> drm_i915_file_private *fpriv,
> case I915_CONTEXT_PARAM_RECOVERABLE:
> if (args->size)
> ret = -EINVAL;
> - else if (args->value)
> - i915_gem_context_set_recoverable(ctx);
> + else if (args->value) {
> + if (!i915_gem_context_is_protected(ctx))
> + i915_gem_context_set_recoverable(ctx)
> ;
> + else
> + ret = -EPERM;
> + }
> else
> i915_gem_context_clear_recoverable(ctx);
> break;
>
> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
remember that we also need to require recoverable flag to false. It
cannot be implicit.
> + if (args->size)
> + ret = -EINVAL;
> + else if (args->value)
> + ret =
> intel_pxp_gem_context_set_protected(ctx->i915,
> +
> &ctx->user_flags,
> +
> UCONTEXT_PROTECTED);
> + break;
> +
> case I915_CONTEXT_PARAM_PRIORITY:
> ret = set_priority(ctx, args);
> break;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index b5c908f3f4f2..173154fdc311 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -70,6 +70,11 @@ static inline void
> i915_gem_context_set_recoverable(struct i915_gem_context *ctx
> set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
> }
>
> +static inline bool i915_gem_context_is_protected(struct
> i915_gem_context *ctx)
> +{
> + return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> +}
> +
> static inline void i915_gem_context_clear_recoverable(struct
> i915_gem_context *ctx)
> {
> clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index 1449f54924e0..0917c9431c65 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -134,7 +134,7 @@ struct i915_gem_context {
> #define UCONTEXT_BANNABLE 2
> #define UCONTEXT_RECOVERABLE 3
> #define UCONTEXT_PERSISTENCE 4
> -
> +#define UCONTEXT_PROTECTED 5
> /**
> * @flags: small set of booleans
> */
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index e2d9b7e1e152..90ac955463f4 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -161,6 +161,11 @@ struct drm_i915_gem_object {
> } mmo;
>
> I915_SELFTEST_DECLARE(struct list_head st_link);
> + /**
> + * @user_flags: small set of booleans set by the user
> + */
> + unsigned long user_flags;
> +#define I915_BO_PROTECTED BIT(0)
>
> unsigned long flags;
> #define I915_BO_ALLOC_CONTIGUOUS BIT(0)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c
> b/drivers/gpu/drm/i915/i915_gem.c
> index c53b13c02e59..611a0b5ab51f 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -184,7 +184,8 @@ static int
> i915_gem_create(struct drm_file *file,
> struct intel_memory_region *mr,
> u64 *size_p,
> - u32 *handle_p)
> + u32 *handle_p,
> + u64 user_flags)
> {
> struct drm_i915_gem_object *obj;
> u32 handle;
> @@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
> if (IS_ERR(obj))
> return PTR_ERR(obj);
>
> + obj->user_flags = user_flags;
> +
> ret = drm_gem_handle_create(file, &obj->base, &handle);
> /* drop reference from allocate - handle holds it now */
> i915_gem_object_put(obj);
> @@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
> return i915_gem_create(file,
>
> intel_memory_region_by_type(to_i915(dev),
> mem_type),
> - &args->size, &args->handle);
> + &args->size, &args->handle, 0);
> }
>
> struct create_ext {
> - struct drm_i915_private *i915;
> + struct drm_i915_private *i915;
> + unsigned long user_flags;
> };
>
> static int __create_setparam(struct drm_i915_gem_object_param *args,
> @@ -273,6 +277,17 @@ static int __create_setparam(struct
> drm_i915_gem_object_param *args,
> return -EINVAL;
> }
>
> + switch (lower_32_bits(args->param)) {
> + case I915_PARAM_PROTECTED_CONTENT:
> + if (args->size) {
> + return -EINVAL;
> + } else if (args->data) {
> + ext_data->user_flags = args->data;
> + return 0;
> + }
> + break;
> + }
> +
> return -EINVAL;
> }
>
> @@ -318,7 +333,7 @@ i915_gem_create_ioctl(struct drm_device *dev,
> void *data,
> return i915_gem_create(file,
> intel_memory_region_by_type(i915,
>
> INTEL_MEMORY_SYSTEM),
> - &args->size, &args->handle);
> + &args->size, &args->handle,
> ext_data.user_flags);
> }
>
> static int
> diff --git a/include/uapi/drm/i915_drm.h
> b/include/uapi/drm/i915_drm.h
> index f9a1d26824b6..6822f11814fa 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1716,6 +1716,15 @@ struct drm_i915_gem_context_param {
> * Default is 16 KiB.
> */
> #define I915_CONTEXT_PARAM_RINGSIZE 0xc
> +
> +/*
> + * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + *
> + * If set to true (1) PAVP content protection is enabled.
> + * When enabled, the context is marked unrecoverable and may
> + * become invalid due to PAVP teardown event or other error.
> + */
> +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
> /* Must be kept compact -- no holes and well documented */
>
> __u64 value;
> @@ -1735,6 +1744,16 @@ struct drm_i915_gem_object_param {
> */
> #define I915_OBJECT_PARAM (1ull<<32)
>
> +/*
> + * I915_PARAM_PROTECTED_CONTENT:
> + *
> + * If set to true (1) buffer contents is expected to be protected by
> + * PAVP encryption and requires decryption for scan out and
> processing.
> + * Protected buffers can only be used in PAVP protected contexts.
> + * A protected buffer may become invalid as a result of PAVP
> teardown.
> + */
> +#define I915_PARAM_PROTECTED_CONTENT 0x1
> +
> __u64 param;
>
> /* Data value or pointer */
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 12/13] drm/i915/pxp: User interface for Protected buffer
2021-01-07 15:58 ` Vivi, Rodrigo
@ 2021-01-18 8:29 ` Huang, Sean Z
0 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-18 8:29 UTC (permalink / raw)
To: Vivi, Rodrigo, Intel-gfx; +Cc: Kondapally, Kalyan, Bommu, Krishnaiah
Hi Rodrigo,
Quoted: " remember that we also need to require recoverable flag to false. It cannot be implicit."
Yes, I have prepared the patch to check the false of recoverable flag in KMD, but haven't merged it into the patch series yet.
Because I would like UMD making the change first accordingly, to prevent breaking the integration test.
Best regards,
Sean
-----Original Message-----
From: Vivi, Rodrigo <rodrigo.vivi@intel.com>
Sent: Thursday, January 7, 2021 7:58 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Cc: Kondapally, Kalyan <kalyan.kondapally@intel.com>; Bommu, Krishnaiah <krishnaiah.bommu@intel.com>
Subject: Re: [Intel-gfx] [RFC-v19 12/13] drm/i915/pxp: User interface for Protected buffer
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>
> This api allow user mode to create Protected buffer and context
> creation.
>
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
> Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
> Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
> Cc: Huang Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 19 +++++++++++++--
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 5 ++++
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 ++++
> drivers/gpu/drm/i915/i915_gem.c | 23 +++++++++++++++--
> --
> include/uapi/drm/i915_drm.h | 19 +++++++++++++++
> 6 files changed, 66 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 68f58762d5e3..00d7ca3071e7 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -81,6 +81,8 @@
> #include "i915_trace.h"
> #include "i915_user_extensions.h"
>
> +#include "pxp/intel_pxp.h"
> +
> #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
>
> static struct i915_global_gem_context { @@ -2022,12 +2024,25 @@
> static int ctx_setparam(struct drm_i915_file_private *fpriv,
> case I915_CONTEXT_PARAM_RECOVERABLE:
> if (args->size)
> ret = -EINVAL;
> - else if (args->value)
> - i915_gem_context_set_recoverable(ctx);
> + else if (args->value) {
> + if (!i915_gem_context_is_protected(ctx))
> + i915_gem_context_set_recoverable(ctx)
> ;
> + else
> + ret = -EPERM;
> + }
> else
> i915_gem_context_clear_recoverable(ctx);
> break;
>
> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
remember that we also need to require recoverable flag to false. It cannot be implicit.
> + if (args->size)
> + ret = -EINVAL;
> + else if (args->value)
> + ret =
> intel_pxp_gem_context_set_protected(ctx->i915,
> +
> &ctx->user_flags,
> +
> UCONTEXT_PROTECTED);
> + break;
> +
> case I915_CONTEXT_PARAM_PRIORITY:
> ret = set_priority(ctx, args);
> break;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index b5c908f3f4f2..173154fdc311 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -70,6 +70,11 @@ static inline void
> i915_gem_context_set_recoverable(struct i915_gem_context *ctx
> set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags); }
>
> +static inline bool i915_gem_context_is_protected(struct
> i915_gem_context *ctx)
> +{
> + return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags); }
> +
> static inline void i915_gem_context_clear_recoverable(struct
> i915_gem_context *ctx)
> {
> clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags); diff --git
> a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index 1449f54924e0..0917c9431c65 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -134,7 +134,7 @@ struct i915_gem_context {
> #define UCONTEXT_BANNABLE 2
> #define UCONTEXT_RECOVERABLE 3
> #define UCONTEXT_PERSISTENCE 4
> -
> +#define UCONTEXT_PROTECTED 5
> /**
> * @flags: small set of booleans
> */
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index e2d9b7e1e152..90ac955463f4 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -161,6 +161,11 @@ struct drm_i915_gem_object {
> } mmo;
>
> I915_SELFTEST_DECLARE(struct list_head st_link);
> + /**
> + * @user_flags: small set of booleans set by the user
> + */
> + unsigned long user_flags;
> +#define I915_BO_PROTECTED BIT(0)
>
> unsigned long flags;
> #define I915_BO_ALLOC_CONTIGUOUS BIT(0) diff --git
> a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index c53b13c02e59..611a0b5ab51f 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -184,7 +184,8 @@ static int
> i915_gem_create(struct drm_file *file,
> struct intel_memory_region *mr,
> u64 *size_p,
> - u32 *handle_p)
> + u32 *handle_p,
> + u64 user_flags)
> {
> struct drm_i915_gem_object *obj;
> u32 handle;
> @@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
> if (IS_ERR(obj))
> return PTR_ERR(obj);
>
> + obj->user_flags = user_flags;
> +
> ret = drm_gem_handle_create(file, &obj->base, &handle);
> /* drop reference from allocate - handle holds it now */
> i915_gem_object_put(obj);
> @@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
> return i915_gem_create(file,
>
> intel_memory_region_by_type(to_i915(dev),
> mem_type),
> - &args->size, &args->handle);
> + &args->size, &args->handle, 0);
> }
>
> struct create_ext {
> - struct drm_i915_private *i915;
> + struct drm_i915_private *i915;
> + unsigned long user_flags;
> };
>
> static int __create_setparam(struct drm_i915_gem_object_param *args,
> @@ -273,6 +277,17 @@ static int __create_setparam(struct
> drm_i915_gem_object_param *args,
> return -EINVAL;
> }
>
> + switch (lower_32_bits(args->param)) {
> + case I915_PARAM_PROTECTED_CONTENT:
> + if (args->size) {
> + return -EINVAL;
> + } else if (args->data) {
> + ext_data->user_flags = args->data;
> + return 0;
> + }
> + break;
> + }
> +
> return -EINVAL;
> }
>
> @@ -318,7 +333,7 @@ i915_gem_create_ioctl(struct drm_device *dev, void
> *data,
> return i915_gem_create(file,
> intel_memory_region_by_type(i915,
>
> INTEL_MEMORY_SYSTEM),
> - &args->size, &args->handle);
> + &args->size, &args->handle,
> ext_data.user_flags);
> }
>
> static int
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index f9a1d26824b6..6822f11814fa 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1716,6 +1716,15 @@ struct drm_i915_gem_context_param {
> * Default is 16 KiB.
> */
> #define I915_CONTEXT_PARAM_RINGSIZE 0xc
> +
> +/*
> + * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + *
> + * If set to true (1) PAVP content protection is enabled.
> + * When enabled, the context is marked unrecoverable and may
> + * become invalid due to PAVP teardown event or other error.
> + */
> +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
> /* Must be kept compact -- no holes and well documented */
>
> __u64 value;
> @@ -1735,6 +1744,16 @@ struct drm_i915_gem_object_param {
> */
> #define I915_OBJECT_PARAM (1ull<<32)
>
> +/*
> + * I915_PARAM_PROTECTED_CONTENT:
> + *
> + * If set to true (1) buffer contents is expected to be protected by
> + * PAVP encryption and requires decryption for scan out and
> processing.
> + * Protected buffers can only be used in PAVP protected contexts.
> + * A protected buffer may become invalid as a result of PAVP
> teardown.
> + */
> +#define I915_PARAM_PROTECTED_CONTENT 0x1
> +
> __u64 param;
>
> /* Data value or pointer */
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 55+ messages in thread
* [Intel-gfx] [RFC-v19 13/13] drm/i915/pxp: Add plane decryption support
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (11 preceding siblings ...)
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 12/13] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
@ 2021-01-06 23:12 ` Huang, Sean Z
2021-01-06 23:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev19) Patchwork
` (5 subsequent siblings)
18 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-06 23:12 UTC (permalink / raw)
To: Intel-gfx; +Cc: Bommu Krishnaiah
From: Anshuman Gupta <anshuman.gupta@intel.com>
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index cf3589fd0ddb..39f8c922ce66 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include <drm/drm_plane_helper.h>
#include <drm/drm_rect.h>
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -768,6 +770,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -804,6 +811,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -814,7 +822,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -890,8 +898,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e8dfe435ca8..0ea7e2a402ae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7209,6 +7209,7 @@ enum {
#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev19)
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (12 preceding siblings ...)
2021-01-06 23:12 ` [Intel-gfx] [RFC-v19 13/13] drm/i915/pxp: Add plane decryption support Huang, Sean Z
@ 2021-01-06 23:47 ` Patchwork
2021-01-07 16:02 ` Vivi, Rodrigo
2021-01-07 0:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (4 subsequent siblings)
18 siblings, 1 reply; 55+ messages in thread
From: Patchwork @ 2021-01-06 23:47 UTC (permalink / raw)
To: Huang, Sean Z; +Cc: intel-gfx
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev19)
URL : https://patchwork.freedesktop.org/series/84620/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fbdd4e2e287d drm/i915/pxp: Introduce Intel PXP component
-:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#119:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 194 lines checked
fdb764188c85 drm/i915/pxp: set KCR reg init during the boot time
20c2f538fd26 drm/i915/pxp: Implement funcs to create the TEE channel
-:8: WARNING:TYPO_SPELLING: 'defualt' may be misspelled - perhaps 'default'?
#8:
(defualt) session.
^^^^^^^
-:85: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#85:
new file mode 100644
total: 0 errors, 2 warnings, 0 checks, 253 lines checked
e77ddc43854a drm/i915/pxp: Create the arbitrary session after boot
-:68: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#68:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 330 lines checked
60d904942ebb drm/i915/pxp: Func to send hardware session termination
-:53: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#53:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 222 lines checked
e06c62d5fd8d drm/i915/pxp: Enable PXP irq worker and callback stub
-:51: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns
#51: FILE: drivers/gpu/drm/i915/i915_reg.h:7970:
+#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
total: 0 errors, 1 warnings, 0 checks, 230 lines checked
2b451866410d drm/i915/pxp: Destroy arb session upon teardown
f74cff978a9a drm/i915/pxp: Enable PXP power management
-:78: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 148 lines checked
f45f6bf27787 drm/i915/pxp: Expose session state for display protection flip
ed1733ee9985 mei: pxp: export pavp client to me client bus
-:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#32:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 277 lines checked
5ed5ea72d630 drm/i915/uapi: introduce drm_i915_gem_create_ext
-:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Joonas Lahtinen joonas.lahtinen@linux.intel.com'
#12:
Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com
-:13: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Matthew Auld matthew.auld@intel.com'
#13:
Cc: Matthew Auld matthew.auld@intel.com
-:46: ERROR:CODE_INDENT: code indent should use tabs where possible
#46: FILE: drivers/gpu/drm/i915/i915_gem.c:265:
+ struct drm_i915_private *i915;$
-:46: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#46: FILE: drivers/gpu/drm/i915/i915_gem.c:265:
+ struct drm_i915_private *i915;$
-:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#50: FILE: drivers/gpu/drm/i915/i915_gem.c:269:
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext *ext_data)
-:95: CHECK:LINE_SPACING: Please don't use multiple blank lines
#95: FILE: drivers/gpu/drm/i915/i915_gem.c:317:
+
+
-:107: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#107: FILE: include/uapi/drm/i915_drm.h:395:
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
-:155: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#155: FILE: include/uapi/drm/i915_drm.h:1736:
+#define I915_OBJECT_PARAM (1ull<<32)
^
total: 3 errors, 2 warnings, 3 checks, 136 lines checked
ae1f0edf901f drm/i915/pxp: User interface for Protected buffer
7ce48b165a12 drm/i915/pxp: Add plane decryption support
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev19)
2021-01-06 23:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev19) Patchwork
@ 2021-01-07 16:02 ` Vivi, Rodrigo
0 siblings, 0 replies; 55+ messages in thread
From: Vivi, Rodrigo @ 2021-01-07 16:02 UTC (permalink / raw)
To: Huang, Sean Z, intel-gfx
On Wed, 2021-01-06 at 23:47 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: Introduce Intel PXP component - Mesa single session (rev19)
> URL : https://patchwork.freedesktop.org/series/84620/
> State : warning
>
> == Summary ==
>
> $ dim checkpatch origin/drm-tip
> fbdd4e2e287d drm/i915/pxp: Introduce Intel PXP component
> -:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s),
> does MAINTAINERS need updating?
> #119:
> new file mode 100644
>
> total: 0 errors, 1 warnings, 0 checks, 194 lines checked
> fdb764188c85 drm/i915/pxp: set KCR reg init during the boot time
> 20c2f538fd26 drm/i915/pxp: Implement funcs to create the TEE channel
> -:8: WARNING:TYPO_SPELLING: 'defualt' may be misspelled - perhaps
> 'default'?
> #8:
> (defualt) session.
> ^^^^^^^
>
> -:85: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s),
> does MAINTAINERS need updating?
> #85:
> new file mode 100644
>
> total: 0 errors, 2 warnings, 0 checks, 253 lines checked
> e77ddc43854a drm/i915/pxp: Create the arbitrary session after boot
> -:68: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s),
> does MAINTAINERS need updating?
> #68:
> new file mode 100644
>
> total: 0 errors, 1 warnings, 0 checks, 330 lines checked
> 60d904942ebb drm/i915/pxp: Func to send hardware session termination
> -:53: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s),
> does MAINTAINERS need updating?
> #53:
> new file mode 100644
>
> total: 0 errors, 1 warnings, 0 checks, 222 lines checked
> e06c62d5fd8d drm/i915/pxp: Enable PXP irq worker and callback stub
> -:51: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100
> columns
> #51: FILE: drivers/gpu/drm/i915/i915_reg.h:7970:
> +#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto
> mask is in bit31-16 (Engine1 Interrupt Mask) */
>
> total: 0 errors, 1 warnings, 0 checks, 230 lines checked
> 2b451866410d drm/i915/pxp: Destroy arb session upon teardown
> f74cff978a9a drm/i915/pxp: Enable PXP power management
> -:78: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s),
> does MAINTAINERS need updating?
> #78:
> new file mode 100644
>
> total: 0 errors, 1 warnings, 0 checks, 148 lines checked
> f45f6bf27787 drm/i915/pxp: Expose session state for display
> protection flip
> ed1733ee9985 mei: pxp: export pavp client to me client bus
> -:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s),
> does MAINTAINERS need updating?
> #32:
> new file mode 100644
>
> total: 0 errors, 1 warnings, 0 checks, 277 lines checked
> 5ed5ea72d630 drm/i915/uapi: introduce drm_i915_gem_create_ext
> -:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Joonas
> Lahtinen joonas.lahtinen@linux.intel.com'
> #12:
> Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com
Please make sure you address some of the checkpatch complains like this
>
> -:13: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Matthew Auld
> matthew.auld@intel.com'
> #13:
> Cc: Matthew Auld matthew.auld@intel.com
this
>
> -:46: ERROR:CODE_INDENT: code indent should use tabs where possible
> #46: FILE: drivers/gpu/drm/i915/i915_gem.c:265:
> + struct drm_i915_private *i915;$
this
>
> -:46: WARNING:LEADING_SPACE: please, no spaces at the start of a line
> #46: FILE: drivers/gpu/drm/i915/i915_gem.c:265:
> + struct drm_i915_private *i915;$
>
this
> -:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open
> parenthesis
> #50: FILE: drivers/gpu/drm/i915/i915_gem.c:269:
> +static int __create_setparam(struct drm_i915_gem_object_param *args,
> + struct
> create_ext *ext_data)
>
this
> -:95: CHECK:LINE_SPACING: Please don't use multiple blank lines
> #95: FILE: drivers/gpu/drm/i915/i915_gem.c:317:
> +
> +
this
> -:107: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
> #107: FILE: include/uapi/drm/i915_drm.h:395:
> +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE +
> DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
>
> -:155: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
> #155: FILE: include/uapi/drm/i915_drm.h:1736:
> +#define I915_OBJECT_PARAM (1ull<<32)
this
> ^
>
> total: 3 errors, 2 warnings, 3 checks, 136 lines checked
> ae1f0edf901f drm/i915/pxp: User interface for Protected buffer
> 7ce48b165a12 drm/i915/pxp: Add plane decryption support
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 55+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Intel PXP component - Mesa single session (rev19)
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (13 preceding siblings ...)
2021-01-06 23:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev19) Patchwork
@ 2021-01-07 0:16 ` Patchwork
2021-01-07 10:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (3 subsequent siblings)
18 siblings, 0 replies; 55+ messages in thread
From: Patchwork @ 2021-01-07 0:16 UTC (permalink / raw)
To: Huang, Sean Z; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3959 bytes --]
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev19)
URL : https://patchwork.freedesktop.org/series/84620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9554 -> Patchwork_19276
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/index.html
Known issues
------------
Here are the changes found in Patchwork_19276 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [PASS][1] -> [FAIL][2] ([i915#1161] / [i915#262])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [FAIL][5] ([i915#579]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
* igt@vgem_basic@dmabuf-fence:
- fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/fi-tgl-y/igt@vgem_basic@dmabuf-fence.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/fi-tgl-y/igt@vgem_basic@dmabuf-fence.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (42 -> 37)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9554 -> Patchwork_19276
CI-20190529: 20190529
CI_DRM_9554: 4786f2a4c7e280974d0b46ca9e30a156eb528d59 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5945: f0ad1a564956d6796d9ff09182c48d78fb00eefe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19276: 7ce48b165a123c9c6834a1078ea167d09912ed16 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7ce48b165a12 drm/i915/pxp: Add plane decryption support
ae1f0edf901f drm/i915/pxp: User interface for Protected buffer
5ed5ea72d630 drm/i915/uapi: introduce drm_i915_gem_create_ext
ed1733ee9985 mei: pxp: export pavp client to me client bus
f45f6bf27787 drm/i915/pxp: Expose session state for display protection flip
f74cff978a9a drm/i915/pxp: Enable PXP power management
2b451866410d drm/i915/pxp: Destroy arb session upon teardown
e06c62d5fd8d drm/i915/pxp: Enable PXP irq worker and callback stub
60d904942ebb drm/i915/pxp: Func to send hardware session termination
e77ddc43854a drm/i915/pxp: Create the arbitrary session after boot
20c2f538fd26 drm/i915/pxp: Implement funcs to create the TEE channel
fdb764188c85 drm/i915/pxp: set KCR reg init during the boot time
fbdd4e2e287d drm/i915/pxp: Introduce Intel PXP component
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/index.html
[-- Attachment #1.2: Type: text/html, Size: 4734 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 55+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce Intel PXP component - Mesa single session (rev19)
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (14 preceding siblings ...)
2021-01-07 0:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-01-07 10:22 ` Patchwork
2021-01-07 15:42 ` [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Vivi, Rodrigo
` (2 subsequent siblings)
18 siblings, 0 replies; 55+ messages in thread
From: Patchwork @ 2021-01-07 10:22 UTC (permalink / raw)
To: Huang, Sean Z; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 25118 bytes --]
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev19)
URL : https://patchwork.freedesktop.org/series/84620/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9554_full -> Patchwork_19276_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19276_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19276_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19276_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_eio@suspend:
- shard-tglb: [PASS][1] -> [DMESG-WARN][2] +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-tglb3/igt@gem_eio@suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-tglb5/igt@gem_eio@suspend.html
* igt@i915_selftest@mock@timelines:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-kbl6/igt@i915_selftest@mock@timelines.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-kbl7/igt@i915_selftest@mock@timelines.html
- shard-iclb: [PASS][5] -> [DMESG-WARN][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-iclb3/igt@i915_selftest@mock@timelines.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-iclb8/igt@i915_selftest@mock@timelines.html
- shard-apl: [PASS][7] -> [DMESG-WARN][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-apl7/igt@i915_selftest@mock@timelines.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-apl1/igt@i915_selftest@mock@timelines.html
- shard-glk: [PASS][9] -> [DMESG-WARN][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-glk8/igt@i915_selftest@mock@timelines.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-glk1/igt@i915_selftest@mock@timelines.html
- shard-skl: [PASS][11] -> [DMESG-WARN][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl9/igt@i915_selftest@mock@timelines.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl2/igt@i915_selftest@mock@timelines.html
- shard-snb: [PASS][13] -> [DMESG-WARN][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-snb7/igt@i915_selftest@mock@timelines.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-snb2/igt@i915_selftest@mock@timelines.html
Known issues
------------
Here are the changes found in Patchwork_19276_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@system-suspend-devices:
- shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#2411])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-tglb3/igt@i915_pm_rpm@system-suspend-devices.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-tglb7/igt@i915_pm_rpm@system-suspend-devices.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: [PASS][17] -> [DMESG-FAIL][18] ([i915#2291] / [i915#541])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl3/igt@i915_selftest@live@gt_heartbeat.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl4/igt@i915_selftest@live@gt_heartbeat.html
- shard-glk: [PASS][19] -> [DMESG-FAIL][20] ([i915#2291])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-glk9/igt@i915_selftest@live@gt_heartbeat.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-glk2/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@mock@vma:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#2295])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl9/igt@i915_selftest@mock@vma.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl2/igt@i915_selftest@mock@vma.html
* igt@kms_async_flips@test-time-stamp:
- shard-skl: [PASS][23] -> [DMESG-FAIL][24] ([i915#142])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl8/igt@kms_async_flips@test-time-stamp.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl7/igt@kms_async_flips@test-time-stamp.html
* igt@kms_chamelium@dp-frame-dump:
- shard-glk: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-glk8/igt@kms_chamelium@dp-frame-dump.html
- shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl7/igt@kms_chamelium@dp-frame-dump.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-random:
- shard-skl: [PASS][27] -> [FAIL][28] ([i915#54]) +4 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: NOTRUN -> [FAIL][29] ([i915#2346])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][30] -> [FAIL][31] ([i915#79])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#2122])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271]) +40 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271]) +12 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-kbl1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu:
- shard-glk: NOTRUN -> [SKIP][36] ([fdo#109271]) +19 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-glk8/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
- shard-skl: NOTRUN -> [FAIL][37] ([i915#49])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-skl: NOTRUN -> [FAIL][38] ([fdo#108145] / [i915#265])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-glk: NOTRUN -> [FAIL][39] ([i915#265])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-glk8/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
- shard-skl: NOTRUN -> [FAIL][40] ([i915#265])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][41] -> [FAIL][42] ([fdo#108145] / [i915#265])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109642] / [fdo#111068])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-iclb5/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][45] -> [SKIP][46] ([fdo#109441])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-d-query-idle:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109278])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-iclb6/igt@kms_vblank@pipe-d-query-idle.html
* igt@runner@aborted:
- shard-snb: NOTRUN -> [FAIL][48] ([i915#2426])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-snb2/igt@runner@aborted.html
#### Possible fixes ####
* {igt@gem_exec_fair@basic-flow@rcs0}:
- shard-tglb: [FAIL][49] ([i915#2842]) -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
* {igt@gem_exec_fair@basic-none@rcs0}:
- shard-kbl: [SKIP][51] ([fdo#109271]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-kbl6/igt@gem_exec_fair@basic-none@rcs0.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-kbl7/igt@gem_exec_fair@basic-none@rcs0.html
* {igt@gem_exec_schedule@u-fairslice@rcs0}:
- shard-glk: [DMESG-WARN][53] ([i915#1610]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-glk8/igt@gem_exec_schedule@u-fairslice@rcs0.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-glk8/igt@gem_exec_schedule@u-fairslice@rcs0.html
- shard-skl: [DMESG-WARN][55] ([i915#1610] / [i915#2803]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl10/igt@gem_exec_schedule@u-fairslice@rcs0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl7/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@i915_pm_rpm@cursor-dpms:
- shard-glk: [DMESG-WARN][57] ([i915#118] / [i915#95]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-glk2/igt@i915_pm_rpm@cursor-dpms.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-glk6/igt@i915_pm_rpm@cursor-dpms.html
* igt@kms_color@pipe-b-ctm-0-5:
- shard-skl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl7/igt@kms_color@pipe-b-ctm-0-5.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl6/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
- shard-skl: [FAIL][61] ([i915#54]) -> [PASS][62] +8 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-dpms:
- shard-kbl: [DMESG-WARN][63] ([i915#165] / [i915#180] / [i915#78]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-dpms.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-dpms.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][65] ([i915#2346] / [i915#533]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@pipe-c-single-bo:
- shard-kbl: [INCOMPLETE][67] -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-kbl1/igt@kms_cursor_legacy@pipe-c-single-bo.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-kbl1/igt@kms_cursor_legacy@pipe-c-single-bo.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][69] ([i915#79]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
- shard-tglb: [FAIL][71] ([i915#2598]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-tglb2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-kbl: [DMESG-WARN][73] ([i915#180] / [i915#78]) -> [PASS][74] +4 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-kbl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-kbl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
* igt@kms_flip@modeset-vs-vblank-race@c-dp1:
- shard-kbl: [DMESG-WARN][75] ([i915#165]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-kbl2/igt@kms_flip@modeset-vs-vblank-race@c-dp1.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-kbl1/igt@kms_flip@modeset-vs-vblank-race@c-dp1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [FAIL][77] ([i915#2122]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl1/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl6/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][79] ([i915#1188]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl5/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-skl: [INCOMPLETE][81] ([i915#146] / [i915#648]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][83] ([fdo#108145] / [i915#265]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][85] ([fdo#109441]) -> [PASS][86] +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-iclb1/igt@kms_psr@psr2_sprite_mmap_gtt.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@perf@polling:
- shard-skl: [FAIL][87] ([i915#1542]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl8/igt@perf@polling.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl10/igt@perf@polling.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][89] ([i915#658]) -> [SKIP][90] ([i915#588])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][91] ([i915#2681] / [i915#2684]) -> [WARN][92] ([i915#1804] / [i915#2684])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][93] ([i915#1804] / [i915#2684]) -> [FAIL][94] ([i915#2680])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@runner@aborted:
- shard-kbl: [FAIL][95] ([i915#2295] / [i915#2505] / [i915#483]) -> ([FAIL][96], [FAIL][97], [FAIL][98]) ([i915#1436] / [i915#2295] / [i915#2426] / [i915#2505] / [i915#483])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-kbl6/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-kbl1/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-kbl7/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-kbl6/igt@runner@aborted.html
- shard-iclb: [FAIL][99] ([i915#2295] / [i915#2724] / [i915#483]) -> ([FAIL][100], [FAIL][101]) ([i915#2295] / [i915#2426] / [i915#2724])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-iclb6/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-iclb8/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-iclb4/igt@runner@aborted.html
- shard-apl: [FAIL][102] ([i915#2295]) -> ([FAIL][103], [FAIL][104], [FAIL][105]) ([i915#1610] / [i915#2295] / [i915#2426])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-apl6/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-apl6/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-apl3/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-apl1/igt@runner@aborted.html
- shard-tglb: [FAIL][106] ([i915#2295] / [i915#2667]) -> ([FAIL][107], [FAIL][108]) ([i915#2295] / [i915#2426] / [i915#2667])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-tglb5/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-tglb7/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-tglb2/igt@runner@aborted.html
- shard-skl: ([FAIL][109], [FAIL][110]) ([i915#2295] / [i915#2426]) -> ([FAIL][111], [FAIL][112], [FAIL][113]) ([i915#1436] / [i915#2295] / [i915#2426] / [i915#483])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl10/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9554/shard-skl2/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl8/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl7/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/shard-skl2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2667]: https://gitlab.freedesktop.org/drm/intel/issues/2667
[i915#2680]: https://gitlab.freedesktop.org/drm/intel/issues/2680
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#2803]: https://gitlab.freedesktop.org/drm/intel/issues/2803
[i915#2822]: https://gitlab.freedesktop.org/drm/intel/issues/2822
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9554 -> Patchwork_19276
CI-20190529: 20190529
CI_DRM_9554: 4786f2a4c7e280974d0b46ca9e30a156eb528d59 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5945: f0ad1a564956d6796d9ff09182c48d78fb00eefe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19276: 7ce48b165a123c9c6834a1078ea167d09912ed16 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19276/index.html
[-- Attachment #1.2: Type: text/html, Size: 30478 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (15 preceding siblings ...)
2021-01-07 10:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-01-07 15:42 ` Vivi, Rodrigo
2021-01-08 11:38 ` Joonas Lahtinen
2021-01-12 20:07 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Introduce Intel PXP component - Mesa single session (rev20) Patchwork
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
18 siblings, 1 reply; 55+ messages in thread
From: Vivi, Rodrigo @ 2021-01-07 15:42 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> PXP (Protected Xe Path) is an i915 component, available on
> GEN12+ that helps to establish the hardware protected session
> and manage the status of the alive software session, as well
> as its life cycle.
>
> This patch series is to allow the kernel space to create and
> manage a single hardware session (a.k.a. default session or
> arbitrary session). So user can allocate the protected buffer,
> which is encrypted with the leverage of the arbitrary hardware
> session.
>
> v2:
> - modification based on code review feedbacks received
> - passing pxp instead of i915 as function argument
> - remove dead code only for multi-session
> - move the pxp init call from i915_drv.c to intel_gt.c
> - remove the tautology naming
>
> v3:
> - rebase to latest drm-tip
>
> v4:
> - Append the split non-mesa patch sereis (commit #14 - #21) into
> this patch series
>
> v5:
> - include "intel_pxp.h" in intel_pxp_sm.h at commit #14 to fix
> the build problem.
>
> v6:
> - Fix the null pointer arb_session access bug in intel_pxp_arb.c
> in
> "04 [RFC-v5] drm/i915/pxp: Create the arbitrary session after
> boot"
>
> v7:
> - Use list_for_each_entry_safe instead of list_for_each_entry
>
> v8:
> - Add MEI vtag support for PXP multi-session usage
>
> v9:
> - Fix error handling bug in commit #5 "Func to send hardware
> session
> termination". In intel_pxp_cmd.c, we should properly assign
> "err = PTR_ERR(x)" if hitting the error case "IS_ERR(x)", this
> is
> the only change in v9.
>
> v10
> - Remove the multi session commits #14-#21, for now we would like
> to
> keep the multi session patches as downstream.
> - Adopt the code review suggestion from Wilson in commit #1
>
> v11
> - In commit #05 "drm/i915/pxp: Func to send hardware session
> termination", we should not assume VCS0 is always on.
> Instead we use available VCS#, could be VCS0, VCS2, etc.
>
> v12
> - Add "#include <linux/mutex.h> in #1 intel_pxp_types.h
>
> v13
> - Add "#include <linux/mutex.h> in #1 intel_pxp_types.h (#v12
> didn't
> actually update the _types.h file...)
>
> v14
> - Add "if (INTEL_GEN(gt->i915) < 12) return;" in #1
> intel_pxp_fini(), just skip for non gen12+ sku
>
> v15
> In #04:
> - Make intel_pxp_arb_reserve_session() as static function to fix
> the
> sparse warning
> - Update value of PXP_TEE_ARB_CMD_BIN
>
> v16
> In #04:
> - Remove the binary from source code via defining the TEE command
> header
>
> v17
> - In #04, directly return intel_pxp_tee_component_fini() if
> pxp_tee_comp_added is off
>
> v18
> - In #09, Add intel_pxp_gem_context_set_protected() to check the
> arb
> session before setting protected flag for gem context
>
> - In #12, Replace i915_gem_context_set_protected() with
> intel_pxp_gem_context_set_protected() to check whether the
> arbitrary
> session is alive
>
> v19
> - In #01, put intel_pxp_fini() in intel_gt_driver_remove()
> instead of
> intel_gt_driver_release() since intel_gt_driver_release() is
> the last
> stage of i915 unbind and we shouldn't call the component_del
> here.
>
> - In #04, check if arbitrary session is alive before
> intel_pxp_arb_create_session()
Please reduce the amount of series revision and start using --in-reply-
to so we can easily see what was addressed from the previous comments
versus what is open.
>
>
> Anshuman Gupta (1):
> drm/i915/pxp: Add plane decryption support
>
> Bommu Krishnaiah (2):
> drm/i915/uapi: introduce drm_i915_gem_create_ext
> drm/i915/pxp: User interface for Protected buffer
>
> Huang, Sean Z (9):
> drm/i915/pxp: Introduce Intel PXP component
> drm/i915/pxp: set KCR reg init during the boot time
> drm/i915/pxp: Implement funcs to create the TEE channel
> drm/i915/pxp: Create the arbitrary session after boot
> drm/i915/pxp: Func to send hardware session termination
> drm/i915/pxp: Enable PXP irq worker and callback stub
> drm/i915/pxp: Destroy arb session upon teardown
> drm/i915/pxp: Enable PXP power management
> drm/i915/pxp: Expose session state for display protection flip
>
> Vitaly Lubart (1):
> mei: pxp: export pavp client to me client bus
>
> drivers/gpu/drm/i915/Kconfig | 22 ++
> drivers/gpu/drm/i915/Makefile | 9 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 19 +-
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 5 +
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
> drivers/gpu/drm/i915/i915_drv.c | 7 +-
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/i915_gem.c | 63 +++-
> drivers/gpu/drm/i915/i915_reg.h | 4 +-
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 181 ++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 81 +++++
> drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 207 +++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 17 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 278
> ++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 20 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 28 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 +
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 ++++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 210 +++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 60 ++++
> drivers/misc/mei/Kconfig | 2 +
> drivers/misc/mei/Makefile | 1 +
> drivers/misc/mei/pxp/Kconfig | 13 +
> drivers/misc/mei/pxp/Makefile | 7 +
> drivers/misc/mei/pxp/mei_pxp.c | 230 +++++++++++++++
> drivers/misc/mei/pxp/mei_pxp.h | 18 ++
> include/drm/i915_component.h | 1 +
> include/drm/i915_pxp_tee_interface.h | 45 +++
> include/uapi/drm/i915_drm.h | 66 +++++
> 37 files changed, 1760 insertions(+), 12 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> create mode 100644 drivers/misc/mei/pxp/Kconfig
> create mode 100644 drivers/misc/mei/pxp/Makefile
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
> create mode 100644 include/drm/i915_pxp_tee_interface.h
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session
2021-01-07 15:42 ` [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Vivi, Rodrigo
@ 2021-01-08 11:38 ` Joonas Lahtinen
0 siblings, 0 replies; 55+ messages in thread
From: Joonas Lahtinen @ 2021-01-08 11:38 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx, Vivi, Rodrigo
Quoting Vivi, Rodrigo (2021-01-07 17:42:12)
> On Wed, 2021-01-06 at 15:12 -0800, Huang, Sean Z wrote:
> > PXP (Protected Xe Path) is an i915 component, available on
> > GEN12+ that helps to establish the hardware protected session
> > and manage the status of the alive software session, as well
> > as its life cycle.
> >
> > This patch series is to allow the kernel space to create and
> > manage a single hardware session (a.k.a. default session or
> > arbitrary session). So user can allocate the protected buffer,
> > which is encrypted with the leverage of the arbitrary hardware
> > session.
> >
> > v2:
> > - modification based on code review feedbacks received
> > - passing pxp instead of i915 as function argument
> > - remove dead code only for multi-session
> > - move the pxp init call from i915_drv.c to intel_gt.c
> > - remove the tautology naming
> >
> > v3:
> > - rebase to latest drm-tip
> >
> > v4:
> > - Append the split non-mesa patch sereis (commit #14 - #21) into
> > this patch series
> >
> > v5:
> > - include "intel_pxp.h" in intel_pxp_sm.h at commit #14 to fix
> > the build problem.
> >
> > v6:
> > - Fix the null pointer arb_session access bug in intel_pxp_arb.c
> > in
> > "04 [RFC-v5] drm/i915/pxp: Create the arbitrary session after
> > boot"
> >
> > v7:
> > - Use list_for_each_entry_safe instead of list_for_each_entry
> >
> > v8:
> > - Add MEI vtag support for PXP multi-session usage
> >
> > v9:
> > - Fix error handling bug in commit #5 "Func to send hardware
> > session
> > termination". In intel_pxp_cmd.c, we should properly assign
> > "err = PTR_ERR(x)" if hitting the error case "IS_ERR(x)", this
> > is
> > the only change in v9.
> >
> > v10
> > - Remove the multi session commits #14-#21, for now we would like
> > to
> > keep the multi session patches as downstream.
> > - Adopt the code review suggestion from Wilson in commit #1
> >
> > v11
> > - In commit #05 "drm/i915/pxp: Func to send hardware session
> > termination", we should not assume VCS0 is always on.
> > Instead we use available VCS#, could be VCS0, VCS2, etc.
> >
> > v12
> > - Add "#include <linux/mutex.h> in #1 intel_pxp_types.h
> >
> > v13
> > - Add "#include <linux/mutex.h> in #1 intel_pxp_types.h (#v12
> > didn't
> > actually update the _types.h file...)
> >
> > v14
> > - Add "if (INTEL_GEN(gt->i915) < 12) return;" in #1
> > intel_pxp_fini(), just skip for non gen12+ sku
> >
> > v15
> > In #04:
> > - Make intel_pxp_arb_reserve_session() as static function to fix
> > the
> > sparse warning
> > - Update value of PXP_TEE_ARB_CMD_BIN
> >
> > v16
> > In #04:
> > - Remove the binary from source code via defining the TEE command
> > header
> >
> > v17
> > - In #04, directly return intel_pxp_tee_component_fini() if
> > pxp_tee_comp_added is off
> >
> > v18
> > - In #09, Add intel_pxp_gem_context_set_protected() to check the
> > arb
> > session before setting protected flag for gem context
> >
> > - In #12, Replace i915_gem_context_set_protected() with
> > intel_pxp_gem_context_set_protected() to check whether the
> > arbitrary
> > session is alive
> >
> > v19
> > - In #01, put intel_pxp_fini() in intel_gt_driver_remove()
> > instead of
> > intel_gt_driver_release() since intel_gt_driver_release() is
> > the last
> > stage of i915 unbind and we shouldn't call the component_del
> > here.
> >
> > - In #04, check if arbitrary session is alive before
> > intel_pxp_arb_create_session()
>
> Please reduce the amount of series revision and start using --in-reply-
> to so we can easily see what was addressed from the previous comments
> versus what is open.
CI doesn't always work nicely with --in-reply-to :/
The changes made to each patch should be noted in the commit message of
the patch, not just in the cover letter. And level of detail of the
changes doesn't need to be verbose.
That way when reviewing v10 after v9, reviewer can also can through
patches which have v10 change entry in them.
Use trybot instead of the mailing list to catch things like missing
includes, so those should not result in new revisions. Only send to the
mailing list a new revision that you have checked to compile and fully
work.
But most importantly, I notice plenty of previously given feedback that
is unaddressed (type0/type1, unnecessary variables like session type
etc. that can only have single value in this series). So all of the
previous feedback needs addressing before continuing the review.
There is lot to be fixed about the coding style to match surroundings,
but that only makes sense as the last step after the series is otherwise
ready.
Regards, Joonas
_______________________________________________
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^ permalink raw reply [flat|nested] 55+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for Introduce Intel PXP component - Mesa single session (rev20)
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (16 preceding siblings ...)
2021-01-07 15:42 ` [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Vivi, Rodrigo
@ 2021-01-12 20:07 ` Patchwork
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
18 siblings, 0 replies; 55+ messages in thread
From: Patchwork @ 2021-01-12 20:07 UTC (permalink / raw)
To: Huang, Sean Z; +Cc: intel-gfx
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev20)
URL : https://patchwork.freedesktop.org/series/84620/
State : failure
== Summary ==
Applying: drm/i915/pxp: Introduce Intel PXP component
Applying: drm/i915/pxp: set KCR reg init during the boot time
Applying: drm/i915/pxp: Implement funcs to create the TEE channel
Applying: drm/i915/pxp: Create the arbitrary session after boot
Applying: drm/i915/pxp: Func to send hardware session termination
error: patch failed: drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c:34
error: drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c: patch does not apply
error: Did you hand edit your patch?
It does not apply to blobs recorded in its index.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Using index info to reconstruct a base tree...
A drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
Patch failed at 0005 drm/i915/pxp: Func to send hardware session termination
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
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^ permalink raw reply [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session
2021-01-06 23:12 [Intel-gfx] [RFC-v19 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (17 preceding siblings ...)
2021-01-12 20:07 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Introduce Intel PXP component - Mesa single session (rev20) Patchwork
@ 2021-01-17 6:45 ` Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
` (12 more replies)
18 siblings, 13 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
PXP (Protected Xe Path) is an i915 component, available on
GEN12+ that helps to establish the hardware protected session
and manage the status of the alive software session, as well
as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (a.k.a. default session or
arbitrary session). So user can allocate the protected buffer,
which is encrypted with the leverage of the arbitrary hardware
session.
rev21:
#01
- Remove the term "Mesa" from the help description of Kconfig
- Remove unnecessary "select INTEL_MEI_TXE" from DRM_I915_PXP
in Kconfig
#02
- Remove "#define KCR_INIT_MASK_SHIFT (16)", but still keep the
macro in this .c file
- Write KCR_INIT reg inly for gen12 during boot, not required
for gen13+
#03
- Remove debug print_hex_dump() from intel_pxp_tee_io_message()
- In struct i915_pxp_component_ops, change "receive" to "recv"
#04
- Rename SESSION_TYPE_TYPE0, SESSION_TYPE_TYPE1 as
SESSION_TYPE_HWDRM, SESSION_TYPE_NONHWDRM to have better meaning.
- Remove enum pxp_session_types and enum pxp_protection_modes
from single session patch series.
#05
In intel_pxp_cmd.c:
- Remove the debug print as well as print_hex_dump()
- Should call i915_gem_object_flush_map() before unpin map
- Using "goto label" instead of bool such as is_engine_pm_get
- We should always return the error if any, instead of skip
with i915_request_set_error_once()
#06
- Fix bug, access i915 pointer before assigning the value at
intel_pxp_irq_handler()
- Writing register GEN11_CRYPTO_RSVD_INTR_ENABLE to enable the
PXP irq
- Remove the unnecessary comment for GEN11_CRYPTO_RSVD_INTR_MASK
#07
- Bug fixing, we need to set the PXP_GLOBAL_TERMINATE 0x320f8
register after arb session termination
- Remove enum pxp_session_types and enum pxp_protection_modes
from single session patch series.
#11
- Fix "Fi.CI.CHECKPATCH" warnings
#12
- Only allow set I915_CONTEXT_PARAM_PROTECTED_CONTENT during
context creation (i915_gem_context_create_ioctl), but not
allow during context set param (i915_gem_context_setparam_ioctl)
Anshuman Gupta (1):
drm/i915/pxp: Add plane decryption support
Bommu Krishnaiah (2):
drm/i915/uapi: introduce drm_i915_gem_create_ext
drm/i915/pxp: User interface for Protected buffer
Huang, Sean Z (9):
drm/i915/pxp: Introduce Intel PXP component
drm/i915/pxp: set KCR reg init during the boot time
drm/i915/pxp: Implement funcs to create the TEE channel
drm/i915/pxp: Create the arbitrary session after boot
drm/i915/pxp: Func to send hardware session termination
drm/i915/pxp: Enable PXP irq worker and callback stub
drm/i915/pxp: Destroy arb session upon teardown
drm/i915/pxp: Enable PXP power management
drm/i915/pxp: Expose session state for display protection flip
Vitaly Lubart (1):
mei: pxp: export pavp client to me client bus
drivers/gpu/drm/i915/Kconfig | 21 ++
drivers/gpu/drm/i915/Makefile | 9 +
drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 +-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 5 +
.../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
drivers/gpu/drm/i915/gem/i915_gem_create.c | 68 +++++-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +
drivers/gpu/drm/i915/gt/intel_gt.c | 5 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 14 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
drivers/gpu/drm/i915/i915_drv.c | 7 +-
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 185 ++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 64 +++++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 208 ++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 17 ++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 223 +++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 19 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 28 +++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 +++++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 202 +++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 38 +++
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 +
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 ++++++++++++++++++
drivers/misc/mei/pxp/mei_pxp.h | 18 ++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45 ++++
include/uapi/drm/i915_drm.h | 66 +++++
37 files changed, 1671 insertions(+), 10 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 01/13] drm/i915/pxp: Introduce Intel PXP component
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
@ 2021-01-17 6:45 ` Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
` (11 subsequent siblings)
12 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (a.k.a default session or
arbitrary session). So Mesa can allocate the protected buffer,
which is encrypted with the leverage of the arbitrary hardware
session.
rev21:
- Remove the term "Mesa" from the help description of Kconfig
- Remove unnecessary "select INTEL_MEI_TXE" from DRM_I915_PXP
in Kconfig
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Kconfig | 21 ++++++++++++++
drivers/gpu/drm/i915/Makefile | 5 ++++
drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 29 ++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 25 +++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 25 +++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 23 ++++++++++++++++
9 files changed, 151 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..f0a8c46126d8 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,27 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ select INTEL_MEI
+ select INTEL_MEI_ME
+ select INTEL_MEI_PXP
+ default y
+ help
+ This option selects INTEL_MEI_ME if it isn't already selected to
+ enabled full PXP Services on Intel platforms.
+
+ PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
+ that helps to establish the hardware protected session and manage
+ the status of the alive software session, as well as its life cycle.
+
+ This patch series is to allow the kernel space to create and
+ manage a single hardware session (a.k.a default session or
+ arbitrary session). So user space can allocate the protected buffer,
+ which is encrypted with the leverage of the arbitrary hardware
+ session.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 006dec54408d..9d27e2d8decc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -265,6 +265,11 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index d8e1ab412634..336ad7deae06 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -18,6 +18,7 @@
#include "intel_uncore.h"
#include "intel_pm.h"
#include "shmem_utils.h"
+#include "pxp/intel_pxp.h"
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
@@ -584,6 +585,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ intel_pxp_init(>->pxp);
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -607,6 +610,8 @@ void intel_gt_driver_remove(struct intel_gt *gt)
{
__intel_gt_disable(gt);
+ intel_pxp_fini(>->pxp);
+
intel_uc_driver_remove(>->uc);
intel_engines_release(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index a83d3e18254d..c4760e2722fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -23,6 +23,7 @@
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_types.h"
struct drm_i915_private;
struct i915_ggtt;
@@ -145,6 +146,8 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
+
+ struct intel_pxp pxp;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index 000000000000..9bc3c7e30654
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+
+void intel_pxp_init(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ if (INTEL_GEN(gt->i915) < 12)
+ return;
+
+ intel_pxp_ctx_init(&pxp->ctx);
+
+ drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
+}
+
+void intel_pxp_fini(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ if (INTEL_GEN(gt->i915) < 12)
+ return;
+
+ intel_pxp_ctx_fini(&pxp->ctx);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
new file mode 100644
index 000000000000..f47bc6bea34f
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_H__
+#define __INTEL_PXP_H__
+
+#include "intel_pxp_types.h"
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_init(struct intel_pxp *pxp);
+void intel_pxp_fini(struct intel_pxp *pxp);
+#else
+static inline void intel_pxp_init(struct intel_pxp *pxp)
+{
+ return 0;
+}
+
+static inline void intel_pxp_fini(struct intel_pxp *pxp)
+{
+}
+#endif
+
+#endif /* __INTEL_PXP_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
new file mode 100644
index 000000000000..2be6bf2f0d0f
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_context.h"
+
+/**
+ * intel_pxp_ctx_init - To init a pxp context.
+ * @ctx: pointer to ctx structure.
+ */
+void intel_pxp_ctx_init(struct pxp_context *ctx)
+{
+ mutex_init(&ctx->mutex);
+ ctx->inited = true;
+}
+
+/**
+ * intel_pxp_ctx_fini - To finish the pxp context.
+ * @ctx: pointer to ctx structure.
+ */
+void intel_pxp_ctx_fini(struct pxp_context *ctx)
+{
+ ctx->inited = false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
new file mode 100644
index 000000000000..f51021c33d45
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_CONTEXT_H__
+#define __INTEL_PXP_CONTEXT_H__
+
+#include <linux/mutex.h>
+#include "intel_pxp_types.h"
+
+void intel_pxp_ctx_init(struct pxp_context *ctx);
+void intel_pxp_ctx_fini(struct pxp_context *ctx);
+
+#endif /* __INTEL_PXP_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
new file mode 100644
index 000000000000..f9b40ea98b1b
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_TYPES_H__
+#define __INTEL_PXP_TYPES_H__
+
+#include <linux/mutex.h>
+
+/* struct pxp_context - Represents combined view of driver and logical HW states. */
+struct pxp_context {
+ /** @mutex: mutex to protect the pxp context */
+ struct mutex mutex;
+
+ bool inited;
+};
+
+struct intel_pxp {
+ struct pxp_context ctx;
+};
+
+#endif /* __INTEL_PXP_TYPES_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 02/13] drm/i915/pxp: set KCR reg init during the boot time
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
@ 2021-01-17 6:45 ` Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 03/13] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
` (10 subsequent siblings)
12 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
rev21:
- Remove "#define KCR_INIT_MASK_SHIFT (16)", but still keep the
macro in this .c file
- Write KCR_INIT reg inly for gen12 during boot, not required
for gen13+
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 9bc3c7e30654..4e9cee7df4f2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,12 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+/* KCR register definitions */
+#define KCR_INIT _MMIO(0x320f0)
+
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << 16))
+
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -15,6 +21,9 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_ctx_init(&pxp->ctx);
+ if (INTEL_GEN(gt->i915) == 12)
+ intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
}
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
@ 2021-01-17 6:45 ` Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 04/13] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
` (9 subsequent siblings)
12 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(default) session.
rev21:
- Remove debug print_hex_dump() from intel_pxp_tee_io_message()
- In struct i915_pxp_component_ops, change "receive" to "recv"
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 129 +++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45 ++++++++
8 files changed, 203 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9d27e2d8decc..07bb0400e016 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -268,7 +268,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
- pxp/intel_pxp_context.o
+ pxp/intel_pxp_context.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f5666b44ea9d..e9cb8e9ca172 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
mutex_init(&dev_priv->hdcp_comp_mutex);
+ mutex_init(&dev_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8376cff5ba86..d2ae5874c516 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1209,6 +1209,12 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 4e9cee7df4f2..81cf845d1b94 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
/* KCR register definitions */
#define KCR_INIT _MMIO(0x320f0)
@@ -24,6 +25,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (INTEL_GEN(gt->i915) == 12)
intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ intel_pxp_tee_component_init(pxp);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
}
@@ -34,5 +37,7 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (INTEL_GEN(gt->i915) < 12)
return;
+ intel_pxp_tee_component_fini(pxp);
+
intel_pxp_ctx_fini(&pxp->ctx);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index 000000000000..e7edd4e1d5b4
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include <linux/component.h>
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
+ return -EINVAL;
+
+ lockdep_assert_held(&i915->pxp_tee_comp_mutex);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in, msg_in_size);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to send TEE message\n");
+ return -EFAULT;
+ }
+
+ ret = pxp_tee_master->ops->recv(pxp_tee_master->tee_dev, msg_out, msg_out_buf_size);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed to receive TEE message\n");
+ return -EFAULT;
+ }
+
+ if (ret > msg_out_buf_size) {
+ drm_err(&i915->drm, "Failed to receive TEE message due to unexpected output size\n");
+ return -EFAULT;
+ }
+
+ *msg_out_size_ptr = ret;
+ ret = 0;
+
+ return ret;
+}
+
+/**
+ * i915_pxp_tee_component_bind - bind funciton to pass the function pointers to pxp_tee
+ * @i915_kdev: pointer to i915 kernel device
+ * @tee_kdev: pointer to tee kernel device
+ * @data: pointer to pxp_tee_master containing the function pointers
+ *
+ * This bind function is called during the system boot or resume from system sleep.
+ *
+ * Return: return 0 if successful.
+ */
+static int i915_pxp_tee_component_bind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+ if (!i915 || !tee_kdev || !data)
+ return -EPERM;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_master = (struct i915_pxp_comp_master *)data;
+ i915->pxp_tee_master->tee_dev = tee_kdev;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ return 0;
+}
+
+static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+ if (!i915 || !tee_kdev || !data)
+ return;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_master = NULL;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+}
+
+static const struct component_ops i915_pxp_tee_component_ops = {
+ .bind = i915_pxp_tee_component_bind,
+ .unbind = i915_pxp_tee_component_unbind,
+};
+
+void intel_pxp_tee_component_init(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops,
+ I915_COMPONENT_PXP);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed at component add(%d)\n", ret);
+ return;
+ }
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_comp_added = true;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+}
+
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ if (!i915->pxp_tee_comp_added) {
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+ return;
+ }
+
+ i915->pxp_tee_comp_added = false;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
new file mode 100644
index 000000000000..4b5e3edb1d9b
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_TEE_H__
+#define __INTEL_PXP_TEE_H__
+
+#include "intel_pxp.h"
+
+void intel_pxp_tee_component_init(struct intel_pxp *pxp);
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_TEE_H__ */
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 55c3b123581b..c1e2a43d2d1e 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -29,6 +29,7 @@
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
+ I915_COMPONENT_PXP
};
/* MAX_PORT is the number of port
diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h
new file mode 100644
index 000000000000..0efd14702b4b
--- /dev/null
+++ b/include/drm/i915_pxp_tee_interface.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef _I915_PXP_TEE_INTERFACE_H_
+#define _I915_PXP_TEE_INTERFACE_H_
+
+#include <linux/mutex.h>
+#include <linux/device.h>
+
+/**
+ * struct i915_pxp_component_ops - ops for PXP services.
+ * @owner: Module providing the ops
+ * @send: sends data to PXP
+ * @receive: receives data from PXP
+ */
+struct i915_pxp_component_ops {
+ /**
+ * @owner: owner of the module provding the ops
+ */
+ struct module *owner;
+
+ int (*send)(struct device *dev, const void *message, size_t size);
+ int (*recv)(struct device *dev, void *buffer, size_t size);
+};
+
+/**
+ * struct i915_pxp_component_master - Used for communication between i915
+ * and TEE drivers for the PXP services
+ * @tee_dev: device that provide the PXP service from TEE Bus.
+ * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
+ */
+struct i915_pxp_comp_master {
+ struct device *tee_dev;
+ const struct i915_pxp_component_ops *ops;
+
+ /* To protect the above members. */
+ struct mutex mutex;
+};
+
+#endif /* _I915_TEE_PXP_INTERFACE_H_ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 04/13] drm/i915/pxp: Create the arbitrary session after boot
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (2 preceding siblings ...)
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 03/13] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
@ 2021-01-17 6:45 ` Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 05/13] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
` (8 subsequent siblings)
12 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
rev21:
- Rename SESSION_TYPE_TYPE0, SESSION_TYPE_TYPE1 as SESSION_TYPE_HWDRM,
SESSION_TYPE_NONHWDRM to have better meaning.
- Remove enum pxp_session_types and enum pxp_protection_modes from
single session patch series.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 122 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 16 +++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 73 +++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 4 +
8 files changed, 221 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 07bb0400e016..e3b7f6b5dadb 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -268,6 +268,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_arb.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 81cf845d1b94..4f033907564a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_arb.h"
/* KCR register definitions */
#define KCR_INIT _MMIO(0x320f0)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
new file mode 100644
index 000000000000..dd98ca407e78
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp_types.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
+
+/* Arbitrary session */
+#define ARB_SESSION_INDEX 0xf
+
+bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp)
+{
+ u32 regval_sip = 0;
+ intel_wakeref_t wakeref;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
+ regval_sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+ }
+
+ return regval_sip & BIT(ARB_SESSION_INDEX);
+}
+
+/* wait hw session_in_play reg to match the current sw state */
+static int wait_arb_hw_sw_state(struct intel_pxp *pxp)
+{
+ const int max_retry = 10;
+ const int ms_delay = 10;
+ int retry = 0;
+ int ret;
+
+ ret = -EINVAL;
+ for (retry = 0; retry < max_retry; retry++) {
+ if (intel_pxp_arb_session_is_in_play(pxp) ==
+ pxp->ctx.arb_is_in_play) {
+ ret = 0;
+ break;
+ }
+
+ msleep(ms_delay);
+ }
+
+ return ret;
+}
+
+static void arb_session_entry_init(struct intel_pxp *pxp)
+{
+ pxp->ctx.arb_is_in_play = false;
+}
+
+static int intel_pxp_arb_reserve_session(struct intel_pxp *pxp)
+{
+ int ret;
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ arb_session_entry_init(pxp);
+ ret = wait_arb_hw_sw_state(pxp);
+
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_mark_session_in_play - To put an reserved protected session to "in_play" state
+ * @pxp: pointer to pxp struct.
+ *
+ * Return: status. 0 means update is successful.
+ */
+static int intel_pxp_arb_mark_session_in_play(struct intel_pxp *pxp)
+{
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ if (pxp->ctx.arb_is_in_play)
+ return -EINVAL;
+
+ pxp->ctx.arb_is_in_play = true;
+ return 0;
+}
+
+int intel_pxp_arb_create_session(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ if (pxp->ctx.flag_display_hm_surface_keys) {
+ drm_err(>->i915->drm, "%s: arb session is alive so skipping the creation\n",
+ __func__);
+ return 0;
+ }
+
+ ret = intel_pxp_arb_reserve_session(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to reserve arb session\n");
+ return ret;
+ }
+
+ ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION_INDEX);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to send tee cmd for arb session creation\n");
+ return ret;
+ }
+
+ ret = intel_pxp_arb_mark_session_in_play(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to mark arb session status in play\n");
+ return ret;
+ }
+
+ pxp->ctx.flag_display_hm_surface_keys = true;
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
new file mode 100644
index 000000000000..2196153dd879
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_ARB_H__
+#define __INTEL_PXP_ARB_H__
+
+#include <linux/types.h>
+
+struct intel_pxp;
+
+int intel_pxp_arb_create_session(struct intel_pxp *pxp);
+bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_ARB_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
index f51021c33d45..bf2feb4aaf6d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -8,6 +8,7 @@
#include <linux/mutex.h>
#include "intel_pxp_types.h"
+#include "intel_pxp_arb.h"
void intel_pxp_ctx_init(struct pxp_context *ctx);
void intel_pxp_ctx_fini(struct pxp_context *ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index e7edd4e1d5b4..4dd33ffb8373 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -10,6 +10,32 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_arb.h"
+
+#define PXP_TEE_APIVER 0x40002
+#define PXP_TEE_ARB_CMDID 0x1e
+#define PXP_TEE_ARB_PROTECTION_MODE 0x2
+
+/* PXP TEE message header */
+struct pxp_tee_cmd_header {
+ u32 api_version;
+ u32 command_id;
+ u32 status;
+ /* Length of the message (excluding the header) */
+ u32 buffer_len;
+} __packed;
+
+/* PXP TEE message input to create a arbitrary session */
+struct pxp_tee_create_arb_in {
+ struct pxp_tee_cmd_header header;
+ u32 protection_mode;
+ u32 session_id;
+} __packed;
+
+/* PXP TEE message output to create a arbitrary session */
+struct pxp_tee_create_arb_out {
+ struct pxp_tee_cmd_header header;
+} __packed;
static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
void *msg_in, u32 msg_in_size,
@@ -62,7 +88,9 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
static int i915_pxp_tee_component_bind(struct device *i915_kdev,
struct device *tee_kdev, void *data)
{
+ int ret = 0;
struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+ struct intel_pxp *pxp = &i915->gt.pxp;
if (!i915 || !tee_kdev || !data)
return -EPERM;
@@ -72,6 +100,19 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
i915->pxp_tee_master->tee_dev = tee_kdev;
mutex_unlock(&i915->pxp_tee_comp_mutex);
+ mutex_lock(&pxp->ctx.mutex);
+
+ /* Create arb session only if tee is ready, during system boot or sleep/resume */
+ if (!intel_pxp_arb_session_is_in_play(pxp))
+ ret = intel_pxp_arb_create_session(pxp);
+
+ mutex_unlock(&pxp->ctx.mutex);
+
+ if (ret) {
+ drm_err(&i915->drm, "Failed to create arb session ret=[%d]\n", ret);
+ return ret;
+ }
+
return 0;
}
@@ -127,3 +168,35 @@ void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
}
+
+int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
+ int arb_session_id)
+{
+ int ret;
+ u32 msg_out_size_received = 0;
+ struct pxp_tee_create_arb_in msg_in = {0};
+ struct pxp_tee_create_arb_out msg_out = {0};
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ msg_in.header.api_version = PXP_TEE_APIVER;
+ msg_in.header.command_id = PXP_TEE_ARB_CMDID;
+ msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header);
+ msg_in.protection_mode = PXP_TEE_ARB_PROTECTION_MODE;
+ msg_in.session_id = arb_session_id;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+
+ ret = intel_pxp_tee_io_message(pxp,
+ &msg_in,
+ sizeof(msg_in),
+ &msg_out, &msg_out_size_received,
+ sizeof(msg_out));
+
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ if (ret)
+ drm_err(&i915->drm, "Failed to send tee msg ret=[%d]\n", ret);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
index 4b5e3edb1d9b..c46f9033f709 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -11,4 +11,7 @@
void intel_pxp_tee_component_init(struct intel_pxp *pxp);
void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
+int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
+ int arb_session_id);
+
#endif /* __INTEL_PXP_TEE_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index f9b40ea98b1b..e2bd320302c2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -14,6 +14,10 @@ struct pxp_context {
struct mutex mutex;
bool inited;
+
+ bool arb_is_in_play;
+
+ bool flag_display_hm_surface_keys;
};
struct intel_pxp {
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 05/13] drm/i915/pxp: Func to send hardware session termination
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (3 preceding siblings ...)
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 04/13] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
@ 2021-01-17 6:45 ` Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
` (7 subsequent siblings)
12 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
rev21:
In intel_pxp_cmd.c:
- Remove the debug print as well as print_hex_dump()
- Should call i915_gem_object_flush_map() before unpin map
- Using "goto label" instead of bool such as is_engine_pm_get
- We should always return the error if any, instead of skip
with i915_request_set_error_once()
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 13 +++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 124 +++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 4 +
5 files changed, 160 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e3b7f6b5dadb..c931ef5e8a85 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -269,6 +269,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_arb.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 4f033907564a..f71677a84405 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -17,10 +17,23 @@
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ int i;
if (INTEL_GEN(gt->i915) < 12)
return;
+ /* Find the first VCS engine present */
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (HAS_ENGINE(gt, _VCS(i))) {
+ pxp->vcs_engine = gt->engine[_VCS(i)];
+ break;
+ }
+ }
+ if (!pxp->vcs_engine) {
+ drm_err(>->i915->drm, "Could not find a VCS engine\n");
+ return;
+ }
+
intel_pxp_ctx_init(&pxp->ctx);
if (INTEL_GEN(gt->i915) == 12)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index 000000000000..6898b8826302
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_cmd.h"
+#include "i915_drv.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ u32 *cmd;
+
+ if (!ce || !ce->engine || !cmd_buf)
+ return ERR_PTR(-EINVAL);
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_err(>->i915->drm, "Failed to %s, invalid cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_err(>->i915->drm, "Failed to i915_gem_object_pin_map()\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ i915_gem_object_flush_map(pool->obj);
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_err(>->i915->drm, "Failed to i915_vma_instance()\n");
+ return batch;
+ }
+
+ return batch;
+}
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ int size = cmd_size_in_dw * 4;
+
+ ce = pxp->vcs_engine->kernel_context;
+ if (!ce)
+ return -EINVAL;
+
+ if (!cmd || cmd_size_in_dw == 0)
+ return -EINVAL;
+
+ intel_engine_pm_get(ce->engine);
+
+ size = round_up(size, PAGE_SIZE);
+ pool = intel_gt_get_buffer_pool(gt, size);
+ if (IS_ERR(pool)) {
+ err = PTR_ERR(pool);
+ goto out_engine_pm_put;
+ }
+
+ batch = intel_pxp_cmd_get_batch(pxp, ce, pool, cmd, cmd_size_in_dw);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_engine_pool_put;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto out_engine_pool_put;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_vma_unpin;
+ }
+
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
+ if (err)
+ goto out_vma_unpin;
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (!err)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err)
+ goto out_vma_unpin;
+
+ if (ce->engine->emit_init_breadcrumb) {
+ err = ce->engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_vma_unpin;
+ }
+
+ err = ce->engine->emit_bb_start(rq, batch->node.start,
+ batch->node.size, 0);
+ if (err)
+ goto out_vma_unpin;
+
+ i915_request_add(rq);
+
+out_vma_unpin:
+ i915_vma_unpin(batch);
+out_engine_pool_put:
+ intel_gt_buffer_pool_put(pool);
+out_engine_pm_put:
+ intel_engine_pm_put(ce->engine);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
new file mode 100644
index 000000000000..d04463962421
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_CMD_H__
+#define __INTEL_PXP_CMD_H__
+
+#include "gt/intel_gt_buffer_pool.h"
+#include "intel_pxp.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw);
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw);
+#endif /* __INTEL_PXP_SM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index e2bd320302c2..19d43b43e483 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -8,6 +8,8 @@
#include <linux/mutex.h>
+struct intel_engine_cs;
+
/* struct pxp_context - Represents combined view of driver and logical HW states. */
struct pxp_context {
/** @mutex: mutex to protect the pxp context */
@@ -22,6 +24,8 @@ struct pxp_context {
struct intel_pxp {
struct pxp_context ctx;
+
+ struct intel_engine_cs *vcs_engine;
};
#endif /* __INTEL_PXP_TYPES_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (4 preceding siblings ...)
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 05/13] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
@ 2021-01-17 6:45 ` Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 07/13] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
` (6 subsequent siblings)
12 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
rev21:
- Fix bug, access i915 pointer before assigning the value at intel_pxp_irq_handler()
- Writing register GEN11_CRYPTO_RSVD_INTR_ENABLE to enable the PXP irq
- Remove the unnecessary comment for GEN11_CRYPTO_RSVD_INTR_MASK
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 14 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 99 ++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 23 ++++-
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 -
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++
7 files changed, 145 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 9830342aa6f4..2241e9abfa3a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -14,6 +14,7 @@
#include "intel_lrc_reg.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -107,6 +108,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>->pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
@@ -233,6 +237,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
+
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0);
}
void gen11_gt_irq_postinstall(struct intel_gt *gt)
@@ -245,6 +252,10 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
const u32 dmask = irqs << 16 | irqs;
const u32 smask = irqs << 16;
+ const u32 smask_pxp =
+ (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
+ PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
+ PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE) << 16;
BUILD_BUG_ON(irqs & 0xffff0000);
@@ -271,6 +282,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
/* Same thing for GuC interrupts */
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
+
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, smask_pxp);
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~smask_pxp);
}
void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 249a81575b9d..97bcecada87f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7943,6 +7943,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE 1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index f71677a84405..99cd93e12455 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -2,6 +2,7 @@
/*
* Copyright(c) 2020 Intel Corporation.
*/
+#include <linux/workqueue.h>
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
@@ -14,6 +15,70 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << 16))
+static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>->irq_lock);
+
+ intel_uncore_write(gt->uncore, GEN11_CRYPTO_RSVD_INTR_MASK, mask << 16);
+}
+
+static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
+{
+ int ret;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ pxp->ctx.global_state_attacked = true;
+
+ mutex_unlock(&pxp->ctx.mutex);
+
+ return ret;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ if (pxp->ctx.global_state_attacked) {
+ pxp->ctx.global_state_attacked = false;
+
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_arb_create_session(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to create arb session\n");
+ goto end;
+ }
+ }
+end:
+ mutex_unlock(&pxp->ctx.mutex);
+ return ret;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work);
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ u32 events = 0;
+
+ spin_lock_irq(>->irq_lock);
+ events = fetch_and_zero(&pxp->current_events);
+ spin_unlock_irq(>->irq_lock);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(pxp);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(pxp);
+
+ spin_lock_irq(>->irq_lock);
+ intel_pxp_write_irq_mask_reg(gt, ~pxp->handled_irr);
+ spin_unlock_irq(>->irq_lock);
+}
+
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -41,6 +106,12 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_tee_component_init(pxp);
+ INIT_WORK(&pxp->irq_work, intel_pxp_irq_work);
+
+ pxp->handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
+ PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
+ PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
}
@@ -55,3 +126,31 @@ void intel_pxp_fini(struct intel_pxp *pxp)
intel_pxp_ctx_fini(&pxp->ctx);
}
+
+/**
+ * intel_pxp_irq_handler - Proxies KCR interrupts to PXP.
+ * @pxp: pointer to pxp struct
+ * @iir: GT interrupt vector associated with the interrupt
+ *
+ * Dispatches each vector element into an IRQ to PXP.
+ */
+void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
+{
+ const u32 events = iir & pxp->handled_irr;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (!gt || !gt->i915 || INTEL_GEN(gt->i915) < 12)
+ return;
+
+ lockdep_assert_held(>->irq_lock);
+
+ if (!events) {
+ drm_err(>->i915->drm, "pxp irq handler called with zero irr\n");
+ return;
+ }
+
+ intel_pxp_write_irq_mask_reg(gt, ~0);
+
+ pxp->current_events |= events;
+ schedule_work(&pxp->irq_work);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index f47bc6bea34f..420da2790624 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -8,15 +8,36 @@
#include "intel_pxp_types.h"
+#define PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED BIT(1)
+#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
+#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+
#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
+int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
+int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp);
+
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
#else
-static inline void intel_pxp_init(struct intel_pxp *pxp)
+static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
+{
+}
+
+static inline int i915_pxp_teardown_required_callback(struct intel_pxp *pxp)
+{
+ return 0;
+}
+
+static inline int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
{
return 0;
}
+static inline void intel_pxp_init(struct intel_pxp *pxp)
+{
+}
+
static inline void intel_pxp_fini(struct intel_pxp *pxp)
{
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
index 2be6bf2f0d0f..4e820258b7ae 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -11,7 +11,10 @@
*/
void intel_pxp_ctx_init(struct pxp_context *ctx)
{
+ ctx->global_state_attacked = false;
+
mutex_init(&ctx->mutex);
+
ctx->inited = true;
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
index bf2feb4aaf6d..f51021c33d45 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -8,7 +8,6 @@
#include <linux/mutex.h>
#include "intel_pxp_types.h"
-#include "intel_pxp_arb.h"
void intel_pxp_ctx_init(struct pxp_context *ctx);
void intel_pxp_ctx_fini(struct pxp_context *ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index 19d43b43e483..dd7445ff2cb8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -7,6 +7,7 @@
#define __INTEL_PXP_TYPES_H__
#include <linux/mutex.h>
+#include <linux/workqueue.h>
struct intel_engine_cs;
@@ -20,9 +21,14 @@ struct pxp_context {
bool arb_is_in_play;
bool flag_display_hm_surface_keys;
+ bool global_state_attacked;
};
struct intel_pxp {
+ struct work_struct irq_work;
+ u32 handled_irr;
+ u32 current_events;
+
struct pxp_context ctx;
struct intel_engine_cs *vcs_engine;
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 07/13] drm/i915/pxp: Destroy arb session upon teardown
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (5 preceding siblings ...)
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
@ 2021-01-17 6:45 ` Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 08/13] drm/i915/pxp: Enable PXP power management Huang, Sean Z
` (5 subsequent siblings)
12 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
rev21:
- Bug fixing, we need to set the PXP_GLOBAL_TERMINATE 0x320f8
register after arb session termination
- Remove enum pxp_session_types and enum pxp_protection_modes from
single session patch series.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 86 ++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 109 +++++++++++++++++++++--
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 11 +--
5 files changed, 200 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 99cd93e12455..e6dd57ec73f5 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -29,6 +29,9 @@ static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
mutex_lock(&pxp->ctx.mutex);
pxp->ctx.global_state_attacked = true;
+ pxp->ctx.flag_display_hm_surface_keys = false;
+
+ ret = intel_pxp_arb_terminate_session_with_global_terminate(pxp);
mutex_unlock(&pxp->ctx.mutex);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
index dd98ca407e78..cde5ddd73da9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -10,9 +10,13 @@
#include "intel_pxp_arb.h"
#include "intel_pxp.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_cmd.h"
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
+/* PXP global terminate register for session termination */
+#define PXP_GLOBAL_TERMINATE _MMIO(0x320f8)
+
/* Arbitrary session */
#define ARB_SESSION_INDEX 0xf
@@ -120,3 +124,85 @@ int intel_pxp_arb_create_session(struct intel_pxp *pxp)
return ret;
}
+
+static int intel_pxp_arb_session_terminate(struct intel_pxp *pxp)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ /* Calculate how many bytes need to be alloc */
+ cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL, ARB_SESSION_INDEX);
+ cmd_size_in_dw += intel_pxp_cmd_add_inline_termination(NULL);
+ cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr, ARB_SESSION_INDEX);
+ cmd_ptr += intel_pxp_cmd_add_inline_termination(cmd_ptr);
+ cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr);
+
+ if (cmd_size_in_dw != (cmd_ptr - cmd)) {
+ ret = -EINVAL;
+ drm_err(>->i915->drm, "Failed to %s\n", __func__);
+ goto end;
+ }
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
+ }
+
+ ret = intel_pxp_cmd_submit(pxp, cmd, cmd_size_in_dw);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to intel_pxp_cmd_submit()\n");
+ goto end;
+ }
+
+end:
+ kfree(cmd);
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_terminate_session_with_global_terminate - Terminate the arb hw session.
+ * @pxp: pointer to pxp struct.
+ *
+ * This function is NOT intended to be called from the ioctl, and need to be protected by
+ * ctx.mutex to ensure no SIP change during the call.
+ *
+ * Return: status. 0 means terminate is successful.
+ */
+int intel_pxp_arb_terminate_session_with_global_terminate(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ /* terminate the hw sessions */
+ ret = intel_pxp_arb_session_terminate(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to intel_pxp_arb_session_terminate\n");
+ return ret;
+ }
+
+ pxp->ctx.arb_is_in_play = false;
+
+ ret = wait_arb_hw_sw_state(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to wait_arb_hw_sw_state\n");
+ return ret;
+ }
+
+ intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1);
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
index 2196153dd879..6b0622e8ba93 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
@@ -11,6 +11,7 @@
struct intel_pxp;
int intel_pxp_arb_create_session(struct intel_pxp *pxp);
+int intel_pxp_arb_terminate_session_with_global_terminate(struct intel_pxp *pxp);
bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp);
#endif /* __INTEL_PXP_ARB_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
index 6898b8826302..6a0fe50c1aeb 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -5,13 +5,29 @@
#include "intel_pxp_cmd.h"
#include "i915_drv.h"
+#include "gt/intel_gpu_commands.h"
#include "gt/intel_context.h"
#include "gt/intel_engine_pm.h"
-struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
- struct intel_context *ce,
- struct intel_gt_buffer_pool_node *pool,
- u32 *cmd_buf, int cmd_size_in_dw)
+/* PXP GPU command definitions */
+
+/* MI_SET_APPID */
+#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
+
+/* MI_FLUSH_DW */
+#define MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE BIT(22)
+
+/* MI_WAIT */
+#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG BIT(9)
+#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG BIT(8)
+
+/* CRYPTO_KEY_EXCHANGE */
+#define CRYPTO_KEY_EXCHANGE ((0x3 << 29) | (0x01609 << 16))
+
+static struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
{
struct i915_vma *batch = ERR_PTR(-EINVAL);
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -46,7 +62,8 @@ struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
return batch;
}
-int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd,
+ int cmd_size_in_dw)
{
int err = -EINVAL;
struct i915_vma *batch;
@@ -122,3 +139,85 @@ int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
return err;
}
+
+int intel_pxp_cmd_add_prolog(struct intel_pxp *pxp, u32 *cmd,
+ int session_index)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_prolog = cmd;
+ const int cmd_prolog_size_in_dw = 10;
+
+ if (!cmd)
+ return cmd_prolog_size_in_dw;
+
+ /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_FLUSH_DW - pxp off */
+ *cmd_prolog++ = MI_FLUSH_DW; /* DW0 */
+ *cmd_prolog++ = 0; /* DW1 */
+ *cmd_prolog++ = 0; /* DW2 */
+
+ /* MI_SET_APPID */
+ *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_SESSION_ID(session_index));
+
+ /* MFX_WAIT */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_FLUSH_DW - pxp on */
+ *cmd_prolog++ = (MI_FLUSH_DW | MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE); /* DW0 */
+ *cmd_prolog++ = 0; /* DW1 */
+ *cmd_prolog++ = 0; /* DW2 */
+
+ /* MFX_WAIT */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ increased_size_in_dw = (cmd_prolog - cmd);
+
+ return increased_size_in_dw;
+}
+
+int intel_pxp_cmd_add_epilog(u32 *cmd)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_epilog = cmd;
+ const int cmd_epilog_size_in_dw = 5;
+
+ if (!cmd)
+ return cmd_epilog_size_in_dw;
+
+ /* MI_FLUSH_DW - pxp off */
+ *cmd_epilog++ = MI_FLUSH_DW; /* DW0 */
+ *cmd_epilog++ = 0; /* DW1 */
+ *cmd_epilog++ = 0; /* DW2 */
+
+ /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
+ *cmd_epilog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_BATCH_BUFFER_END */
+ *cmd_epilog++ = MI_BATCH_BUFFER_END;
+
+ increased_size_in_dw = (cmd_epilog - cmd);
+ return increased_size_in_dw;
+}
+
+int intel_pxp_cmd_add_inline_termination(u32 *cmd)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_termin = cmd;
+ const int cmd_termin_size_in_dw = 2;
+
+ if (!cmd)
+ return cmd_termin_size_in_dw;
+
+ /* CRYPTO_KEY_EXCHANGE - session inline termination */
+ *cmd_termin++ = CRYPTO_KEY_EXCHANGE; /* DW0 */
+ *cmd_termin++ = 0; /* DW1 */
+
+ increased_size_in_dw = (cmd_termin - cmd);
+ return increased_size_in_dw;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
index d04463962421..efd26e4987a4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
@@ -9,10 +9,11 @@
#include "gt/intel_gt_buffer_pool.h"
#include "intel_pxp.h"
-struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
- struct intel_context *ce,
- struct intel_gt_buffer_pool_node *pool,
- u32 *cmd_buf, int cmd_size_in_dw);
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd,
+ int cmd_size_in_dw);
+int intel_pxp_cmd_add_prolog(struct intel_pxp *pxp, u32 *cmd,
+ int session_index);
+int intel_pxp_cmd_add_epilog(u32 *cmd);
+int intel_pxp_cmd_add_inline_termination(u32 *cmd);
-int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 08/13] drm/i915/pxp: Enable PXP power management
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (6 preceding siblings ...)
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 07/13] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
@ 2021-01-17 6:45 ` Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 09/13] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
` (4 subsequent siblings)
12 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++
drivers/gpu/drm/i915/i915_drv.c | 4 ++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 ++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 +++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 +
6 files changed, 106 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c931ef5e8a85..eba360ed84d8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -271,6 +271,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_arb.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index c94e8ac884eb..ae0387e419a2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -20,6 +20,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -266,6 +267,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>->uc);
+ intel_pxp_pm_resume(>->pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -300,6 +303,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_pm_prepare_suspend(>->pxp);
intel_uc_suspend(>->uc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e9cb8e9ca172..19db49206e0c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1342,6 +1344,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(&dev_priv->gt.pxp);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index 000000000000..5a1b5ad4f997
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp_context.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+ if (!pxp->ctx.inited)
+ return;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ /* Disable PXP-IOCTLs */
+ pxp->ctx.global_state_in_suspend = true;
+
+ mutex_unlock(&pxp->ctx.mutex);
+}
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+ if (!pxp->ctx.inited)
+ return;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ if (pxp->ctx.global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ pxp->ctx.global_state_attacked = false;
+
+ pxp->ctx.flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(&pxp->ctx.mutex);
+}
+
+int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (!pxp->ctx.inited)
+ return 0;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (pxp->ctx.global_state_in_suspend) {
+ ret = intel_pxp_arb_terminate_session_with_global_terminate(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to terminate the arb session\n");
+ goto end;
+ }
+
+ pxp->ctx.global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(&pxp->ctx.mutex);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
new file mode 100644
index 000000000000..135bfb59aaf7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_PM_H__
+#define __INTEL_PXP_PM_H__
+
+#include "i915_drv.h"
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp);
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp);
+int intel_pxp_pm_resume(struct intel_pxp *pxp);
+#else
+static inline void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+}
+
+static inline void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+}
+
+static inline int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ return 0;
+}
+#endif
+
+#endif /* __INTEL_PXP_PM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index dd7445ff2cb8..e825553db46e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -22,6 +22,7 @@ struct pxp_context {
bool flag_display_hm_surface_keys;
bool global_state_attacked;
+ bool global_state_in_suspend;
};
struct intel_pxp {
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 09/13] drm/i915/pxp: Expose session state for display protection flip
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (7 preceding siblings ...)
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 08/13] drm/i915/pxp: Enable PXP power management Huang, Sean Z
@ 2021-01-17 6:45 ` Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 10/13] mei: pxp: export pavp client to me client bus Huang, Sean Z
` (3 subsequent siblings)
12 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive. And Implement the funciton to set
the protected flag for gem context.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 26 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 18 +++++++++++++
include/uapi/drm/i915_drm.h | 9 +++++++
4 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 1449f54924e0..31137adca788 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -134,6 +134,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index e6dd57ec73f5..373d3e3f3536 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -157,3 +157,29 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
pxp->current_events |= events;
schedule_work(&pxp->irq_work);
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ if (i915->gt.pxp.ctx.inited &&
+ i915->gt.pxp.ctx.flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
+
+int intel_pxp_gem_context_create_param(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+ if (!ctx || !args)
+ return -EINVAL;
+
+ if (args->param == I915_CONTEXT_PARAM_PROTECTED_CONTENT) {
+ if (!intel_pxp_arb_session_is_in_play(&ctx->i915->gt.pxp))
+ return -EINVAL;
+
+ if (args->value)
+ set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 420da2790624..6031f26968ec 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,6 +12,10 @@
#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+struct drm_i915_private;
+struct i915_gem_context;
+struct drm_i915_gem_context_param;
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
@@ -19,6 +23,9 @@ int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp);
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
+int intel_pxp_gem_context_create_param(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args);
#else
static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
{
@@ -41,6 +48,17 @@ static inline void intel_pxp_init(struct intel_pxp *pxp)
static inline void intel_pxp_fini(struct intel_pxp *pxp)
{
}
+
+static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ return false;
+}
+
+static inline int intel_pxp_gem_context_create_param(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+ return 0;
+}
#endif
#endif /* __INTEL_PXP_H__ */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 1987e2ea79a3..00fd1c2bcbb3 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1694,6 +1694,15 @@ struct drm_i915_gem_context_param {
* Default is 16 KiB.
*/
#define I915_CONTEXT_PARAM_RINGSIZE 0xc
+
+/*
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true (1) PAVP content protection is enabled.
+ * When enabled, the context is marked unrecoverable and may
+ * become invalid due to PAVP teardown event or other error.
+ */
+#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
/* Must be kept compact -- no holes and well documented */
__u64 value;
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 10/13] mei: pxp: export pavp client to me client bus
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (8 preceding siblings ...)
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 09/13] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
@ 2021-01-17 6:45 ` Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
` (2 subsequent siblings)
12 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav, Vitaly Lubart
From: Vitaly Lubart <vitaly.lubart@intel.com>
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +++++++++++++++++++++++++++++++++
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index 000000000000..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index 000000000000..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index 000000000000..bd31fce1e6ba
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/uuid.h>
+#include <linux/mei_cl_bus.h>
+#include <linux/component.h>
+#include <drm/drm_connector.h>
+#include <drm/i915_component.h>
+#include <drm/i915_pxp_tee_interface.h>
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .recv = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = &mei_pxp_ops;
+ comp_master->tee_dev = dev;
+ ret = component_bind_all(dev, comp_master);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static void mei_component_master_unbind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+
+ dev_dbg(dev, "%s\n", __func__);
+ component_unbind_all(dev, comp_master);
+}
+
+static const struct component_master_ops mei_component_master_ops = {
+ .bind = mei_component_master_bind,
+ .unbind = mei_component_master_unbind,
+};
+
+/**
+ * mei_pxp_component_match - compare function for matching mei pxp.
+ *
+ * The function checks if the driver is i915, the subcomponent is PXP
+ * and the grand parent of pxp and the parent of i915 are the same
+ * PCH device.
+ *
+ * @dev: master device
+ * @subcomponent: subcomponent to match (I915_COMPONENT_PXP)
+ * @data: compare data (mei pxp device)
+ *
+ * Return:
+ * * 1 - if components match
+ * * 0 - otherwise
+ */
+static int mei_pxp_component_match(struct device *dev, int subcomponent,
+ void *data)
+{
+ struct device *base = data;
+
+ if (subcomponent != I915_COMPONENT_PXP)
+ return 0;
+
+ if (strcmp(dev->driver->name, "i915") == 0) {
+ base = base->parent;
+ if (!base)
+ return 0;
+
+ base = base->parent;
+ dev = dev->parent;
+ return (base && dev && dev == base);
+ }
+
+ return 0;
+}
+
+static int mei_pxp_probe(struct mei_cl_device *cldev,
+ const struct mei_cl_device_id *id)
+{
+ struct i915_pxp_comp_master *comp_master;
+ struct component_match *master_match;
+ int ret;
+
+ ret = mei_cldev_enable(cldev);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret);
+ goto enable_err_exit;
+ }
+
+ comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL);
+ if (!comp_master) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ master_match = NULL;
+ component_match_add_typed(&cldev->dev, &master_match,
+ mei_pxp_component_match, &cldev->dev);
+ if (IS_ERR_OR_NULL(master_match)) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ mei_cldev_set_drvdata(cldev, comp_master);
+ ret = component_master_add_with_match(&cldev->dev,
+ &mei_component_master_ops,
+ master_match);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "Master comp add failed %d\n", ret);
+ goto err_exit;
+ }
+
+ return 0;
+
+err_exit:
+ mei_cldev_set_drvdata(cldev, NULL);
+ kfree(comp_master);
+ mei_cldev_disable(cldev);
+enable_err_exit:
+ return ret;
+}
+
+static int mei_pxp_remove(struct mei_cl_device *cldev)
+{
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+
+ component_master_del(&cldev->dev, &mei_component_master_ops);
+ kfree(comp_master);
+ mei_cldev_set_drvdata(cldev, NULL);
+
+ return mei_cldev_disable(cldev);
+}
+
+/* fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 : PAVP GUID*/
+#define MEI_GUID_PXP GUID_INIT(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \
+ 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1)
+
+static struct mei_cl_device_id mei_pxp_tbl[] = {
+ { .uuid = MEI_GUID_PXP, .version = MEI_CL_VERSION_ANY },
+ { }
+};
+MODULE_DEVICE_TABLE(mei, mei_pxp_tbl);
+
+static struct mei_cl_driver mei_pxp_driver = {
+ .id_table = mei_pxp_tbl,
+ .name = KBUILD_MODNAME,
+ .probe = mei_pxp_probe,
+ .remove = mei_pxp_remove,
+};
+
+module_mei_cl_driver(mei_pxp_driver);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MEI PXP");
diff --git a/drivers/misc/mei/pxp/mei_pxp.h b/drivers/misc/mei/pxp/mei_pxp.h
new file mode 100644
index 000000000000..e7b15373fefd
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef __MEI_PXP_H__
+#define __MEI_PXP_H__
+
+/* me_pxp_status: Enumeration of all PXP Status Codes */
+enum me_pxp_status {
+ ME_PXP_STATUS_SUCCESS = 0x0000,
+
+};
+
+#endif /* __MEI_PXP_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (9 preceding siblings ...)
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 10/13] mei: pxp: export pavp client to me client bus Huang, Sean Z
@ 2021-01-17 6:45 ` Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 12/13] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 13/13] drm/i915/pxp: Add plane decryption support Huang, Sean Z
12 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav, Matthew Auld, Bommu Krishnaiah
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
rev21:
- Fix "Fi.CI.CHECKPATCH" warnings
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 41 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
include/uapi/drm/i915_drm.h | 47 ++++++++++++++++++++++
3 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 45d60e3d98e3..3ad3413c459f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -7,6 +7,7 @@
#include "gem/i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_user_extensions.h"
static int
i915_gem_create(struct drm_file *file,
@@ -91,6 +92,35 @@ i915_gem_dumb_create(struct drm_file *file,
&args->size, &args->handle);
}
+struct create_ext {
+ struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext *ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(&ext.param, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -102,10 +132,19 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ &ext_data);
+ if (ret)
+ return ret;
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 19db49206e0c..0e3d04c50f53 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1731,7 +1731,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 00fd1c2bcbb3..aa232ded9951 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -729,6 +730,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+ * Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ */
+ __u64 size;
+ /**
+ * Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ __u32 pad;
+#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
+#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
+ (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
+ __u64 extensions;
+
+};
+
struct drm_i915_gem_pread {
/** Handle for the object being read. */
__u32 handle;
@@ -1708,6 +1730,31 @@ struct drm_i915_gem_context_param {
__u64 value;
};
+struct drm_i915_gem_object_param {
+ /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
+ __u32 handle;
+
+ /* Data pointer size */
+ __u32 size;
+
+/*
+ * I915_OBJECT_PARAM:
+ *
+ * Select object namespace for the param.
+ */
+#define I915_OBJECT_PARAM (1ull << 32)
+
+ __u64 param;
+
+ /* Data value or pointer */
+ __u64 data;
+};
+
+struct drm_i915_gem_create_ext_setparam {
+ struct i915_user_extension base;
+ struct drm_i915_gem_object_param param;
+};
+
/**
* Context SSEU programming
*
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 12/13] drm/i915/pxp: User interface for Protected buffer
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (10 preceding siblings ...)
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
@ 2021-01-17 6:45 ` Huang, Sean Z
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 13/13] drm/i915/pxp: Add plane decryption support Huang, Sean Z
12 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav, Huang Sean Z, Bommu Krishnaiah, Kondapally Kalyan
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
This api allow user mode to create Protected buffer and context creation.
rev21:
- Only allow set I915_CONTEXT_PARAM_PROTECTED_CONTENT during context
creation (i915_gem_context_create_ioctl), but not allow during
context set param (i915_gem_context_setparam_ioctl)
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
Cc: Huang Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 +++++++++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 5 ++++
drivers/gpu/drm/i915/gem/i915_gem_create.c | 27 ++++++++++++++++---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5 ++++
include/uapi/drm/i915_drm.h | 10 +++++++
5 files changed, 57 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 4d2f40cf237b..0b8e1b3887f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -81,6 +81,8 @@
#include "i915_trace.h"
#include "i915_user_extensions.h"
+#include "pxp/intel_pxp.h"
+
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
static struct i915_global_gem_context {
@@ -2004,8 +2006,12 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
@@ -2052,6 +2058,7 @@ static int create_setparam(struct i915_user_extension __user *ext, void *data)
{
struct drm_i915_gem_context_create_ext_setparam local;
const struct create_ext *arg = data;
+ int ret;
if (copy_from_user(&local, ext, sizeof(local)))
return -EFAULT;
@@ -2059,6 +2066,10 @@ static int create_setparam(struct i915_user_extension __user *ext, void *data)
if (local.param.ctx_id)
return -EINVAL;
+ ret = intel_pxp_gem_context_create_param(arg->ctx, &local.param);
+ if (ret)
+ return ret;
+
return ctx_setparam(arg->fpriv, arg->ctx, &local.param);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index b5c908f3f4f2..173154fdc311 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,11 @@ static inline void i915_gem_context_set_recoverable(struct i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
}
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context *ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 3ad3413c459f..c9b83217a6da 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -5,6 +5,7 @@
#include "gem/i915_gem_ioctls.h"
#include "gem/i915_gem_region.h"
+#include "pxp/intel_pxp.h"
#include "i915_drv.h"
#include "i915_user_extensions.h"
@@ -13,7 +14,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -35,6 +37,8 @@ i915_gem_create(struct drm_file *file,
GEM_BUG_ON(size != obj->base.size);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -89,11 +93,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
mem_type),
- &args->size, &args->handle);
+ &args->size, &args->handle, 0);
}
struct create_ext {
struct drm_i915_private *i915;
+ unsigned long user_flags;
};
static int __create_setparam(struct drm_i915_gem_object_param *args,
@@ -104,6 +109,17 @@ static int __create_setparam(struct drm_i915_gem_object_param *args,
return -EINVAL;
}
+ switch (lower_32_bits(args->param)) {
+ case I915_PARAM_PROTECTED_CONTENT:
+ if (args->size) {
+ return -EINVAL;
+ } else if (args->data) {
+ ext_data->user_flags = args->data;
+ return 0;
+ }
+ break;
+ }
+
return -EINVAL;
}
@@ -145,8 +161,13 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
if (ret)
return ret;
+ if (ext_data.user_flags & I915_BO_PROTECTED) {
+ if (!intel_pxp_gem_object_status(i915))
+ return -EINVAL;
+ }
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
- &args->size, &args->handle);
+ &args->size, &args->handle, ext_data.user_flags);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+ * @user_flags: small set of booleans set by the user
+ */
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index aa232ded9951..17a6e3545570 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1744,6 +1744,16 @@ struct drm_i915_gem_object_param {
*/
#define I915_OBJECT_PARAM (1ull << 32)
+/*
+ * I915_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true (1) buffer contents is expected to be protected by
+ * PAVP encryption and requires decryption for scan out and processing.
+ * Protected buffers can only be used in PAVP protected contexts.
+ * A protected buffer may become invalid as a result of PAVP teardown.
+ */
+#define I915_PARAM_PROTECTED_CONTENT 0x1
+
__u64 param;
/* Data value or pointer */
--
2.17.1
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^ permalink raw reply related [flat|nested] 55+ messages in thread* [Intel-gfx] [RFC-v21 13/13] drm/i915/pxp: Add plane decryption support
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (11 preceding siblings ...)
2021-01-17 6:45 ` [Intel-gfx] [RFC-v21 12/13] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
@ 2021-01-17 6:45 ` Huang, Sean Z
12 siblings, 0 replies; 55+ messages in thread
From: Huang, Sean Z @ 2021-01-17 6:45 UTC (permalink / raw)
To: Intel-gfx; +Cc: Bommu Krishnaiah, kumar.gaurav
From: Anshuman Gupta <anshuman.gupta@intel.com>
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index cf3589fd0ddb..39f8c922ce66 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include <drm/drm_plane_helper.h>
#include <drm/drm_rect.h>
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -768,6 +770,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -804,6 +811,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -814,7 +822,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -890,8 +898,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 97bcecada87f..7a4817054bc8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7208,6 +7208,7 @@ enum {
#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
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^ permalink raw reply related [flat|nested] 55+ messages in thread