* [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support @ 2021-01-08 12:09 Tejas Upadhyay 2021-01-08 16:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9_bc : Add TGP PCH support (rev2) Patchwork ` (2 more replies) 0 siblings, 3 replies; 8+ messages in thread From: Tejas Upadhyay @ 2021-01-08 12:09 UTC (permalink / raw) To: intel-gfx, hariom.pandey, jani.nikula, matthew.d.roper We have TGP PCH support for Tigerlake and Rocketlake. Similarly now TGP PCH can be used with Cometlake CPU. Changes since V3 : - Rebased to top drm-tip commit - dev_priv replaced with i915 for new API - Enable default Port B,C,D detection for TGP && GEN9_BC Changes since V2 : - IS_COMETLAKE replaced with IS_GEN9_BC - VBT ddc pin remapping added - Added dedicated HPD pin and DDC pin handling API Changes since V1 : - Matched HPD Pin mapping for PORT C and PORT D of CML CPU. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 9 +++++++++ drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++++-- drivers/gpu/drm/i915/display/intel_display.c | 9 ++++++++- drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/intel_pch.c | 3 ++- 5 files changed, 44 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 987cf509337f..730b7f45e5d4 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1630,6 +1630,12 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = { [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, }; +static const u8 gen9bc_tgp_ddc_pin_map[] = { + [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, + [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP, + [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP, +}; + static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) { const u8 *ddc_pin_map; @@ -1640,6 +1646,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) { ddc_pin_map = rkl_pch_tgp_ddc_pin_map; n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); + } else if (HAS_PCH_TGP(dev_priv) && IS_GEN9_BC(dev_priv)) { + ddc_pin_map = gen9bc_tgp_ddc_pin_map; + n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { ddc_pin_map = icp_ddc_pin_map; n_entries = ARRAY_SIZE(icp_ddc_pin_map); diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3df6913369bc..13f1268e2cff 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -5337,7 +5337,9 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) { - if (port >= PORT_TC1) + if (IS_GEN9_BC(dev_priv) && port >= PORT_C) + return HPD_PORT_TC1 + port - PORT_C; + else if (port >= PORT_TC1) return HPD_PORT_TC1 + port - PORT_TC1; else return HPD_PORT_A + port - PORT_A; @@ -5493,7 +5495,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); else if (IS_ROCKETLAKE(dev_priv)) encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); - else if (INTEL_GEN(dev_priv) >= 12) + else if (INTEL_GEN(dev_priv) >= 12 || (IS_GEN9_BC(dev_priv) && + HAS_PCH_TGP(dev_priv))) encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); else if (IS_JSL_EHL(dev_priv)) encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0189d379a55e..81c93c49ddef 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -16212,7 +16212,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP * register */ - found = intel_de_read(dev_priv, SFUSE_STRAP); + if (HAS_PCH_TGP(dev_priv)) { + /* W/A due to lack of STRAP config on TGP PCH*/ + found = (SFUSE_STRAP_DDIB_DETECTED | + SFUSE_STRAP_DDIC_DETECTED | + SFUSE_STRAP_DDID_DETECTED); + } else { + found = intel_de_read(dev_priv, SFUSE_STRAP); + } if (found & SFUSE_STRAP_DDIB_DETECTED) intel_ddi_init(dev_priv, PORT_B); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index c5959590562b..aa3b4a659f96 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3130,6 +3130,24 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) return GMBUS_PIN_1_BXT + phy; } +static u8 gen9bc_port_to_ddc_pin(struct drm_i915_private *i915, enum port port) +{ + enum phy phy = intel_port_to_phy(i915, port); + + drm_WARN_ON(&i915->drm, port == PORT_A); + + /* + * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, + * final two outputs use type-c pins, even though they're actually + * combo outputs. With CMP, the traditional DDI A-D pins are used for + * all outputs. + */ + if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) + return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; + + return GMBUS_PIN_1_BXT + phy; +} + static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) { return intel_port_to_phy(dev_priv, port) + 1; @@ -3176,6 +3194,8 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); else if (IS_ROCKETLAKE(dev_priv)) ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); + else if (IS_GEN9_BC(dev_priv) && HAS_PCH_TGP(dev_priv)) + ddc_pin = gen9bc_port_to_ddc_pin(dev_priv, port); else if (HAS_PCH_MCC(dev_priv)) ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index f31c0dabd0cc..c1bc2d032360 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -121,7 +121,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) case INTEL_PCH_TGP2_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n"); drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) && - !IS_ROCKETLAKE(dev_priv)); + !IS_ROCKETLAKE(dev_priv) && + !IS_GEN9_BC(dev_priv)); return PCH_TGP; case INTEL_PCH_JSP_DEVICE_ID_TYPE: case INTEL_PCH_JSP2_DEVICE_ID_TYPE: -- 2.30.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9_bc : Add TGP PCH support (rev2) 2021-01-08 12:09 [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support Tejas Upadhyay @ 2021-01-08 16:21 ` Patchwork 2021-01-08 20:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-01-12 0:21 ` [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support Rodrigo Vivi 2 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2021-01-08 16:21 UTC (permalink / raw) To: Tejas Upadhyay; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 2364 bytes --] == Series Details == Series: drm/i915/gen9_bc : Add TGP PCH support (rev2) URL : https://patchwork.freedesktop.org/series/85502/ State : success == Summary == CI Bug Log - changes from CI_DRM_9566 -> Patchwork_19291 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/index.html Known issues ------------ Here are the changes found in Patchwork_19291 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html #### Possible fixes #### * igt@gem_flink_basic@bad-flink: - fi-tgl-y: [DMESG-WARN][3] ([i915#402]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/fi-tgl-y/igt@gem_flink_basic@bad-flink.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/fi-tgl-y/igt@gem_flink_basic@bad-flink.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 37) ------------------------------ Missing (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes ------------- * Linux: CI_DRM_9566 -> Patchwork_19291 CI-20190529: 20190529 CI_DRM_9566: 43ca049026a4c8808645c7f21cb0fc34a337c612 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5951: fec3b9c7d88357144f0d7a1447b9316a1c81da1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19291: 4167cb3a91fe63a8b79e9ad0b5b7adb9f33a0e26 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4167cb3a91fe drm/i915/gen9_bc : Add TGP PCH support == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/index.html [-- Attachment #1.2: Type: text/html, Size: 2992 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gen9_bc : Add TGP PCH support (rev2) 2021-01-08 12:09 [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support Tejas Upadhyay 2021-01-08 16:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9_bc : Add TGP PCH support (rev2) Patchwork @ 2021-01-08 20:24 ` Patchwork 2021-01-12 0:21 ` [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support Rodrigo Vivi 2 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2021-01-08 20:24 UTC (permalink / raw) To: Tejas Upadhyay; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 20112 bytes --] == Series Details == Series: drm/i915/gen9_bc : Add TGP PCH support (rev2) URL : https://patchwork.freedesktop.org/series/85502/ State : success == Summary == CI Bug Log - changes from CI_DRM_9566_full -> Patchwork_19291_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_19291_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@feature_discovery@display-2x: - shard-tglb: NOTRUN -> [SKIP][1] ([i915#1839]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@feature_discovery@display-2x.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-skl: [PASS][2] -> [INCOMPLETE][3] ([i915#198]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl4/igt@gem_ctx_isolation@preservation-s3@vcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html * igt@gem_ctx_persistence@engines-hang: - shard-hsw: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-hsw4/igt@gem_ctx_persistence@engines-hang.html * igt@gem_eio@in-flight-contexts-immediate: - shard-hsw: [PASS][5] -> [INCOMPLETE][6] ([i915#2870]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-hsw7/igt@gem_eio@in-flight-contexts-immediate.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-hsw7/igt@gem_eio@in-flight-contexts-immediate.html * igt@gem_pread@exhaustion: - shard-hsw: NOTRUN -> [WARN][7] ([i915#2658]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-hsw4/igt@gem_pread@exhaustion.html * igt@gem_userptr_blits@process-exit-mmap@wc: - shard-hsw: NOTRUN -> [SKIP][8] ([fdo#109271]) +195 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-hsw4/igt@gem_userptr_blits@process-exit-mmap@wc.html * igt@gem_workarounds@suspend-resume: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#146] / [i915#198]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl6/igt@gem_workarounds@suspend-resume.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl1/igt@gem_workarounds@suspend-resume.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1436] / [i915#716]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl9/igt@gen9_exec_parse@allowed-single.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl10/igt@gen9_exec_parse@allowed-single.html * igt@gen9_exec_parse@bb-start-cmd: - shard-tglb: NOTRUN -> [SKIP][13] ([fdo#112306]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@gen9_exec_parse@bb-start-cmd.html * igt@i915_module_load@reload-with-fault-injection: - shard-snb: [PASS][14] -> [INCOMPLETE][15] ([i915#2880]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-snb7/igt@i915_module_load@reload-with-fault-injection.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl10/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_selftest@live@gt_lrc: - shard-tglb: NOTRUN -> [DMESG-FAIL][17] ([i915#2373]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@gt_pm: - shard-tglb: NOTRUN -> [DMESG-FAIL][18] ([i915#1759] / [i915#2291]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@i915_selftest@live@gt_pm.html * igt@kms_ccs@pipe-c-missing-ccs-buffer: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111304]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl10/igt@kms_ccs@pipe-c-missing-ccs-buffer.html * igt@kms_color_chamelium@pipe-b-ctm-0-75: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#109284] / [fdo#111827]) +2 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@kms_color_chamelium@pipe-b-ctm-0-75.html * igt@kms_color_chamelium@pipe-d-gamma: - shard-hsw: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +15 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-hsw4/igt@kms_color_chamelium@pipe-d-gamma.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen: - shard-skl: NOTRUN -> [FAIL][22] ([i915#54]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-random: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#54]) +10 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html * igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding: - shard-tglb: NOTRUN -> [SKIP][25] ([fdo#109279]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html - shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271]) +9 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl7/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: - shard-tglb: NOTRUN -> [SKIP][27] ([fdo#111825]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][28] -> [FAIL][29] ([i915#2346]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-tglb: [PASS][30] -> [FAIL][31] ([i915#2598]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [PASS][32] -> [FAIL][33] ([i915#79]) +1 similar issue [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1: - shard-skl: [PASS][34] -> [FAIL][35] ([i915#2122]) +2 similar issues [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt: - shard-skl: NOTRUN -> [DMESG-WARN][36] ([i915#1982]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][37] -> [FAIL][38] ([i915#1188]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-iclb3/igt@kms_psr@psr2_cursor_plane_move.html * igt@kms_writeback@writeback-fb-id: - shard-tglb: NOTRUN -> [SKIP][41] ([i915#2437]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@kms_writeback@writeback-fb-id.html * igt@runner@aborted: - shard-hsw: NOTRUN -> [FAIL][42] ([i915#1436] / [i915#2505]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-hsw7/igt@runner@aborted.html #### Possible fixes #### * {igt@gem_exec_fair@basic-none-vip@rcs0}: - shard-kbl: [FAIL][43] ([i915#2842]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-kbl1/igt@gem_exec_fair@basic-none-vip@rcs0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-kbl1/igt@gem_exec_fair@basic-none-vip@rcs0.html * {igt@gem_exec_schedule@u-fairslice@rcs0}: - shard-kbl: [DMESG-WARN][45] ([i915#1610] / [i915#2803]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-kbl1/igt@gem_exec_schedule@u-fairslice@rcs0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-kbl6/igt@gem_exec_schedule@u-fairslice@rcs0.html * igt@gem_exec_whisper@basic-contexts-priority: - shard-glk: [DMESG-WARN][47] ([i915#118] / [i915#95]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-glk5/igt@gem_exec_whisper@basic-contexts-priority.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-glk4/igt@gem_exec_whisper@basic-contexts-priority.html * {igt@gem_vm_create@destroy-race}: - shard-tglb: [TIMEOUT][49] ([i915#2795]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-tglb8/igt@gem_vm_create@destroy-race.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@gem_vm_create@destroy-race.html * igt@gem_workarounds@suspend-resume-context: - shard-tglb: [INCOMPLETE][51] ([i915#2295] / [i915#456]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-tglb2/igt@gem_workarounds@suspend-resume-context.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb5/igt@gem_workarounds@suspend-resume-context.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [FAIL][53] ([i915#2521]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl5/igt@kms_async_flips@alternate-sync-async-flip.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen: - shard-skl: [FAIL][55] ([i915#54]) -> [PASS][56] +5 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-tglb: [FAIL][57] ([i915#2598]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-tglb7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank@b-edp1: - shard-skl: [FAIL][59] ([i915#2122]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html * igt@kms_hdr@bpc-switch: - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl1/igt@kms_hdr@bpc-switch.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl5/igt@kms_hdr@bpc-switch.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [FAIL][63] ([fdo#108145] / [i915#265]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-kbl: [DMESG-WARN][65] ([i915#165] / [i915#180] / [i915#2621] / [i915#78]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-y.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-kbl4/igt@kms_plane_lowres@pipe-a-tiling-y.html * igt@kms_psr2_su@page_flip: - shard-iclb: [SKIP][67] ([fdo#109642] / [fdo#111068]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-iclb8/igt@kms_psr2_su@page_flip.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-iclb2/igt@kms_psr2_su@page_flip.html #### Warnings #### * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][69] ([i915#2681] / [i915#2684]) -> [WARN][70] ([i915#2684]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][71] ([i915#1804] / [i915#2684]) -> [FAIL][72] ([i915#2680]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html * igt@kms_content_protection@srm: - shard-apl: [SKIP][73] ([fdo#109271]) -> [TIMEOUT][74] ([i915#1319]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-apl1/igt@kms_content_protection@srm.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-apl7/igt@kms_content_protection@srm.html * igt@runner@aborted: - shard-skl: ([FAIL][75], [FAIL][76]) ([i915#2029] / [i915#2295]) -> [FAIL][77] ([i915#1436] / [i915#2295]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl8/igt@runner@aborted.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9566/shard-skl4/igt@runner@aborted.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/shard-skl10/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112306]: https://bugs.freedesktop.org/show_bug.cgi?id=112306 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598 [i915#2621]: https://gitlab.freedesktop.org/drm/intel/issues/2621 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 [i915#2680]: https://gitlab.freedesktop.org/drm/intel/issues/2680 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#2795]: https://gitlab.freedesktop.org/drm/intel/issues/2795 [i915#2803]: https://gitlab.freedesktop.org/drm/intel/issues/2803 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2870]: https://gitlab.freedesktop.org/drm/intel/issues/2870 [i915#2880]: https://gitlab.freedesktop.org/drm/intel/issues/2880 [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_9566 -> Patchwork_19291 CI-20190529: 20190529 CI_DRM_9566: 43ca049026a4c8808645c7f21cb0fc34a337c612 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5951: fec3b9c7d88357144f0d7a1447b9316a1c81da1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19291: 4167cb3a91fe63a8b79e9ad0b5b7adb9f33a0e26 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19291/index.html [-- Attachment #1.2: Type: text/html, Size: 23040 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support 2021-01-08 12:09 [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support Tejas Upadhyay 2021-01-08 16:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9_bc : Add TGP PCH support (rev2) Patchwork 2021-01-08 20:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork @ 2021-01-12 0:21 ` Rodrigo Vivi 2021-01-12 1:30 ` Matt Roper 2 siblings, 1 reply; 8+ messages in thread From: Rodrigo Vivi @ 2021-01-12 0:21 UTC (permalink / raw) To: Tejas Upadhyay; +Cc: intel-gfx, hariom.pandey On Fri, Jan 08, 2021 at 05:39:22PM +0530, Tejas Upadhyay wrote: > We have TGP PCH support for Tigerlake and Rocketlake. Similarly > now TGP PCH can be used with Cometlake CPU. > > Changes since V3 : > - Rebased to top drm-tip commit > - dev_priv replaced with i915 for new API > - Enable default Port B,C,D detection for TGP && GEN9_BC > Changes since V2 : > - IS_COMETLAKE replaced with IS_GEN9_BC > - VBT ddc pin remapping added > - Added dedicated HPD pin and DDC pin handling API > Changes since V1 : > - Matched HPD Pin mapping for PORT C and PORT D of CML CPU. > > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> > --- > drivers/gpu/drm/i915/display/intel_bios.c | 9 +++++++++ > drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++++-- > drivers/gpu/drm/i915/display/intel_display.c | 9 ++++++++- > drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++++ > drivers/gpu/drm/i915/intel_pch.c | 3 ++- > 5 files changed, 44 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c > index 987cf509337f..730b7f45e5d4 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -1630,6 +1630,12 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = { > [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, > }; > > +static const u8 gen9bc_tgp_ddc_pin_map[] = { > + [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, > + [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP, > + [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP, > +}; Could you please point out the spec you are using here? VBT's spec at BSpec - at Block 2 I can see the TGP table is same as ICP. So I'm kind of confused now. > + > static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) > { > const u8 *ddc_pin_map; > @@ -1640,6 +1646,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) > } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) { > ddc_pin_map = rkl_pch_tgp_ddc_pin_map; > n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); > + } else if (HAS_PCH_TGP(dev_priv) && IS_GEN9_BC(dev_priv)) { > + ddc_pin_map = gen9bc_tgp_ddc_pin_map; > + n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); > } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { > ddc_pin_map = icp_ddc_pin_map; > n_entries = ARRAY_SIZE(icp_ddc_pin_map); > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 3df6913369bc..13f1268e2cff 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -5337,7 +5337,9 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, > static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, > enum port port) > { > - if (port >= PORT_TC1) > + if (IS_GEN9_BC(dev_priv) && port >= PORT_C) gen9 in tgl function?! please, no! > + return HPD_PORT_TC1 + port - PORT_C; > + else if (port >= PORT_TC1) > return HPD_PORT_TC1 + port - PORT_TC1; > else > return HPD_PORT_A + port - PORT_A; > @@ -5493,7 +5495,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); > else if (IS_ROCKETLAKE(dev_priv)) > encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); > - else if (INTEL_GEN(dev_priv) >= 12) > + else if (INTEL_GEN(dev_priv) >= 12 || (IS_GEN9_BC(dev_priv) && > + HAS_PCH_TGP(dev_priv))) Here's another aspect that I don't like in this code. It mixes the gfx gen with the PCH in many places. Something is not right... > encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); > else if (IS_JSL_EHL(dev_priv)) > encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 0189d379a55e..81c93c49ddef 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -16212,7 +16212,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > > /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP > * register */ > - found = intel_de_read(dev_priv, SFUSE_STRAP); > + if (HAS_PCH_TGP(dev_priv)) { > + /* W/A due to lack of STRAP config on TGP PCH*/ > + found = (SFUSE_STRAP_DDIB_DETECTED | > + SFUSE_STRAP_DDIC_DETECTED | > + SFUSE_STRAP_DDID_DETECTED); > + } else { > + found = intel_de_read(dev_priv, SFUSE_STRAP); > + } oh, do we still need this :( > > if (found & SFUSE_STRAP_DDIB_DETECTED) > intel_ddi_init(dev_priv, PORT_B); > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c > index c5959590562b..aa3b4a659f96 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > @@ -3130,6 +3130,24 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) > return GMBUS_PIN_1_BXT + phy; > } > > +static u8 gen9bc_port_to_ddc_pin(struct drm_i915_private *i915, enum port port) > +{ > + enum phy phy = intel_port_to_phy(i915, port); > + > + drm_WARN_ON(&i915->drm, port == PORT_A); > + > + /* > + * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, > + * final two outputs use type-c pins, even though they're actually > + * combo outputs. With CMP, the traditional DDI A-D pins are used for > + * all outputs. > + */ > + if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) > + return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; > + > + return GMBUS_PIN_1_BXT + phy; > +} > + > static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) > { > return intel_port_to_phy(dev_priv, port) + 1; > @@ -3176,6 +3194,8 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) > ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); > else if (IS_ROCKETLAKE(dev_priv)) > ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); > + else if (IS_GEN9_BC(dev_priv) && HAS_PCH_TGP(dev_priv)) > + ddc_pin = gen9bc_port_to_ddc_pin(dev_priv, port); > else if (HAS_PCH_MCC(dev_priv)) > ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); > else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) > diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c > index f31c0dabd0cc..c1bc2d032360 100644 > --- a/drivers/gpu/drm/i915/intel_pch.c > +++ b/drivers/gpu/drm/i915/intel_pch.c > @@ -121,7 +121,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) > case INTEL_PCH_TGP2_DEVICE_ID_TYPE: > drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n"); > drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) && > - !IS_ROCKETLAKE(dev_priv)); > + !IS_ROCKETLAKE(dev_priv) && > + !IS_GEN9_BC(dev_priv)); > return PCH_TGP; > case INTEL_PCH_JSP_DEVICE_ID_TYPE: > case INTEL_PCH_JSP2_DEVICE_ID_TYPE: > -- > 2.30.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support 2021-01-12 0:21 ` [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support Rodrigo Vivi @ 2021-01-12 1:30 ` Matt Roper 2021-01-12 3:35 ` Lucas De Marchi 2021-01-19 15:52 ` Rodrigo Vivi 0 siblings, 2 replies; 8+ messages in thread From: Matt Roper @ 2021-01-12 1:30 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx, hariom.pandey On Mon, Jan 11, 2021 at 07:21:55PM -0500, Rodrigo Vivi wrote: > On Fri, Jan 08, 2021 at 05:39:22PM +0530, Tejas Upadhyay wrote: > > We have TGP PCH support for Tigerlake and Rocketlake. Similarly > > now TGP PCH can be used with Cometlake CPU. > > > > Changes since V3 : > > - Rebased to top drm-tip commit > > - dev_priv replaced with i915 for new API > > - Enable default Port B,C,D detection for TGP && GEN9_BC > > Changes since V2 : > > - IS_COMETLAKE replaced with IS_GEN9_BC > > - VBT ddc pin remapping added > > - Added dedicated HPD pin and DDC pin handling API > > Changes since V1 : > > - Matched HPD Pin mapping for PORT C and PORT D of CML CPU. > > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_bios.c | 9 +++++++++ > > drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++++-- > > drivers/gpu/drm/i915/display/intel_display.c | 9 ++++++++- > > drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++++ > > drivers/gpu/drm/i915/intel_pch.c | 3 ++- > > 5 files changed, 44 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c > > index 987cf509337f..730b7f45e5d4 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bios.c > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > > @@ -1630,6 +1630,12 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = { > > [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, > > }; > > > > +static const u8 gen9bc_tgp_ddc_pin_map[] = { > > + [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, > > + [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP, > > + [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP, > > +}; > > Could you please point out the spec you are using here? > > VBT's spec at BSpec - at Block 2 > I can see the TGP table is same as ICP. > > So I'm kind of confused now. It's a weird place to document it, but bspec 49181 has a compatibility section that describes how to map the TGP pins when paired with a gen9bc CPU. > > > + > > static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) > > { > > const u8 *ddc_pin_map; > > @@ -1640,6 +1646,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) > > } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) { > > ddc_pin_map = rkl_pch_tgp_ddc_pin_map; > > n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); > > + } else if (HAS_PCH_TGP(dev_priv) && IS_GEN9_BC(dev_priv)) { > > + ddc_pin_map = gen9bc_tgp_ddc_pin_map; > > + n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); > > } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { > > ddc_pin_map = icp_ddc_pin_map; > > n_entries = ARRAY_SIZE(icp_ddc_pin_map); > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 3df6913369bc..13f1268e2cff 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -5337,7 +5337,9 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, > > static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, > > enum port port) > > { > > - if (port >= PORT_TC1) > > + if (IS_GEN9_BC(dev_priv) && port >= PORT_C) > > gen9 in tgl function?! > please, no! We should probably rename this function to tgp since it ultimately gets called on every possible TGP platform (TGL+TGP, RKL+TGP, gen9+TGP). If it weren't for RKL+CMP, I'd say that all these functions should just be named after the PCH, but I guess the TC ports on RKL+CMP break the pattern. I think the real plan once we get some free time is to kill off a bunch of these output-based functions and define DDI/port/phy/VBT/HPD/DDC mapping for outputs declaratively in a table since all the special cases we're running into on recent platforms are turning the logic-based approach into a mess. > > > + return HPD_PORT_TC1 + port - PORT_C; > > + else if (port >= PORT_TC1) > > return HPD_PORT_TC1 + port - PORT_TC1; > > else > > return HPD_PORT_A + port - PORT_A; > > @@ -5493,7 +5495,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > > encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); > > else if (IS_ROCKETLAKE(dev_priv)) > > encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); > > - else if (INTEL_GEN(dev_priv) >= 12) > > + else if (INTEL_GEN(dev_priv) >= 12 || (IS_GEN9_BC(dev_priv) && > > + HAS_PCH_TGP(dev_priv))) > > Here's another aspect that I don't like in this code. > It mixes the gfx gen with the PCH in many places. > > Something is not right... > > > encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); > > else if (IS_JSL_EHL(dev_priv)) > > encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index 0189d379a55e..81c93c49ddef 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -16212,7 +16212,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > > > > /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP > > * register */ > > - found = intel_de_read(dev_priv, SFUSE_STRAP); > > + if (HAS_PCH_TGP(dev_priv)) { > > + /* W/A due to lack of STRAP config on TGP PCH*/ > > + found = (SFUSE_STRAP_DDIB_DETECTED | > > + SFUSE_STRAP_DDIC_DETECTED | > > + SFUSE_STRAP_DDID_DETECTED); > > + } else { > > + found = intel_de_read(dev_priv, SFUSE_STRAP); > > + } > > oh, do we still need this :( We've always needed it on gen9 (unless we're willing to rely solely on the VBT like we do for more recent platforms). But when a gen9 platform is paired with a TGP PCH, the strap bits won't be there (since this is a south display register), so we have no choice but to rely on VBT. Matt > > > > > if (found & SFUSE_STRAP_DDIB_DETECTED) > > intel_ddi_init(dev_priv, PORT_B); > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c > > index c5959590562b..aa3b4a659f96 100644 > > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > > @@ -3130,6 +3130,24 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) > > return GMBUS_PIN_1_BXT + phy; > > } > > > > +static u8 gen9bc_port_to_ddc_pin(struct drm_i915_private *i915, enum port port) > > +{ > > + enum phy phy = intel_port_to_phy(i915, port); > > + > > + drm_WARN_ON(&i915->drm, port == PORT_A); > > + > > + /* > > + * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, > > + * final two outputs use type-c pins, even though they're actually > > + * combo outputs. With CMP, the traditional DDI A-D pins are used for > > + * all outputs. > > + */ > > + if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) > > + return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; > > + > > + return GMBUS_PIN_1_BXT + phy; > > +} > > + > > static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) > > { > > return intel_port_to_phy(dev_priv, port) + 1; > > @@ -3176,6 +3194,8 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) > > ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); > > else if (IS_ROCKETLAKE(dev_priv)) > > ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); > > + else if (IS_GEN9_BC(dev_priv) && HAS_PCH_TGP(dev_priv)) > > + ddc_pin = gen9bc_port_to_ddc_pin(dev_priv, port); > > else if (HAS_PCH_MCC(dev_priv)) > > ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); > > else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) > > diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c > > index f31c0dabd0cc..c1bc2d032360 100644 > > --- a/drivers/gpu/drm/i915/intel_pch.c > > +++ b/drivers/gpu/drm/i915/intel_pch.c > > @@ -121,7 +121,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) > > case INTEL_PCH_TGP2_DEVICE_ID_TYPE: > > drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n"); > > drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) && > > - !IS_ROCKETLAKE(dev_priv)); > > + !IS_ROCKETLAKE(dev_priv) && > > + !IS_GEN9_BC(dev_priv)); > > return PCH_TGP; > > case INTEL_PCH_JSP_DEVICE_ID_TYPE: > > case INTEL_PCH_JSP2_DEVICE_ID_TYPE: > > -- > > 2.30.0 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support 2021-01-12 1:30 ` Matt Roper @ 2021-01-12 3:35 ` Lucas De Marchi 2021-01-19 15:52 ` Rodrigo Vivi 1 sibling, 0 replies; 8+ messages in thread From: Lucas De Marchi @ 2021-01-12 3:35 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx, hariom.pandey On Mon, Jan 11, 2021 at 05:30:00PM -0800, Matt Roper wrote: >On Mon, Jan 11, 2021 at 07:21:55PM -0500, Rodrigo Vivi wrote: >> On Fri, Jan 08, 2021 at 05:39:22PM +0530, Tejas Upadhyay wrote: >> > We have TGP PCH support for Tigerlake and Rocketlake. Similarly >> > now TGP PCH can be used with Cometlake CPU. >> > >> > Changes since V3 : >> > - Rebased to top drm-tip commit >> > - dev_priv replaced with i915 for new API >> > - Enable default Port B,C,D detection for TGP && GEN9_BC >> > Changes since V2 : >> > - IS_COMETLAKE replaced with IS_GEN9_BC >> > - VBT ddc pin remapping added >> > - Added dedicated HPD pin and DDC pin handling API >> > Changes since V1 : >> > - Matched HPD Pin mapping for PORT C and PORT D of CML CPU. >> > >> > Cc: Matt Roper <matthew.d.roper@intel.com> >> > Cc: Jani Nikula <jani.nikula@linux.intel.com> >> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> >> > --- >> > drivers/gpu/drm/i915/display/intel_bios.c | 9 +++++++++ >> > drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++++-- >> > drivers/gpu/drm/i915/display/intel_display.c | 9 ++++++++- >> > drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++++ >> > drivers/gpu/drm/i915/intel_pch.c | 3 ++- >> > 5 files changed, 44 insertions(+), 4 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c >> > index 987cf509337f..730b7f45e5d4 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_bios.c >> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c >> > @@ -1630,6 +1630,12 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = { >> > [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, >> > }; >> > >> > +static const u8 gen9bc_tgp_ddc_pin_map[] = { >> > + [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, >> > + [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP, >> > + [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP, >> > +}; >> >> Could you please point out the spec you are using here? >> >> VBT's spec at BSpec - at Block 2 >> I can see the TGP table is same as ICP. >> >> So I'm kind of confused now. > >It's a weird place to document it, but bspec 49181 has a compatibility >section that describes how to map the TGP pins when paired with a gen9bc >CPU. > >> >> > + >> > static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) >> > { >> > const u8 *ddc_pin_map; >> > @@ -1640,6 +1646,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) >> > } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) { >> > ddc_pin_map = rkl_pch_tgp_ddc_pin_map; >> > n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); >> > + } else if (HAS_PCH_TGP(dev_priv) && IS_GEN9_BC(dev_priv)) { >> > + ddc_pin_map = gen9bc_tgp_ddc_pin_map; >> > + n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); >> > } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { >> > ddc_pin_map = icp_ddc_pin_map; >> > n_entries = ARRAY_SIZE(icp_ddc_pin_map); >> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c >> > index 3df6913369bc..13f1268e2cff 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c >> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c >> > @@ -5337,7 +5337,9 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, >> > static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, >> > enum port port) >> > { >> > - if (port >= PORT_TC1) >> > + if (IS_GEN9_BC(dev_priv) && port >= PORT_C) >> >> gen9 in tgl function?! >> please, no! > >We should probably rename this function to tgp since it ultimately gets >called on every possible TGP platform (TGL+TGP, RKL+TGP, gen9+TGP). If >it weren't for RKL+CMP, I'd say that all these functions should just be >named after the PCH, but I guess the TC ports on RKL+CMP break the >pattern. > >I think the real plan once we get some free time is to kill off a bunch >of these output-based functions and define DDI/port/phy/VBT/HPD/DDC >mapping for outputs declaratively in a table since all the special cases >we're running into on recent platforms are turning the logic-based >approach into a mess. sounds like the direction I wanted to go with https://patchwork.freedesktop.org/patch/346524/?series=71330&rev=1 there was ddi/por/phy/vbt in a single table, and we could add the remaining ones. Lucas De Marchi > >> >> > + return HPD_PORT_TC1 + port - PORT_C; >> > + else if (port >= PORT_TC1) >> > return HPD_PORT_TC1 + port - PORT_TC1; >> > else >> > return HPD_PORT_A + port - PORT_A; >> > @@ -5493,7 +5495,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) >> > encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); >> > else if (IS_ROCKETLAKE(dev_priv)) >> > encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); >> > - else if (INTEL_GEN(dev_priv) >= 12) >> > + else if (INTEL_GEN(dev_priv) >= 12 || (IS_GEN9_BC(dev_priv) && >> > + HAS_PCH_TGP(dev_priv))) >> >> Here's another aspect that I don't like in this code. >> It mixes the gfx gen with the PCH in many places. >> >> Something is not right... >> >> > encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); >> > else if (IS_JSL_EHL(dev_priv)) >> > encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); >> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c >> > index 0189d379a55e..81c93c49ddef 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_display.c >> > +++ b/drivers/gpu/drm/i915/display/intel_display.c >> > @@ -16212,7 +16212,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) >> > >> > /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP >> > * register */ >> > - found = intel_de_read(dev_priv, SFUSE_STRAP); >> > + if (HAS_PCH_TGP(dev_priv)) { >> > + /* W/A due to lack of STRAP config on TGP PCH*/ >> > + found = (SFUSE_STRAP_DDIB_DETECTED | >> > + SFUSE_STRAP_DDIC_DETECTED | >> > + SFUSE_STRAP_DDID_DETECTED); >> > + } else { >> > + found = intel_de_read(dev_priv, SFUSE_STRAP); >> > + } >> >> oh, do we still need this :( > >We've always needed it on gen9 (unless we're willing to rely solely on >the VBT like we do for more recent platforms). But when a gen9 platform >is paired with a TGP PCH, the strap bits won't be there (since this is a >south display register), so we have no choice but to rely on VBT. > > >Matt > >> >> > >> > if (found & SFUSE_STRAP_DDIB_DETECTED) >> > intel_ddi_init(dev_priv, PORT_B); >> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c >> > index c5959590562b..aa3b4a659f96 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c >> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c >> > @@ -3130,6 +3130,24 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) >> > return GMBUS_PIN_1_BXT + phy; >> > } >> > >> > +static u8 gen9bc_port_to_ddc_pin(struct drm_i915_private *i915, enum port port) >> > +{ >> > + enum phy phy = intel_port_to_phy(i915, port); >> > + >> > + drm_WARN_ON(&i915->drm, port == PORT_A); >> > + >> > + /* >> > + * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, >> > + * final two outputs use type-c pins, even though they're actually >> > + * combo outputs. With CMP, the traditional DDI A-D pins are used for >> > + * all outputs. >> > + */ >> > + if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) >> > + return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; >> > + >> > + return GMBUS_PIN_1_BXT + phy; >> > +} >> > + >> > static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) >> > { >> > return intel_port_to_phy(dev_priv, port) + 1; >> > @@ -3176,6 +3194,8 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) >> > ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); >> > else if (IS_ROCKETLAKE(dev_priv)) >> > ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); >> > + else if (IS_GEN9_BC(dev_priv) && HAS_PCH_TGP(dev_priv)) >> > + ddc_pin = gen9bc_port_to_ddc_pin(dev_priv, port); >> > else if (HAS_PCH_MCC(dev_priv)) >> > ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); >> > else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) >> > diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c >> > index f31c0dabd0cc..c1bc2d032360 100644 >> > --- a/drivers/gpu/drm/i915/intel_pch.c >> > +++ b/drivers/gpu/drm/i915/intel_pch.c >> > @@ -121,7 +121,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) >> > case INTEL_PCH_TGP2_DEVICE_ID_TYPE: >> > drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n"); >> > drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) && >> > - !IS_ROCKETLAKE(dev_priv)); >> > + !IS_ROCKETLAKE(dev_priv) && >> > + !IS_GEN9_BC(dev_priv)); >> > return PCH_TGP; >> > case INTEL_PCH_JSP_DEVICE_ID_TYPE: >> > case INTEL_PCH_JSP2_DEVICE_ID_TYPE: >> > -- >> > 2.30.0 >> > >> > _______________________________________________ >> > Intel-gfx mailing list >> > Intel-gfx@lists.freedesktop.org >> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > >-- >Matt Roper >Graphics Software Engineer >VTT-OSGC Platform Enablement >Intel Corporation >(916) 356-2795 >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support 2021-01-12 1:30 ` Matt Roper 2021-01-12 3:35 ` Lucas De Marchi @ 2021-01-19 15:52 ` Rodrigo Vivi 2021-01-19 16:13 ` Ville Syrjälä 1 sibling, 1 reply; 8+ messages in thread From: Rodrigo Vivi @ 2021-01-19 15:52 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx, hariom.pandey On Mon, Jan 11, 2021 at 05:30:00PM -0800, Matt Roper wrote: > On Mon, Jan 11, 2021 at 07:21:55PM -0500, Rodrigo Vivi wrote: > > On Fri, Jan 08, 2021 at 05:39:22PM +0530, Tejas Upadhyay wrote: > > > We have TGP PCH support for Tigerlake and Rocketlake. Similarly > > > now TGP PCH can be used with Cometlake CPU. > > > > > > Changes since V3 : > > > - Rebased to top drm-tip commit > > > - dev_priv replaced with i915 for new API > > > - Enable default Port B,C,D detection for TGP && GEN9_BC > > > Changes since V2 : > > > - IS_COMETLAKE replaced with IS_GEN9_BC > > > - VBT ddc pin remapping added > > > - Added dedicated HPD pin and DDC pin handling API > > > Changes since V1 : > > > - Matched HPD Pin mapping for PORT C and PORT D of CML CPU. > > > > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > > > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_bios.c | 9 +++++++++ > > > drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++++-- > > > drivers/gpu/drm/i915/display/intel_display.c | 9 ++++++++- > > > drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++++ > > > drivers/gpu/drm/i915/intel_pch.c | 3 ++- > > > 5 files changed, 44 insertions(+), 4 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c > > > index 987cf509337f..730b7f45e5d4 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_bios.c > > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > > > @@ -1630,6 +1630,12 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = { > > > [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, > > > }; > > > > > > +static const u8 gen9bc_tgp_ddc_pin_map[] = { > > > + [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, > > > + [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP, > > > + [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP, > > > +}; > > > > Could you please point out the spec you are using here? > > > > VBT's spec at BSpec - at Block 2 > > I can see the TGP table is same as ICP. > > > > So I'm kind of confused now. > > It's a weird place to document it, but bspec 49181 has a compatibility > section that describes how to map the TGP pins when paired with a gen9bc > CPU. Really weird place, but it makes some sense now. We should file a BSpec bug and request this information to be consolidated with VBT one. > > > > > > + > > > static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) > > > { > > > const u8 *ddc_pin_map; > > > @@ -1640,6 +1646,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) > > > } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) { > > > ddc_pin_map = rkl_pch_tgp_ddc_pin_map; > > > n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); > > > + } else if (HAS_PCH_TGP(dev_priv) && IS_GEN9_BC(dev_priv)) { > > > + ddc_pin_map = gen9bc_tgp_ddc_pin_map; > > > + n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); > > > } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { > > > ddc_pin_map = icp_ddc_pin_map; > > > n_entries = ARRAY_SIZE(icp_ddc_pin_map); > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index 3df6913369bc..13f1268e2cff 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -5337,7 +5337,9 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, > > > static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, > > > enum port port) > > > { > > > - if (port >= PORT_TC1) > > > + if (IS_GEN9_BC(dev_priv) && port >= PORT_C) > > > > gen9 in tgl function?! > > please, no! > > We should probably rename this function to tgp since it ultimately gets > called on every possible TGP platform (TGL+TGP, RKL+TGP, gen9+TGP). If > it weren't for RKL+CMP, I'd say that all these functions should just be > named after the PCH, but I guess the TC ports on RKL+CMP break the > pattern. okay, so we need at least this. A rename with a return if not tgp. But please not gen9 call/check inside a gen12 function. > > I think the real plan once we get some free time is to kill off a bunch > of these output-based functions and define DDI/port/phy/VBT/HPD/DDC > mapping for outputs declaratively in a table since all the special cases > we're running into on recent platforms are turning the logic-based > approach into a mess. This long term plan looks good, but we cannot have a mess right now. This patch needs rework. > > > > > > + return HPD_PORT_TC1 + port - PORT_C; > > > + else if (port >= PORT_TC1) > > > return HPD_PORT_TC1 + port - PORT_TC1; > > > else > > > return HPD_PORT_A + port - PORT_A; > > > @@ -5493,7 +5495,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > > > encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); > > > else if (IS_ROCKETLAKE(dev_priv)) > > > encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); > > > - else if (INTEL_GEN(dev_priv) >= 12) > > > + else if (INTEL_GEN(dev_priv) >= 12 || (IS_GEN9_BC(dev_priv) && > > > + HAS_PCH_TGP(dev_priv))) > > > > Here's another aspect that I don't like in this code. > > It mixes the gfx gen with the PCH in many places. > > > > Something is not right... This is another critical part of this patch that needs to be reworked before we can accept. We shouldn't mix gt-gen and pch checks... > > > > > encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); > > > else if (IS_JSL_EHL(dev_priv)) > > > encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > index 0189d379a55e..81c93c49ddef 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -16212,7 +16212,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > > > > > > /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP > > > * register */ > > > - found = intel_de_read(dev_priv, SFUSE_STRAP); > > > + if (HAS_PCH_TGP(dev_priv)) { > > > + /* W/A due to lack of STRAP config on TGP PCH*/ > > > + found = (SFUSE_STRAP_DDIB_DETECTED | > > > + SFUSE_STRAP_DDIC_DETECTED | > > > + SFUSE_STRAP_DDID_DETECTED); > > > + } else { > > > + found = intel_de_read(dev_priv, SFUSE_STRAP); > > > + } > > > > oh, do we still need this :( > > We've always needed it on gen9 (unless we're willing to rely solely on > the VBT like we do for more recent platforms). But when a gen9 platform > is paired with a TGP PCH, the strap bits won't be there (since this is a > south display register), so we have no choice but to rely on VBT. okay, so please remove the other one from the HAS_DDI part and move everything together with a separated IS_GEN9_BC... Thanks, Rodrigo. > > > Matt > > > > > > > > > if (found & SFUSE_STRAP_DDIB_DETECTED) > > > intel_ddi_init(dev_priv, PORT_B); > > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c > > > index c5959590562b..aa3b4a659f96 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > > > @@ -3130,6 +3130,24 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) > > > return GMBUS_PIN_1_BXT + phy; > > > } > > > > > > +static u8 gen9bc_port_to_ddc_pin(struct drm_i915_private *i915, enum port port) > > > +{ > > > + enum phy phy = intel_port_to_phy(i915, port); > > > + > > > + drm_WARN_ON(&i915->drm, port == PORT_A); > > > + > > > + /* > > > + * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, > > > + * final two outputs use type-c pins, even though they're actually > > > + * combo outputs. With CMP, the traditional DDI A-D pins are used for > > > + * all outputs. > > > + */ > > > + if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) > > > + return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; > > > + > > > + return GMBUS_PIN_1_BXT + phy; > > > +} > > > + > > > static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) > > > { > > > return intel_port_to_phy(dev_priv, port) + 1; > > > @@ -3176,6 +3194,8 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) > > > ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); > > > else if (IS_ROCKETLAKE(dev_priv)) > > > ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); > > > + else if (IS_GEN9_BC(dev_priv) && HAS_PCH_TGP(dev_priv)) > > > + ddc_pin = gen9bc_port_to_ddc_pin(dev_priv, port); > > > else if (HAS_PCH_MCC(dev_priv)) > > > ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); > > > else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) > > > diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c > > > index f31c0dabd0cc..c1bc2d032360 100644 > > > --- a/drivers/gpu/drm/i915/intel_pch.c > > > +++ b/drivers/gpu/drm/i915/intel_pch.c > > > @@ -121,7 +121,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) > > > case INTEL_PCH_TGP2_DEVICE_ID_TYPE: > > > drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n"); > > > drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) && > > > - !IS_ROCKETLAKE(dev_priv)); > > > + !IS_ROCKETLAKE(dev_priv) && > > > + !IS_GEN9_BC(dev_priv)); > > > return PCH_TGP; > > > case INTEL_PCH_JSP_DEVICE_ID_TYPE: > > > case INTEL_PCH_JSP2_DEVICE_ID_TYPE: > > > -- > > > 2.30.0 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795 > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support 2021-01-19 15:52 ` Rodrigo Vivi @ 2021-01-19 16:13 ` Ville Syrjälä 0 siblings, 0 replies; 8+ messages in thread From: Ville Syrjälä @ 2021-01-19 16:13 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx, hariom.pandey On Tue, Jan 19, 2021 at 10:52:47AM -0500, Rodrigo Vivi wrote: > On Mon, Jan 11, 2021 at 05:30:00PM -0800, Matt Roper wrote: > > On Mon, Jan 11, 2021 at 07:21:55PM -0500, Rodrigo Vivi wrote: > > > On Fri, Jan 08, 2021 at 05:39:22PM +0530, Tejas Upadhyay wrote: > > > > We have TGP PCH support for Tigerlake and Rocketlake. Similarly > > > > now TGP PCH can be used with Cometlake CPU. > > > > > > > > Changes since V3 : > > > > - Rebased to top drm-tip commit > > > > - dev_priv replaced with i915 for new API > > > > - Enable default Port B,C,D detection for TGP && GEN9_BC > > > > Changes since V2 : > > > > - IS_COMETLAKE replaced with IS_GEN9_BC > > > > - VBT ddc pin remapping added > > > > - Added dedicated HPD pin and DDC pin handling API > > > > Changes since V1 : > > > > - Matched HPD Pin mapping for PORT C and PORT D of CML CPU. > > > > > > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > > > > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_bios.c | 9 +++++++++ > > > > drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++++-- > > > > drivers/gpu/drm/i915/display/intel_display.c | 9 ++++++++- > > > > drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++++ > > > > drivers/gpu/drm/i915/intel_pch.c | 3 ++- > > > > 5 files changed, 44 insertions(+), 4 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c > > > > index 987cf509337f..730b7f45e5d4 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_bios.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > > > > @@ -1630,6 +1630,12 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = { > > > > [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, > > > > }; > > > > > > > > +static const u8 gen9bc_tgp_ddc_pin_map[] = { > > > > + [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, > > > > + [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP, > > > > + [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP, > > > > +}; > > > > > > Could you please point out the spec you are using here? > > > > > > VBT's spec at BSpec - at Block 2 > > > I can see the TGP table is same as ICP. > > > > > > So I'm kind of confused now. > > > > It's a weird place to document it, but bspec 49181 has a compatibility > > section that describes how to map the TGP pins when paired with a gen9bc > > CPU. > > Really weird place, but it makes some sense now. > We should file a BSpec bug and request this information to be consolidated > with VBT one. > > > > > > > > > > + > > > > static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) > > > > { > > > > const u8 *ddc_pin_map; > > > > @@ -1640,6 +1646,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) > > > > } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) { > > > > ddc_pin_map = rkl_pch_tgp_ddc_pin_map; > > > > n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); > > > > + } else if (HAS_PCH_TGP(dev_priv) && IS_GEN9_BC(dev_priv)) { > > > > + ddc_pin_map = gen9bc_tgp_ddc_pin_map; > > > > + n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); > > > > } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { > > > > ddc_pin_map = icp_ddc_pin_map; > > > > n_entries = ARRAY_SIZE(icp_ddc_pin_map); > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > index 3df6913369bc..13f1268e2cff 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > @@ -5337,7 +5337,9 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, > > > > static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, > > > > enum port port) > > > > { > > > > - if (port >= PORT_TC1) > > > > + if (IS_GEN9_BC(dev_priv) && port >= PORT_C) > > > > > > gen9 in tgl function?! > > > please, no! > > > > We should probably rename this function to tgp since it ultimately gets > > called on every possible TGP platform (TGL+TGP, RKL+TGP, gen9+TGP). If > > it weren't for RKL+CMP, I'd say that all these functions should just be > > named after the PCH, but I guess the TC ports on RKL+CMP break the > > pattern. > > okay, so we need at least this. static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) { if (HAS_PCH_TGP(dev_priv)) return icl_hpd_pin(dev_priv, port); return HPD_PORT_A + port - PORT_A; } is what I have sitting in a local branch. Just never upstreamed it since I wasn't sure the rkl+tgp was going to be a real thing. Also this patch should be split into several independent parts. -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-01-19 16:13 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-01-08 12:09 [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support Tejas Upadhyay 2021-01-08 16:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9_bc : Add TGP PCH support (rev2) Patchwork 2021-01-08 20:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-01-12 0:21 ` [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support Rodrigo Vivi 2021-01-12 1:30 ` Matt Roper 2021-01-12 3:35 ` Lucas De Marchi 2021-01-19 15:52 ` Rodrigo Vivi 2021-01-19 16:13 ` Ville Syrjälä
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