From: Michael Walle <michael@walle.cc> To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org>, Michal Simek <michal.simek@xilinx.com>, Arnd Bergmann <arnd@arndb.de>, Olof Johansson <olof@lixom.net>, soc@kernel.org, Michael Walle <michael@walle.cc> Subject: [PATCH 3/3] ARM: dts: add Ebang EBAZ4205 device tree Date: Wed, 20 Jan 2021 20:40:33 +0100 [thread overview] Message-ID: <20210120194033.26970-4-michael@walle.cc> (raw) In-Reply-To: <20210120194033.26970-1-michael@walle.cc> The Ebang EBAZ4205 is a simple board based on the Xilinx Zynq-7000 SoC. Its features are: - one serial port - 256 MB RAM - 128 MB NAND flash - SDcard slot - IP101GA 10/100 Mbit Ethernet PHY (connected to PL IOs) - two LEDs (connected to PL IOs) - one Push Button (connect to PL IOs) - (optional) RTC - (optional) Input voltage supervisor The NAND flash is not supported in mainline linux yet. Unfortunately, the PHY is connected via the PL, thus for working ethernet the FPGA has to be configured. Also, depending on the board variant, the PHY has no external crystal and its clock needs to be driven by the PL. FCLK3 is used for this and is kept enabled. Signed-off-by: Michael Walle <michael@walle.cc> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zynq-ebaz4205.dts | 109 ++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 arch/arm/boot/dts/zynq-ebaz4205.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bf80fd901f61..03ac2e665241 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1312,6 +1312,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \ wm8850-w70v2.dtb dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-cc108.dtb \ + zynq-ebaz4205.dtb \ zynq-microzed.dtb \ zynq-parallella.dtb \ zynq-zc702.dtb \ diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts new file mode 100644 index 000000000000..e802d4ae8804 --- /dev/null +++ b/arch/arm/boot/dts/zynq-ebaz4205.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Michael Walle <michael@walle.cc> + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Ebang EBAZ4205"; + compatible = "ebang,ebaz4205", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; + fclk-enable = <8>; +}; + +&gem0 { + status = "okay"; + phy-mode = "mii"; + phy-handle = <&phy>; + + /* PHY clock */ + assigned-clocks = <&clkc 18>; + assigned-clock-rates = <25000000>; + + phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pinctrl0 { + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_2_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_2_grp"; + io-standard = <3>; + slew-rate = <0>; + bias-disable; + }; + + mux-cd { + groups = "gpio0_34_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "gpio0_34_grp"; + io-standard = <3>; + slew-rate = <0>; + bias-high-impedance; + bias-pull-up; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_4_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_4_grp"; + io-standard = <3>; + slew-rate = <0>; + }; + + conf-rx { + pins = "MIO25"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO24"; + bias-disable; + }; + }; +}; + +&sdhci0 { + status = "okay"; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Michael Walle <michael@walle.cc> To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Arnd Bergmann <arnd@arndb.de>, Michael Walle <michael@walle.cc>, Michal Simek <michal.simek@xilinx.com>, soc@kernel.org, Rob Herring <robh+dt@kernel.org>, Olof Johansson <olof@lixom.net> Subject: [PATCH 3/3] ARM: dts: add Ebang EBAZ4205 device tree Date: Wed, 20 Jan 2021 20:40:33 +0100 [thread overview] Message-ID: <20210120194033.26970-4-michael@walle.cc> (raw) Message-ID: <20210120194033.umkaXqh664uhvN7Atj_Q7QbA5NfbwteLxyCg3r9dDv0@z> (raw) In-Reply-To: <20210120194033.26970-1-michael@walle.cc> The Ebang EBAZ4205 is a simple board based on the Xilinx Zynq-7000 SoC. Its features are: - one serial port - 256 MB RAM - 128 MB NAND flash - SDcard slot - IP101GA 10/100 Mbit Ethernet PHY (connected to PL IOs) - two LEDs (connected to PL IOs) - one Push Button (connect to PL IOs) - (optional) RTC - (optional) Input voltage supervisor The NAND flash is not supported in mainline linux yet. Unfortunately, the PHY is connected via the PL, thus for working ethernet the FPGA has to be configured. Also, depending on the board variant, the PHY has no external crystal and its clock needs to be driven by the PL. FCLK3 is used for this and is kept enabled. Signed-off-by: Michael Walle <michael@walle.cc> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zynq-ebaz4205.dts | 109 ++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 arch/arm/boot/dts/zynq-ebaz4205.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bf80fd901f61..03ac2e665241 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1312,6 +1312,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \ wm8850-w70v2.dtb dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-cc108.dtb \ + zynq-ebaz4205.dtb \ zynq-microzed.dtb \ zynq-parallella.dtb \ zynq-zc702.dtb \ diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts new file mode 100644 index 000000000000..e802d4ae8804 --- /dev/null +++ b/arch/arm/boot/dts/zynq-ebaz4205.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Michael Walle <michael@walle.cc> + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Ebang EBAZ4205"; + compatible = "ebang,ebaz4205", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; + fclk-enable = <8>; +}; + +&gem0 { + status = "okay"; + phy-mode = "mii"; + phy-handle = <&phy>; + + /* PHY clock */ + assigned-clocks = <&clkc 18>; + assigned-clock-rates = <25000000>; + + phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pinctrl0 { + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_2_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_2_grp"; + io-standard = <3>; + slew-rate = <0>; + bias-disable; + }; + + mux-cd { + groups = "gpio0_34_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "gpio0_34_grp"; + io-standard = <3>; + slew-rate = <0>; + bias-high-impedance; + bias-pull-up; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_4_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_4_grp"; + io-standard = <3>; + slew-rate = <0>; + }; + + conf-rx { + pins = "MIO25"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO24"; + bias-disable; + }; + }; +}; + +&sdhci0 { + status = "okay"; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-20 19:47 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-20 19:40 [PATCH 0/3] add Ebang EBAZ4205 support Michael Walle 2021-01-20 19:40 ` Michael Walle 2021-01-20 19:40 ` [PATCH 1/3] dt-bindings: add ebang vendor prefix Michael Walle 2021-01-20 19:40 ` Michael Walle 2021-02-09 2:32 ` Rob Herring 2021-02-09 2:32 ` Rob Herring 2021-01-20 19:40 ` [PATCH 2/3] dt-bindings: arm: add Ebang EBAZ4205 board Michael Walle 2021-01-20 19:40 ` Michael Walle 2021-01-20 19:40 ` Michael Walle [this message] 2021-01-20 19:40 ` [PATCH 3/3] ARM: dts: add Ebang EBAZ4205 device tree Michael Walle 2021-01-21 9:25 ` [PATCH 0/3] add Ebang EBAZ4205 support Michal Simek 2021-01-21 9:25 ` Michal Simek 2021-01-21 9:35 ` Michael Walle 2021-01-21 9:35 ` Michael Walle 2021-01-21 9:57 ` Michal Simek 2021-01-21 9:57 ` Michal Simek 2021-01-21 10:13 ` Michael Walle 2021-01-21 10:13 ` Michael Walle 2021-01-21 10:23 ` Michal Simek 2021-01-21 10:23 ` Michal Simek 2021-01-21 10:41 ` Michael Walle 2021-01-21 10:41 ` Michael Walle 2021-01-21 13:16 ` Michal Simek 2021-01-21 13:16 ` Michal Simek 2021-01-21 15:14 ` Michael Walle 2021-01-21 15:14 ` Michael Walle 2021-01-26 13:31 ` Michal Simek 2021-01-26 13:31 ` Michal Simek
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