* [PATCH v2 1/4] arm64: dts: renesas: r8a779a0: add & update SCIF nodes
2021-01-21 11:00 [PATCH v2 0/4] v3u: add support for SCIF Wolfram Sang
@ 2021-01-21 11:00 ` Wolfram Sang
2021-01-22 10:39 ` Geert Uytterhoeven
2021-01-21 11:00 ` [PATCH v2 2/4] arm64: dts: renesas: falcon: add SCIF0 nodes Wolfram Sang
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Wolfram Sang @ 2021-01-21 11:00 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Wolfram Sang, Linh Phung, Geert Uytterhoeven
This is the result of multiple patches taken from the BSP, combined,
rebased, and properly sorted. SCIF0 gets DMA properties, other SCIFs are
entirely new.
Signed-off-by: Linh Phung <linh.phung.jy@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
Changes since v1:
* fixed sorting
arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 50 +++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 45b4ea1965d4..7e311b591d5c 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -663,11 +663,61 @@ scif0: serial@e6e60000 {
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>;
+ dma-names = "tx", "rx";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
};
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a779a0",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>,
+ <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6c50000 {
+ compatible = "renesas,scif-r8a779a0",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>,
+ <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x57>, <&dmac1 0x56>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c40000 {
+ compatible = "renesas,scif-r8a779a0",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 705>,
+ <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x59>, <&dmac1 0x58>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 705>;
+ status = "disabled";
+ };
+
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 1/4] arm64: dts: renesas: r8a779a0: add & update SCIF nodes
2021-01-21 11:00 ` [PATCH v2 1/4] arm64: dts: renesas: r8a779a0: add & update SCIF nodes Wolfram Sang
@ 2021-01-22 10:39 ` Geert Uytterhoeven
0 siblings, 0 replies; 9+ messages in thread
From: Geert Uytterhoeven @ 2021-01-22 10:39 UTC (permalink / raw)
To: Wolfram Sang; +Cc: Linux-Renesas, Linh Phung
On Thu, Jan 21, 2021 at 12:00 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> This is the result of multiple patches taken from the BSP, combined,
> rebased, and properly sorted. SCIF0 gets DMA properties, other SCIFs are
> entirely new.
>
> Signed-off-by: Linh Phung <linh.phung.jy@renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
> Changes since v1:
> * fixed sorting
Thx, will queue in renesas-devel for v5.12.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/4] arm64: dts: renesas: falcon: add SCIF0 nodes
2021-01-21 11:00 [PATCH v2 0/4] v3u: add support for SCIF Wolfram Sang
2021-01-21 11:00 ` [PATCH v2 1/4] arm64: dts: renesas: r8a779a0: add & update SCIF nodes Wolfram Sang
@ 2021-01-21 11:00 ` Wolfram Sang
2021-01-22 10:41 ` Geert Uytterhoeven
2021-01-21 11:00 ` [PATCH v2 3/4] arm64: dts: renesas: r8a779a0: Add HSCIF support Wolfram Sang
2021-01-21 11:00 ` [PATCH v2 4/4] HACK: make hscif0 console Wolfram Sang
3 siblings, 1 reply; 9+ messages in thread
From: Wolfram Sang @ 2021-01-21 11:00 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Wolfram Sang
SCIF0 has been enabled by the firmware, so it worked already. Still, add
the proper nodes to make it work in any case.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
Changes since v1:
* moved to Falcon CPU dtsi
.../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
index c54d1e287a49..1a36239cdc5d 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
@@ -225,6 +225,9 @@ &mmc0 {
};
&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
avb0_pins: avb0 {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
@@ -368,8 +371,26 @@ mmc_pins: mmc {
function = "mmc";
power-source = <1800>;
};
+
+ scif0_pins: scif0 {
+ groups = "scif0_data", "scif0_ctrl";
+ function = "scif0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk";
+ function = "scif_clk";
+ };
};
&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
status = "okay";
};
+
+&scif_clk {
+ clock-frequency = <24000000>;
+};
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 2/4] arm64: dts: renesas: falcon: add SCIF0 nodes
2021-01-21 11:00 ` [PATCH v2 2/4] arm64: dts: renesas: falcon: add SCIF0 nodes Wolfram Sang
@ 2021-01-22 10:41 ` Geert Uytterhoeven
0 siblings, 0 replies; 9+ messages in thread
From: Geert Uytterhoeven @ 2021-01-22 10:41 UTC (permalink / raw)
To: Wolfram Sang; +Cc: Linux-Renesas
On Thu, Jan 21, 2021 at 12:05 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> SCIF0 has been enabled by the firmware, so it worked already. Still, add
> the proper nodes to make it work in any case.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
> Changes since v1:
> * moved to Falcon CPU dtsi
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.12.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/4] arm64: dts: renesas: r8a779a0: Add HSCIF support
2021-01-21 11:00 [PATCH v2 0/4] v3u: add support for SCIF Wolfram Sang
2021-01-21 11:00 ` [PATCH v2 1/4] arm64: dts: renesas: r8a779a0: add & update SCIF nodes Wolfram Sang
2021-01-21 11:00 ` [PATCH v2 2/4] arm64: dts: renesas: falcon: add SCIF0 nodes Wolfram Sang
@ 2021-01-21 11:00 ` Wolfram Sang
2021-01-22 10:43 ` Geert Uytterhoeven
2021-01-21 11:00 ` [PATCH v2 4/4] HACK: make hscif0 console Wolfram Sang
3 siblings, 1 reply; 9+ messages in thread
From: Wolfram Sang @ 2021-01-21 11:00 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Linh Phung, Geert Uytterhoeven, Wolfram Sang
From: Linh Phung <linh.phung.jy@renesas.com>
Define the generic parts of the HSCIF[0-3] device nodes.
Signed-off-by: Linh Phung <linh.phung.jy@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
---
Changes since v1: none
arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 64 +++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 7e311b591d5c..6d93b1e4a471 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -308,6 +308,70 @@ i2c2: i2c@e6510000 {
status = "disabled";
};
+ hscif0: serial@e6540000 {
+ compatible = "renesas,hscif-r8a779a0",
+ "renesas,rcar-gen3-hscif", "renesas,hscif";
+ reg = <0 0xe6540000 0 0x60>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 514>,
+ <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 514>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e6550000 {
+ compatible = "renesas,hscif-r8a779a0",
+ "renesas,rcar-gen3-hscif", "renesas,hscif";
+ reg = <0 0xe6550000 0 0x60>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 515>,
+ <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 515>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e6560000 {
+ compatible = "renesas,hscif-r8a779a0",
+ "renesas,rcar-gen3-hscif", "renesas,hscif";
+ reg = <0 0xe6560000 0 0x60>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 516>,
+ <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 516>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a0000 {
+ compatible = "renesas,hscif-r8a779a0",
+ "renesas,rcar-gen3-hscif", "renesas,hscif";
+ reg = <0 0xe66a0000 0 0x60>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x37>, <&dmac1 0x36>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
i2c3: i2c@e66d0000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 3/4] arm64: dts: renesas: r8a779a0: Add HSCIF support
2021-01-21 11:00 ` [PATCH v2 3/4] arm64: dts: renesas: r8a779a0: Add HSCIF support Wolfram Sang
@ 2021-01-22 10:43 ` Geert Uytterhoeven
2021-01-25 9:19 ` Geert Uytterhoeven
0 siblings, 1 reply; 9+ messages in thread
From: Geert Uytterhoeven @ 2021-01-22 10:43 UTC (permalink / raw)
To: Wolfram Sang; +Cc: Linux-Renesas, Linh Phung, Wolfram Sang
On Thu, Jan 21, 2021 at 12:00 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> From: Linh Phung <linh.phung.jy@renesas.com>
>
> Define the generic parts of the HSCIF[0-3] device nodes.
>
> Signed-off-by: Linh Phung <linh.phung.jy@renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Wolfram Sang <wsa@kernel.org>
> ---
> Changes since v1: none
Thx, will queue in renesas-devel for v5.12.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2 3/4] arm64: dts: renesas: r8a779a0: Add HSCIF support
2021-01-22 10:43 ` Geert Uytterhoeven
@ 2021-01-25 9:19 ` Geert Uytterhoeven
0 siblings, 0 replies; 9+ messages in thread
From: Geert Uytterhoeven @ 2021-01-25 9:19 UTC (permalink / raw)
To: Wolfram Sang; +Cc: Linux-Renesas, Linh Phung, Wolfram Sang
On Fri, Jan 22, 2021 at 11:43 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Thu, Jan 21, 2021 at 12:00 PM Wolfram Sang
> <wsa+renesas@sang-engineering.com> wrote:
> > From: Linh Phung <linh.phung.jy@renesas.com>
> >
> > Define the generic parts of the HSCIF[0-3] device nodes.
> >
> > Signed-off-by: Linh Phung <linh.phung.jy@renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Signed-off-by: Wolfram Sang <wsa@kernel.org>
> > ---
> > Changes since v1: none
>
> Thx, will queue in renesas-devel for v5.12.
... after moving all HSCIF nodes after all I2C nodes.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 4/4] HACK: make hscif0 console
2021-01-21 11:00 [PATCH v2 0/4] v3u: add support for SCIF Wolfram Sang
` (2 preceding siblings ...)
2021-01-21 11:00 ` [PATCH v2 3/4] arm64: dts: renesas: r8a779a0: Add HSCIF support Wolfram Sang
@ 2021-01-21 11:00 ` Wolfram Sang
3 siblings, 0 replies; 9+ messages in thread
From: Wolfram Sang @ 2021-01-21 11:00 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Wolfram Sang
Just for testing, not for upstream!
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
Changes since v1:
* marked explicitly as HACK
arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 12 ++++++++----
arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts | 2 +-
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
index 1a36239cdc5d..60cc460612ab 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
@@ -372,9 +372,9 @@ mmc_pins: mmc {
power-source = <1800>;
};
- scif0_pins: scif0 {
- groups = "scif0_data", "scif0_ctrl";
- function = "scif0";
+ hscif0_pins: hscif0 {
+ groups = "hscif0_data", "hscif0_ctrl";
+ function = "hscif0";
};
scif_clk_pins: scif_clk {
@@ -384,7 +384,11 @@ scif_clk_pins: scif_clk {
};
&scif0 {
- pinctrl-0 = <&scif0_pins>;
+ status = "disabled";
+};
+
+&hscif0 {
+ pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
index 5617b81dd7dc..9a129e6a78b6 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
@@ -14,7 +14,7 @@ / {
aliases {
ethernet0 = &avb0;
- serial0 = &scif0;
+ serial0 = &hscif0;
};
chosen {
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread