* [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
0 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: git, devicetree, mturquette, sboyd, gregkh, devel, Shubhrajyoti Datta
In the thread [1] Greg suggested that we move the driver
to the clk from the staging.
Add patches to address the concerns regarding the fractional and
set rate support in the TODO.
The patch set does the following
- Trivial fixes for kernel doc.
- Move the driver to the clk folder
- Add capability to set rate.
- Add fractional support.
- Add support for configurable outputs.
- Make the output names unique so that multiple instances
do not crib.
Changes in the v3:
Added the cover-letter.
Add patches for rate setting and fractional support
Add patches for warning.
Remove the driver from staging as suggested
v4:
Reorder the patches.
Merge the CLK_IS_BASIC patch.
Add the yaml form of binding document
v5:
Fix a mismerge
v6:
Fix the yaml warning
use poll timedout
v7:
Binding doc updates
Use common divisor function.
[1] https://spinics.net/lists/linux-driver-devel/msg117326.html
Shubhrajyoti Datta (7):
dt-bindings: add documentation of xilinx clocking wizard
clk: clock-wizard: Add the clockwizard to clk directory
clk: clock-wizard: Fix kernel-doc warning
clk: clock-wizard: Add support for dynamic reconfiguration
clk: clock-wizard: Add support for fractional support
clk: clock-wizard: Remove the hardcoding of the clock outputs
clk: clock-wizard: Update the fixed factor divisors
.../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++
drivers/clk/Kconfig | 9 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-xlnx-clock-wizard.c | 689 +++++++++++++++++++++
drivers/staging/Kconfig | 2 -
drivers/staging/Makefile | 1 -
drivers/staging/clocking-wizard/Kconfig | 10 -
drivers/staging/clocking-wizard/Makefile | 2 -
drivers/staging/clocking-wizard/TODO | 12 -
.../clocking-wizard/clk-xlnx-clock-wizard.c | 333 ----------
drivers/staging/clocking-wizard/dt-binding.txt | 30 -
11 files changed, 764 insertions(+), 390 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c
delete mode 100644 drivers/staging/clocking-wizard/Kconfig
delete mode 100644 drivers/staging/clocking-wizard/Makefile
delete mode 100644 drivers/staging/clocking-wizard/TODO
delete mode 100644 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
delete mode 100644 drivers/staging/clocking-wizard/dt-binding.txt
--
2.1.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
0 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: devel, devicetree, sboyd, gregkh, mturquette, Shubhrajyoti Datta, git
In the thread [1] Greg suggested that we move the driver
to the clk from the staging.
Add patches to address the concerns regarding the fractional and
set rate support in the TODO.
The patch set does the following
- Trivial fixes for kernel doc.
- Move the driver to the clk folder
- Add capability to set rate.
- Add fractional support.
- Add support for configurable outputs.
- Make the output names unique so that multiple instances
do not crib.
Changes in the v3:
Added the cover-letter.
Add patches for rate setting and fractional support
Add patches for warning.
Remove the driver from staging as suggested
v4:
Reorder the patches.
Merge the CLK_IS_BASIC patch.
Add the yaml form of binding document
v5:
Fix a mismerge
v6:
Fix the yaml warning
use poll timedout
v7:
Binding doc updates
Use common divisor function.
[1] https://spinics.net/lists/linux-driver-devel/msg117326.html
Shubhrajyoti Datta (7):
dt-bindings: add documentation of xilinx clocking wizard
clk: clock-wizard: Add the clockwizard to clk directory
clk: clock-wizard: Fix kernel-doc warning
clk: clock-wizard: Add support for dynamic reconfiguration
clk: clock-wizard: Add support for fractional support
clk: clock-wizard: Remove the hardcoding of the clock outputs
clk: clock-wizard: Update the fixed factor divisors
.../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++
drivers/clk/Kconfig | 9 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-xlnx-clock-wizard.c | 689 +++++++++++++++++++++
drivers/staging/Kconfig | 2 -
drivers/staging/Makefile | 1 -
drivers/staging/clocking-wizard/Kconfig | 10 -
drivers/staging/clocking-wizard/Makefile | 2 -
drivers/staging/clocking-wizard/TODO | 12 -
.../clocking-wizard/clk-xlnx-clock-wizard.c | 333 ----------
drivers/staging/clocking-wizard/dt-binding.txt | 30 -
11 files changed, 764 insertions(+), 390 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c
delete mode 100644 drivers/staging/clocking-wizard/Kconfig
delete mode 100644 drivers/staging/clocking-wizard/Makefile
delete mode 100644 drivers/staging/clocking-wizard/TODO
delete mode 100644 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
delete mode 100644 drivers/staging/clocking-wizard/dt-binding.txt
--
2.1.1
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v7 1/7] dt-bindings: add documentation of xilinx clocking wizard
2020-11-04 15:06 ` Shubhrajyoti Datta
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
-1 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: git, devicetree, mturquette, sboyd, gregkh, devel, Shubhrajyoti Datta
Add the devicetree binding for the xilinx clocking wizard.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
v6:
Fix a yaml warning
v7:
Add vendor prefix speed-grade
.../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++++++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
new file mode 100644
index 0000000..a19b9bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx clocking wizard
+
+maintainers:
+ - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
+
+description: |
+ The clocking wizard is a soft ip clocking block of Xilinx versal. It
+ reads required input clock frequencies from the devicetree and acts as clock
+ clock output.
+
+select: false
+
+properties:
+ compatible:
+ - enum:
+ - xlnx,clocking-wizard
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ items:
+ - description: clock input
+ - description: axi clock
+
+ clock-names:
+ items:
+ - const: clk_in1
+ - const: s_axi_aclk
+
+ xlnx,speed-grade:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [1, 2, 3]
+ description:
+ Speed grade of the device.
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - speed-grade
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-generator@40040000 {
+ #clock-cells = <1>;
+ reg = <0x40040000 0x1000>;
+ compatible = "xlnx,clocking-wizard";
+ xlnx,speed-grade = <1>;
+ clock-names = "clk_in1", "s_axi_aclk";
+ clocks = <&clkc 15>, <&clkc 15>;
+ clock-output-names = "clk_out1", "clk_out2",
+ "clk_out3", "clk_out4", "clk_out5",
+ "clk_out6", "clk_out7";
+ };
+...
--
2.1.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v7 1/7] dt-bindings: add documentation of xilinx clocking wizard
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
0 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: devel, devicetree, sboyd, gregkh, mturquette, Shubhrajyoti Datta, git
Add the devicetree binding for the xilinx clocking wizard.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
v6:
Fix a yaml warning
v7:
Add vendor prefix speed-grade
.../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++++++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
new file mode 100644
index 0000000..a19b9bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx clocking wizard
+
+maintainers:
+ - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
+
+description: |
+ The clocking wizard is a soft ip clocking block of Xilinx versal. It
+ reads required input clock frequencies from the devicetree and acts as clock
+ clock output.
+
+select: false
+
+properties:
+ compatible:
+ - enum:
+ - xlnx,clocking-wizard
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ items:
+ - description: clock input
+ - description: axi clock
+
+ clock-names:
+ items:
+ - const: clk_in1
+ - const: s_axi_aclk
+
+ xlnx,speed-grade:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [1, 2, 3]
+ description:
+ Speed grade of the device.
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - speed-grade
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-generator@40040000 {
+ #clock-cells = <1>;
+ reg = <0x40040000 0x1000>;
+ compatible = "xlnx,clocking-wizard";
+ xlnx,speed-grade = <1>;
+ clock-names = "clk_in1", "s_axi_aclk";
+ clocks = <&clkc 15>, <&clkc 15>;
+ clock-output-names = "clk_out1", "clk_out2",
+ "clk_out3", "clk_out4", "clk_out5",
+ "clk_out6", "clk_out7";
+ };
+...
--
2.1.1
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v7 2/7] clk: clock-wizard: Add the clockwizard to clk directory
2020-11-04 15:06 ` Shubhrajyoti Datta
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
-1 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: git, devicetree, mturquette, sboyd, gregkh, devel, Shubhrajyoti Datta
Add clocking wizard driver to clk.
And delete the driver from the staging as it is in drivers/clk.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
v7:
Combined the patch for deletion and add of the driver
dropping the ack from Greg for the staging as it is a combined patch.
Add vendor prefix to speedgrade
drivers/clk/Kconfig | 9 +++++++
drivers/clk/Makefile | 1 +
.../clk-xlnx-clock-wizard.c | 6 +++--
drivers/staging/Kconfig | 2 --
drivers/staging/Makefile | 1 -
drivers/staging/clocking-wizard/Kconfig | 10 --------
drivers/staging/clocking-wizard/Makefile | 2 --
drivers/staging/clocking-wizard/TODO | 12 ---------
drivers/staging/clocking-wizard/dt-binding.txt | 30 ----------------------
9 files changed, 14 insertions(+), 59 deletions(-)
rename drivers/{staging/clocking-wizard => clk}/clk-xlnx-clock-wizard.c (98%)
delete mode 100644 drivers/staging/clocking-wizard/Kconfig
delete mode 100644 drivers/staging/clocking-wizard/Makefile
delete mode 100644 drivers/staging/clocking-wizard/TODO
delete mode 100644 drivers/staging/clocking-wizard/dt-binding.txt
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4026fac..a0e29dd 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -359,6 +359,15 @@ config COMMON_CLK_FIXED_MMIO
help
Support for Memory Mapped IO Fixed clocks
+config COMMON_CLK_XLNX_CLKWZRD
+ tristate "Xilinx Clocking Wizard"
+ depends on COMMON_CLK && OF
+ help
+ Support for the Xilinx Clocking Wizard IP core clock generator.
+ Adds support for clocking wizard and compatible.
+ This driver supports the Xilinx clocking wizard programmable clock
+ synthesizer. The number of output is configurable in the design.
+
source "drivers/clk/actions/Kconfig"
source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/baikal-t1/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index da8fcf1..1ad6414 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
+obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
# please keep this section sorted lexicographically by directory path name
obj-y += actions/
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c
similarity index 98%
rename from drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
rename to drivers/clk/clk-xlnx-clock-wizard.c
index e52a64b..1bab68e 100644
--- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -2,9 +2,11 @@
/*
* Xilinx 'Clocking Wizard' driver
*
- * Copyright (C) 2013 - 2014 Xilinx
+ * Copyright (C) 2013 - 2020 Xilinx
*
* Sören Brinkmann <soren.brinkmann@xilinx.com>
+ * Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
+ *
*/
#include <linux/platform_device.h>
@@ -146,7 +148,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
if (IS_ERR(clk_wzrd->base))
return PTR_ERR(clk_wzrd->base);
- ret = of_property_read_u32(np, "speed-grade", &clk_wzrd->speed_grade);
+ ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade);
if (!ret) {
if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) {
dev_warn(&pdev->dev, "invalid speed grade '%d'\n",
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index e6c831c..bae49c6 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -76,8 +76,6 @@ source "drivers/staging/gs_fpgaboot/Kconfig"
source "drivers/staging/unisys/Kconfig"
-source "drivers/staging/clocking-wizard/Kconfig"
-
source "drivers/staging/fbtft/Kconfig"
source "drivers/staging/fsl-dpaa2/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index a3b1fd0..f5a3e57 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -28,7 +28,6 @@ obj-$(CONFIG_FIREWIRE_SERIAL) += fwserial/
obj-$(CONFIG_GOLDFISH) += goldfish/
obj-$(CONFIG_GS_FPGABOOT) += gs_fpgaboot/
obj-$(CONFIG_UNISYSSPAR) += unisys/
-obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clocking-wizard/
obj-$(CONFIG_FB_TFT) += fbtft/
obj-$(CONFIG_FSL_DPAA2) += fsl-dpaa2/
obj-$(CONFIG_MOST) += most/
diff --git a/drivers/staging/clocking-wizard/Kconfig b/drivers/staging/clocking-wizard/Kconfig
deleted file mode 100644
index 69cf514..0000000
--- a/drivers/staging/clocking-wizard/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Xilinx Clocking Wizard Driver
-#
-
-config COMMON_CLK_XLNX_CLKWZRD
- tristate "Xilinx Clocking Wizard"
- depends on COMMON_CLK && OF && IOMEM
- help
- Support for the Xilinx Clocking Wizard IP core clock generator.
diff --git a/drivers/staging/clocking-wizard/Makefile b/drivers/staging/clocking-wizard/Makefile
deleted file mode 100644
index b1f9152..0000000
--- a/drivers/staging/clocking-wizard/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
diff --git a/drivers/staging/clocking-wizard/TODO b/drivers/staging/clocking-wizard/TODO
deleted file mode 100644
index ebe99db..0000000
--- a/drivers/staging/clocking-wizard/TODO
+++ /dev/null
@@ -1,12 +0,0 @@
-TODO:
- - support for fractional multiplier
- - support for fractional divider (output 0 only)
- - support for set_rate() operations (may benefit from Stephen Boyd's
- refactoring of the clk primitives: https://lkml.org/lkml/2014/9/5/766)
- - review arithmetic
- - overflow after multiplication?
- - maximize accuracy before divisions
-
-Patches to:
- Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- Sören Brinkmann <soren.brinkmann@xilinx.com>
diff --git a/drivers/staging/clocking-wizard/dt-binding.txt b/drivers/staging/clocking-wizard/dt-binding.txt
deleted file mode 100644
index efb67ff..0000000
--- a/drivers/staging/clocking-wizard/dt-binding.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-Binding for Xilinx Clocking Wizard IP Core
-
-This binding uses the common clock binding[1]. Details about the devices can be
-found in the product guide[2].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Clocking Wizard Product Guide
-https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf
-
-Required properties:
- - compatible: Must be 'xlnx,clocking-wizard'
- - reg: Base and size of the cores register space
- - clocks: Handle to input clock
- - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk'
- - clock-output-names: Names for the output clocks
-
-Optional properties:
- - speed-grade: Speed grade of the device (valid values are 1..3)
-
-Example:
- clock-generator@40040000 {
- reg = <0x40040000 0x1000>;
- compatible = "xlnx,clocking-wizard";
- speed-grade = <1>;
- clock-names = "clk_in1", "s_axi_aclk";
- clocks = <&clkc 15>, <&clkc 15>;
- clock-output-names = "clk_out0", "clk_out1", "clk_out2",
- "clk_out3", "clk_out4", "clk_out5",
- "clk_out6", "clk_out7";
- };
--
2.1.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v7 2/7] clk: clock-wizard: Add the clockwizard to clk directory
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
0 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: devel, devicetree, sboyd, gregkh, mturquette, Shubhrajyoti Datta, git
Add clocking wizard driver to clk.
And delete the driver from the staging as it is in drivers/clk.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
v7:
Combined the patch for deletion and add of the driver
dropping the ack from Greg for the staging as it is a combined patch.
Add vendor prefix to speedgrade
drivers/clk/Kconfig | 9 +++++++
drivers/clk/Makefile | 1 +
.../clk-xlnx-clock-wizard.c | 6 +++--
drivers/staging/Kconfig | 2 --
drivers/staging/Makefile | 1 -
drivers/staging/clocking-wizard/Kconfig | 10 --------
drivers/staging/clocking-wizard/Makefile | 2 --
drivers/staging/clocking-wizard/TODO | 12 ---------
drivers/staging/clocking-wizard/dt-binding.txt | 30 ----------------------
9 files changed, 14 insertions(+), 59 deletions(-)
rename drivers/{staging/clocking-wizard => clk}/clk-xlnx-clock-wizard.c (98%)
delete mode 100644 drivers/staging/clocking-wizard/Kconfig
delete mode 100644 drivers/staging/clocking-wizard/Makefile
delete mode 100644 drivers/staging/clocking-wizard/TODO
delete mode 100644 drivers/staging/clocking-wizard/dt-binding.txt
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4026fac..a0e29dd 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -359,6 +359,15 @@ config COMMON_CLK_FIXED_MMIO
help
Support for Memory Mapped IO Fixed clocks
+config COMMON_CLK_XLNX_CLKWZRD
+ tristate "Xilinx Clocking Wizard"
+ depends on COMMON_CLK && OF
+ help
+ Support for the Xilinx Clocking Wizard IP core clock generator.
+ Adds support for clocking wizard and compatible.
+ This driver supports the Xilinx clocking wizard programmable clock
+ synthesizer. The number of output is configurable in the design.
+
source "drivers/clk/actions/Kconfig"
source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/baikal-t1/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index da8fcf1..1ad6414 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
+obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
# please keep this section sorted lexicographically by directory path name
obj-y += actions/
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c
similarity index 98%
rename from drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
rename to drivers/clk/clk-xlnx-clock-wizard.c
index e52a64b..1bab68e 100644
--- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -2,9 +2,11 @@
/*
* Xilinx 'Clocking Wizard' driver
*
- * Copyright (C) 2013 - 2014 Xilinx
+ * Copyright (C) 2013 - 2020 Xilinx
*
* Sören Brinkmann <soren.brinkmann@xilinx.com>
+ * Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
+ *
*/
#include <linux/platform_device.h>
@@ -146,7 +148,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
if (IS_ERR(clk_wzrd->base))
return PTR_ERR(clk_wzrd->base);
- ret = of_property_read_u32(np, "speed-grade", &clk_wzrd->speed_grade);
+ ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade);
if (!ret) {
if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) {
dev_warn(&pdev->dev, "invalid speed grade '%d'\n",
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index e6c831c..bae49c6 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -76,8 +76,6 @@ source "drivers/staging/gs_fpgaboot/Kconfig"
source "drivers/staging/unisys/Kconfig"
-source "drivers/staging/clocking-wizard/Kconfig"
-
source "drivers/staging/fbtft/Kconfig"
source "drivers/staging/fsl-dpaa2/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index a3b1fd0..f5a3e57 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -28,7 +28,6 @@ obj-$(CONFIG_FIREWIRE_SERIAL) += fwserial/
obj-$(CONFIG_GOLDFISH) += goldfish/
obj-$(CONFIG_GS_FPGABOOT) += gs_fpgaboot/
obj-$(CONFIG_UNISYSSPAR) += unisys/
-obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clocking-wizard/
obj-$(CONFIG_FB_TFT) += fbtft/
obj-$(CONFIG_FSL_DPAA2) += fsl-dpaa2/
obj-$(CONFIG_MOST) += most/
diff --git a/drivers/staging/clocking-wizard/Kconfig b/drivers/staging/clocking-wizard/Kconfig
deleted file mode 100644
index 69cf514..0000000
--- a/drivers/staging/clocking-wizard/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Xilinx Clocking Wizard Driver
-#
-
-config COMMON_CLK_XLNX_CLKWZRD
- tristate "Xilinx Clocking Wizard"
- depends on COMMON_CLK && OF && IOMEM
- help
- Support for the Xilinx Clocking Wizard IP core clock generator.
diff --git a/drivers/staging/clocking-wizard/Makefile b/drivers/staging/clocking-wizard/Makefile
deleted file mode 100644
index b1f9152..0000000
--- a/drivers/staging/clocking-wizard/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
diff --git a/drivers/staging/clocking-wizard/TODO b/drivers/staging/clocking-wizard/TODO
deleted file mode 100644
index ebe99db..0000000
--- a/drivers/staging/clocking-wizard/TODO
+++ /dev/null
@@ -1,12 +0,0 @@
-TODO:
- - support for fractional multiplier
- - support for fractional divider (output 0 only)
- - support for set_rate() operations (may benefit from Stephen Boyd's
- refactoring of the clk primitives: https://lkml.org/lkml/2014/9/5/766)
- - review arithmetic
- - overflow after multiplication?
- - maximize accuracy before divisions
-
-Patches to:
- Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- Sören Brinkmann <soren.brinkmann@xilinx.com>
diff --git a/drivers/staging/clocking-wizard/dt-binding.txt b/drivers/staging/clocking-wizard/dt-binding.txt
deleted file mode 100644
index efb67ff..0000000
--- a/drivers/staging/clocking-wizard/dt-binding.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-Binding for Xilinx Clocking Wizard IP Core
-
-This binding uses the common clock binding[1]. Details about the devices can be
-found in the product guide[2].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Clocking Wizard Product Guide
-https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf
-
-Required properties:
- - compatible: Must be 'xlnx,clocking-wizard'
- - reg: Base and size of the cores register space
- - clocks: Handle to input clock
- - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk'
- - clock-output-names: Names for the output clocks
-
-Optional properties:
- - speed-grade: Speed grade of the device (valid values are 1..3)
-
-Example:
- clock-generator@40040000 {
- reg = <0x40040000 0x1000>;
- compatible = "xlnx,clocking-wizard";
- speed-grade = <1>;
- clock-names = "clk_in1", "s_axi_aclk";
- clocks = <&clkc 15>, <&clkc 15>;
- clock-output-names = "clk_out0", "clk_out1", "clk_out2",
- "clk_out3", "clk_out4", "clk_out5",
- "clk_out6", "clk_out7";
- };
--
2.1.1
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v7 3/7] clk: clock-wizard: Fix kernel-doc warning
2020-11-04 15:06 ` Shubhrajyoti Datta
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
-1 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: git, devicetree, mturquette, sboyd, gregkh, devel, Shubhrajyoti Datta
Update description for the clocking wizard structure
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
drivers/clk/clk-xlnx-clock-wizard.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c
index 1bab68e..fb2d555 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -40,7 +40,8 @@ enum clk_wzrd_int_clks {
};
/**
- * struct clk_wzrd:
+ * struct clk_wzrd - Clock wizard private data structure
+ *
* @clk_data: Clock data
* @nb: Notifier block
* @base: Memory base
--
2.1.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v7 3/7] clk: clock-wizard: Fix kernel-doc warning
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
0 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: devel, devicetree, sboyd, gregkh, mturquette, Shubhrajyoti Datta, git
Update description for the clocking wizard structure
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
drivers/clk/clk-xlnx-clock-wizard.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c
index 1bab68e..fb2d555 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -40,7 +40,8 @@ enum clk_wzrd_int_clks {
};
/**
- * struct clk_wzrd:
+ * struct clk_wzrd - Clock wizard private data structure
+ *
* @clk_data: Clock data
* @nb: Notifier block
* @base: Memory base
--
2.1.1
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v7 4/7] clk: clock-wizard: Add support for dynamic reconfiguration
2020-11-04 15:06 ` Shubhrajyoti Datta
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
-1 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: git, devicetree, mturquette, sboyd, gregkh, devel,
Shubhrajyoti Datta, Chirag Parekh
The patch adds support for dynamic reconfiguration of clock output rate.
Output clocks are registered as dividers and set rate callback function
is used for dynamic reconfiguration.
Based on the initial work from Chirag.
Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
v6:
Remove the typecast.
use min for capping frequency.
use polled timeout
v7:
Use devm functions
Add the spinlock
drivers/clk/clk-xlnx-clock-wizard.c | 181 ++++++++++++++++++++++++++++++++++--
1 file changed, 175 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c
index fb2d555..5581b24 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -17,6 +17,7 @@
#include <linux/of.h>
#include <linux/module.h>
#include <linux/err.h>
+#include <linux/iopoll.h>
#define WZRD_NUM_OUTPUTS 7
#define WZRD_ACLK_MAX_FREQ 250000000UL
@@ -31,8 +32,23 @@
#define WZRD_DIVCLK_DIVIDE_SHIFT 0
#define WZRD_DIVCLK_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
#define WZRD_CLKOUT_DIVIDE_SHIFT 0
+#define WZRD_CLKOUT_DIVIDE_WIDTH 8
#define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
+#define WZRD_DR_MAX_INT_DIV_VALUE 255
+#define WZRD_DR_NUM_RETRIES 10000
+#define WZRD_DR_STATUS_REG_OFFSET 0x04
+#define WZRD_DR_LOCK_BIT_MASK 0x00000001
+#define WZRD_DR_INIT_REG_OFFSET 0x25C
+#define WZRD_DR_DIV_TO_PHASE_OFFSET 4
+#define WZRD_DR_BEGIN_DYNA_RECONF 0x03
+
+/* Get the mask from width */
+#define div_mask(width) ((1 << (width)) - 1)
+
+/* Extract divider instance from clock hardware instance */
+#define to_clk_wzrd_divider(_hw) container_of(_hw, struct clk_wzrd_divider, hw)
+
enum clk_wzrd_int_clks {
wzrd_clk_mul,
wzrd_clk_mul_div,
@@ -64,6 +80,29 @@ struct clk_wzrd {
bool suspended;
};
+/**
+ * struct clk_wzrd_divider - clock divider specific to clk_wzrd
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @base: base address of register containing the divider
+ * @offset: offset address of register containing the divider
+ * @shift: shift to the divider bit field
+ * @width: width of the divider bit field
+ * @flags: clk_wzrd divider flags
+ * @table: array of value/divider pairs, last entry should have div = 0
+ * @lock: register lock
+ */
+struct clk_wzrd_divider {
+ struct clk_hw hw;
+ void __iomem *base;
+ u16 offset;
+ u8 shift;
+ u8 width;
+ u8 flags;
+ const struct clk_div_table *table;
+ spinlock_t *lock; /* divider lock */
+};
+
#define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb)
/* maximum frequencies for input/output clocks per speed grade */
@@ -73,6 +112,132 @@ static const unsigned long clk_wzrd_max_freq[] = {
1066000000UL
};
+/* spin lock variable for clk_wzrd */
+static DEFINE_SPINLOCK(clkwzrd_lock);
+
+static unsigned long clk_wzrd_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
+ void __iomem *div_addr = divider->base + divider->offset;
+ unsigned int val;
+
+ val = readl(div_addr) >> divider->shift;
+ val &= div_mask(divider->width);
+
+ return divider_recalc_rate(hw, parent_rate, val, divider->table,
+ divider->flags, divider->width);
+}
+
+static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int err = 0;
+ u32 value;
+ unsigned long flags = 0;
+ struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
+ void __iomem *div_addr = divider->base + divider->offset;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ value = DIV_ROUND_CLOSEST(parent_rate, rate);
+
+ /* Cap the value to max */
+ min_t(u32, value, WZRD_DR_MAX_INT_DIV_VALUE);
+
+ /* Set divisor and clear phase offset */
+ writel(value, div_addr);
+ writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
+
+ /* Check status register */
+ err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
+ value, value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
+ if (err)
+ goto err_reconfig;
+
+ /* Initiate reconfiguration */
+ writel(WZRD_DR_BEGIN_DYNA_RECONF,
+ divider->base + WZRD_DR_INIT_REG_OFFSET);
+
+ /* Check status register */
+ err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
+ value, value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
+err_reconfig:
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+ return err;
+}
+
+static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ u8 div;
+
+ /*
+ * since we don't change parent rate we just round rate to closest
+ * achievable
+ */
+ div = DIV_ROUND_CLOSEST(*prate, rate);
+
+ return (*prate / div);
+}
+
+static const struct clk_ops clk_wzrd_clk_divider_ops = {
+ .round_rate = clk_wzrd_round_rate,
+ .set_rate = clk_wzrd_dynamic_reconfig,
+ .recalc_rate = clk_wzrd_recalc_rate,
+};
+
+static struct clk *clk_wzrd_register_divider(struct device *dev,
+ const char *name,
+ const char *parent_name,
+ unsigned long flags,
+ void __iomem *base, u16 offset,
+ u8 shift, u8 width,
+ u8 clk_divider_flags,
+ const struct clk_div_table *table,
+ spinlock_t *lock)
+{
+ struct clk_wzrd_divider *div;
+ struct clk_hw *hw;
+ struct clk_init_data init;
+ int ret;
+
+ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &clk_wzrd_clk_divider_ops;
+ init.flags = flags;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ div->base = base;
+ div->offset = offset;
+ div->shift = shift;
+ div->width = width;
+ div->flags = clk_divider_flags;
+ div->lock = lock;
+ div->hw.init = &init;
+ div->table = table;
+
+ /* register the clock */
+ hw = &div->hw;
+ ret = devm_clk_hw_register(dev, hw);
+ if (ret)
+ hw = ERR_PTR(ret);
+
+ return hw->clk;
+}
+
static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event,
void *data)
{
@@ -223,7 +388,8 @@ static int clk_wzrd_probe(struct platform_device *pdev)
clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_fixed_factor
(&pdev->dev, clk_name,
__clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]),
- 0, 1, reg);
+ flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ALLOW_ZERO, &clkwzrd_lock);
if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) {
dev_err(&pdev->dev, "unable to register divider clock\n");
ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]);
@@ -241,11 +407,14 @@ static int clk_wzrd_probe(struct platform_device *pdev)
ret = -EINVAL;
goto err_rm_int_clks;
}
- reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2) + i * 12);
- reg &= WZRD_CLKOUT_DIVIDE_MASK;
- reg >>= WZRD_CLKOUT_DIVIDE_SHIFT;
- clk_wzrd->clkout[i] = clk_register_fixed_factor
- (&pdev->dev, clkout_name, clk_name, 0, 1, reg);
+ clk_wzrd->clkout[i] = clk_wzrd_register_divider(&pdev->dev,
+ clkout_name,
+ clk_name, 0,
+ clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
+ WZRD_CLKOUT_DIVIDE_SHIFT,
+ WZRD_CLKOUT_DIVIDE_WIDTH,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ NULL, &clkwzrd_lock);
if (IS_ERR(clk_wzrd->clkout[i])) {
int j;
--
2.1.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v7 4/7] clk: clock-wizard: Add support for dynamic reconfiguration
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
0 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: devel, devicetree, Chirag Parekh, sboyd, gregkh, mturquette,
Shubhrajyoti Datta, git
The patch adds support for dynamic reconfiguration of clock output rate.
Output clocks are registered as dividers and set rate callback function
is used for dynamic reconfiguration.
Based on the initial work from Chirag.
Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
v6:
Remove the typecast.
use min for capping frequency.
use polled timeout
v7:
Use devm functions
Add the spinlock
drivers/clk/clk-xlnx-clock-wizard.c | 181 ++++++++++++++++++++++++++++++++++--
1 file changed, 175 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c
index fb2d555..5581b24 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -17,6 +17,7 @@
#include <linux/of.h>
#include <linux/module.h>
#include <linux/err.h>
+#include <linux/iopoll.h>
#define WZRD_NUM_OUTPUTS 7
#define WZRD_ACLK_MAX_FREQ 250000000UL
@@ -31,8 +32,23 @@
#define WZRD_DIVCLK_DIVIDE_SHIFT 0
#define WZRD_DIVCLK_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
#define WZRD_CLKOUT_DIVIDE_SHIFT 0
+#define WZRD_CLKOUT_DIVIDE_WIDTH 8
#define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
+#define WZRD_DR_MAX_INT_DIV_VALUE 255
+#define WZRD_DR_NUM_RETRIES 10000
+#define WZRD_DR_STATUS_REG_OFFSET 0x04
+#define WZRD_DR_LOCK_BIT_MASK 0x00000001
+#define WZRD_DR_INIT_REG_OFFSET 0x25C
+#define WZRD_DR_DIV_TO_PHASE_OFFSET 4
+#define WZRD_DR_BEGIN_DYNA_RECONF 0x03
+
+/* Get the mask from width */
+#define div_mask(width) ((1 << (width)) - 1)
+
+/* Extract divider instance from clock hardware instance */
+#define to_clk_wzrd_divider(_hw) container_of(_hw, struct clk_wzrd_divider, hw)
+
enum clk_wzrd_int_clks {
wzrd_clk_mul,
wzrd_clk_mul_div,
@@ -64,6 +80,29 @@ struct clk_wzrd {
bool suspended;
};
+/**
+ * struct clk_wzrd_divider - clock divider specific to clk_wzrd
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @base: base address of register containing the divider
+ * @offset: offset address of register containing the divider
+ * @shift: shift to the divider bit field
+ * @width: width of the divider bit field
+ * @flags: clk_wzrd divider flags
+ * @table: array of value/divider pairs, last entry should have div = 0
+ * @lock: register lock
+ */
+struct clk_wzrd_divider {
+ struct clk_hw hw;
+ void __iomem *base;
+ u16 offset;
+ u8 shift;
+ u8 width;
+ u8 flags;
+ const struct clk_div_table *table;
+ spinlock_t *lock; /* divider lock */
+};
+
#define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb)
/* maximum frequencies for input/output clocks per speed grade */
@@ -73,6 +112,132 @@ static const unsigned long clk_wzrd_max_freq[] = {
1066000000UL
};
+/* spin lock variable for clk_wzrd */
+static DEFINE_SPINLOCK(clkwzrd_lock);
+
+static unsigned long clk_wzrd_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
+ void __iomem *div_addr = divider->base + divider->offset;
+ unsigned int val;
+
+ val = readl(div_addr) >> divider->shift;
+ val &= div_mask(divider->width);
+
+ return divider_recalc_rate(hw, parent_rate, val, divider->table,
+ divider->flags, divider->width);
+}
+
+static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int err = 0;
+ u32 value;
+ unsigned long flags = 0;
+ struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
+ void __iomem *div_addr = divider->base + divider->offset;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ value = DIV_ROUND_CLOSEST(parent_rate, rate);
+
+ /* Cap the value to max */
+ min_t(u32, value, WZRD_DR_MAX_INT_DIV_VALUE);
+
+ /* Set divisor and clear phase offset */
+ writel(value, div_addr);
+ writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
+
+ /* Check status register */
+ err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
+ value, value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
+ if (err)
+ goto err_reconfig;
+
+ /* Initiate reconfiguration */
+ writel(WZRD_DR_BEGIN_DYNA_RECONF,
+ divider->base + WZRD_DR_INIT_REG_OFFSET);
+
+ /* Check status register */
+ err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
+ value, value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
+err_reconfig:
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+ return err;
+}
+
+static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ u8 div;
+
+ /*
+ * since we don't change parent rate we just round rate to closest
+ * achievable
+ */
+ div = DIV_ROUND_CLOSEST(*prate, rate);
+
+ return (*prate / div);
+}
+
+static const struct clk_ops clk_wzrd_clk_divider_ops = {
+ .round_rate = clk_wzrd_round_rate,
+ .set_rate = clk_wzrd_dynamic_reconfig,
+ .recalc_rate = clk_wzrd_recalc_rate,
+};
+
+static struct clk *clk_wzrd_register_divider(struct device *dev,
+ const char *name,
+ const char *parent_name,
+ unsigned long flags,
+ void __iomem *base, u16 offset,
+ u8 shift, u8 width,
+ u8 clk_divider_flags,
+ const struct clk_div_table *table,
+ spinlock_t *lock)
+{
+ struct clk_wzrd_divider *div;
+ struct clk_hw *hw;
+ struct clk_init_data init;
+ int ret;
+
+ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &clk_wzrd_clk_divider_ops;
+ init.flags = flags;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ div->base = base;
+ div->offset = offset;
+ div->shift = shift;
+ div->width = width;
+ div->flags = clk_divider_flags;
+ div->lock = lock;
+ div->hw.init = &init;
+ div->table = table;
+
+ /* register the clock */
+ hw = &div->hw;
+ ret = devm_clk_hw_register(dev, hw);
+ if (ret)
+ hw = ERR_PTR(ret);
+
+ return hw->clk;
+}
+
static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event,
void *data)
{
@@ -223,7 +388,8 @@ static int clk_wzrd_probe(struct platform_device *pdev)
clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_fixed_factor
(&pdev->dev, clk_name,
__clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]),
- 0, 1, reg);
+ flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ALLOW_ZERO, &clkwzrd_lock);
if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) {
dev_err(&pdev->dev, "unable to register divider clock\n");
ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]);
@@ -241,11 +407,14 @@ static int clk_wzrd_probe(struct platform_device *pdev)
ret = -EINVAL;
goto err_rm_int_clks;
}
- reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2) + i * 12);
- reg &= WZRD_CLKOUT_DIVIDE_MASK;
- reg >>= WZRD_CLKOUT_DIVIDE_SHIFT;
- clk_wzrd->clkout[i] = clk_register_fixed_factor
- (&pdev->dev, clkout_name, clk_name, 0, 1, reg);
+ clk_wzrd->clkout[i] = clk_wzrd_register_divider(&pdev->dev,
+ clkout_name,
+ clk_name, 0,
+ clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
+ WZRD_CLKOUT_DIVIDE_SHIFT,
+ WZRD_CLKOUT_DIVIDE_WIDTH,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ NULL, &clkwzrd_lock);
if (IS_ERR(clk_wzrd->clkout[i])) {
int j;
--
2.1.1
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v7 5/7] clk: clock-wizard: Add support for fractional support
2020-11-04 15:06 ` Shubhrajyoti Datta
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
-1 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: git, devicetree, mturquette, sboyd, gregkh, devel, Shubhrajyoti Datta
Currently the set rate granularity is to integral divisors.
Add support for the fractional divisors.
Only the first output0 is fractional in the hardware.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
v7:
Remove unnecessary comments
use mult_frac
use a common divisor function.
drivers/clk/clk-xlnx-clock-wizard.c | 219 ++++++++++++++++++++++++++++++++----
1 file changed, 199 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c
index 5581b24..ed3b0ef 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -29,20 +29,25 @@
#define WZRD_CLKFBOUT_MULT_SHIFT 8
#define WZRD_CLKFBOUT_MULT_MASK (0xff << WZRD_CLKFBOUT_MULT_SHIFT)
+#define WZRD_CLKFBOUT_FRAC_SHIFT 16
+#define WZRD_CLKFBOUT_FRAC_MASK (0x3ff << WZRD_CLKFBOUT_FRAC_SHIFT)
#define WZRD_DIVCLK_DIVIDE_SHIFT 0
#define WZRD_DIVCLK_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
#define WZRD_CLKOUT_DIVIDE_SHIFT 0
#define WZRD_CLKOUT_DIVIDE_WIDTH 8
#define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
+#define WZRD_CLKOUT_FRAC_SHIFT 8
+#define WZRD_CLKOUT_FRAC_MASK 0x3ff
#define WZRD_DR_MAX_INT_DIV_VALUE 255
-#define WZRD_DR_NUM_RETRIES 10000
#define WZRD_DR_STATUS_REG_OFFSET 0x04
#define WZRD_DR_LOCK_BIT_MASK 0x00000001
#define WZRD_DR_INIT_REG_OFFSET 0x25C
#define WZRD_DR_DIV_TO_PHASE_OFFSET 4
#define WZRD_DR_BEGIN_DYNA_RECONF 0x03
+#define WZRD_USEC_POLL 10
+#define WZRD_TIMEOUT_POLL 1000
/* Get the mask from width */
#define div_mask(width) ((1 << (width)) - 1)
@@ -52,6 +57,7 @@
enum clk_wzrd_int_clks {
wzrd_clk_mul,
wzrd_clk_mul_div,
+ wzrd_clk_mul_frac,
wzrd_clk_int_max
};
@@ -186,7 +192,7 @@ static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate,
*/
div = DIV_ROUND_CLOSEST(*prate, rate);
- return (*prate / div);
+ return *prate / div;
}
static const struct clk_ops clk_wzrd_clk_divider_ops = {
@@ -195,6 +201,117 @@ static const struct clk_ops clk_wzrd_clk_divider_ops = {
.recalc_rate = clk_wzrd_recalc_rate,
};
+static unsigned long clk_wzrd_recalc_ratef(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ unsigned int val;
+ u32 div, frac;
+ struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
+ void __iomem *div_addr = divider->base + divider->offset;
+
+ val = readl(div_addr);
+ div = val & div_mask(divider->width);
+ frac = (val >> WZRD_CLKOUT_FRAC_SHIFT) & WZRD_CLKOUT_FRAC_MASK;
+
+ return mult_frac(parent_rate, 1000, (div * 1000) + frac);
+}
+
+static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int err;
+ u32 value, pre;
+ unsigned long rate_div, f, clockout0_div;
+ struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
+ void __iomem *div_addr = divider->base + divider->offset;
+
+ rate_div = ((parent_rate * 1000) / rate);
+ clockout0_div = rate_div / 1000;
+
+ pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate);
+ f = (u32)(pre - (clockout0_div * 1000));
+ f = f & WZRD_CLKOUT_FRAC_MASK;
+ f = f << WZRD_CLKOUT_DIVIDE_WIDTH;
+
+ value = (f | (clockout0_div & WZRD_CLKOUT_DIVIDE_MASK));
+
+ /* Set divisor and clear phase offset */
+ writel(value, div_addr);
+ writel(0x0, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
+
+ /* Check status register */
+ err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
+ value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
+ if (err)
+ return err;
+
+ /* Initiate reconfiguration */
+ writel(WZRD_DR_BEGIN_DYNA_RECONF,
+ divider->base + WZRD_DR_INIT_REG_OFFSET);
+
+ /* Check status register */
+ return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
+ value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
+}
+
+static long clk_wzrd_round_rate_f(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ return rate;
+}
+
+static const struct clk_ops clk_wzrd_clk_divider_ops_f = {
+ .round_rate = clk_wzrd_round_rate_f,
+ .set_rate = clk_wzrd_dynamic_reconfig_f,
+ .recalc_rate = clk_wzrd_recalc_ratef,
+};
+
+static struct clk *clk_wzrd_register_divf(struct device *dev,
+ const char *name,
+ const char *parent_name,
+ unsigned long flags,
+ void __iomem *base, u16 offset,
+ u8 shift, u8 width,
+ u8 clk_divider_flags,
+ const struct clk_div_table *table,
+ spinlock_t *lock)
+{
+ struct clk_wzrd_divider *div;
+ struct clk_hw *hw;
+ struct clk_init_data init;
+ int ret;
+
+ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+
+ init.ops = &clk_wzrd_clk_divider_ops_f;
+
+ init.flags = flags;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ div->base = base;
+ div->offset = offset;
+ div->shift = shift;
+ div->width = width;
+ div->flags = clk_divider_flags;
+ div->lock = lock;
+ div->hw.init = &init;
+ div->table = table;
+
+ hw = &div->hw;
+ ret = devm_clk_hw_register(dev, hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return hw->clk;
+}
+
static struct clk *clk_wzrd_register_divider(struct device *dev,
const char *name,
const char *parent_name,
@@ -229,7 +346,6 @@ static struct clk *clk_wzrd_register_divider(struct device *dev,
div->hw.init = &init;
div->table = table;
- /* register the clock */
hw = &div->hw;
ret = devm_clk_hw_register(dev, hw);
if (ret)
@@ -237,7 +353,6 @@ static struct clk *clk_wzrd_register_divider(struct device *dev,
return hw->clk;
}
-
static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event,
void *data)
{
@@ -267,6 +382,61 @@ static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event,
}
}
+static int clk_wzrd_register_dividers(struct platform_device *pdev,
+ const char *clk_name)
+{
+ int i, ret;
+ struct device_node *np = pdev->dev.of_node;
+ int outputs;
+ unsigned long flags = 0;
+ struct clk_wzrd *clk_wzrd = platform_get_drvdata(pdev);
+ const char *clkout_name;
+
+ outputs = of_property_count_strings(np, "clock-output-names");
+ if (outputs == 1)
+ flags = CLK_SET_RATE_PARENT;
+
+ for (i = outputs - 1; i >= 0 ; i--) {
+ if (of_property_read_string_index(np, "clock-output-names", i,
+ &clkout_name)) {
+ dev_err(&pdev->dev,
+ "clock output name not specified\n");
+ ret = -EINVAL;
+ return ret;
+ }
+
+ if (!i)
+ clk_wzrd->clkout[i] = clk_wzrd_register_divf
+ (&pdev->dev, clkout_name,
+ clk_name, flags,
+ clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
+ WZRD_CLKOUT_DIVIDE_SHIFT,
+ WZRD_CLKOUT_DIVIDE_WIDTH,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ NULL, &clkwzrd_lock);
+ else
+ clk_wzrd->clkout[i] = clk_wzrd_register_divider
+ (&pdev->dev, clkout_name,
+ clk_name, 0,
+ clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
+ WZRD_CLKOUT_DIVIDE_SHIFT,
+ WZRD_CLKOUT_DIVIDE_WIDTH,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ NULL, &clkwzrd_lock);
+
+ if (IS_ERR(clk_wzrd->clkout[i])) {
+ int j;
+
+ for (j = i + 1; j < outputs; j++)
+ clk_unregister(clk_wzrd->clkout[j]);
+ dev_err(&pdev->dev,
+ "unable to register divider clock\n");
+ ret = PTR_ERR(clk_wzrd->clkout[i]);
+ return ret;
+ }
+ }
+ return 0;
+}
static int __maybe_unused clk_wzrd_suspend(struct device *dev)
{
struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
@@ -298,8 +468,8 @@ static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend,
static int clk_wzrd_probe(struct platform_device *pdev)
{
- int i, ret;
- u32 reg;
+ int ret;
+ u32 reg, reg_f, mult;
unsigned long rate;
const char *clk_name;
struct clk_wzrd *clk_wzrd;
@@ -349,17 +519,13 @@ static int clk_wzrd_probe(struct platform_device *pdev)
goto err_disable_clk;
}
- /* we don't support fractional div/mul yet */
- reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
- WZRD_CLKFBOUT_FRAC_EN;
- reg |= readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2)) &
- WZRD_CLKOUT0_FRAC_EN;
- if (reg)
- dev_warn(&pdev->dev, "fractional div/mul not supported\n");
+ reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0));
+ reg_f = reg & WZRD_CLKFBOUT_FRAC_MASK;
+ reg_f = reg_f >> WZRD_CLKFBOUT_FRAC_SHIFT;
- /* register multiplier */
- reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
- WZRD_CLKFBOUT_MULT_MASK) >> WZRD_CLKFBOUT_MULT_SHIFT;
+ reg = reg & WZRD_CLKFBOUT_MULT_MASK;
+ reg = reg >> WZRD_CLKFBOUT_MULT_SHIFT;
+ mult = (reg * 1000) + reg_f;
clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev));
if (!clk_name) {
ret = -ENOMEM;
@@ -368,8 +534,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor
(&pdev->dev, clk_name,
__clk_get_name(clk_wzrd->clk_in1),
- 0, reg, 1);
- kfree(clk_name);
+ 0, mult, 1000);
if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) {
dev_err(&pdev->dev, "unable to register fixed-factor clock\n");
ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]);
@@ -407,8 +572,18 @@ static int clk_wzrd_probe(struct platform_device *pdev)
ret = -EINVAL;
goto err_rm_int_clks;
}
- clk_wzrd->clkout[i] = clk_wzrd_register_divider(&pdev->dev,
- clkout_name,
+ if (!i)
+ clk_wzrd->clkout[i] = clk_wzrd_register_divf
+ (&pdev->dev, clkout_name,
+ clk_name, 0,
+ clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
+ WZRD_CLKOUT_DIVIDE_SHIFT,
+ WZRD_CLKOUT_DIVIDE_WIDTH,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ NULL, &clkwzrd_lock);
+ else
+ clk_wzrd->clkout[i] = clk_wzrd_register_divider
+ (&pdev->dev, clkout_name,
clk_name, 0,
clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
WZRD_CLKOUT_DIVIDE_SHIFT,
@@ -427,6 +602,10 @@ static int clk_wzrd_probe(struct platform_device *pdev)
}
}
+ ret = clk_wzrd_register_dividers(pdev, clk_name);
+ if (ret)
+ goto err_rm_int_clks;
+
kfree(clk_name);
clk_wzrd->clk_data.clks = clk_wzrd->clkout;
--
2.1.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v7 5/7] clk: clock-wizard: Add support for fractional support
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
0 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: devel, devicetree, sboyd, gregkh, mturquette, Shubhrajyoti Datta, git
Currently the set rate granularity is to integral divisors.
Add support for the fractional divisors.
Only the first output0 is fractional in the hardware.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
v7:
Remove unnecessary comments
use mult_frac
use a common divisor function.
drivers/clk/clk-xlnx-clock-wizard.c | 219 ++++++++++++++++++++++++++++++++----
1 file changed, 199 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c
index 5581b24..ed3b0ef 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -29,20 +29,25 @@
#define WZRD_CLKFBOUT_MULT_SHIFT 8
#define WZRD_CLKFBOUT_MULT_MASK (0xff << WZRD_CLKFBOUT_MULT_SHIFT)
+#define WZRD_CLKFBOUT_FRAC_SHIFT 16
+#define WZRD_CLKFBOUT_FRAC_MASK (0x3ff << WZRD_CLKFBOUT_FRAC_SHIFT)
#define WZRD_DIVCLK_DIVIDE_SHIFT 0
#define WZRD_DIVCLK_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
#define WZRD_CLKOUT_DIVIDE_SHIFT 0
#define WZRD_CLKOUT_DIVIDE_WIDTH 8
#define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
+#define WZRD_CLKOUT_FRAC_SHIFT 8
+#define WZRD_CLKOUT_FRAC_MASK 0x3ff
#define WZRD_DR_MAX_INT_DIV_VALUE 255
-#define WZRD_DR_NUM_RETRIES 10000
#define WZRD_DR_STATUS_REG_OFFSET 0x04
#define WZRD_DR_LOCK_BIT_MASK 0x00000001
#define WZRD_DR_INIT_REG_OFFSET 0x25C
#define WZRD_DR_DIV_TO_PHASE_OFFSET 4
#define WZRD_DR_BEGIN_DYNA_RECONF 0x03
+#define WZRD_USEC_POLL 10
+#define WZRD_TIMEOUT_POLL 1000
/* Get the mask from width */
#define div_mask(width) ((1 << (width)) - 1)
@@ -52,6 +57,7 @@
enum clk_wzrd_int_clks {
wzrd_clk_mul,
wzrd_clk_mul_div,
+ wzrd_clk_mul_frac,
wzrd_clk_int_max
};
@@ -186,7 +192,7 @@ static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate,
*/
div = DIV_ROUND_CLOSEST(*prate, rate);
- return (*prate / div);
+ return *prate / div;
}
static const struct clk_ops clk_wzrd_clk_divider_ops = {
@@ -195,6 +201,117 @@ static const struct clk_ops clk_wzrd_clk_divider_ops = {
.recalc_rate = clk_wzrd_recalc_rate,
};
+static unsigned long clk_wzrd_recalc_ratef(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ unsigned int val;
+ u32 div, frac;
+ struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
+ void __iomem *div_addr = divider->base + divider->offset;
+
+ val = readl(div_addr);
+ div = val & div_mask(divider->width);
+ frac = (val >> WZRD_CLKOUT_FRAC_SHIFT) & WZRD_CLKOUT_FRAC_MASK;
+
+ return mult_frac(parent_rate, 1000, (div * 1000) + frac);
+}
+
+static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int err;
+ u32 value, pre;
+ unsigned long rate_div, f, clockout0_div;
+ struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
+ void __iomem *div_addr = divider->base + divider->offset;
+
+ rate_div = ((parent_rate * 1000) / rate);
+ clockout0_div = rate_div / 1000;
+
+ pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate);
+ f = (u32)(pre - (clockout0_div * 1000));
+ f = f & WZRD_CLKOUT_FRAC_MASK;
+ f = f << WZRD_CLKOUT_DIVIDE_WIDTH;
+
+ value = (f | (clockout0_div & WZRD_CLKOUT_DIVIDE_MASK));
+
+ /* Set divisor and clear phase offset */
+ writel(value, div_addr);
+ writel(0x0, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
+
+ /* Check status register */
+ err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
+ value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
+ if (err)
+ return err;
+
+ /* Initiate reconfiguration */
+ writel(WZRD_DR_BEGIN_DYNA_RECONF,
+ divider->base + WZRD_DR_INIT_REG_OFFSET);
+
+ /* Check status register */
+ return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
+ value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
+}
+
+static long clk_wzrd_round_rate_f(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ return rate;
+}
+
+static const struct clk_ops clk_wzrd_clk_divider_ops_f = {
+ .round_rate = clk_wzrd_round_rate_f,
+ .set_rate = clk_wzrd_dynamic_reconfig_f,
+ .recalc_rate = clk_wzrd_recalc_ratef,
+};
+
+static struct clk *clk_wzrd_register_divf(struct device *dev,
+ const char *name,
+ const char *parent_name,
+ unsigned long flags,
+ void __iomem *base, u16 offset,
+ u8 shift, u8 width,
+ u8 clk_divider_flags,
+ const struct clk_div_table *table,
+ spinlock_t *lock)
+{
+ struct clk_wzrd_divider *div;
+ struct clk_hw *hw;
+ struct clk_init_data init;
+ int ret;
+
+ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+
+ init.ops = &clk_wzrd_clk_divider_ops_f;
+
+ init.flags = flags;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ div->base = base;
+ div->offset = offset;
+ div->shift = shift;
+ div->width = width;
+ div->flags = clk_divider_flags;
+ div->lock = lock;
+ div->hw.init = &init;
+ div->table = table;
+
+ hw = &div->hw;
+ ret = devm_clk_hw_register(dev, hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return hw->clk;
+}
+
static struct clk *clk_wzrd_register_divider(struct device *dev,
const char *name,
const char *parent_name,
@@ -229,7 +346,6 @@ static struct clk *clk_wzrd_register_divider(struct device *dev,
div->hw.init = &init;
div->table = table;
- /* register the clock */
hw = &div->hw;
ret = devm_clk_hw_register(dev, hw);
if (ret)
@@ -237,7 +353,6 @@ static struct clk *clk_wzrd_register_divider(struct device *dev,
return hw->clk;
}
-
static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event,
void *data)
{
@@ -267,6 +382,61 @@ static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event,
}
}
+static int clk_wzrd_register_dividers(struct platform_device *pdev,
+ const char *clk_name)
+{
+ int i, ret;
+ struct device_node *np = pdev->dev.of_node;
+ int outputs;
+ unsigned long flags = 0;
+ struct clk_wzrd *clk_wzrd = platform_get_drvdata(pdev);
+ const char *clkout_name;
+
+ outputs = of_property_count_strings(np, "clock-output-names");
+ if (outputs == 1)
+ flags = CLK_SET_RATE_PARENT;
+
+ for (i = outputs - 1; i >= 0 ; i--) {
+ if (of_property_read_string_index(np, "clock-output-names", i,
+ &clkout_name)) {
+ dev_err(&pdev->dev,
+ "clock output name not specified\n");
+ ret = -EINVAL;
+ return ret;
+ }
+
+ if (!i)
+ clk_wzrd->clkout[i] = clk_wzrd_register_divf
+ (&pdev->dev, clkout_name,
+ clk_name, flags,
+ clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
+ WZRD_CLKOUT_DIVIDE_SHIFT,
+ WZRD_CLKOUT_DIVIDE_WIDTH,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ NULL, &clkwzrd_lock);
+ else
+ clk_wzrd->clkout[i] = clk_wzrd_register_divider
+ (&pdev->dev, clkout_name,
+ clk_name, 0,
+ clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
+ WZRD_CLKOUT_DIVIDE_SHIFT,
+ WZRD_CLKOUT_DIVIDE_WIDTH,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ NULL, &clkwzrd_lock);
+
+ if (IS_ERR(clk_wzrd->clkout[i])) {
+ int j;
+
+ for (j = i + 1; j < outputs; j++)
+ clk_unregister(clk_wzrd->clkout[j]);
+ dev_err(&pdev->dev,
+ "unable to register divider clock\n");
+ ret = PTR_ERR(clk_wzrd->clkout[i]);
+ return ret;
+ }
+ }
+ return 0;
+}
static int __maybe_unused clk_wzrd_suspend(struct device *dev)
{
struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
@@ -298,8 +468,8 @@ static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend,
static int clk_wzrd_probe(struct platform_device *pdev)
{
- int i, ret;
- u32 reg;
+ int ret;
+ u32 reg, reg_f, mult;
unsigned long rate;
const char *clk_name;
struct clk_wzrd *clk_wzrd;
@@ -349,17 +519,13 @@ static int clk_wzrd_probe(struct platform_device *pdev)
goto err_disable_clk;
}
- /* we don't support fractional div/mul yet */
- reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
- WZRD_CLKFBOUT_FRAC_EN;
- reg |= readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2)) &
- WZRD_CLKOUT0_FRAC_EN;
- if (reg)
- dev_warn(&pdev->dev, "fractional div/mul not supported\n");
+ reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0));
+ reg_f = reg & WZRD_CLKFBOUT_FRAC_MASK;
+ reg_f = reg_f >> WZRD_CLKFBOUT_FRAC_SHIFT;
- /* register multiplier */
- reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
- WZRD_CLKFBOUT_MULT_MASK) >> WZRD_CLKFBOUT_MULT_SHIFT;
+ reg = reg & WZRD_CLKFBOUT_MULT_MASK;
+ reg = reg >> WZRD_CLKFBOUT_MULT_SHIFT;
+ mult = (reg * 1000) + reg_f;
clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev));
if (!clk_name) {
ret = -ENOMEM;
@@ -368,8 +534,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor
(&pdev->dev, clk_name,
__clk_get_name(clk_wzrd->clk_in1),
- 0, reg, 1);
- kfree(clk_name);
+ 0, mult, 1000);
if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) {
dev_err(&pdev->dev, "unable to register fixed-factor clock\n");
ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]);
@@ -407,8 +572,18 @@ static int clk_wzrd_probe(struct platform_device *pdev)
ret = -EINVAL;
goto err_rm_int_clks;
}
- clk_wzrd->clkout[i] = clk_wzrd_register_divider(&pdev->dev,
- clkout_name,
+ if (!i)
+ clk_wzrd->clkout[i] = clk_wzrd_register_divf
+ (&pdev->dev, clkout_name,
+ clk_name, 0,
+ clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
+ WZRD_CLKOUT_DIVIDE_SHIFT,
+ WZRD_CLKOUT_DIVIDE_WIDTH,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ NULL, &clkwzrd_lock);
+ else
+ clk_wzrd->clkout[i] = clk_wzrd_register_divider
+ (&pdev->dev, clkout_name,
clk_name, 0,
clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
WZRD_CLKOUT_DIVIDE_SHIFT,
@@ -427,6 +602,10 @@ static int clk_wzrd_probe(struct platform_device *pdev)
}
}
+ ret = clk_wzrd_register_dividers(pdev, clk_name);
+ if (ret)
+ goto err_rm_int_clks;
+
kfree(clk_name);
clk_wzrd->clk_data.clks = clk_wzrd->clkout;
--
2.1.1
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v7 6/7] clk: clock-wizard: Remove the hardcoding of the clock outputs
2020-11-04 15:06 ` Shubhrajyoti Datta
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
-1 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: git, devicetree, mturquette, sboyd, gregkh, devel, Shubhrajyoti Datta
The number of output clocks are configurable in the hardware.
Currently the driver registers the maximum number of outputs.
Fix the same by registering only the outputs that are there.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
v4:
Assign output in this patch
drivers/clk/clk-xlnx-clock-wizard.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c
index ed3b0ef..d403a74 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -473,6 +473,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
unsigned long rate;
const char *clk_name;
struct clk_wzrd *clk_wzrd;
+ int outputs;
struct device_node *np = pdev->dev.of_node;
clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL);
@@ -541,6 +542,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
goto err_disable_clk;
}
+ outputs = of_property_count_strings(np, "clock-output-names");
/* register div */
reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT;
@@ -562,7 +564,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
}
/* register div per output */
- for (i = WZRD_NUM_OUTPUTS - 1; i >= 0 ; i--) {
+ for (i = outputs - 1; i >= 0 ; i--) {
const char *clkout_name;
if (of_property_read_string_index(np, "clock-output-names", i,
@@ -593,7 +595,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
if (IS_ERR(clk_wzrd->clkout[i])) {
int j;
- for (j = i + 1; j < WZRD_NUM_OUTPUTS; j++)
+ for (j = i + 1; j < outputs; j++)
clk_unregister(clk_wzrd->clkout[j]);
dev_err(&pdev->dev,
"unable to register divider clock\n");
--
2.1.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v7 6/7] clk: clock-wizard: Remove the hardcoding of the clock outputs
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
0 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: devel, devicetree, sboyd, gregkh, mturquette, Shubhrajyoti Datta, git
The number of output clocks are configurable in the hardware.
Currently the driver registers the maximum number of outputs.
Fix the same by registering only the outputs that are there.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
v4:
Assign output in this patch
drivers/clk/clk-xlnx-clock-wizard.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c
index ed3b0ef..d403a74 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -473,6 +473,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
unsigned long rate;
const char *clk_name;
struct clk_wzrd *clk_wzrd;
+ int outputs;
struct device_node *np = pdev->dev.of_node;
clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL);
@@ -541,6 +542,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
goto err_disable_clk;
}
+ outputs = of_property_count_strings(np, "clock-output-names");
/* register div */
reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT;
@@ -562,7 +564,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
}
/* register div per output */
- for (i = WZRD_NUM_OUTPUTS - 1; i >= 0 ; i--) {
+ for (i = outputs - 1; i >= 0 ; i--) {
const char *clkout_name;
if (of_property_read_string_index(np, "clock-output-names", i,
@@ -593,7 +595,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
if (IS_ERR(clk_wzrd->clkout[i])) {
int j;
- for (j = i + 1; j < WZRD_NUM_OUTPUTS; j++)
+ for (j = i + 1; j < outputs; j++)
clk_unregister(clk_wzrd->clkout[j]);
dev_err(&pdev->dev,
"unable to register divider clock\n");
--
2.1.1
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v7 7/7] clk: clock-wizard: Update the fixed factor divisors
2020-11-04 15:06 ` Shubhrajyoti Datta
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
-1 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: git, devicetree, mturquette, sboyd, gregkh, devel, Shubhrajyoti Datta
Update the fixed factor clock registration to register the divisors.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
drivers/clk/clk-xlnx-clock-wizard.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c
index d403a74..7f09522 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -472,8 +472,10 @@ static int clk_wzrd_probe(struct platform_device *pdev)
u32 reg, reg_f, mult;
unsigned long rate;
const char *clk_name;
+ void __iomem *ctrl_reg;
struct clk_wzrd *clk_wzrd;
int outputs;
+ unsigned long flags = 0;
struct device_node *np = pdev->dev.of_node;
clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL);
@@ -543,16 +545,17 @@ static int clk_wzrd_probe(struct platform_device *pdev)
}
outputs = of_property_count_strings(np, "clock-output-names");
- /* register div */
- reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
- WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT;
+ if (outputs == 1)
+ flags = CLK_SET_RATE_PARENT;
clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev));
if (!clk_name) {
ret = -ENOMEM;
goto err_rm_int_clk;
}
- clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_fixed_factor
+ ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(0);
+ /* register div */
+ clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_divider
(&pdev->dev, clk_name,
__clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]),
flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED |
@@ -577,7 +580,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
if (!i)
clk_wzrd->clkout[i] = clk_wzrd_register_divf
(&pdev->dev, clkout_name,
- clk_name, 0,
+ clk_name, flags,
clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
WZRD_CLKOUT_DIVIDE_SHIFT,
WZRD_CLKOUT_DIVIDE_WIDTH,
--
2.1.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v7 7/7] clk: clock-wizard: Update the fixed factor divisors
@ 2020-11-04 15:06 ` Shubhrajyoti Datta
0 siblings, 0 replies; 32+ messages in thread
From: Shubhrajyoti Datta @ 2020-11-04 15:06 UTC (permalink / raw)
To: linux-clk
Cc: devel, devicetree, sboyd, gregkh, mturquette, Shubhrajyoti Datta, git
Update the fixed factor clock registration to register the divisors.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
drivers/clk/clk-xlnx-clock-wizard.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c
index d403a74..7f09522 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -472,8 +472,10 @@ static int clk_wzrd_probe(struct platform_device *pdev)
u32 reg, reg_f, mult;
unsigned long rate;
const char *clk_name;
+ void __iomem *ctrl_reg;
struct clk_wzrd *clk_wzrd;
int outputs;
+ unsigned long flags = 0;
struct device_node *np = pdev->dev.of_node;
clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL);
@@ -543,16 +545,17 @@ static int clk_wzrd_probe(struct platform_device *pdev)
}
outputs = of_property_count_strings(np, "clock-output-names");
- /* register div */
- reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
- WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT;
+ if (outputs == 1)
+ flags = CLK_SET_RATE_PARENT;
clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev));
if (!clk_name) {
ret = -ENOMEM;
goto err_rm_int_clk;
}
- clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_fixed_factor
+ ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(0);
+ /* register div */
+ clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_divider
(&pdev->dev, clk_name,
__clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]),
flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED |
@@ -577,7 +580,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
if (!i)
clk_wzrd->clkout[i] = clk_wzrd_register_divf
(&pdev->dev, clkout_name,
- clk_name, 0,
+ clk_name, flags,
clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
WZRD_CLKOUT_DIVIDE_SHIFT,
WZRD_CLKOUT_DIVIDE_WIDTH,
--
2.1.1
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v7 1/7] dt-bindings: add documentation of xilinx clocking wizard
2020-11-04 15:06 ` Shubhrajyoti Datta
@ 2020-11-04 19:11 ` Rob Herring
-1 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2020-11-04 19:11 UTC (permalink / raw)
To: Shubhrajyoti Datta
Cc: git, mturquette, sboyd, devicetree, gregkh, devel, linux-clk
On Wed, 04 Nov 2020 20:36:41 +0530, Shubhrajyoti Datta wrote:
> Add the devicetree binding for the xilinx clocking wizard.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> ---
> v6:
> Fix a yaml warning
> v7:
> Add vendor prefix speed-grade
>
> .../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
./Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml:21:7: [warning] wrong indentation: expected 4 but found 6 (indentation)
./Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml:38:7: [warning] wrong indentation: expected 4 but found 6 (indentation)
./Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml:40:5: [error] syntax error: expected <block end>, but found '<block mapping start>' (syntax)
dtschema/dtc warnings/errors:
Traceback (most recent call last):
File "/usr/local/bin/dt-extract-example", line 45, in <module>
binding = yaml.load(open(args.yamlfile, encoding='utf-8').read())
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 343, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 111, in get_single_data
node = self.composer.get_single_node()
File "_ruamel_yaml.pyx", line 706, in _ruamel_yaml.CParser.get_single_node
File "_ruamel_yaml.pyx", line 724, in _ruamel_yaml.CParser._compose_document
File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 891, in _ruamel_yaml.CParser._compose_mapping_node
File "_ruamel_yaml.pyx", line 904, in _ruamel_yaml.CParser._parse_next_event
ruamel.yaml.parser.ParserError: while parsing a block mapping
in "<unicode string>", line 20, column 3
did not find expected key
in "<unicode string>", line 40, column 5
make[1]: *** [Documentation/devicetree/bindings/Makefile:20: Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.example.dts] Error 1
make[1]: *** Deleting file 'Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.example.dts'
make[1]: *** Waiting for unfinished jobs....
make[1]: *** [Documentation/devicetree/bindings/Makefile:59: Documentation/devicetree/bindings/processed-schema-examples.json] Error 123
make: *** [Makefile:1364: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1394053
The base for the patch is generally the last rc1. Any dependencies
should be noted.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 1/7] dt-bindings: add documentation of xilinx clocking wizard
@ 2020-11-04 19:11 ` Rob Herring
0 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2020-11-04 19:11 UTC (permalink / raw)
To: Shubhrajyoti Datta
Cc: devel, devicetree, sboyd, gregkh, mturquette, git, linux-clk
On Wed, 04 Nov 2020 20:36:41 +0530, Shubhrajyoti Datta wrote:
> Add the devicetree binding for the xilinx clocking wizard.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> ---
> v6:
> Fix a yaml warning
> v7:
> Add vendor prefix speed-grade
>
> .../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
./Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml:21:7: [warning] wrong indentation: expected 4 but found 6 (indentation)
./Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml:38:7: [warning] wrong indentation: expected 4 but found 6 (indentation)
./Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml:40:5: [error] syntax error: expected <block end>, but found '<block mapping start>' (syntax)
dtschema/dtc warnings/errors:
Traceback (most recent call last):
File "/usr/local/bin/dt-extract-example", line 45, in <module>
binding = yaml.load(open(args.yamlfile, encoding='utf-8').read())
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 343, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 111, in get_single_data
node = self.composer.get_single_node()
File "_ruamel_yaml.pyx", line 706, in _ruamel_yaml.CParser.get_single_node
File "_ruamel_yaml.pyx", line 724, in _ruamel_yaml.CParser._compose_document
File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 891, in _ruamel_yaml.CParser._compose_mapping_node
File "_ruamel_yaml.pyx", line 904, in _ruamel_yaml.CParser._parse_next_event
ruamel.yaml.parser.ParserError: while parsing a block mapping
in "<unicode string>", line 20, column 3
did not find expected key
in "<unicode string>", line 40, column 5
make[1]: *** [Documentation/devicetree/bindings/Makefile:20: Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.example.dts] Error 1
make[1]: *** Deleting file 'Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.example.dts'
make[1]: *** Waiting for unfinished jobs....
make[1]: *** [Documentation/devicetree/bindings/Makefile:59: Documentation/devicetree/bindings/processed-schema-examples.json] Error 123
make: *** [Makefile:1364: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1394053
The base for the patch is generally the last rc1. Any dependencies
should be noted.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 1/7] dt-bindings: add documentation of xilinx clocking wizard
2020-11-04 15:06 ` Shubhrajyoti Datta
@ 2020-11-04 19:15 ` Rob Herring
-1 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2020-11-04 19:15 UTC (permalink / raw)
To: Shubhrajyoti Datta
Cc: linux-clk, git, devicetree, mturquette, sboyd, gregkh, devel
On Wed, Nov 04, 2020 at 08:36:41PM +0530, Shubhrajyoti Datta wrote:
> Add the devicetree binding for the xilinx clocking wizard.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> ---
> v6:
> Fix a yaml warning
> v7:
> Add vendor prefix speed-grade
>
> .../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> new file mode 100644
> index 0000000..a19b9bb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx clocking wizard
> +
> +maintainers:
> + - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> +
> +description: |
> + The clocking wizard is a soft ip clocking block of Xilinx versal. It
> + reads required input clock frequencies from the devicetree and acts as clock
> + clock output.
> +
> +select: false
Why? That's one way to make the example pass with your schema...
> +
> +properties:
> + compatible:
> + - enum:
> + - xlnx,clocking-wizard
> +
> + "#clock-cells":
> + const: 1
> +
> + clocks:
> + items:
> + - description: clock input
> + - description: axi clock
> +
> + clock-names:
> + items:
> + - const: clk_in1
> + - const: s_axi_aclk
> +
> + xlnx,speed-grade:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [1, 2, 3]
> + description:
> + Speed grade of the device.
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - clocks
> + - clock-names
> + - speed-grade
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-generator@40040000 {
> + #clock-cells = <1>;
> + reg = <0x40040000 0x1000>;
> + compatible = "xlnx,clocking-wizard";
> + xlnx,speed-grade = <1>;
> + clock-names = "clk_in1", "s_axi_aclk";
> + clocks = <&clkc 15>, <&clkc 15>;
> + clock-output-names = "clk_out1", "clk_out2",
> + "clk_out3", "clk_out4", "clk_out5",
> + "clk_out6", "clk_out7";
> + };
> +...
> --
> 2.1.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 1/7] dt-bindings: add documentation of xilinx clocking wizard
@ 2020-11-04 19:15 ` Rob Herring
0 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2020-11-04 19:15 UTC (permalink / raw)
To: Shubhrajyoti Datta
Cc: devel, devicetree, sboyd, gregkh, mturquette, git, linux-clk
On Wed, Nov 04, 2020 at 08:36:41PM +0530, Shubhrajyoti Datta wrote:
> Add the devicetree binding for the xilinx clocking wizard.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> ---
> v6:
> Fix a yaml warning
> v7:
> Add vendor prefix speed-grade
>
> .../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> new file mode 100644
> index 0000000..a19b9bb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx clocking wizard
> +
> +maintainers:
> + - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> +
> +description: |
> + The clocking wizard is a soft ip clocking block of Xilinx versal. It
> + reads required input clock frequencies from the devicetree and acts as clock
> + clock output.
> +
> +select: false
Why? That's one way to make the example pass with your schema...
> +
> +properties:
> + compatible:
> + - enum:
> + - xlnx,clocking-wizard
> +
> + "#clock-cells":
> + const: 1
> +
> + clocks:
> + items:
> + - description: clock input
> + - description: axi clock
> +
> + clock-names:
> + items:
> + - const: clk_in1
> + - const: s_axi_aclk
> +
> + xlnx,speed-grade:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [1, 2, 3]
> + description:
> + Speed grade of the device.
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - clocks
> + - clock-names
> + - speed-grade
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-generator@40040000 {
> + #clock-cells = <1>;
> + reg = <0x40040000 0x1000>;
> + compatible = "xlnx,clocking-wizard";
> + xlnx,speed-grade = <1>;
> + clock-names = "clk_in1", "s_axi_aclk";
> + clocks = <&clkc 15>, <&clkc 15>;
> + clock-output-names = "clk_out1", "clk_out2",
> + "clk_out3", "clk_out4", "clk_out5",
> + "clk_out6", "clk_out7";
> + };
> +...
> --
> 2.1.1
>
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
2020-11-04 15:06 ` Shubhrajyoti Datta
@ 2020-12-13 5:36 ` Stephen Boyd
-1 siblings, 0 replies; 32+ messages in thread
From: Stephen Boyd @ 2020-12-13 5:36 UTC (permalink / raw)
To: Shubhrajyoti Datta, linux-clk
Cc: git, devicetree, mturquette, gregkh, devel, Shubhrajyoti Datta
Quoting Shubhrajyoti Datta (2020-11-04 07:06:40)
>
> Shubhrajyoti Datta (7):
> dt-bindings: add documentation of xilinx clocking wizard
Any chance to respond to Robs comments?
> clk: clock-wizard: Add the clockwizard to clk directory
Is it called 'wizard' anywhere in the documentation? I wonder if there
is a better name that could be found for this.
> clk: clock-wizard: Fix kernel-doc warning
> clk: clock-wizard: Add support for dynamic reconfiguration
> clk: clock-wizard: Add support for fractional support
> clk: clock-wizard: Remove the hardcoding of the clock outputs
> clk: clock-wizard: Update the fixed factor divisors
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
@ 2020-12-13 5:36 ` Stephen Boyd
0 siblings, 0 replies; 32+ messages in thread
From: Stephen Boyd @ 2020-12-13 5:36 UTC (permalink / raw)
To: Shubhrajyoti Datta, linux-clk
Cc: devel, devicetree, gregkh, mturquette, Shubhrajyoti Datta, git
Quoting Shubhrajyoti Datta (2020-11-04 07:06:40)
>
> Shubhrajyoti Datta (7):
> dt-bindings: add documentation of xilinx clocking wizard
Any chance to respond to Robs comments?
> clk: clock-wizard: Add the clockwizard to clk directory
Is it called 'wizard' anywhere in the documentation? I wonder if there
is a better name that could be found for this.
> clk: clock-wizard: Fix kernel-doc warning
> clk: clock-wizard: Add support for dynamic reconfiguration
> clk: clock-wizard: Add support for fractional support
> clk: clock-wizard: Remove the hardcoding of the clock outputs
> clk: clock-wizard: Update the fixed factor divisors
>
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
2020-11-04 15:06 ` Shubhrajyoti Datta
@ 2020-12-15 9:13 ` Michal Simek
-1 siblings, 0 replies; 32+ messages in thread
From: Michal Simek @ 2020-12-15 9:13 UTC (permalink / raw)
To: Shubhrajyoti Datta, linux-clk, Stephen Boyd
Cc: git, devicetree, mturquette, gregkh, devel
Hi Stephen,
On 04. 11. 20 16:06, Shubhrajyoti Datta wrote:
>
> In the thread [1] Greg suggested that we move the driver
> to the clk from the staging.
> Add patches to address the concerns regarding the fractional and
> set rate support in the TODO.
>
> The patch set does the following
> - Trivial fixes for kernel doc.
> - Move the driver to the clk folder
> - Add capability to set rate.
> - Add fractional support.
> - Add support for configurable outputs.
> - Make the output names unique so that multiple instances
> do not crib.
>
> Changes in the v3:
> Added the cover-letter.
> Add patches for rate setting and fractional support
> Add patches for warning.
> Remove the driver from staging as suggested
>
> v4:
> Reorder the patches.
> Merge the CLK_IS_BASIC patch.
> Add the yaml form of binding document
>
> v5:
> Fix a mismerge
>
> v6:
> Fix the yaml warning
> use poll timedout
>
> v7:
> Binding doc updates
> Use common divisor function.
>
> [1] https://spinics.net/lists/linux-driver-devel/msg117326.html
>
> Shubhrajyoti Datta (7):
> dt-bindings: add documentation of xilinx clocking wizard
> clk: clock-wizard: Add the clockwizard to clk directory
> clk: clock-wizard: Fix kernel-doc warning
> clk: clock-wizard: Add support for dynamic reconfiguration
> clk: clock-wizard: Add support for fractional support
> clk: clock-wizard: Remove the hardcoding of the clock outputs
> clk: clock-wizard: Update the fixed factor divisors
>
> .../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++
> drivers/clk/Kconfig | 9 +
> drivers/clk/Makefile | 1 +
> drivers/clk/clk-xlnx-clock-wizard.c | 689 +++++++++++++++++++++
> drivers/staging/Kconfig | 2 -
> drivers/staging/Makefile | 1 -
> drivers/staging/clocking-wizard/Kconfig | 10 -
> drivers/staging/clocking-wizard/Makefile | 2 -
> drivers/staging/clocking-wizard/TODO | 12 -
> .../clocking-wizard/clk-xlnx-clock-wizard.c | 333 ----------
> drivers/staging/clocking-wizard/dt-binding.txt | 30 -
> 11 files changed, 764 insertions(+), 390 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c
> delete mode 100644 drivers/staging/clocking-wizard/Kconfig
> delete mode 100644 drivers/staging/clocking-wizard/Makefile
> delete mode 100644 drivers/staging/clocking-wizard/TODO
> delete mode 100644 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
> delete mode 100644 drivers/staging/clocking-wizard/dt-binding.txt
>
Can you please take a look at this series?
Thanks,
Michal
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
@ 2020-12-15 9:13 ` Michal Simek
0 siblings, 0 replies; 32+ messages in thread
From: Michal Simek @ 2020-12-15 9:13 UTC (permalink / raw)
To: Shubhrajyoti Datta, linux-clk, Stephen Boyd
Cc: devel, devicetree, mturquette, git, gregkh
Hi Stephen,
On 04. 11. 20 16:06, Shubhrajyoti Datta wrote:
>
> In the thread [1] Greg suggested that we move the driver
> to the clk from the staging.
> Add patches to address the concerns regarding the fractional and
> set rate support in the TODO.
>
> The patch set does the following
> - Trivial fixes for kernel doc.
> - Move the driver to the clk folder
> - Add capability to set rate.
> - Add fractional support.
> - Add support for configurable outputs.
> - Make the output names unique so that multiple instances
> do not crib.
>
> Changes in the v3:
> Added the cover-letter.
> Add patches for rate setting and fractional support
> Add patches for warning.
> Remove the driver from staging as suggested
>
> v4:
> Reorder the patches.
> Merge the CLK_IS_BASIC patch.
> Add the yaml form of binding document
>
> v5:
> Fix a mismerge
>
> v6:
> Fix the yaml warning
> use poll timedout
>
> v7:
> Binding doc updates
> Use common divisor function.
>
> [1] https://spinics.net/lists/linux-driver-devel/msg117326.html
>
> Shubhrajyoti Datta (7):
> dt-bindings: add documentation of xilinx clocking wizard
> clk: clock-wizard: Add the clockwizard to clk directory
> clk: clock-wizard: Fix kernel-doc warning
> clk: clock-wizard: Add support for dynamic reconfiguration
> clk: clock-wizard: Add support for fractional support
> clk: clock-wizard: Remove the hardcoding of the clock outputs
> clk: clock-wizard: Update the fixed factor divisors
>
> .../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++
> drivers/clk/Kconfig | 9 +
> drivers/clk/Makefile | 1 +
> drivers/clk/clk-xlnx-clock-wizard.c | 689 +++++++++++++++++++++
> drivers/staging/Kconfig | 2 -
> drivers/staging/Makefile | 1 -
> drivers/staging/clocking-wizard/Kconfig | 10 -
> drivers/staging/clocking-wizard/Makefile | 2 -
> drivers/staging/clocking-wizard/TODO | 12 -
> .../clocking-wizard/clk-xlnx-clock-wizard.c | 333 ----------
> drivers/staging/clocking-wizard/dt-binding.txt | 30 -
> 11 files changed, 764 insertions(+), 390 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c
> delete mode 100644 drivers/staging/clocking-wizard/Kconfig
> delete mode 100644 drivers/staging/clocking-wizard/Makefile
> delete mode 100644 drivers/staging/clocking-wizard/TODO
> delete mode 100644 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
> delete mode 100644 drivers/staging/clocking-wizard/dt-binding.txt
>
Can you please take a look at this series?
Thanks,
Michal
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
2020-12-15 9:13 ` Michal Simek
@ 2020-12-15 19:10 ` Stephen Boyd
-1 siblings, 0 replies; 32+ messages in thread
From: Stephen Boyd @ 2020-12-15 19:10 UTC (permalink / raw)
To: Michal Simek, Shubhrajyoti Datta, linux-clk
Cc: git, devicetree, mturquette, gregkh, devel
Quoting Michal Simek (2020-12-15 01:13:46)
>
> Can you please take a look at this series?
>
I did, see https://lore.kernel.org/r/160783777786.1580929.1950826106627397616@swboyd.mtv.corp.google.com
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
@ 2020-12-15 19:10 ` Stephen Boyd
0 siblings, 0 replies; 32+ messages in thread
From: Stephen Boyd @ 2020-12-15 19:10 UTC (permalink / raw)
To: Michal Simek, Shubhrajyoti Datta, linux-clk
Cc: devel, devicetree, mturquette, git, gregkh
Quoting Michal Simek (2020-12-15 01:13:46)
>
> Can you please take a look at this series?
>
I did, see https://lore.kernel.org/r/160783777786.1580929.1950826106627397616@swboyd.mtv.corp.google.com
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
2020-11-04 15:06 ` Shubhrajyoti Datta
@ 2021-01-21 14:39 ` Miquel Raynal
-1 siblings, 0 replies; 32+ messages in thread
From: Miquel Raynal @ 2021-01-21 14:39 UTC (permalink / raw)
To: Shubhrajyoti Datta
Cc: linux-clk, devel, devicetree, sboyd, gregkh, mturquette, git
Hi Shubhrajyoti,
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> wrote on Wed, 4 Nov
2020 20:36:40 +0530:
> In the thread [1] Greg suggested that we move the driver
> to the clk from the staging.
> Add patches to address the concerns regarding the fractional and
> set rate support in the TODO.
>
> The patch set does the following
> - Trivial fixes for kernel doc.
> - Move the driver to the clk folder
> - Add capability to set rate.
> - Add fractional support.
> - Add support for configurable outputs.
> - Make the output names unique so that multiple instances
> do not crib.
Can someone tell me the status of this series? I think it would
benefit everyone to have this driver "officially" supported in the
main tree, unless there are crucial issues; in this case it might be
good to know which ones?
Thanks,
Miquèl
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
@ 2021-01-21 14:39 ` Miquel Raynal
0 siblings, 0 replies; 32+ messages in thread
From: Miquel Raynal @ 2021-01-21 14:39 UTC (permalink / raw)
To: Shubhrajyoti Datta
Cc: devel, devicetree, sboyd, gregkh, mturquette, git, linux-clk
Hi Shubhrajyoti,
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> wrote on Wed, 4 Nov
2020 20:36:40 +0530:
> In the thread [1] Greg suggested that we move the driver
> to the clk from the staging.
> Add patches to address the concerns regarding the fractional and
> set rate support in the TODO.
>
> The patch set does the following
> - Trivial fixes for kernel doc.
> - Move the driver to the clk folder
> - Add capability to set rate.
> - Add fractional support.
> - Add support for configurable outputs.
> - Make the output names unique so that multiple instances
> do not crib.
Can someone tell me the status of this series? I think it would
benefit everyone to have this driver "officially" supported in the
main tree, unless there are crucial issues; in this case it might be
good to know which ones?
Thanks,
Miquèl
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
2020-12-13 5:36 ` Stephen Boyd
@ 2021-01-21 14:40 ` Michal Simek
-1 siblings, 0 replies; 32+ messages in thread
From: Michal Simek @ 2021-01-21 14:40 UTC (permalink / raw)
To: Stephen Boyd, Shubhrajyoti Datta, linux-clk, Michal Simek, Srinivas Goud
Cc: devel, devicetree, gregkh, mturquette, git
Hi Stephen,
First of all sorry for very slow response. I didn't get this email even
xilinx alias is in CC. Something is really fishy here.
On 12/13/20 6:36 AM, Stephen Boyd wrote:
> Quoting Shubhrajyoti Datta (2020-11-04 07:06:40)
>>
>> Shubhrajyoti Datta (7):
>> dt-bindings: add documentation of xilinx clocking wizard
>
> Any chance to respond to Robs comments?
I will ensure that Rob's comments are addresses.
>
>> clk: clock-wizard: Add the clockwizard to clk directory
>
> Is it called 'wizard' anywhere in the documentation? I wonder if there
> is a better name that could be found for this.
It is really clocking wizard based on documentation.
https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf
Can you please review that 6 patches if there is a need for any change
for v8?
Thanks,
Michal
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
@ 2021-01-21 14:40 ` Michal Simek
0 siblings, 0 replies; 32+ messages in thread
From: Michal Simek @ 2021-01-21 14:40 UTC (permalink / raw)
To: Stephen Boyd, Shubhrajyoti Datta, linux-clk, Michal Simek, Srinivas Goud
Cc: devel, devicetree, mturquette, git, gregkh
Hi Stephen,
First of all sorry for very slow response. I didn't get this email even
xilinx alias is in CC. Something is really fishy here.
On 12/13/20 6:36 AM, Stephen Boyd wrote:
> Quoting Shubhrajyoti Datta (2020-11-04 07:06:40)
>>
>> Shubhrajyoti Datta (7):
>> dt-bindings: add documentation of xilinx clocking wizard
>
> Any chance to respond to Robs comments?
I will ensure that Rob's comments are addresses.
>
>> clk: clock-wizard: Add the clockwizard to clk directory
>
> Is it called 'wizard' anywhere in the documentation? I wonder if there
> is a better name that could be found for this.
It is really clocking wizard based on documentation.
https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf
Can you please review that 6 patches if there is a need for any change
for v8?
Thanks,
Michal
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
2021-01-21 14:39 ` Miquel Raynal
@ 2021-02-12 14:20 ` Michal Simek
-1 siblings, 0 replies; 32+ messages in thread
From: Michal Simek @ 2021-02-12 14:20 UTC (permalink / raw)
To: Miquel Raynal, Shubhrajyoti Datta
Cc: linux-clk, devel, devicetree, sboyd, gregkh, mturquette, git
Hi Miquel,
On 1/21/21 3:39 PM, Miquel Raynal wrote:
> Hi Shubhrajyoti,
>
> Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> wrote on Wed, 4 Nov
> 2020 20:36:40 +0530:
>
>> In the thread [1] Greg suggested that we move the driver
>> to the clk from the staging.
>> Add patches to address the concerns regarding the fractional and
>> set rate support in the TODO.
>>
>> The patch set does the following
>> - Trivial fixes for kernel doc.
>> - Move the driver to the clk folder
>> - Add capability to set rate.
>> - Add fractional support.
>> - Add support for configurable outputs.
>> - Make the output names unique so that multiple instances
>> do not crib.
>
> Can someone tell me the status of this series? I think it would
> benefit everyone to have this driver "officially" supported in the
> main tree, unless there are crucial issues; in this case it might be
> good to know which ones?
v8 was sent here.
https://lore.kernel.org/r/1612446810-6113-1-git-send-email-shubhrajyoti.datta@xilinx.com
Unfortunately v9 is required.
Shubhrajyoti: Can you please keep Miquel in CC on v9?
Thanks,
Michal
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
@ 2021-02-12 14:20 ` Michal Simek
0 siblings, 0 replies; 32+ messages in thread
From: Michal Simek @ 2021-02-12 14:20 UTC (permalink / raw)
To: Miquel Raynal, Shubhrajyoti Datta
Cc: devel, devicetree, sboyd, gregkh, mturquette, git, linux-clk
Hi Miquel,
On 1/21/21 3:39 PM, Miquel Raynal wrote:
> Hi Shubhrajyoti,
>
> Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> wrote on Wed, 4 Nov
> 2020 20:36:40 +0530:
>
>> In the thread [1] Greg suggested that we move the driver
>> to the clk from the staging.
>> Add patches to address the concerns regarding the fractional and
>> set rate support in the TODO.
>>
>> The patch set does the following
>> - Trivial fixes for kernel doc.
>> - Move the driver to the clk folder
>> - Add capability to set rate.
>> - Add fractional support.
>> - Add support for configurable outputs.
>> - Make the output names unique so that multiple instances
>> do not crib.
>
> Can someone tell me the status of this series? I think it would
> benefit everyone to have this driver "officially" supported in the
> main tree, unless there are crucial issues; in this case it might be
> good to know which ones?
v8 was sent here.
https://lore.kernel.org/r/1612446810-6113-1-git-send-email-shubhrajyoti.datta@xilinx.com
Unfortunately v9 is required.
Shubhrajyoti: Can you please keep Miquel in CC on v9?
Thanks,
Michal
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2021-02-12 18:55 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-04 15:06 [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates Shubhrajyoti Datta
2020-11-04 15:06 ` Shubhrajyoti Datta
2020-11-04 15:06 ` [PATCH v7 1/7] dt-bindings: add documentation of xilinx clocking wizard Shubhrajyoti Datta
2020-11-04 15:06 ` Shubhrajyoti Datta
2020-11-04 19:11 ` Rob Herring
2020-11-04 19:11 ` Rob Herring
2020-11-04 19:15 ` Rob Herring
2020-11-04 19:15 ` Rob Herring
2020-11-04 15:06 ` [PATCH v7 2/7] clk: clock-wizard: Add the clockwizard to clk directory Shubhrajyoti Datta
2020-11-04 15:06 ` Shubhrajyoti Datta
2020-11-04 15:06 ` [PATCH v7 3/7] clk: clock-wizard: Fix kernel-doc warning Shubhrajyoti Datta
2020-11-04 15:06 ` Shubhrajyoti Datta
2020-11-04 15:06 ` [PATCH v7 4/7] clk: clock-wizard: Add support for dynamic reconfiguration Shubhrajyoti Datta
2020-11-04 15:06 ` Shubhrajyoti Datta
2020-11-04 15:06 ` [PATCH v7 5/7] clk: clock-wizard: Add support for fractional support Shubhrajyoti Datta
2020-11-04 15:06 ` Shubhrajyoti Datta
2020-11-04 15:06 ` [PATCH v7 6/7] clk: clock-wizard: Remove the hardcoding of the clock outputs Shubhrajyoti Datta
2020-11-04 15:06 ` Shubhrajyoti Datta
2020-11-04 15:06 ` [PATCH v7 7/7] clk: clock-wizard: Update the fixed factor divisors Shubhrajyoti Datta
2020-11-04 15:06 ` Shubhrajyoti Datta
2020-12-13 5:36 ` [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates Stephen Boyd
2020-12-13 5:36 ` Stephen Boyd
2021-01-21 14:40 ` Michal Simek
2021-01-21 14:40 ` Michal Simek
2020-12-15 9:13 ` Michal Simek
2020-12-15 9:13 ` Michal Simek
2020-12-15 19:10 ` Stephen Boyd
2020-12-15 19:10 ` Stephen Boyd
2021-01-21 14:39 ` Miquel Raynal
2021-01-21 14:39 ` Miquel Raynal
2021-02-12 14:20 ` Michal Simek
2021-02-12 14:20 ` Michal Simek
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