* [PATCH 1/3] clk: imx: Add ECSPI to iMX8MN
@ 2021-01-18 23:58 Marek Vasut
2021-01-18 23:58 ` [PATCH 2/3] spi: imx: Define register bits in the driver Marek Vasut
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Marek Vasut @ 2021-01-18 23:58 UTC (permalink / raw)
To: u-boot
Add ECSPI clock entries to iMX8MN clock driver. Only make those entries
available in case SPI support in U-Boot is enabled at all to conserve
space, esp. in SPL.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
drivers/clk/imx/clk-imx8mn.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index e29d902544c..e398d7de02a 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -105,6 +105,20 @@ static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sy
static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
"sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
+#if CONFIG_IS_ENABLED(DM_SPI)
+static const char *imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+ "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+ "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+ "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m", "audio_pll2_out", };
+#endif
+
static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
@@ -440,6 +454,21 @@ static int imx8mn_clk_probe(struct udevice *dev)
base + 0x40a0, 0));
#endif
+#if CONFIG_IS_ENABLED(DM_SPI)
+ clk_dm(IMX8MN_CLK_ECSPI1,
+ imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
+ clk_dm(IMX8MN_CLK_ECSPI2,
+ imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
+ clk_dm(IMX8MN_CLK_ECSPI3,
+ imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
+ clk_dm(IMX8MN_CLK_ECSPI1_ROOT,
+ imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+ clk_dm(IMX8MN_CLK_ECSPI2_ROOT,
+ imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+ clk_dm(IMX8MN_CLK_ECSPI3_ROOT,
+ imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+#endif
+
return 0;
}
--
2.29.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] spi: imx: Define register bits in the driver
2021-01-18 23:58 [PATCH 1/3] clk: imx: Add ECSPI to iMX8MN Marek Vasut
@ 2021-01-18 23:58 ` Marek Vasut
2021-01-23 15:50 ` sbabic at denx.de
2021-01-18 23:58 ` [PATCH 3/3] spi: imx: Use clock framework if enabled Marek Vasut
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Marek Vasut @ 2021-01-18 23:58 UTC (permalink / raw)
To: u-boot
The CSPI/ECSPI register bits do not differ between newer SoCs, instead
of having multiple copies of the same thing for each iMX SoC, define
the bits in the driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/include/asm/arch-mx25/imx-regs.h | 30 ---------
arch/arm/include/asm/arch-mx31/imx-regs.h | 31 ---------
arch/arm/include/asm/arch-mx35/imx-regs.h | 30 ---------
arch/arm/include/asm/arch-mx5/imx-regs.h | 36 -----------
arch/arm/include/asm/arch-mx6/imx-regs.h | 36 -----------
arch/arm/include/asm/arch-mx7/imx-regs.h | 37 -----------
drivers/spi/mxc_spi.c | 76 +++++++++++++++++++++++
7 files changed, 76 insertions(+), 200 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 5d0974f3283..57809697c1a 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -269,18 +269,6 @@ struct epit_regs {
u32 cnr; /* Counter register */
};
-/* CSPI registers */
-struct cspi_regs {
- u32 rxdata;
- u32 txdata;
- u32 ctrl;
- u32 intr;
- u32 dma;
- u32 stat;
- u32 period;
- u32 test;
-};
-
#endif
#define ARCH_MXC
@@ -508,24 +496,6 @@ struct cspi_regs {
/*
* CSPI register definitions
*/
-#define MXC_CSPI
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_SMC (1 << 3)
-#define MXC_CSPICTRL_POL (1 << 4)
-#define MXC_CSPICTRL_PHA (1 << 5)
-#define MXC_CSPICTRL_SSCTL (1 << 6)
-#define MXC_CSPICTRL_SSPOL (1 << 7)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
-#define MXC_CSPICTRL_TC (1 << 7)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPICTRL_MAXBITS 0xfff
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 4
-
#define MXC_SPI_BASE_ADDRESSES \
IMX_CSPI1_BASE, \
IMX_CSPI2_BASE, \
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 9e271d6ea2e..566db549ec6 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -39,17 +39,6 @@ struct clock_control_regs {
u32 pdr2;
};
-struct cspi_regs {
- u32 rxdata;
- u32 txdata;
- u32 ctrl;
- u32 intr;
- u32 dma;
- u32 stat;
- u32 period;
- u32 test;
-};
-
/* IIM control registers */
struct iim_regs {
u32 iim_stat;
@@ -889,26 +878,6 @@ struct esdc_regs {
/*
* CSPI register definitions
*/
-#define MXC_CSPI
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_SMC (1 << 3)
-#define MXC_CSPICTRL_POL (1 << 4)
-#define MXC_CSPICTRL_PHA (1 << 5)
-#define MXC_CSPICTRL_SSCTL (1 << 6)
-#define MXC_CSPICTRL_SSPOL (1 << 7)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
-#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
-#define MXC_CSPICTRL_TC (1 << 8)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPICTRL_MAXBITS 0x1f
-
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 4
-
-
#define MXC_SPI_BASE_ADDRESSES \
0x43fa4000, \
0x50010000, \
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
index 8ee0754c8e5..35090047c70 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -170,24 +170,6 @@
/*
* CSPI register definitions
*/
-#define MXC_CSPI
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_SMC (1 << 3)
-#define MXC_CSPICTRL_POL (1 << 4)
-#define MXC_CSPICTRL_PHA (1 << 5)
-#define MXC_CSPICTRL_SSCTL (1 << 6)
-#define MXC_CSPICTRL_SSPOL (1 << 7)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
-#define MXC_CSPICTRL_TC (1 << 7)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPICTRL_MAXBITS 0xfff
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 4
-
#define MXC_SPI_BASE_ADDRESSES \
0x43fa4000, \
0x50010000,
@@ -280,18 +262,6 @@ struct gpt_regs {
u32 counter; /* counter */
};
-/* CSPI registers */
-struct cspi_regs {
- u32 rxdata;
- u32 txdata;
- u32 ctrl;
- u32 intr;
- u32 dma;
- u32 stat;
- u32 period;
- u32 test;
-};
-
struct esdc_regs {
u32 esdctl0;
u32 esdcfg0;
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 3d1cc683228..2731b7fb59b 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -204,30 +204,6 @@
/*
* CSPI register definitions
*/
-#define MXC_ECSPI
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
-#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
-#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
-#define MXC_CSPICTRL_MAXBITS 0xfff
-#define MXC_CSPICTRL_TC (1 << 7)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 32
-
-/* Bit position inside CTRL register to be associated with SS */
-#define MXC_CSPICTRL_CHAN 18
-
-/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_PHA 0 /* SCLK phase control */
-#define MXC_CSPICON_POL 4 /* SCLK polarity */
-#define MXC_CSPICON_SSPOL 12 /* SS polarity */
-#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#define MXC_SPI_BASE_ADDRESSES \
CSPI1_BASE_ADDR, \
CSPI2_BASE_ADDR, \
@@ -476,18 +452,6 @@ struct srtc_regs {
u32 hpienr; /* 0x38 */
};
-/* CSPI registers */
-struct cspi_regs {
- u32 rxdata;
- u32 txdata;
- u32 ctrl;
- u32 cfg;
- u32 intr;
- u32 dma;
- u32 stat;
- u32 period;
-};
-
struct iim_regs {
u32 stat;
u32 statm;
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index ccd48e83055..a8a5bf7a575 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -668,46 +668,10 @@ struct gpc {
#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
-/* ECSPI registers */
-struct cspi_regs {
- u32 rxdata;
- u32 txdata;
- u32 ctrl;
- u32 cfg;
- u32 intr;
- u32 dma;
- u32 stat;
- u32 period;
-};
-
/*
* CSPI register definitions
*/
-#define MXC_ECSPI
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
-#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
-#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
-#define MXC_CSPICTRL_MAXBITS 0xfff
-#define MXC_CSPICTRL_TC (1 << 7)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 32
#define SPI_MAX_NUM 4
-
-/* Bit position inside CTRL register to be associated with SS */
-#define MXC_CSPICTRL_CHAN 18
-
-/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_PHA 0 /* SCLK phase control */
-#define MXC_CSPICON_POL 4 /* SCLK polarity */
-#define MXC_CSPICON_SSPOL 12 /* SS polarity */
-#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
#define MXC_SPI_BASE_ADDRESSES \
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index f37419c07f1..5cab12f30d8 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -842,46 +842,9 @@ struct iomuxc_gpr_base_regs {
u32 gpr[23]; /* 0x000 */
};
-/* ECSPI registers */
-struct cspi_regs {
- u32 rxdata;
- u32 txdata;
- u32 ctrl;
- u32 cfg;
- u32 intr;
- u32 dma;
- u32 stat;
- u32 period;
-};
-
/*
* CSPI register definitions
*/
-#define MXC_ECSPI
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
-#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
-#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
-#define MXC_CSPICTRL_MAXBITS 0xfff
-#define MXC_CSPICTRL_TC (1 << 7)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 32
-
-/* Bit position inside CTRL register to be associated with SS */
-#define MXC_CSPICTRL_CHAN 18
-
-/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_PHA 0 /* SCLK phase control */
-#define MXC_CSPICON_POL 4 /* SCLK polarity */
-#define MXC_CSPICON_SSPOL 12 /* SS polarity */
-#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
-
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index e90a06a66de..849808fb916 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -20,6 +20,82 @@
DECLARE_GLOBAL_DATA_PTR;
+/* MX35 and older is CSPI */
+#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35)
+#define MXC_CSPI
+struct cspi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctrl;
+ u32 intr;
+ u32 dma;
+ u32 stat;
+ u32 period;
+ u32 test;
+};
+
+#define MXC_CSPICTRL_EN BIT(0)
+#define MXC_CSPICTRL_MODE BIT(1)
+#define MXC_CSPICTRL_XCH BIT(2)
+#define MXC_CSPICTRL_SMC BIT(3)
+#define MXC_CSPICTRL_POL BIT(4)
+#define MXC_CSPICTRL_PHA BIT(5)
+#define MXC_CSPICTRL_SSCTL BIT(6)
+#define MXC_CSPICTRL_SSPOL BIT(7)
+#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_RXOVF BIT(6)
+#define MXC_CSPIPERIOD_32KHZ BIT(15)
+#define MAX_SPI_BYTES 4
+#if defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_TC BIT(7)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#else /* MX31 */
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
+#define MXC_CSPICTRL_TC BIT(8)
+#define MXC_CSPICTRL_MAXBITS 0x1f
+#endif
+
+#else /* MX51 and newer is ECSPI */
+#define MXC_ECSPI
+struct cspi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctrl;
+ u32 cfg;
+ u32 intr;
+ u32 dma;
+ u32 stat;
+ u32 period;
+};
+
+#define MXC_CSPICTRL_EN BIT(0)
+#define MXC_CSPICTRL_MODE BIT(1)
+#define MXC_CSPICTRL_XCH BIT(2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#define MXC_CSPICTRL_TC BIT(7)
+#define MXC_CSPICTRL_RXOVF BIT(6)
+#define MXC_CSPIPERIOD_32KHZ BIT(15)
+#define MAX_SPI_BYTES 32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN 18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
+#endif
+
#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
* datasheet, the correct one is in the Freescale's Linux driver */
--
2.29.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] spi: imx: Use clock framework if enabled
2021-01-18 23:58 [PATCH 1/3] clk: imx: Add ECSPI to iMX8MN Marek Vasut
2021-01-18 23:58 ` [PATCH 2/3] spi: imx: Define register bits in the driver Marek Vasut
@ 2021-01-18 23:58 ` Marek Vasut
2021-01-23 15:50 ` sbabic at denx.de
2021-01-19 1:42 ` [PATCH 1/3] clk: imx: Add ECSPI to iMX8MN Peng Fan
2021-01-23 15:49 ` sbabic at denx.de
3 siblings, 1 reply; 7+ messages in thread
From: Marek Vasut @ 2021-01-18 23:58 UTC (permalink / raw)
To: u-boot
In case the clock framework is enabled, enable the SPI controller clock
and obtain max frequency from the clock framework.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
---
drivers/spi/mxc_spi.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 849808fb916..3377200d24f 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
@@ -617,8 +618,19 @@ static int mxc_spi_probe(struct udevice *bus)
if (mxcs->base == FDT_ADDR_T_NONE)
return -ENODEV;
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+ ret = clk_get_by_index(bus, 0, &clk);
+ if (ret)
+ return ret;
+
+ clk_enable(&clk);
+
+ mxcs->max_hz = clk_get_rate(&clk);
+#else
mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
20000000);
+#endif
return 0;
}
--
2.29.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 1/3] clk: imx: Add ECSPI to iMX8MN
2021-01-18 23:58 [PATCH 1/3] clk: imx: Add ECSPI to iMX8MN Marek Vasut
2021-01-18 23:58 ` [PATCH 2/3] spi: imx: Define register bits in the driver Marek Vasut
2021-01-18 23:58 ` [PATCH 3/3] spi: imx: Use clock framework if enabled Marek Vasut
@ 2021-01-19 1:42 ` Peng Fan
2021-01-23 15:49 ` sbabic at denx.de
3 siblings, 0 replies; 7+ messages in thread
From: Peng Fan @ 2021-01-19 1:42 UTC (permalink / raw)
To: u-boot
> Subject: [PATCH 1/3] clk: imx: Add ECSPI to iMX8MN
>
> Add ECSPI clock entries to iMX8MN clock driver. Only make those entries
> available in case SPI support in U-Boot is enabled at all to conserve space, esp.
> in SPL.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> drivers/clk/imx/clk-imx8mn.c | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index e29d902544c..e398d7de02a 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -105,6 +105,20 @@ static const char *imx8mn_usdhc1_sels[] =
> {"clock-osc-24m", "sys_pll1_400m", "sy static const char
> *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m",
> "sys_pll1_800m", "sys_pll2_500m",
> "sys_pll3_out", "sys_pll1_266m",
> "audio_pll2_out", "sys_pll1_100m", };
>
> +#if CONFIG_IS_ENABLED(DM_SPI)
> +static const char *imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m",
> "sys_pll1_40m",
> + "sys_pll1_160m", "sys_pll1_800m",
> "sys_pll3_out",
> + "sys_pll2_250m", "audio_pll2_out", };
> +
> +static const char *imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m",
> "sys_pll1_40m",
> + "sys_pll1_160m", "sys_pll1_800m",
> "sys_pll3_out",
> + "sys_pll2_250m", "audio_pll2_out", };
> +
> +static const char *imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m",
> "sys_pll1_40m",
> + "sys_pll1_160m", "sys_pll1_800m",
> "sys_pll3_out",
> + "sys_pll2_250m", "audio_pll2_out", }; #endif
> +
> static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m",
> "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
> "video_pll1_out", "audio_pll2_out",
> "sys_pll1_133m", };
>
> @@ -440,6 +454,21 @@ static int imx8mn_clk_probe(struct udevice *dev)
> base + 0x40a0, 0));
> #endif
>
> +#if CONFIG_IS_ENABLED(DM_SPI)
> + clk_dm(IMX8MN_CLK_ECSPI1,
> + imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base +
> 0xb280));
> + clk_dm(IMX8MN_CLK_ECSPI2,
> + imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base +
> 0xb300));
> + clk_dm(IMX8MN_CLK_ECSPI3,
> + imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base +
> 0xc180));
> + clk_dm(IMX8MN_CLK_ECSPI1_ROOT,
> + imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
> + clk_dm(IMX8MN_CLK_ECSPI2_ROOT,
> + imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
> + clk_dm(IMX8MN_CLK_ECSPI3_ROOT,
> + imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
> +#endif
> +
> return 0;
> }
Reviewed-by: Peng Fan <peng.fan@nxp.com>
>
> --
> 2.29.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/3] clk: imx: Add ECSPI to iMX8MN
2021-01-18 23:58 [PATCH 1/3] clk: imx: Add ECSPI to iMX8MN Marek Vasut
` (2 preceding siblings ...)
2021-01-19 1:42 ` [PATCH 1/3] clk: imx: Add ECSPI to iMX8MN Peng Fan
@ 2021-01-23 15:49 ` sbabic at denx.de
3 siblings, 0 replies; 7+ messages in thread
From: sbabic at denx.de @ 2021-01-23 15:49 UTC (permalink / raw)
To: u-boot
> Add ECSPI clock entries to iMX8MN clock driver. Only make those entries
> available in case SPI support in U-Boot is enabled at all to conserve
> space, esp. in SPL.
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/3] spi: imx: Use clock framework if enabled
2021-01-18 23:58 ` [PATCH 3/3] spi: imx: Use clock framework if enabled Marek Vasut
@ 2021-01-23 15:50 ` sbabic at denx.de
0 siblings, 0 replies; 7+ messages in thread
From: sbabic at denx.de @ 2021-01-23 15:50 UTC (permalink / raw)
To: u-boot
> In case the clock framework is enabled, enable the SPI controller clock
> and obtain max frequency from the clock framework.
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Jagan Teki <jagan@amarulasolutions.com>
> Cc: Stefano Babic <sbabic@denx.de>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/3] spi: imx: Define register bits in the driver
2021-01-18 23:58 ` [PATCH 2/3] spi: imx: Define register bits in the driver Marek Vasut
@ 2021-01-23 15:50 ` sbabic at denx.de
0 siblings, 0 replies; 7+ messages in thread
From: sbabic at denx.de @ 2021-01-23 15:50 UTC (permalink / raw)
To: u-boot
> The CSPI/ECSPI register bits do not differ between newer SoCs, instead
> of having multiple copies of the same thing for each iMX SoC, define
> the bits in the driver.
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Jagan Teki <jagan@amarulasolutions.com>
> Cc: Stefano Babic <sbabic@denx.de>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-01-23 15:50 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-18 23:58 [PATCH 1/3] clk: imx: Add ECSPI to iMX8MN Marek Vasut
2021-01-18 23:58 ` [PATCH 2/3] spi: imx: Define register bits in the driver Marek Vasut
2021-01-23 15:50 ` sbabic at denx.de
2021-01-18 23:58 ` [PATCH 3/3] spi: imx: Use clock framework if enabled Marek Vasut
2021-01-23 15:50 ` sbabic at denx.de
2021-01-19 1:42 ` [PATCH 1/3] clk: imx: Add ECSPI to iMX8MN Peng Fan
2021-01-23 15:49 ` sbabic at denx.de
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