* [linux-next:master 4935/5542] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:776: undefined reference to `__udivdi3'
@ 2021-01-24 10:49 ` kernel test robot
0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2021-01-24 10:49 UTC (permalink / raw)
To: Bhawanpreet Lakha
Cc: kbuild-all, Linux Memory Management List, Alex Deucher,
Joshua Aberback, Nicholas Kazlauskas
[-- Attachment #1: Type: text/plain, Size: 9846 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head: 226871e2eda4832d94c3239add7e52ad17b81ce5
commit: ea7154d8d9fb26129f51e4d763febe97a13228a5 [4935/5542] drm/amd/display: Update dcn30_apply_idle_power_optimizations() code
config: i386-randconfig-a001-20210124 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-20) 9.3.0
reproduce (this is a W=1 build):
# https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=ea7154d8d9fb26129f51e4d763febe97a13228a5
git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
git fetch --no-tags linux-next master
git checkout ea7154d8d9fb26129f51e4d763febe97a13228a5
# save the attached .config to linux build tree
make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
ld: drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.o: in function `dcn30_apply_idle_power_optimizations':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:776: undefined reference to `__udivdi3'
>> ld: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:804: undefined reference to `__divdi3'
ld: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:819: undefined reference to `__divdi3'
vim +776 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c
709
710 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
711 {
712 union dmub_rb_cmd cmd;
713 uint32_t tmr_delay = 0, tmr_scale = 0;
714 struct dc_cursor_attributes cursor_attr;
715 bool cursor_cache_enable = false;
716 struct dc_stream_state *stream = NULL;
717 struct dc_plane_state *plane = NULL;
718
719 if (!dc->ctx->dmub_srv)
720 return false;
721
722 if (enable) {
723 if (dc->current_state) {
724 int i;
725
726 /* First, check no-memory-requests case */
727 for (i = 0; i < dc->current_state->stream_count; i++) {
728 if (dc->current_state->stream_status[i].plane_count)
729 /* Fail eligibility on a visible stream */
730 break;
731 }
732
733 if (i == dc->current_state->stream_count) {
734 /* Enable no-memory-requests case */
735 memset(&cmd, 0, sizeof(cmd));
736 cmd.mall.header.type = DMUB_CMD__MALL;
737 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
738 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
739
740 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
741 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
742
743 return true;
744 }
745
746 stream = dc->current_state->streams[0];
747 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
748
749 if (stream && plane) {
750 cursor_cache_enable = stream->cursor_position.enable &&
751 plane->address.grph.cursor_cache_addr.quad_part;
752 cursor_attr = stream->cursor_attributes;
753 }
754
755 /*
756 * Second, check MALL eligibility
757 *
758 * single display only, single surface only, 8 and 16 bit formats only, no VM,
759 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
760 *
761 * TODO: When we implement multi-display, PSR displays will be allowed if there is
762 * a non-PSR display present, since in that case we can't do D0i3.2
763 */
764 if (dc->current_state->stream_count == 1 &&
765 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
766 dc->current_state->stream_status[0].plane_count == 1 &&
767 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
768 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
769 plane->address.page_table_base.quad_part == 0 &&
770 dc->hwss.does_plane_fit_in_mall &&
771 dc->hwss.does_plane_fit_in_mall(dc, plane,
772 cursor_cache_enable ? &cursor_attr : NULL)) {
773 unsigned int v_total = stream->adjust.v_total_max ?
774 stream->adjust.v_total_max : stream->timing.v_total;
775 unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz *
> 776 100LL / (v_total * stream->timing.h_total);
777
778 /*
779 * one frame time in microsec:
780 * Delay_Us = 1000000 / refresh
781 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
782 *
783 * one frame time modified by 'additional timer percent' (p):
784 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
785 * = dynamic_delay_us * (1 + p / 100)
786 * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
787 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
788 *
789 * formula for timer duration based on parameters, from regspec:
790 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
791 *
792 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
793 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
794 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
795 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
796 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
797 *
798 * need to round up the result of the division before the subtraction
799 */
800 unsigned int denom = refresh_hz * 6528;
801 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
802
803 tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
> 804 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
805 denom) - 64LL;
806
807 /* scale should be increased until it fits into 6 bits */
808 while (tmr_delay & ~0x3F) {
809 tmr_scale++;
810
811 if (tmr_scale > 3) {
812 /* Delay exceeds range of hysteresis timer */
813 ASSERT(false);
814 return false;
815 }
816
817 denom *= 2;
818 tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
819 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
820 denom) - 64LL;
821 }
822
823 /* Copy HW cursor */
824 if (cursor_cache_enable) {
825 memset(&cmd, 0, sizeof(cmd));
826 cmd.mall.header.type = DMUB_CMD__MALL;
827 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
828 cmd.mall.header.payload_bytes =
829 sizeof(cmd.mall) - sizeof(cmd.mall.header);
830
831 switch (cursor_attr.color_format) {
832 case CURSOR_MODE_MONO:
833 cmd.mall.cursor_bpp = 2;
834 break;
835 case CURSOR_MODE_COLOR_1BIT_AND:
836 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
837 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
838 cmd.mall.cursor_bpp = 32;
839 break;
840
841 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
842 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
843 cmd.mall.cursor_bpp = 64;
844 break;
845 }
846
847 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
848 cmd.mall.cursor_copy_dst.quad_part =
849 plane->address.grph.cursor_cache_addr.quad_part;
850 cmd.mall.cursor_width = cursor_attr.width;
851 cmd.mall.cursor_height = cursor_attr.height;
852 cmd.mall.cursor_pitch = cursor_attr.pitch;
853
854 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
855 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
856 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
857
858 /* Use copied cursor, and it's okay to not switch back */
859 cursor_attr.address.quad_part =
860 plane->address.grph.cursor_cache_addr.quad_part;
861 dc_stream_set_cursor_attributes(stream, &cursor_attr);
862 }
863
864 /* Enable MALL */
865 memset(&cmd, 0, sizeof(cmd));
866 cmd.mall.header.type = DMUB_CMD__MALL;
867 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
868 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
869 cmd.mall.tmr_delay = tmr_delay;
870 cmd.mall.tmr_scale = tmr_scale;
871 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
872
873 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
874 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
875
876 return true;
877 }
878 }
879
880 /* No applicable optimizations */
881 return false;
882 }
883
884 /* Disable MALL */
885 memset(&cmd, 0, sizeof(cmd));
886 cmd.mall.header.type = DMUB_CMD__MALL;
887 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
888 cmd.mall.header.payload_bytes =
889 sizeof(cmd.mall) - sizeof(cmd.mall.header);
890
891 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
892 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
893 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
894
895 return true;
896 }
897
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 36200 bytes --]
^ permalink raw reply [flat|nested] 2+ messages in thread
* [linux-next:master 4935/5542] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:776: undefined reference to `__udivdi3'
@ 2021-01-24 10:49 ` kernel test robot
0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2021-01-24 10:49 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 10067 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head: 226871e2eda4832d94c3239add7e52ad17b81ce5
commit: ea7154d8d9fb26129f51e4d763febe97a13228a5 [4935/5542] drm/amd/display: Update dcn30_apply_idle_power_optimizations() code
config: i386-randconfig-a001-20210124 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-20) 9.3.0
reproduce (this is a W=1 build):
# https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=ea7154d8d9fb26129f51e4d763febe97a13228a5
git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
git fetch --no-tags linux-next master
git checkout ea7154d8d9fb26129f51e4d763febe97a13228a5
# save the attached .config to linux build tree
make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
ld: drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.o: in function `dcn30_apply_idle_power_optimizations':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:776: undefined reference to `__udivdi3'
>> ld: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:804: undefined reference to `__divdi3'
ld: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:819: undefined reference to `__divdi3'
vim +776 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c
709
710 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
711 {
712 union dmub_rb_cmd cmd;
713 uint32_t tmr_delay = 0, tmr_scale = 0;
714 struct dc_cursor_attributes cursor_attr;
715 bool cursor_cache_enable = false;
716 struct dc_stream_state *stream = NULL;
717 struct dc_plane_state *plane = NULL;
718
719 if (!dc->ctx->dmub_srv)
720 return false;
721
722 if (enable) {
723 if (dc->current_state) {
724 int i;
725
726 /* First, check no-memory-requests case */
727 for (i = 0; i < dc->current_state->stream_count; i++) {
728 if (dc->current_state->stream_status[i].plane_count)
729 /* Fail eligibility on a visible stream */
730 break;
731 }
732
733 if (i == dc->current_state->stream_count) {
734 /* Enable no-memory-requests case */
735 memset(&cmd, 0, sizeof(cmd));
736 cmd.mall.header.type = DMUB_CMD__MALL;
737 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
738 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
739
740 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
741 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
742
743 return true;
744 }
745
746 stream = dc->current_state->streams[0];
747 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
748
749 if (stream && plane) {
750 cursor_cache_enable = stream->cursor_position.enable &&
751 plane->address.grph.cursor_cache_addr.quad_part;
752 cursor_attr = stream->cursor_attributes;
753 }
754
755 /*
756 * Second, check MALL eligibility
757 *
758 * single display only, single surface only, 8 and 16 bit formats only, no VM,
759 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
760 *
761 * TODO: When we implement multi-display, PSR displays will be allowed if there is
762 * a non-PSR display present, since in that case we can't do D0i3.2
763 */
764 if (dc->current_state->stream_count == 1 &&
765 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
766 dc->current_state->stream_status[0].plane_count == 1 &&
767 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
768 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
769 plane->address.page_table_base.quad_part == 0 &&
770 dc->hwss.does_plane_fit_in_mall &&
771 dc->hwss.does_plane_fit_in_mall(dc, plane,
772 cursor_cache_enable ? &cursor_attr : NULL)) {
773 unsigned int v_total = stream->adjust.v_total_max ?
774 stream->adjust.v_total_max : stream->timing.v_total;
775 unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz *
> 776 100LL / (v_total * stream->timing.h_total);
777
778 /*
779 * one frame time in microsec:
780 * Delay_Us = 1000000 / refresh
781 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
782 *
783 * one frame time modified by 'additional timer percent' (p):
784 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
785 * = dynamic_delay_us * (1 + p / 100)
786 * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
787 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
788 *
789 * formula for timer duration based on parameters, from regspec:
790 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
791 *
792 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
793 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
794 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
795 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
796 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
797 *
798 * need to round up the result of the division before the subtraction
799 */
800 unsigned int denom = refresh_hz * 6528;
801 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
802
803 tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
> 804 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
805 denom) - 64LL;
806
807 /* scale should be increased until it fits into 6 bits */
808 while (tmr_delay & ~0x3F) {
809 tmr_scale++;
810
811 if (tmr_scale > 3) {
812 /* Delay exceeds range of hysteresis timer */
813 ASSERT(false);
814 return false;
815 }
816
817 denom *= 2;
818 tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
819 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
820 denom) - 64LL;
821 }
822
823 /* Copy HW cursor */
824 if (cursor_cache_enable) {
825 memset(&cmd, 0, sizeof(cmd));
826 cmd.mall.header.type = DMUB_CMD__MALL;
827 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
828 cmd.mall.header.payload_bytes =
829 sizeof(cmd.mall) - sizeof(cmd.mall.header);
830
831 switch (cursor_attr.color_format) {
832 case CURSOR_MODE_MONO:
833 cmd.mall.cursor_bpp = 2;
834 break;
835 case CURSOR_MODE_COLOR_1BIT_AND:
836 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
837 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
838 cmd.mall.cursor_bpp = 32;
839 break;
840
841 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
842 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
843 cmd.mall.cursor_bpp = 64;
844 break;
845 }
846
847 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
848 cmd.mall.cursor_copy_dst.quad_part =
849 plane->address.grph.cursor_cache_addr.quad_part;
850 cmd.mall.cursor_width = cursor_attr.width;
851 cmd.mall.cursor_height = cursor_attr.height;
852 cmd.mall.cursor_pitch = cursor_attr.pitch;
853
854 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
855 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
856 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
857
858 /* Use copied cursor, and it's okay to not switch back */
859 cursor_attr.address.quad_part =
860 plane->address.grph.cursor_cache_addr.quad_part;
861 dc_stream_set_cursor_attributes(stream, &cursor_attr);
862 }
863
864 /* Enable MALL */
865 memset(&cmd, 0, sizeof(cmd));
866 cmd.mall.header.type = DMUB_CMD__MALL;
867 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
868 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
869 cmd.mall.tmr_delay = tmr_delay;
870 cmd.mall.tmr_scale = tmr_scale;
871 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
872
873 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
874 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
875
876 return true;
877 }
878 }
879
880 /* No applicable optimizations */
881 return false;
882 }
883
884 /* Disable MALL */
885 memset(&cmd, 0, sizeof(cmd));
886 cmd.mall.header.type = DMUB_CMD__MALL;
887 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
888 cmd.mall.header.payload_bytes =
889 sizeof(cmd.mall) - sizeof(cmd.mall.header);
890
891 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
892 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
893 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
894
895 return true;
896 }
897
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 36200 bytes --]
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end of thread, other threads:[~2021-01-24 10:50 UTC | newest]
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2021-01-24 10:49 [linux-next:master 4935/5542] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:776: undefined reference to `__udivdi3' kernel test robot
2021-01-24 10:49 ` kernel test robot
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