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* [PATCH 1/3] clk: imx8mq: add PLL monitor output
@ 2021-01-25 17:41 ` Lucas Stach
  0 siblings, 0 replies; 16+ messages in thread
From: Lucas Stach @ 2021-01-25 17:41 UTC (permalink / raw)
  To: Stephen Boyd, Shawn Guo, Michael Turquette
  Cc: Fabio Estevam, NXP Linux Team, Peng Fan, Abel Vesa, linux-clk,
	linux-arm-kernel, kernel, patchwork-lst

The PLL monitor is mentioned as a debug feature in the reference manual,
but there are some boards that use this clock output as a reference clock
for board level components. Add support for those clocks in the clock
driver, so this clock output can be used properly.

Note that the VIDEO1, GPU and VPU mux inputs are rotated compared to the
description in the reference manual. The order in this patch has been
empirically validated.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/clk/imx/clk-imx8mq.c             | 22 ++++++++++++++++++++++
 include/dt-bindings/clock/imx8mq-clock.h | 16 +++++++++++++++-
 2 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 779ea69e639c..4dd4ae9d022b 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -270,6 +270,14 @@ static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "os
 static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m",
 					  "sys3_pll_out", "audio_pll1_out", "video_pll1_out", "ckil", };
 
+static const char * const pllout_monitor_sels[] = {"osc_25m", "osc_27m", "dummy", "dummy", "ckil",
+						   "audio_pll1_out_monitor", "audio_pll2_out_monitor",
+						   "video_pll1_out_monitor", "gpu_pll_out_monitor",
+						   "vpu_pll_out_monitor", "arm_pll_out_monitor",
+						   "sys_pll1_out_monitor", "sys_pll2_out_monitor",
+						   "sys_pll3_out_monitor", "dram_pll_out_monitor",
+						   "video_pll2_out_monitor", };
+
 static struct clk_hw_onecell_data *clk_hw_data;
 static struct clk_hw **hws;
 
@@ -399,6 +407,20 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);
 	hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);
 
+	hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3);
+	hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3);
+	hws[IMX8MQ_CLK_MON_VIDEO_PLL1_DIV] = imx_clk_hw_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3);
+	hws[IMX8MQ_CLK_MON_GPU_PLL_DIV] = imx_clk_hw_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3);
+	hws[IMX8MQ_CLK_MON_VPU_PLL_DIV] = imx_clk_hw_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3);
+	hws[IMX8MQ_CLK_MON_ARM_PLL_DIV] = imx_clk_hw_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3);
+	hws[IMX8MQ_CLK_MON_SYS_PLL1_DIV] = imx_clk_hw_divider("sys_pll1_out_monitor", "sys1_pll_out", base + 0x7c, 0, 3);
+	hws[IMX8MQ_CLK_MON_SYS_PLL2_DIV] = imx_clk_hw_divider("sys_pll2_out_monitor", "sys2_pll_out", base + 0x7c, 4, 3);
+	hws[IMX8MQ_CLK_MON_SYS_PLL3_DIV] = imx_clk_hw_divider("sys_pll3_out_monitor", "sys3_pll_out", base + 0x7c, 8, 3);
+	hws[IMX8MQ_CLK_MON_DRAM_PLL_DIV] = imx_clk_hw_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3);
+	hws[IMX8MQ_CLK_MON_VIDEO_PLL2_DIV] = imx_clk_hw_divider("video_pll2_out_monitor", "video2_pll_out", base + 0x7c, 16, 3);
+	hws[IMX8MQ_CLK_MON_SEL] = imx_clk_hw_mux("pllout_monitor_sel", base + 0x74, 0, 4, pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels));
+	hws[IMX8MQ_CLK_MON_CLK2_OUT] = imx_clk_hw_gate("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4);
+
 	np = dev->of_node;
 	base = devm_platform_ioremap_resource(pdev, 0);
 	if (WARN_ON(IS_ERR(base)))
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index 9b8045d75b8b..82e907ce7bdd 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -431,6 +431,20 @@
 
 #define IMX8MQ_CLK_A53_CORE			289
 
-#define IMX8MQ_CLK_END				290
+#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV		290
+#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV		291
+#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV		292
+#define IMX8MQ_CLK_MON_GPU_PLL_DIV		293
+#define IMX8MQ_CLK_MON_VPU_PLL_DIV		294
+#define IMX8MQ_CLK_MON_ARM_PLL_DIV		295
+#define IMX8MQ_CLK_MON_SYS_PLL1_DIV		296
+#define IMX8MQ_CLK_MON_SYS_PLL2_DIV		297
+#define IMX8MQ_CLK_MON_SYS_PLL3_DIV		298
+#define IMX8MQ_CLK_MON_DRAM_PLL_DIV		299
+#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV		300
+#define IMX8MQ_CLK_MON_SEL			301
+#define IMX8MQ_CLK_MON_CLK2_OUT			302
+
+#define IMX8MQ_CLK_END				303
 
 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [PATCH 1/3] clk: imx8mq: add PLL monitor output
@ 2021-01-25 17:41 ` Lucas Stach
  0 siblings, 0 replies; 16+ messages in thread
From: Lucas Stach @ 2021-01-25 17:41 UTC (permalink / raw)
  To: Stephen Boyd, Shawn Guo, Michael Turquette
  Cc: Peng Fan, Abel Vesa, patchwork-lst, NXP Linux Team, kernel,
	Fabio Estevam, linux-clk, linux-arm-kernel

The PLL monitor is mentioned as a debug feature in the reference manual,
but there are some boards that use this clock output as a reference clock
for board level components. Add support for those clocks in the clock
driver, so this clock output can be used properly.

Note that the VIDEO1, GPU and VPU mux inputs are rotated compared to the
description in the reference manual. The order in this patch has been
empirically validated.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/clk/imx/clk-imx8mq.c             | 22 ++++++++++++++++++++++
 include/dt-bindings/clock/imx8mq-clock.h | 16 +++++++++++++++-
 2 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 779ea69e639c..4dd4ae9d022b 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -270,6 +270,14 @@ static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "os
 static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m",
 					  "sys3_pll_out", "audio_pll1_out", "video_pll1_out", "ckil", };
 
+static const char * const pllout_monitor_sels[] = {"osc_25m", "osc_27m", "dummy", "dummy", "ckil",
+						   "audio_pll1_out_monitor", "audio_pll2_out_monitor",
+						   "video_pll1_out_monitor", "gpu_pll_out_monitor",
+						   "vpu_pll_out_monitor", "arm_pll_out_monitor",
+						   "sys_pll1_out_monitor", "sys_pll2_out_monitor",
+						   "sys_pll3_out_monitor", "dram_pll_out_monitor",
+						   "video_pll2_out_monitor", };
+
 static struct clk_hw_onecell_data *clk_hw_data;
 static struct clk_hw **hws;
 
@@ -399,6 +407,20 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);
 	hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);
 
+	hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3);
+	hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3);
+	hws[IMX8MQ_CLK_MON_VIDEO_PLL1_DIV] = imx_clk_hw_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3);
+	hws[IMX8MQ_CLK_MON_GPU_PLL_DIV] = imx_clk_hw_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3);
+	hws[IMX8MQ_CLK_MON_VPU_PLL_DIV] = imx_clk_hw_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3);
+	hws[IMX8MQ_CLK_MON_ARM_PLL_DIV] = imx_clk_hw_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3);
+	hws[IMX8MQ_CLK_MON_SYS_PLL1_DIV] = imx_clk_hw_divider("sys_pll1_out_monitor", "sys1_pll_out", base + 0x7c, 0, 3);
+	hws[IMX8MQ_CLK_MON_SYS_PLL2_DIV] = imx_clk_hw_divider("sys_pll2_out_monitor", "sys2_pll_out", base + 0x7c, 4, 3);
+	hws[IMX8MQ_CLK_MON_SYS_PLL3_DIV] = imx_clk_hw_divider("sys_pll3_out_monitor", "sys3_pll_out", base + 0x7c, 8, 3);
+	hws[IMX8MQ_CLK_MON_DRAM_PLL_DIV] = imx_clk_hw_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3);
+	hws[IMX8MQ_CLK_MON_VIDEO_PLL2_DIV] = imx_clk_hw_divider("video_pll2_out_monitor", "video2_pll_out", base + 0x7c, 16, 3);
+	hws[IMX8MQ_CLK_MON_SEL] = imx_clk_hw_mux("pllout_monitor_sel", base + 0x74, 0, 4, pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels));
+	hws[IMX8MQ_CLK_MON_CLK2_OUT] = imx_clk_hw_gate("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4);
+
 	np = dev->of_node;
 	base = devm_platform_ioremap_resource(pdev, 0);
 	if (WARN_ON(IS_ERR(base)))
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index 9b8045d75b8b..82e907ce7bdd 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -431,6 +431,20 @@
 
 #define IMX8MQ_CLK_A53_CORE			289
 
-#define IMX8MQ_CLK_END				290
+#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV		290
+#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV		291
+#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV		292
+#define IMX8MQ_CLK_MON_GPU_PLL_DIV		293
+#define IMX8MQ_CLK_MON_VPU_PLL_DIV		294
+#define IMX8MQ_CLK_MON_ARM_PLL_DIV		295
+#define IMX8MQ_CLK_MON_SYS_PLL1_DIV		296
+#define IMX8MQ_CLK_MON_SYS_PLL2_DIV		297
+#define IMX8MQ_CLK_MON_SYS_PLL3_DIV		298
+#define IMX8MQ_CLK_MON_DRAM_PLL_DIV		299
+#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV		300
+#define IMX8MQ_CLK_MON_SEL			301
+#define IMX8MQ_CLK_MON_CLK2_OUT			302
+
+#define IMX8MQ_CLK_END				303
 
 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [PATCH 2/3] clk: imx8mm: add clkout1/2 support
  2021-01-25 17:41 ` Lucas Stach
@ 2021-01-25 17:41   ` Lucas Stach
  -1 siblings, 0 replies; 16+ messages in thread
From: Lucas Stach @ 2021-01-25 17:41 UTC (permalink / raw)
  To: Stephen Boyd, Shawn Guo, Michael Turquette
  Cc: Fabio Estevam, NXP Linux Team, Peng Fan, Abel Vesa, linux-clk,
	linux-arm-kernel, kernel, patchwork-lst

clkout1 and clkout2 allow to supply clocks from the SoC to the board,
which is used by some board designs to provide reference clocks.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/clk/imx/clk-imx8mm.c             | 12 ++++++++++++
 include/dt-bindings/clock/imx8mm-clock.h | 10 +++++++++-
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 7c905861af5d..6a01eec36dd0 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -288,6 +288,11 @@ static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "
 static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
 					  "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", };
 
+static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+					   "dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
+					   "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
+					   "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
+
 static struct clk_hw_onecell_data *clk_hw_data;
 static struct clk_hw **hws;
 
@@ -410,6 +415,13 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
 	hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
 
+	hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
+	hws[IMX8MM_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
+	hws[IMX8MM_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
+	hws[IMX8MM_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
+	hws[IMX8MM_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
+	hws[IMX8MM_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
+
 	np = dev->of_node;
 	base = devm_platform_ioremap_resource(pdev, 0);
 	if (WARN_ON(IS_ERR(base)))
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
index e63a5530aed7..47c6f7f9582c 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -274,6 +274,14 @@
 
 #define IMX8MM_CLK_A53_CORE			251
 
-#define IMX8MM_CLK_END				252
+#define IMX8MM_CLK_CLKOUT1_SEL			252
+#define IMX8MM_CLK_CLKOUT1_DIV			253
+#define IMX8MM_CLK_CLKOUT1			254
+#define IMX8MM_CLK_CLKOUT2_SEL			255
+#define IMX8MM_CLK_CLKOUT2_DIV			256
+#define IMX8MM_CLK_CLKOUT2			257
+
+
+#define IMX8MM_CLK_END				258
 
 #endif
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [PATCH 2/3] clk: imx8mm: add clkout1/2 support
@ 2021-01-25 17:41   ` Lucas Stach
  0 siblings, 0 replies; 16+ messages in thread
From: Lucas Stach @ 2021-01-25 17:41 UTC (permalink / raw)
  To: Stephen Boyd, Shawn Guo, Michael Turquette
  Cc: Peng Fan, Abel Vesa, patchwork-lst, NXP Linux Team, kernel,
	Fabio Estevam, linux-clk, linux-arm-kernel

clkout1 and clkout2 allow to supply clocks from the SoC to the board,
which is used by some board designs to provide reference clocks.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/clk/imx/clk-imx8mm.c             | 12 ++++++++++++
 include/dt-bindings/clock/imx8mm-clock.h | 10 +++++++++-
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 7c905861af5d..6a01eec36dd0 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -288,6 +288,11 @@ static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "
 static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
 					  "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", };
 
+static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+					   "dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
+					   "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
+					   "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
+
 static struct clk_hw_onecell_data *clk_hw_data;
 static struct clk_hw **hws;
 
@@ -410,6 +415,13 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
 	hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
 
+	hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
+	hws[IMX8MM_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
+	hws[IMX8MM_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
+	hws[IMX8MM_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
+	hws[IMX8MM_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
+	hws[IMX8MM_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
+
 	np = dev->of_node;
 	base = devm_platform_ioremap_resource(pdev, 0);
 	if (WARN_ON(IS_ERR(base)))
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
index e63a5530aed7..47c6f7f9582c 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -274,6 +274,14 @@
 
 #define IMX8MM_CLK_A53_CORE			251
 
-#define IMX8MM_CLK_END				252
+#define IMX8MM_CLK_CLKOUT1_SEL			252
+#define IMX8MM_CLK_CLKOUT1_DIV			253
+#define IMX8MM_CLK_CLKOUT1			254
+#define IMX8MM_CLK_CLKOUT2_SEL			255
+#define IMX8MM_CLK_CLKOUT2_DIV			256
+#define IMX8MM_CLK_CLKOUT2			257
+
+
+#define IMX8MM_CLK_END				258
 
 #endif
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [PATCH 3/3] clk: imx8mn: add clkout1/2 support
  2021-01-25 17:41 ` Lucas Stach
@ 2021-01-25 17:41   ` Lucas Stach
  -1 siblings, 0 replies; 16+ messages in thread
From: Lucas Stach @ 2021-01-25 17:41 UTC (permalink / raw)
  To: Stephen Boyd, Shawn Guo, Michael Turquette
  Cc: Fabio Estevam, NXP Linux Team, Peng Fan, Abel Vesa, linux-clk,
	linux-arm-kernel, kernel, patchwork-lst

clkout1 and clkout2 allow to supply clocks from the SoC to the board,
which is used by some board designs to provide reference clocks.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
This hasn't been tested on HW, but is just based on the reference manual.
---
 drivers/clk/imx/clk-imx8mn.c             | 12 ++++++++++++
 include/dt-bindings/clock/imx8mn-clock.h |  9 ++++++++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 3c21db942d5b..324c5fd0aa04 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -281,6 +281,11 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy
 						 "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
 						 "video_pll1_out", "osc_32k", };
 
+static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+					   "dummy", "dummy", "gpu_pll_out", "dummy",
+					   "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
+					   "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
+
 static struct clk_hw_onecell_data *clk_hw_data;
 static struct clk_hw **hws;
 
@@ -405,6 +410,13 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
 	hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
 
+	hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
+	hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
+	hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
+	hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
+	hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
+	hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
+
 	np = dev->of_node;
 	base = devm_platform_ioremap_resource(pdev, 0);
 	if (WARN_ON(IS_ERR(base))) {
diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
index 621ea0e87c67..d24b627cb2e7 100644
--- a/include/dt-bindings/clock/imx8mn-clock.h
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -234,6 +234,13 @@
 
 #define IMX8MN_CLK_A53_CORE			214
 
-#define IMX8MN_CLK_END				215
+#define IMX8MN_CLK_CLKOUT1_SEL			215
+#define IMX8MN_CLK_CLKOUT1_DIV			216
+#define IMX8MN_CLK_CLKOUT1			217
+#define IMX8MN_CLK_CLKOUT2_SEL			218
+#define IMX8MN_CLK_CLKOUT2_DIV			219
+#define IMX8MN_CLK_CLKOUT2			220
+
+#define IMX8MN_CLK_END				221
 
 #endif
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [PATCH 3/3] clk: imx8mn: add clkout1/2 support
@ 2021-01-25 17:41   ` Lucas Stach
  0 siblings, 0 replies; 16+ messages in thread
From: Lucas Stach @ 2021-01-25 17:41 UTC (permalink / raw)
  To: Stephen Boyd, Shawn Guo, Michael Turquette
  Cc: Peng Fan, Abel Vesa, patchwork-lst, NXP Linux Team, kernel,
	Fabio Estevam, linux-clk, linux-arm-kernel

clkout1 and clkout2 allow to supply clocks from the SoC to the board,
which is used by some board designs to provide reference clocks.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
This hasn't been tested on HW, but is just based on the reference manual.
---
 drivers/clk/imx/clk-imx8mn.c             | 12 ++++++++++++
 include/dt-bindings/clock/imx8mn-clock.h |  9 ++++++++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 3c21db942d5b..324c5fd0aa04 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -281,6 +281,11 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy
 						 "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
 						 "video_pll1_out", "osc_32k", };
 
+static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+					   "dummy", "dummy", "gpu_pll_out", "dummy",
+					   "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
+					   "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
+
 static struct clk_hw_onecell_data *clk_hw_data;
 static struct clk_hw **hws;
 
@@ -405,6 +410,13 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
 	hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
 
+	hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
+	hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
+	hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
+	hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
+	hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
+	hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
+
 	np = dev->of_node;
 	base = devm_platform_ioremap_resource(pdev, 0);
 	if (WARN_ON(IS_ERR(base))) {
diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
index 621ea0e87c67..d24b627cb2e7 100644
--- a/include/dt-bindings/clock/imx8mn-clock.h
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -234,6 +234,13 @@
 
 #define IMX8MN_CLK_A53_CORE			214
 
-#define IMX8MN_CLK_END				215
+#define IMX8MN_CLK_CLKOUT1_SEL			215
+#define IMX8MN_CLK_CLKOUT1_DIV			216
+#define IMX8MN_CLK_CLKOUT1			217
+#define IMX8MN_CLK_CLKOUT2_SEL			218
+#define IMX8MN_CLK_CLKOUT2_DIV			219
+#define IMX8MN_CLK_CLKOUT2			220
+
+#define IMX8MN_CLK_END				221
 
 #endif
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] clk: imx8mq: add PLL monitor output
  2021-01-25 17:41 ` Lucas Stach
@ 2021-01-25 18:19   ` Abel Vesa
  -1 siblings, 0 replies; 16+ messages in thread
From: Abel Vesa @ 2021-01-25 18:19 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Stephen Boyd, Shawn Guo, Michael Turquette, Fabio Estevam,
	NXP Linux Team, Peng Fan, linux-clk, linux-arm-kernel, kernel,
	patchwork-lst

On 21-01-25 18:41:33, Lucas Stach wrote:
> The PLL monitor is mentioned as a debug feature in the reference manual,
> but there are some boards that use this clock output as a reference clock
> for board level components. Add support for those clocks in the clock
> driver, so this clock output can be used properly.
> 
> Note that the VIDEO1, GPU and VPU mux inputs are rotated compared to the
> description in the reference manual. The order in this patch has been
> empirically validated.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/clk/imx/clk-imx8mq.c             | 22 ++++++++++++++++++++++
>  include/dt-bindings/clock/imx8mq-clock.h | 16 +++++++++++++++-
>  2 files changed, 37 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> index 779ea69e639c..4dd4ae9d022b 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -270,6 +270,14 @@ static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "os
>  static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m",
>  					  "sys3_pll_out", "audio_pll1_out", "video_pll1_out", "ckil", };
>  
> +static const char * const pllout_monitor_sels[] = {"osc_25m", "osc_27m", "dummy", "dummy", "ckil",
> +						   "audio_pll1_out_monitor", "audio_pll2_out_monitor",
> +						   "video_pll1_out_monitor", "gpu_pll_out_monitor",
> +						   "vpu_pll_out_monitor", "arm_pll_out_monitor",
> +						   "sys_pll1_out_monitor", "sys_pll2_out_monitor",
> +						   "sys_pll3_out_monitor", "dram_pll_out_monitor",
> +						   "video_pll2_out_monitor", };
> +
>  static struct clk_hw_onecell_data *clk_hw_data;
>  static struct clk_hw **hws;
>  
> @@ -399,6 +407,20 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);
>  	hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);
>  
> +	hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3);
> +	hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3);
> +	hws[IMX8MQ_CLK_MON_VIDEO_PLL1_DIV] = imx_clk_hw_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3);
> +	hws[IMX8MQ_CLK_MON_GPU_PLL_DIV] = imx_clk_hw_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3);
> +	hws[IMX8MQ_CLK_MON_VPU_PLL_DIV] = imx_clk_hw_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3);
> +	hws[IMX8MQ_CLK_MON_ARM_PLL_DIV] = imx_clk_hw_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3);
> +	hws[IMX8MQ_CLK_MON_SYS_PLL1_DIV] = imx_clk_hw_divider("sys_pll1_out_monitor", "sys1_pll_out", base + 0x7c, 0, 3);
> +	hws[IMX8MQ_CLK_MON_SYS_PLL2_DIV] = imx_clk_hw_divider("sys_pll2_out_monitor", "sys2_pll_out", base + 0x7c, 4, 3);
> +	hws[IMX8MQ_CLK_MON_SYS_PLL3_DIV] = imx_clk_hw_divider("sys_pll3_out_monitor", "sys3_pll_out", base + 0x7c, 8, 3);
> +	hws[IMX8MQ_CLK_MON_DRAM_PLL_DIV] = imx_clk_hw_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3);
> +	hws[IMX8MQ_CLK_MON_VIDEO_PLL2_DIV] = imx_clk_hw_divider("video_pll2_out_monitor", "video2_pll_out", base + 0x7c, 16, 3);
> +	hws[IMX8MQ_CLK_MON_SEL] = imx_clk_hw_mux("pllout_monitor_sel", base + 0x74, 0, 4, pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels));
> +	hws[IMX8MQ_CLK_MON_CLK2_OUT] = imx_clk_hw_gate("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4);
> +
>  	np = dev->of_node;
>  	base = devm_platform_ioremap_resource(pdev, 0);
>  	if (WARN_ON(IS_ERR(base)))
> diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
> index 9b8045d75b8b..82e907ce7bdd 100644
> --- a/include/dt-bindings/clock/imx8mq-clock.h
> +++ b/include/dt-bindings/clock/imx8mq-clock.h
> @@ -431,6 +431,20 @@
>  
>  #define IMX8MQ_CLK_A53_CORE			289

This goes through a different tree.

> -#define IMX8MQ_CLK_END				290
> +#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV		290
> +#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV		291
> +#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV		292
> +#define IMX8MQ_CLK_MON_GPU_PLL_DIV		293
> +#define IMX8MQ_CLK_MON_VPU_PLL_DIV		294
> +#define IMX8MQ_CLK_MON_ARM_PLL_DIV		295
> +#define IMX8MQ_CLK_MON_SYS_PLL1_DIV		296
> +#define IMX8MQ_CLK_MON_SYS_PLL2_DIV		297
> +#define IMX8MQ_CLK_MON_SYS_PLL3_DIV		298
> +#define IMX8MQ_CLK_MON_DRAM_PLL_DIV		299
> +#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV		300
> +#define IMX8MQ_CLK_MON_SEL			301
> +#define IMX8MQ_CLK_MON_CLK2_OUT			302
> +
> +#define IMX8MQ_CLK_END				303
>  
>  #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
> -- 
> 2.20.1
> 

Everything else looks good to me.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] clk: imx8mq: add PLL monitor output
@ 2021-01-25 18:19   ` Abel Vesa
  0 siblings, 0 replies; 16+ messages in thread
From: Abel Vesa @ 2021-01-25 18:19 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Peng Fan, Stephen Boyd, Shawn Guo, Michael Turquette,
	patchwork-lst, NXP Linux Team, kernel, Fabio Estevam, linux-clk,
	linux-arm-kernel

On 21-01-25 18:41:33, Lucas Stach wrote:
> The PLL monitor is mentioned as a debug feature in the reference manual,
> but there are some boards that use this clock output as a reference clock
> for board level components. Add support for those clocks in the clock
> driver, so this clock output can be used properly.
> 
> Note that the VIDEO1, GPU and VPU mux inputs are rotated compared to the
> description in the reference manual. The order in this patch has been
> empirically validated.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/clk/imx/clk-imx8mq.c             | 22 ++++++++++++++++++++++
>  include/dt-bindings/clock/imx8mq-clock.h | 16 +++++++++++++++-
>  2 files changed, 37 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> index 779ea69e639c..4dd4ae9d022b 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -270,6 +270,14 @@ static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "os
>  static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m",
>  					  "sys3_pll_out", "audio_pll1_out", "video_pll1_out", "ckil", };
>  
> +static const char * const pllout_monitor_sels[] = {"osc_25m", "osc_27m", "dummy", "dummy", "ckil",
> +						   "audio_pll1_out_monitor", "audio_pll2_out_monitor",
> +						   "video_pll1_out_monitor", "gpu_pll_out_monitor",
> +						   "vpu_pll_out_monitor", "arm_pll_out_monitor",
> +						   "sys_pll1_out_monitor", "sys_pll2_out_monitor",
> +						   "sys_pll3_out_monitor", "dram_pll_out_monitor",
> +						   "video_pll2_out_monitor", };
> +
>  static struct clk_hw_onecell_data *clk_hw_data;
>  static struct clk_hw **hws;
>  
> @@ -399,6 +407,20 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);
>  	hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);
>  
> +	hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3);
> +	hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3);
> +	hws[IMX8MQ_CLK_MON_VIDEO_PLL1_DIV] = imx_clk_hw_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3);
> +	hws[IMX8MQ_CLK_MON_GPU_PLL_DIV] = imx_clk_hw_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3);
> +	hws[IMX8MQ_CLK_MON_VPU_PLL_DIV] = imx_clk_hw_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3);
> +	hws[IMX8MQ_CLK_MON_ARM_PLL_DIV] = imx_clk_hw_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3);
> +	hws[IMX8MQ_CLK_MON_SYS_PLL1_DIV] = imx_clk_hw_divider("sys_pll1_out_monitor", "sys1_pll_out", base + 0x7c, 0, 3);
> +	hws[IMX8MQ_CLK_MON_SYS_PLL2_DIV] = imx_clk_hw_divider("sys_pll2_out_monitor", "sys2_pll_out", base + 0x7c, 4, 3);
> +	hws[IMX8MQ_CLK_MON_SYS_PLL3_DIV] = imx_clk_hw_divider("sys_pll3_out_monitor", "sys3_pll_out", base + 0x7c, 8, 3);
> +	hws[IMX8MQ_CLK_MON_DRAM_PLL_DIV] = imx_clk_hw_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3);
> +	hws[IMX8MQ_CLK_MON_VIDEO_PLL2_DIV] = imx_clk_hw_divider("video_pll2_out_monitor", "video2_pll_out", base + 0x7c, 16, 3);
> +	hws[IMX8MQ_CLK_MON_SEL] = imx_clk_hw_mux("pllout_monitor_sel", base + 0x74, 0, 4, pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels));
> +	hws[IMX8MQ_CLK_MON_CLK2_OUT] = imx_clk_hw_gate("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4);
> +
>  	np = dev->of_node;
>  	base = devm_platform_ioremap_resource(pdev, 0);
>  	if (WARN_ON(IS_ERR(base)))
> diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
> index 9b8045d75b8b..82e907ce7bdd 100644
> --- a/include/dt-bindings/clock/imx8mq-clock.h
> +++ b/include/dt-bindings/clock/imx8mq-clock.h
> @@ -431,6 +431,20 @@
>  
>  #define IMX8MQ_CLK_A53_CORE			289

This goes through a different tree.

> -#define IMX8MQ_CLK_END				290
> +#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV		290
> +#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV		291
> +#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV		292
> +#define IMX8MQ_CLK_MON_GPU_PLL_DIV		293
> +#define IMX8MQ_CLK_MON_VPU_PLL_DIV		294
> +#define IMX8MQ_CLK_MON_ARM_PLL_DIV		295
> +#define IMX8MQ_CLK_MON_SYS_PLL1_DIV		296
> +#define IMX8MQ_CLK_MON_SYS_PLL2_DIV		297
> +#define IMX8MQ_CLK_MON_SYS_PLL3_DIV		298
> +#define IMX8MQ_CLK_MON_DRAM_PLL_DIV		299
> +#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV		300
> +#define IMX8MQ_CLK_MON_SEL			301
> +#define IMX8MQ_CLK_MON_CLK2_OUT			302
> +
> +#define IMX8MQ_CLK_END				303
>  
>  #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
> -- 
> 2.20.1
> 

Everything else looks good to me.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] clk: imx8mq: add PLL monitor output
  2021-01-25 18:19   ` Abel Vesa
@ 2021-01-25 18:24     ` Abel Vesa
  -1 siblings, 0 replies; 16+ messages in thread
From: Abel Vesa @ 2021-01-25 18:24 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Stephen Boyd, Shawn Guo, Michael Turquette, Fabio Estevam,
	NXP Linux Team, Peng Fan, linux-clk, linux-arm-kernel, kernel,
	patchwork-lst

On 21-01-25 20:19:07, Abel Vesa wrote:
> On 21-01-25 18:41:33, Lucas Stach wrote:
> > The PLL monitor is mentioned as a debug feature in the reference manual,
> > but there are some boards that use this clock output as a reference clock
> > for board level components. Add support for those clocks in the clock
> > driver, so this clock output can be used properly.
> > 
> > Note that the VIDEO1, GPU and VPU mux inputs are rotated compared to the
> > description in the reference manual. The order in this patch has been
> > empirically validated.
> > 
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> >  drivers/clk/imx/clk-imx8mq.c             | 22 ++++++++++++++++++++++
> >  include/dt-bindings/clock/imx8mq-clock.h | 16 +++++++++++++++-
> >  2 files changed, 37 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> > index 779ea69e639c..4dd4ae9d022b 100644
> > --- a/drivers/clk/imx/clk-imx8mq.c
> > +++ b/drivers/clk/imx/clk-imx8mq.c
> > @@ -270,6 +270,14 @@ static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "os
> >  static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m",
> >  					  "sys3_pll_out", "audio_pll1_out", "video_pll1_out", "ckil", };
> >  
> > +static const char * const pllout_monitor_sels[] = {"osc_25m", "osc_27m", "dummy", "dummy", "ckil",
> > +						   "audio_pll1_out_monitor", "audio_pll2_out_monitor",
> > +						   "video_pll1_out_monitor", "gpu_pll_out_monitor",
> > +						   "vpu_pll_out_monitor", "arm_pll_out_monitor",
> > +						   "sys_pll1_out_monitor", "sys_pll2_out_monitor",
> > +						   "sys_pll3_out_monitor", "dram_pll_out_monitor",
> > +						   "video_pll2_out_monitor", };
> > +
> >  static struct clk_hw_onecell_data *clk_hw_data;
> >  static struct clk_hw **hws;
> >  
> > @@ -399,6 +407,20 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
> >  	hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);
> >  	hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);
> >  
> > +	hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3);
> > +	hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3);
> > +	hws[IMX8MQ_CLK_MON_VIDEO_PLL1_DIV] = imx_clk_hw_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3);
> > +	hws[IMX8MQ_CLK_MON_GPU_PLL_DIV] = imx_clk_hw_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3);
> > +	hws[IMX8MQ_CLK_MON_VPU_PLL_DIV] = imx_clk_hw_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3);
> > +	hws[IMX8MQ_CLK_MON_ARM_PLL_DIV] = imx_clk_hw_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3);
> > +	hws[IMX8MQ_CLK_MON_SYS_PLL1_DIV] = imx_clk_hw_divider("sys_pll1_out_monitor", "sys1_pll_out", base + 0x7c, 0, 3);
> > +	hws[IMX8MQ_CLK_MON_SYS_PLL2_DIV] = imx_clk_hw_divider("sys_pll2_out_monitor", "sys2_pll_out", base + 0x7c, 4, 3);
> > +	hws[IMX8MQ_CLK_MON_SYS_PLL3_DIV] = imx_clk_hw_divider("sys_pll3_out_monitor", "sys3_pll_out", base + 0x7c, 8, 3);
> > +	hws[IMX8MQ_CLK_MON_DRAM_PLL_DIV] = imx_clk_hw_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3);
> > +	hws[IMX8MQ_CLK_MON_VIDEO_PLL2_DIV] = imx_clk_hw_divider("video_pll2_out_monitor", "video2_pll_out", base + 0x7c, 16, 3);
> > +	hws[IMX8MQ_CLK_MON_SEL] = imx_clk_hw_mux("pllout_monitor_sel", base + 0x74, 0, 4, pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels));
> > +	hws[IMX8MQ_CLK_MON_CLK2_OUT] = imx_clk_hw_gate("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4);
> > +
> >  	np = dev->of_node;
> >  	base = devm_platform_ioremap_resource(pdev, 0);
> >  	if (WARN_ON(IS_ERR(base)))
> > diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
> > index 9b8045d75b8b..82e907ce7bdd 100644
> > --- a/include/dt-bindings/clock/imx8mq-clock.h
> > +++ b/include/dt-bindings/clock/imx8mq-clock.h
> > @@ -431,6 +431,20 @@
> >  
> >  #define IMX8MQ_CLK_A53_CORE			289
> 
> This goes through a different tree.
> 

Scratch that.

> > -#define IMX8MQ_CLK_END				290
> > +#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV		290
> > +#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV		291
> > +#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV		292
> > +#define IMX8MQ_CLK_MON_GPU_PLL_DIV		293
> > +#define IMX8MQ_CLK_MON_VPU_PLL_DIV		294
> > +#define IMX8MQ_CLK_MON_ARM_PLL_DIV		295
> > +#define IMX8MQ_CLK_MON_SYS_PLL1_DIV		296
> > +#define IMX8MQ_CLK_MON_SYS_PLL2_DIV		297
> > +#define IMX8MQ_CLK_MON_SYS_PLL3_DIV		298
> > +#define IMX8MQ_CLK_MON_DRAM_PLL_DIV		299
> > +#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV		300
> > +#define IMX8MQ_CLK_MON_SEL			301
> > +#define IMX8MQ_CLK_MON_CLK2_OUT			302
> > +
> > +#define IMX8MQ_CLK_END				303
> >  
> >  #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
> > -- 
> > 2.20.1
> > 
> 
> Everything else looks good to me.
> 
> Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] clk: imx8mq: add PLL monitor output
@ 2021-01-25 18:24     ` Abel Vesa
  0 siblings, 0 replies; 16+ messages in thread
From: Abel Vesa @ 2021-01-25 18:24 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Peng Fan, Stephen Boyd, Shawn Guo, Michael Turquette,
	patchwork-lst, NXP Linux Team, kernel, Fabio Estevam, linux-clk,
	linux-arm-kernel

On 21-01-25 20:19:07, Abel Vesa wrote:
> On 21-01-25 18:41:33, Lucas Stach wrote:
> > The PLL monitor is mentioned as a debug feature in the reference manual,
> > but there are some boards that use this clock output as a reference clock
> > for board level components. Add support for those clocks in the clock
> > driver, so this clock output can be used properly.
> > 
> > Note that the VIDEO1, GPU and VPU mux inputs are rotated compared to the
> > description in the reference manual. The order in this patch has been
> > empirically validated.
> > 
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> >  drivers/clk/imx/clk-imx8mq.c             | 22 ++++++++++++++++++++++
> >  include/dt-bindings/clock/imx8mq-clock.h | 16 +++++++++++++++-
> >  2 files changed, 37 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> > index 779ea69e639c..4dd4ae9d022b 100644
> > --- a/drivers/clk/imx/clk-imx8mq.c
> > +++ b/drivers/clk/imx/clk-imx8mq.c
> > @@ -270,6 +270,14 @@ static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "os
> >  static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m",
> >  					  "sys3_pll_out", "audio_pll1_out", "video_pll1_out", "ckil", };
> >  
> > +static const char * const pllout_monitor_sels[] = {"osc_25m", "osc_27m", "dummy", "dummy", "ckil",
> > +						   "audio_pll1_out_monitor", "audio_pll2_out_monitor",
> > +						   "video_pll1_out_monitor", "gpu_pll_out_monitor",
> > +						   "vpu_pll_out_monitor", "arm_pll_out_monitor",
> > +						   "sys_pll1_out_monitor", "sys_pll2_out_monitor",
> > +						   "sys_pll3_out_monitor", "dram_pll_out_monitor",
> > +						   "video_pll2_out_monitor", };
> > +
> >  static struct clk_hw_onecell_data *clk_hw_data;
> >  static struct clk_hw **hws;
> >  
> > @@ -399,6 +407,20 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
> >  	hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);
> >  	hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);
> >  
> > +	hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3);
> > +	hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3);
> > +	hws[IMX8MQ_CLK_MON_VIDEO_PLL1_DIV] = imx_clk_hw_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3);
> > +	hws[IMX8MQ_CLK_MON_GPU_PLL_DIV] = imx_clk_hw_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3);
> > +	hws[IMX8MQ_CLK_MON_VPU_PLL_DIV] = imx_clk_hw_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3);
> > +	hws[IMX8MQ_CLK_MON_ARM_PLL_DIV] = imx_clk_hw_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3);
> > +	hws[IMX8MQ_CLK_MON_SYS_PLL1_DIV] = imx_clk_hw_divider("sys_pll1_out_monitor", "sys1_pll_out", base + 0x7c, 0, 3);
> > +	hws[IMX8MQ_CLK_MON_SYS_PLL2_DIV] = imx_clk_hw_divider("sys_pll2_out_monitor", "sys2_pll_out", base + 0x7c, 4, 3);
> > +	hws[IMX8MQ_CLK_MON_SYS_PLL3_DIV] = imx_clk_hw_divider("sys_pll3_out_monitor", "sys3_pll_out", base + 0x7c, 8, 3);
> > +	hws[IMX8MQ_CLK_MON_DRAM_PLL_DIV] = imx_clk_hw_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3);
> > +	hws[IMX8MQ_CLK_MON_VIDEO_PLL2_DIV] = imx_clk_hw_divider("video_pll2_out_monitor", "video2_pll_out", base + 0x7c, 16, 3);
> > +	hws[IMX8MQ_CLK_MON_SEL] = imx_clk_hw_mux("pllout_monitor_sel", base + 0x74, 0, 4, pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels));
> > +	hws[IMX8MQ_CLK_MON_CLK2_OUT] = imx_clk_hw_gate("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4);
> > +
> >  	np = dev->of_node;
> >  	base = devm_platform_ioremap_resource(pdev, 0);
> >  	if (WARN_ON(IS_ERR(base)))
> > diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
> > index 9b8045d75b8b..82e907ce7bdd 100644
> > --- a/include/dt-bindings/clock/imx8mq-clock.h
> > +++ b/include/dt-bindings/clock/imx8mq-clock.h
> > @@ -431,6 +431,20 @@
> >  
> >  #define IMX8MQ_CLK_A53_CORE			289
> 
> This goes through a different tree.
> 

Scratch that.

> > -#define IMX8MQ_CLK_END				290
> > +#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV		290
> > +#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV		291
> > +#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV		292
> > +#define IMX8MQ_CLK_MON_GPU_PLL_DIV		293
> > +#define IMX8MQ_CLK_MON_VPU_PLL_DIV		294
> > +#define IMX8MQ_CLK_MON_ARM_PLL_DIV		295
> > +#define IMX8MQ_CLK_MON_SYS_PLL1_DIV		296
> > +#define IMX8MQ_CLK_MON_SYS_PLL2_DIV		297
> > +#define IMX8MQ_CLK_MON_SYS_PLL3_DIV		298
> > +#define IMX8MQ_CLK_MON_DRAM_PLL_DIV		299
> > +#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV		300
> > +#define IMX8MQ_CLK_MON_SEL			301
> > +#define IMX8MQ_CLK_MON_CLK2_OUT			302
> > +
> > +#define IMX8MQ_CLK_END				303
> >  
> >  #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
> > -- 
> > 2.20.1
> > 
> 
> Everything else looks good to me.
> 
> Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] clk: imx8mn: add clkout1/2 support
  2021-01-25 17:41   ` Lucas Stach
@ 2021-01-25 18:36     ` Abel Vesa
  -1 siblings, 0 replies; 16+ messages in thread
From: Abel Vesa @ 2021-01-25 18:36 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Stephen Boyd, Shawn Guo, Michael Turquette, Fabio Estevam,
	NXP Linux Team, Peng Fan, linux-clk, linux-arm-kernel, kernel,
	patchwork-lst

On 21-01-25 18:41:35, Lucas Stach wrote:
> clkout1 and clkout2 allow to supply clocks from the SoC to the board,
> which is used by some board designs to provide reference clocks.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Looks good to me.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
> This hasn't been tested on HW, but is just based on the reference manual.
> ---
>  drivers/clk/imx/clk-imx8mn.c             | 12 ++++++++++++
>  include/dt-bindings/clock/imx8mn-clock.h |  9 ++++++++-
>  2 files changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index 3c21db942d5b..324c5fd0aa04 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -281,6 +281,11 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy
>  						 "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
>  						 "video_pll1_out", "osc_32k", };
>  
> +static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
> +					   "dummy", "dummy", "gpu_pll_out", "dummy",
> +					   "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
> +					   "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
> +
>  static struct clk_hw_onecell_data *clk_hw_data;
>  static struct clk_hw **hws;
>  
> @@ -405,6 +410,13 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
>  	hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
>  
> +	hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> +	hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
> +	hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
> +	hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> +	hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
> +	hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
> +
>  	np = dev->of_node;
>  	base = devm_platform_ioremap_resource(pdev, 0);
>  	if (WARN_ON(IS_ERR(base))) {
> diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
> index 621ea0e87c67..d24b627cb2e7 100644
> --- a/include/dt-bindings/clock/imx8mn-clock.h
> +++ b/include/dt-bindings/clock/imx8mn-clock.h
> @@ -234,6 +234,13 @@
>  
>  #define IMX8MN_CLK_A53_CORE			214
>  
> -#define IMX8MN_CLK_END				215
> +#define IMX8MN_CLK_CLKOUT1_SEL			215
> +#define IMX8MN_CLK_CLKOUT1_DIV			216
> +#define IMX8MN_CLK_CLKOUT1			217
> +#define IMX8MN_CLK_CLKOUT2_SEL			218
> +#define IMX8MN_CLK_CLKOUT2_DIV			219
> +#define IMX8MN_CLK_CLKOUT2			220
> +
> +#define IMX8MN_CLK_END				221
>  
>  #endif
> -- 
> 2.20.1
> 

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] clk: imx8mn: add clkout1/2 support
@ 2021-01-25 18:36     ` Abel Vesa
  0 siblings, 0 replies; 16+ messages in thread
From: Abel Vesa @ 2021-01-25 18:36 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Peng Fan, Stephen Boyd, Shawn Guo, Michael Turquette,
	patchwork-lst, NXP Linux Team, kernel, Fabio Estevam, linux-clk,
	linux-arm-kernel

On 21-01-25 18:41:35, Lucas Stach wrote:
> clkout1 and clkout2 allow to supply clocks from the SoC to the board,
> which is used by some board designs to provide reference clocks.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Looks good to me.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
> This hasn't been tested on HW, but is just based on the reference manual.
> ---
>  drivers/clk/imx/clk-imx8mn.c             | 12 ++++++++++++
>  include/dt-bindings/clock/imx8mn-clock.h |  9 ++++++++-
>  2 files changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index 3c21db942d5b..324c5fd0aa04 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -281,6 +281,11 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy
>  						 "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
>  						 "video_pll1_out", "osc_32k", };
>  
> +static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
> +					   "dummy", "dummy", "gpu_pll_out", "dummy",
> +					   "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
> +					   "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
> +
>  static struct clk_hw_onecell_data *clk_hw_data;
>  static struct clk_hw **hws;
>  
> @@ -405,6 +410,13 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
>  	hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
>  
> +	hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> +	hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
> +	hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
> +	hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> +	hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
> +	hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
> +
>  	np = dev->of_node;
>  	base = devm_platform_ioremap_resource(pdev, 0);
>  	if (WARN_ON(IS_ERR(base))) {
> diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
> index 621ea0e87c67..d24b627cb2e7 100644
> --- a/include/dt-bindings/clock/imx8mn-clock.h
> +++ b/include/dt-bindings/clock/imx8mn-clock.h
> @@ -234,6 +234,13 @@
>  
>  #define IMX8MN_CLK_A53_CORE			214
>  
> -#define IMX8MN_CLK_END				215
> +#define IMX8MN_CLK_CLKOUT1_SEL			215
> +#define IMX8MN_CLK_CLKOUT1_DIV			216
> +#define IMX8MN_CLK_CLKOUT1			217
> +#define IMX8MN_CLK_CLKOUT2_SEL			218
> +#define IMX8MN_CLK_CLKOUT2_DIV			219
> +#define IMX8MN_CLK_CLKOUT2			220
> +
> +#define IMX8MN_CLK_END				221
>  
>  #endif
> -- 
> 2.20.1
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 2/3] clk: imx8mm: add clkout1/2 support
  2021-01-25 17:41   ` Lucas Stach
@ 2021-01-25 18:36     ` Abel Vesa
  -1 siblings, 0 replies; 16+ messages in thread
From: Abel Vesa @ 2021-01-25 18:36 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Stephen Boyd, Shawn Guo, Michael Turquette, Fabio Estevam,
	NXP Linux Team, Peng Fan, linux-clk, linux-arm-kernel, kernel,
	patchwork-lst

On 21-01-25 18:41:34, Lucas Stach wrote:
> clkout1 and clkout2 allow to supply clocks from the SoC to the board,
> which is used by some board designs to provide reference clocks.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Looks good to me.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>  drivers/clk/imx/clk-imx8mm.c             | 12 ++++++++++++
>  include/dt-bindings/clock/imx8mm-clock.h | 10 +++++++++-
>  2 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index 7c905861af5d..6a01eec36dd0 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -288,6 +288,11 @@ static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "
>  static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
>  					  "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", };
>  
> +static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
> +					   "dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
> +					   "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
> +					   "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
> +
>  static struct clk_hw_onecell_data *clk_hw_data;
>  static struct clk_hw **hws;
>  
> @@ -410,6 +415,13 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
>  	hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
>  
> +	hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> +	hws[IMX8MM_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
> +	hws[IMX8MM_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
> +	hws[IMX8MM_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> +	hws[IMX8MM_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
> +	hws[IMX8MM_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
> +
>  	np = dev->of_node;
>  	base = devm_platform_ioremap_resource(pdev, 0);
>  	if (WARN_ON(IS_ERR(base)))
> diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
> index e63a5530aed7..47c6f7f9582c 100644
> --- a/include/dt-bindings/clock/imx8mm-clock.h
> +++ b/include/dt-bindings/clock/imx8mm-clock.h
> @@ -274,6 +274,14 @@
>  
>  #define IMX8MM_CLK_A53_CORE			251
>  
> -#define IMX8MM_CLK_END				252
> +#define IMX8MM_CLK_CLKOUT1_SEL			252
> +#define IMX8MM_CLK_CLKOUT1_DIV			253
> +#define IMX8MM_CLK_CLKOUT1			254
> +#define IMX8MM_CLK_CLKOUT2_SEL			255
> +#define IMX8MM_CLK_CLKOUT2_DIV			256
> +#define IMX8MM_CLK_CLKOUT2			257
> +
> +
> +#define IMX8MM_CLK_END				258
>  
>  #endif
> -- 
> 2.20.1
> 

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 2/3] clk: imx8mm: add clkout1/2 support
@ 2021-01-25 18:36     ` Abel Vesa
  0 siblings, 0 replies; 16+ messages in thread
From: Abel Vesa @ 2021-01-25 18:36 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Peng Fan, Stephen Boyd, Shawn Guo, Michael Turquette,
	patchwork-lst, NXP Linux Team, kernel, Fabio Estevam, linux-clk,
	linux-arm-kernel

On 21-01-25 18:41:34, Lucas Stach wrote:
> clkout1 and clkout2 allow to supply clocks from the SoC to the board,
> which is used by some board designs to provide reference clocks.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Looks good to me.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>  drivers/clk/imx/clk-imx8mm.c             | 12 ++++++++++++
>  include/dt-bindings/clock/imx8mm-clock.h | 10 +++++++++-
>  2 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index 7c905861af5d..6a01eec36dd0 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -288,6 +288,11 @@ static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "
>  static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
>  					  "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", };
>  
> +static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
> +					   "dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
> +					   "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
> +					   "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
> +
>  static struct clk_hw_onecell_data *clk_hw_data;
>  static struct clk_hw **hws;
>  
> @@ -410,6 +415,13 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
>  	hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
>  
> +	hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> +	hws[IMX8MM_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
> +	hws[IMX8MM_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
> +	hws[IMX8MM_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> +	hws[IMX8MM_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
> +	hws[IMX8MM_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
> +
>  	np = dev->of_node;
>  	base = devm_platform_ioremap_resource(pdev, 0);
>  	if (WARN_ON(IS_ERR(base)))
> diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
> index e63a5530aed7..47c6f7f9582c 100644
> --- a/include/dt-bindings/clock/imx8mm-clock.h
> +++ b/include/dt-bindings/clock/imx8mm-clock.h
> @@ -274,6 +274,14 @@
>  
>  #define IMX8MM_CLK_A53_CORE			251
>  
> -#define IMX8MM_CLK_END				252
> +#define IMX8MM_CLK_CLKOUT1_SEL			252
> +#define IMX8MM_CLK_CLKOUT1_DIV			253
> +#define IMX8MM_CLK_CLKOUT1			254
> +#define IMX8MM_CLK_CLKOUT2_SEL			255
> +#define IMX8MM_CLK_CLKOUT2_DIV			256
> +#define IMX8MM_CLK_CLKOUT2			257
> +
> +
> +#define IMX8MM_CLK_END				258
>  
>  #endif
> -- 
> 2.20.1
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] clk: imx8mq: add PLL monitor output
  2021-01-25 17:41 ` Lucas Stach
@ 2021-01-30 13:36   ` Shawn Guo
  -1 siblings, 0 replies; 16+ messages in thread
From: Shawn Guo @ 2021-01-30 13:36 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Stephen Boyd, Michael Turquette, Fabio Estevam, NXP Linux Team,
	Peng Fan, Abel Vesa, linux-clk, linux-arm-kernel, kernel,
	patchwork-lst

On Mon, Jan 25, 2021 at 06:41:33PM +0100, Lucas Stach wrote:
> The PLL monitor is mentioned as a debug feature in the reference manual,
> but there are some boards that use this clock output as a reference clock
> for board level components. Add support for those clocks in the clock
> driver, so this clock output can be used properly.
> 
> Note that the VIDEO1, GPU and VPU mux inputs are rotated compared to the
> description in the reference manual. The order in this patch has been
> empirically validated.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Applied all 3, thanks.

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] clk: imx8mq: add PLL monitor output
@ 2021-01-30 13:36   ` Shawn Guo
  0 siblings, 0 replies; 16+ messages in thread
From: Shawn Guo @ 2021-01-30 13:36 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Peng Fan, Abel Vesa, Stephen Boyd, Michael Turquette,
	patchwork-lst, NXP Linux Team, kernel, Fabio Estevam, linux-clk,
	linux-arm-kernel

On Mon, Jan 25, 2021 at 06:41:33PM +0100, Lucas Stach wrote:
> The PLL monitor is mentioned as a debug feature in the reference manual,
> but there are some boards that use this clock output as a reference clock
> for board level components. Add support for those clocks in the clock
> driver, so this clock output can be used properly.
> 
> Note that the VIDEO1, GPU and VPU mux inputs are rotated compared to the
> description in the reference manual. The order in this patch has been
> empirically validated.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Applied all 3, thanks.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread
end of thread, other threads:[~2021-01-30 13:37 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-25 17:41 [PATCH 1/3] clk: imx8mq: add PLL monitor output Lucas Stach
2021-01-25 17:41 ` Lucas Stach
2021-01-25 17:41 ` [PATCH 2/3] clk: imx8mm: add clkout1/2 support Lucas Stach
2021-01-25 17:41   ` Lucas Stach
2021-01-25 18:36   ` Abel Vesa
2021-01-25 18:36     ` Abel Vesa
2021-01-25 17:41 ` [PATCH 3/3] clk: imx8mn: " Lucas Stach
2021-01-25 17:41   ` Lucas Stach
2021-01-25 18:36   ` Abel Vesa
2021-01-25 18:36     ` Abel Vesa
2021-01-25 18:19 ` [PATCH 1/3] clk: imx8mq: add PLL monitor output Abel Vesa
2021-01-25 18:19   ` Abel Vesa
2021-01-25 18:24   ` Abel Vesa
2021-01-25 18:24     ` Abel Vesa
2021-01-30 13:36 ` Shawn Guo
2021-01-30 13:36   ` Shawn Guo

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