* [PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR
@ 2021-01-26 14:56 Suzuki K Poulose
2021-01-27 12:00 ` Suzuki K Poulose
0 siblings, 1 reply; 9+ messages in thread
From: Suzuki K Poulose @ 2021-01-26 14:56 UTC (permalink / raw)
To: mathieu.poirier
Cc: Suzuki K Poulose, coresight, anshuman.khandual, stable, leo.yan,
linux-arm-kernel, mike.leach
TRCSTALLCTLR register is only implemented if
TRCIDR3.STALLCTL == 0b1
Make sure the driver touches the register only it is implemented.
Cc: stable@kernel.vger.org
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++---
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 3 +++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index b40e3c2bf818..814b49dae0c7 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -367,7 +367,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
- etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
@@ -1545,7 +1546,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
- state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
@@ -1657,7 +1659,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
- etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 1c490bcef3ad..cd9249fbf913 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -296,6 +296,9 @@ static ssize_t mode_store(struct device *dev,
if (kstrtoul(buf, 16, &val))
return -EINVAL;
+ if ((val & ETM_MODE_ISTALL_EN) && !drvdata->stallctl)
+ return -EINVAL;
+
spin_lock(&drvdata->spinlock);
config->mode = val & ETMv4_MODE_ALL;
--
2.24.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2] coresight: etm4x: Handle accesses to TRCSTALLCTLR
2021-01-26 14:56 [PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR Suzuki K Poulose
@ 2021-01-27 12:00 ` Suzuki K Poulose
0 siblings, 0 replies; 9+ messages in thread
From: Suzuki K Poulose @ 2021-01-27 12:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: coresight, linux-kernel, Suzuki K Poulose, stable,
Mathieu Poirier, Leo Yan, Mike Leach
TRCSTALLCTLR register is only implemented if
TRCIDR3.STALLCTL == 0b1
Make sure the driver touches the register only it is implemented.
Cc: stable@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Changes since v1:
- No change to the patch, fixed the stable email address and
added usual reviewers.
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++---
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 3 +++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index b40e3c2bf818..814b49dae0c7 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -367,7 +367,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
- etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
@@ -1545,7 +1546,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
- state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
@@ -1657,7 +1659,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
- etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 1c490bcef3ad..cd9249fbf913 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -296,6 +296,9 @@ static ssize_t mode_store(struct device *dev,
if (kstrtoul(buf, 16, &val))
return -EINVAL;
+ if ((val & ETM_MODE_ISTALL_EN) && !drvdata->stallctl)
+ return -EINVAL;
+
spin_lock(&drvdata->spinlock);
config->mode = val & ETMv4_MODE_ALL;
--
2.24.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2] coresight: etm4x: Handle accesses to TRCSTALLCTLR
@ 2021-01-27 12:00 ` Suzuki K Poulose
0 siblings, 0 replies; 9+ messages in thread
From: Suzuki K Poulose @ 2021-01-27 12:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Mathieu Poirier, Suzuki K Poulose, coresight, linux-kernel,
stable, Leo Yan, Mike Leach
TRCSTALLCTLR register is only implemented if
TRCIDR3.STALLCTL == 0b1
Make sure the driver touches the register only it is implemented.
Cc: stable@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Changes since v1:
- No change to the patch, fixed the stable email address and
added usual reviewers.
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++---
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 3 +++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index b40e3c2bf818..814b49dae0c7 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -367,7 +367,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
- etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
@@ -1545,7 +1546,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
- state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
@@ -1657,7 +1659,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
- etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 1c490bcef3ad..cd9249fbf913 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -296,6 +296,9 @@ static ssize_t mode_store(struct device *dev,
if (kstrtoul(buf, 16, &val))
return -EINVAL;
+ if ((val & ETM_MODE_ISTALL_EN) && !drvdata->stallctl)
+ return -EINVAL;
+
spin_lock(&drvdata->spinlock);
config->mode = val & ETMv4_MODE_ALL;
--
2.24.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2] coresight: etm4x: Handle accesses to TRCSTALLCTLR
2021-01-27 12:00 ` Suzuki K Poulose
@ 2021-01-27 17:43 ` Mathieu Poirier
-1 siblings, 0 replies; 9+ messages in thread
From: Mathieu Poirier @ 2021-01-27 17:43 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: linux-arm-kernel, coresight, linux-kernel, stable, Leo Yan, Mike Leach
Good day,
On Wed, Jan 27, 2021 at 12:00:32PM +0000, Suzuki K Poulose wrote:
> TRCSTALLCTLR register is only implemented if
>
> TRCIDR3.STALLCTL == 0b1
>
> Make sure the driver touches the register only it is implemented.
>
> Cc: stable@vger.kernel.org
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Leo Yan <leo.yan@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> Changes since v1:
> - No change to the patch, fixed the stable email address and
> added usual reviewers.
> ---
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++---
> drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 3 +++
> 2 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index b40e3c2bf818..814b49dae0c7 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -367,7 +367,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
> etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
> etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
> - etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
> + if (drvdata->stallctl)
> + etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
> etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
> etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
> etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
> @@ -1545,7 +1546,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
> state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
> state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
> - state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
> + if (drvdata->stallctl)
> + state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
> state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
> state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
> state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
> @@ -1657,7 +1659,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
> etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
> etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
> etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
> - etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
> + if (drvdata->stallctl)
> + etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
> etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
> etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
> etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 1c490bcef3ad..cd9249fbf913 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -296,6 +296,9 @@ static ssize_t mode_store(struct device *dev,
> if (kstrtoul(buf, 16, &val))
> return -EINVAL;
>
> + if ((val & ETM_MODE_ISTALL_EN) && !drvdata->stallctl)
> + return -EINVAL;
> +
We have two choices here:
1) Follow what is already done in this function for implementation define
options like ETM_MODE_BB, ETMv4_MODE_CTXID, ETM_MODE_RETURNSTACK and others. In
that case we would have:
/* bit[8], Instruction stall bit */
if ((config->mode & ETM_MODE_ISTALL_EN) && drvdata->stallctl == true))
config->stall_ctrl |= BIT(8);
else
config->stall_ctrl &= ~BIT(8);
2) Return -EINVAL when something is not supported, like you have above. In that
case we'd have to enact the same behavior for all the options, which has the
potential of breaking user space.
I think option 1 is best.
Thanks,
Mathieu
> spin_lock(&drvdata->spinlock);
> config->mode = val & ETMv4_MODE_ALL;
>
> --
> 2.24.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] coresight: etm4x: Handle accesses to TRCSTALLCTLR
@ 2021-01-27 17:43 ` Mathieu Poirier
0 siblings, 0 replies; 9+ messages in thread
From: Mathieu Poirier @ 2021-01-27 17:43 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: coresight, linux-kernel, stable, Leo Yan, linux-arm-kernel, Mike Leach
Good day,
On Wed, Jan 27, 2021 at 12:00:32PM +0000, Suzuki K Poulose wrote:
> TRCSTALLCTLR register is only implemented if
>
> TRCIDR3.STALLCTL == 0b1
>
> Make sure the driver touches the register only it is implemented.
>
> Cc: stable@vger.kernel.org
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Leo Yan <leo.yan@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> Changes since v1:
> - No change to the patch, fixed the stable email address and
> added usual reviewers.
> ---
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++---
> drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 3 +++
> 2 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index b40e3c2bf818..814b49dae0c7 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -367,7 +367,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
> etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
> etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
> - etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
> + if (drvdata->stallctl)
> + etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
> etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
> etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
> etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
> @@ -1545,7 +1546,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
> state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
> state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
> - state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
> + if (drvdata->stallctl)
> + state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
> state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
> state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
> state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
> @@ -1657,7 +1659,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
> etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
> etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
> etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
> - etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
> + if (drvdata->stallctl)
> + etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
> etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
> etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
> etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 1c490bcef3ad..cd9249fbf913 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -296,6 +296,9 @@ static ssize_t mode_store(struct device *dev,
> if (kstrtoul(buf, 16, &val))
> return -EINVAL;
>
> + if ((val & ETM_MODE_ISTALL_EN) && !drvdata->stallctl)
> + return -EINVAL;
> +
We have two choices here:
1) Follow what is already done in this function for implementation define
options like ETM_MODE_BB, ETMv4_MODE_CTXID, ETM_MODE_RETURNSTACK and others. In
that case we would have:
/* bit[8], Instruction stall bit */
if ((config->mode & ETM_MODE_ISTALL_EN) && drvdata->stallctl == true))
config->stall_ctrl |= BIT(8);
else
config->stall_ctrl &= ~BIT(8);
2) Return -EINVAL when something is not supported, like you have above. In that
case we'd have to enact the same behavior for all the options, which has the
potential of breaking user space.
I think option 1 is best.
Thanks,
Mathieu
> spin_lock(&drvdata->spinlock);
> config->mode = val & ETMv4_MODE_ALL;
>
> --
> 2.24.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] coresight: etm4x: Handle accesses to TRCSTALLCTLR
2021-01-27 17:43 ` Mathieu Poirier
@ 2021-01-27 18:29 ` Suzuki K Poulose
-1 siblings, 0 replies; 9+ messages in thread
From: Suzuki K Poulose @ 2021-01-27 18:29 UTC (permalink / raw)
To: Mathieu Poirier
Cc: linux-arm-kernel, coresight, linux-kernel, stable, Leo Yan, Mike Leach
On 1/27/21 5:43 PM, Mathieu Poirier wrote:
> Good day,
>
> On Wed, Jan 27, 2021 at 12:00:32PM +0000, Suzuki K Poulose wrote:
>> TRCSTALLCTLR register is only implemented if
>>
>> TRCIDR3.STALLCTL == 0b1
>>
>> Make sure the driver touches the register only it is implemented.
>>
>> Cc: stable@vger.kernel.org
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Leo Yan <leo.yan@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>> Changes since v1:
>> - No change to the patch, fixed the stable email address and
>> added usual reviewers.
>> ---
>> drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++---
>> drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 3 +++
>> 2 files changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> index b40e3c2bf818..814b49dae0c7 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> @@ -367,7 +367,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
>> etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
>> etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
>> etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
>> - etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
>> + if (drvdata->stallctl)
>> + etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
>> etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
>> etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
>> etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
>> @@ -1545,7 +1546,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
>> state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
>> state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
>> state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
>> - state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
>> + if (drvdata->stallctl)
>> + state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
>> state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
>> state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
>> state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
>> @@ -1657,7 +1659,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
>> etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
>> etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
>> etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
>> - etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
>> + if (drvdata->stallctl)
>> + etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
>> etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
>> etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
>> etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
>> index 1c490bcef3ad..cd9249fbf913 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
>> @@ -296,6 +296,9 @@ static ssize_t mode_store(struct device *dev,
>> if (kstrtoul(buf, 16, &val))
>> return -EINVAL;
>>
>> + if ((val & ETM_MODE_ISTALL_EN) && !drvdata->stallctl)
>> + return -EINVAL;
>> +
>
> We have two choices here:
>
> 1) Follow what is already done in this function for implementation define
> options like ETM_MODE_BB, ETMv4_MODE_CTXID, ETM_MODE_RETURNSTACK and others. In
> that case we would have:
>
> /* bit[8], Instruction stall bit */
> if ((config->mode & ETM_MODE_ISTALL_EN) && drvdata->stallctl == true))
> config->stall_ctrl |= BIT(8);
> else
> config->stall_ctrl &= ~BIT(8);
>
> 2) Return -EINVAL when something is not supported, like you have above. In that
> case we'd have to enact the same behavior for all the options, which has the > potential of breaking user space.
I did think about this and but now I agree 1 is better for now. I will respin.
Cheers
Suzuki
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] coresight: etm4x: Handle accesses to TRCSTALLCTLR
@ 2021-01-27 18:29 ` Suzuki K Poulose
0 siblings, 0 replies; 9+ messages in thread
From: Suzuki K Poulose @ 2021-01-27 18:29 UTC (permalink / raw)
To: Mathieu Poirier
Cc: coresight, linux-kernel, stable, Leo Yan, linux-arm-kernel, Mike Leach
On 1/27/21 5:43 PM, Mathieu Poirier wrote:
> Good day,
>
> On Wed, Jan 27, 2021 at 12:00:32PM +0000, Suzuki K Poulose wrote:
>> TRCSTALLCTLR register is only implemented if
>>
>> TRCIDR3.STALLCTL == 0b1
>>
>> Make sure the driver touches the register only it is implemented.
>>
>> Cc: stable@vger.kernel.org
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Leo Yan <leo.yan@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>> Changes since v1:
>> - No change to the patch, fixed the stable email address and
>> added usual reviewers.
>> ---
>> drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++---
>> drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 3 +++
>> 2 files changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> index b40e3c2bf818..814b49dae0c7 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> @@ -367,7 +367,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
>> etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
>> etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
>> etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
>> - etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
>> + if (drvdata->stallctl)
>> + etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
>> etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
>> etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
>> etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
>> @@ -1545,7 +1546,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
>> state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
>> state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
>> state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
>> - state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
>> + if (drvdata->stallctl)
>> + state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
>> state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
>> state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
>> state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
>> @@ -1657,7 +1659,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
>> etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
>> etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
>> etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
>> - etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
>> + if (drvdata->stallctl)
>> + etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
>> etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
>> etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
>> etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
>> index 1c490bcef3ad..cd9249fbf913 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
>> @@ -296,6 +296,9 @@ static ssize_t mode_store(struct device *dev,
>> if (kstrtoul(buf, 16, &val))
>> return -EINVAL;
>>
>> + if ((val & ETM_MODE_ISTALL_EN) && !drvdata->stallctl)
>> + return -EINVAL;
>> +
>
> We have two choices here:
>
> 1) Follow what is already done in this function for implementation define
> options like ETM_MODE_BB, ETMv4_MODE_CTXID, ETM_MODE_RETURNSTACK and others. In
> that case we would have:
>
> /* bit[8], Instruction stall bit */
> if ((config->mode & ETM_MODE_ISTALL_EN) && drvdata->stallctl == true))
> config->stall_ctrl |= BIT(8);
> else
> config->stall_ctrl &= ~BIT(8);
>
> 2) Return -EINVAL when something is not supported, like you have above. In that
> case we'd have to enact the same behavior for all the options, which has the > potential of breaking user space.
I did think about this and but now I agree 1 is better for now. I will respin.
Cheers
Suzuki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* FAILED: patch "[PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR" failed to apply to 5.11-stable tree
@ 2021-02-28 13:51 gregkh
2021-03-01 12:15 ` [PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR Suzuki K Poulose
0 siblings, 1 reply; 9+ messages in thread
From: gregkh @ 2021-02-28 13:51 UTC (permalink / raw)
To: suzuki.poulose, gregkh, leo.yan, mathieu.poirier, mike.leach; +Cc: stable
The patch below does not apply to the 5.11-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to <stable@vger.kernel.org>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From f72896063396b0cb205cbf0fd76ec6ab3ca11c8a Mon Sep 17 00:00:00 2001
From: Suzuki K Poulose <suzuki.poulose@arm.com>
Date: Mon, 1 Feb 2021 11:13:51 -0700
Subject: [PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR
TRCSTALLCTLR register is only implemented if
TRCIDR3.STALLCTL == 0b1
Make sure the driver touches the register only it is implemented.
Link: https://lore.kernel.org/r/20210127184617.3684379-1-suzuki.poulose@arm.com
Cc: stable@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-32-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 473ab7480a36..5017d33ba4f5 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -306,7 +306,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
- etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
@@ -1463,7 +1464,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
- state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
@@ -1575,7 +1577,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
- etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index b646d53a3133..0995a10790f4 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -389,7 +389,7 @@ static ssize_t mode_store(struct device *dev,
config->eventctrl1 &= ~BIT(12);
/* bit[8], Instruction stall bit */
- if (config->mode & ETM_MODE_ISTALL_EN)
+ if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true))
config->stall_ctrl |= BIT(8);
else
config->stall_ctrl &= ~BIT(8);
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR
2021-02-28 13:51 FAILED: patch "[PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR" failed to apply to 5.11-stable tree gregkh
@ 2021-03-01 12:15 ` Suzuki K Poulose
2021-03-01 12:22 ` Greg KH
0 siblings, 1 reply; 9+ messages in thread
From: Suzuki K Poulose @ 2021-03-01 12:15 UTC (permalink / raw)
To: stable; +Cc: suzuki.poulose, gregkh, mathieu.poirier, mike.leach, leo.yan
commit f72896063396b0cb205cbf0fd76ec6ab3ca11c8a upstream
TRCSTALLCTLR register is only implemented if
TRCIDR3.STALLCTL == 0b1
Make sure the driver touches the register only it is implemented.
Link: https://lore.kernel.org/r/20210127184617.3684379-1-suzuki.poulose@arm.com
Cc: stable@vger.kernel.org # v5.11-
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++---
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +-
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index b20b6ff17cf6..8ff35b9397da 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -226,7 +226,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
- writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);
@@ -1288,7 +1289,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
state->trcauxctlr = readl(drvdata->base + TRCAUXCTLR);
state->trceventctl0r = readl(drvdata->base + TRCEVENTCTL0R);
state->trceventctl1r = readl(drvdata->base + TRCEVENTCTL1R);
- state->trcstallctlr = readl(drvdata->base + TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ state->trcstallctlr = readl(drvdata->base + TRCSTALLCTLR);
state->trctsctlr = readl(drvdata->base + TRCTSCTLR);
state->trcsyncpr = readl(drvdata->base + TRCSYNCPR);
state->trcccctlr = readl(drvdata->base + TRCCCCTLR);
@@ -1397,7 +1399,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
writel_relaxed(state->trcauxctlr, drvdata->base + TRCAUXCTLR);
writel_relaxed(state->trceventctl0r, drvdata->base + TRCEVENTCTL0R);
writel_relaxed(state->trceventctl1r, drvdata->base + TRCEVENTCTL1R);
- writel_relaxed(state->trcstallctlr, drvdata->base + TRCSTALLCTLR);
+ if (drvdata->stallctl)
+ writel_relaxed(state->trcstallctlr, drvdata->base + TRCSTALLCTLR);
writel_relaxed(state->trctsctlr, drvdata->base + TRCTSCTLR);
writel_relaxed(state->trcsyncpr, drvdata->base + TRCSYNCPR);
writel_relaxed(state->trcccctlr, drvdata->base + TRCCCCTLR);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 989ce7b8ade7..4682f2613996 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -389,7 +389,7 @@ static ssize_t mode_store(struct device *dev,
config->eventctrl1 &= ~BIT(12);
/* bit[8], Instruction stall bit */
- if (config->mode & ETM_MODE_ISTALL_EN)
+ if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true))
config->stall_ctrl |= BIT(8);
else
config->stall_ctrl &= ~BIT(8);
--
2.24.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR
2021-03-01 12:15 ` [PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR Suzuki K Poulose
@ 2021-03-01 12:22 ` Greg KH
0 siblings, 0 replies; 9+ messages in thread
From: Greg KH @ 2021-03-01 12:22 UTC (permalink / raw)
To: Suzuki K Poulose; +Cc: stable, mathieu.poirier, mike.leach, leo.yan
On Mon, Mar 01, 2021 at 12:15:49PM +0000, Suzuki K Poulose wrote:
> commit f72896063396b0cb205cbf0fd76ec6ab3ca11c8a upstream
>
> TRCSTALLCTLR register is only implemented if
>
> TRCIDR3.STALLCTL == 0b1
>
> Make sure the driver touches the register only it is implemented.
>
> Link: https://lore.kernel.org/r/20210127184617.3684379-1-suzuki.poulose@arm.com
> Cc: stable@vger.kernel.org # v5.11-
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Leo Yan <leo.yan@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++---
> drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +-
> 2 files changed, 7 insertions(+), 4 deletions(-)
Now queued up to 5.10.y and 5.11.y, thanks.
greg k-h
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-- links below jump to the message on this page --
2021-01-26 14:56 [PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR Suzuki K Poulose
2021-01-27 12:00 ` [PATCH v2] " Suzuki K Poulose
2021-01-27 12:00 ` Suzuki K Poulose
2021-01-27 17:43 ` Mathieu Poirier
2021-01-27 17:43 ` Mathieu Poirier
2021-01-27 18:29 ` Suzuki K Poulose
2021-01-27 18:29 ` Suzuki K Poulose
2021-02-28 13:51 FAILED: patch "[PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR" failed to apply to 5.11-stable tree gregkh
2021-03-01 12:15 ` [PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR Suzuki K Poulose
2021-03-01 12:22 ` Greg KH
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