* [PATCH v3 1/4] hw/mips: Add a bootloader helper
2021-01-27 6:54 [PATCH v3 0/4] MIPS Bootloader helper Jiaxun Yang
@ 2021-01-27 6:54 ` Jiaxun Yang
2021-02-21 11:44 ` Philippe Mathieu-Daudé
2021-02-21 13:16 ` Philippe Mathieu-Daudé
2021-01-27 6:54 ` [PATCH v3 2/4] hw/mips: Use bl_gen_kernel_jump to generate bootloaders Jiaxun Yang
` (4 subsequent siblings)
5 siblings, 2 replies; 11+ messages in thread
From: Jiaxun Yang @ 2021-01-27 6:54 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Huacai Chen,
Philippe Mathieu-Daudé,
Aurelien Jarno
Add a bootloader helper to generate simple bootloaders for kernel.
It can help us reduce inline hex hack and also keep MIPS release 6
compatibility easier.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
include/hw/mips/bootloader.h | 49 +++++++++++
hw/mips/bootloader.c | 164 +++++++++++++++++++++++++++++++++++
hw/mips/meson.build | 2 +-
3 files changed, 214 insertions(+), 1 deletion(-)
create mode 100644 include/hw/mips/bootloader.h
create mode 100644 hw/mips/bootloader.c
diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
new file mode 100644
index 0000000000..2a0e1a11c9
--- /dev/null
+++ b/include/hw/mips/bootloader.h
@@ -0,0 +1,49 @@
+#ifndef HW_MIPS_BOOTLOADER_H
+#define HW_MIPS_BOOTLOADER_H
+
+#include "exec/cpu-defs.h"
+
+void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr);
+void bl_gen_jump_kernel(uint32_t **p, target_ulong sp, target_ulong a0,
+ target_ulong a1, target_ulong a2, target_ulong a3,
+ target_ulong kernel_addr);
+void bl_gen_write_ulong(uint32_t **p, target_ulong val, target_ulong addr);
+void bl_gen_write_u32(uint32_t **p, uint32_t val, target_ulong addr);
+void bl_gen_write_u64(uint32_t **p, uint64_t val, target_ulong addr);
+
+typedef enum bl_reg {
+ BL_REG_ZERO = 0,
+ BL_REG_AT = 1,
+ BL_REG_V0 = 2,
+ BL_REG_V1 = 3,
+ BL_REG_A0 = 4,
+ BL_REG_A1 = 5,
+ BL_REG_A2 = 6,
+ BL_REG_A3 = 7,
+ BL_REG_T0 = 8,
+ BL_REG_T1 = 9,
+ BL_REG_T2 = 10,
+ BL_REG_T3 = 11,
+ BL_REG_T4 = 12,
+ BL_REG_T5 = 13,
+ BL_REG_T6 = 14,
+ BL_REG_T7 = 15,
+ BL_REG_S0 = 16,
+ BL_REG_S1 = 17,
+ BL_REG_S2 = 18,
+ BL_REG_S3 = 19,
+ BL_REG_S4 = 20,
+ BL_REG_S5 = 21,
+ BL_REG_S6 = 22,
+ BL_REG_S7 = 23,
+ BL_REG_T8 = 24,
+ BL_REG_T9 = 25,
+ BL_REG_K0 = 26,
+ BL_REG_K1 = 27,
+ BL_REG_GP = 28,
+ BL_REG_SP = 29,
+ BL_REG_FP = 30,
+ BL_REG_RA = 31,
+} bl_reg;
+
+#endif
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
new file mode 100644
index 0000000000..8989db870e
--- /dev/null
+++ b/hw/mips/bootloader.c
@@ -0,0 +1,164 @@
+/*
+ * Utility for QEMU MIPS to generate it's simple bootloader
+ *
+ * Instructions used here are carefully selected to keep compatibility with
+ * MIPS Release 6.
+ *
+ * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "cpu.h"
+#include "hw/mips/bootloader.h"
+
+/* Base types */
+static void bl_gen_nop(uint32_t **p)
+{
+ stl_p(*p, 0);
+ *p = *p + 1;
+}
+
+static void bl_gen_r_type(uint32_t **p, uint8_t opcode, bl_reg rs, bl_reg rt,
+ bl_reg rd, uint8_t shift, uint8_t funct)
+{
+ uint32_t insn = 0;
+
+ insn = deposit32(insn, 26, 6, opcode);
+ insn = deposit32(insn, 21, 5, rs);
+ insn = deposit32(insn, 16, 5, rt);
+ insn = deposit32(insn, 11, 5, rd);
+ insn = deposit32(insn, 6, 5, shift);
+ insn = deposit32(insn, 0, 6, funct);
+
+ stl_p(*p, insn);
+ *p = *p + 1;
+}
+
+static void bl_gen_i_type(uint32_t **p, uint8_t opcode, bl_reg rs, bl_reg rt,
+ uint16_t imm)
+{
+ uint32_t insn = 0;
+
+ insn = deposit32(insn, 26, 6, opcode);
+ insn = deposit32(insn, 21, 5, rs);
+ insn = deposit32(insn, 16, 5, rt);
+ insn = deposit32(insn, 0, 16, imm);
+
+ stl_p(*p, insn);
+ *p = *p + 1;
+}
+
+static bool bootcpu_supports_isa(uint64_t isa_mask)
+{
+ return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask);
+}
+
+/* Single instructions */
+static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa)
+{
+ if (bootcpu_supports_isa(ISA_MIPS3)) {
+ bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
+ } else {
+ g_assert_not_reached(); /* unsupported */
+ }
+}
+
+static void bl_gen_jalr(uint32_t **p, bl_reg rs)
+{
+ bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x9);
+}
+
+static void bl_gen_lui(uint32_t **p, bl_reg rt, uint16_t imm)
+{
+ /* R6: It's a alias of AUI with RS = 0 */
+ bl_gen_i_type(p, 0xf, 0, rt, imm);
+}
+
+static void bl_gen_ori(uint32_t **p, bl_reg rt, bl_reg rs, uint16_t imm)
+{
+ bl_gen_i_type(p, 0xd, rs, rt, imm);
+}
+
+static void bl_gen_sw(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
+{
+ bl_gen_i_type(p, 0x2b, base, rt, offset);
+}
+
+static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
+{
+ if (bootcpu_supports_isa(ISA_MIPS3)) {
+ bl_gen_i_type(p, 0x3f, base, rt, offset);
+ } else {
+ g_assert_not_reached(); /* unsupported */
+ }
+}
+
+/* Pseudo instructions */
+static void bl_gen_li(uint32_t **p, bl_reg rt, uint32_t imm)
+{
+ bl_gen_lui(p, rt, extract32(imm, 16, 16));
+ bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
+}
+
+static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm)
+{
+ bl_gen_li(p, rt, extract64(imm, 32, 32));
+ bl_gen_dsll(p, rt, rt, 16);
+ bl_gen_ori(p, rt, rt, extract64(imm, 16, 16));
+ bl_gen_dsll(p, rt, rt, 16);
+ bl_gen_ori(p, rt, rt, extract64(imm, 0, 16));
+}
+
+static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm)
+{
+ if (bootcpu_supports_isa(ISA_MIPS3)) {
+ bl_gen_dli(p, rt, imm); /* 64bit */
+ } else {
+ bl_gen_li(p, rt, imm); /* 32bit */
+ }
+}
+
+/* Helpers */
+void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr)
+{
+ bl_gen_load_ulong(p, BL_REG_T9, jump_addr);
+ bl_gen_jalr(p, BL_REG_T9);
+ bl_gen_nop(p); /* delay slot */
+}
+
+void bl_gen_jump_kernel(uint32_t **p, target_ulong sp, target_ulong a0,
+ target_ulong a1, target_ulong a2, target_ulong a3,
+ target_ulong kernel_addr)
+{
+ bl_gen_load_ulong(p, BL_REG_SP, sp);
+ bl_gen_load_ulong(p, BL_REG_A0, a0);
+ bl_gen_load_ulong(p, BL_REG_A1, a1);
+ bl_gen_load_ulong(p, BL_REG_A2, a2);
+ bl_gen_load_ulong(p, BL_REG_A3, a3);
+
+ bl_gen_jump_to(p, kernel_addr);
+}
+
+void bl_gen_write_ulong(uint32_t **p, target_ulong val, target_ulong addr)
+{
+ bl_gen_load_ulong(p, BL_REG_K0, val);
+ bl_gen_load_ulong(p, BL_REG_K1, addr);
+ bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0);
+}
+
+void bl_gen_write_u32(uint32_t **p, uint32_t val, target_ulong addr)
+{
+ bl_gen_li(p, BL_REG_K0, val);
+ bl_gen_load_ulong(p, BL_REG_K1, addr);
+ bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
+}
+
+void bl_gen_write_u64(uint32_t **p, uint64_t val, target_ulong addr)
+{
+ bl_gen_dli(p, BL_REG_K0, val);
+ bl_gen_load_ulong(p, BL_REG_K1, addr);
+ bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0);
+}
diff --git a/hw/mips/meson.build b/hw/mips/meson.build
index ee19cc204d..1195716dc7 100644
--- a/hw/mips/meson.build
+++ b/hw/mips/meson.build
@@ -1,5 +1,5 @@
mips_ss = ss.source_set()
-mips_ss.add(files('mips_int.c'))
+mips_ss.add(files('bootloader.c', 'mips_int.c'))
mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c'))
mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c'))
--
2.30.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 1/4] hw/mips: Add a bootloader helper
2021-01-27 6:54 ` [PATCH v3 1/4] hw/mips: Add a bootloader helper Jiaxun Yang
@ 2021-02-21 11:44 ` Philippe Mathieu-Daudé
2021-02-21 13:16 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 11+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-21 11:44 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno, Paul Burton
On 1/27/21 7:54 AM, Jiaxun Yang wrote:
> Add a bootloader helper to generate simple bootloaders for kernel.
> It can help us reduce inline hex hack and also keep MIPS release 6
> compatibility easier.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> include/hw/mips/bootloader.h | 49 +++++++++++
> hw/mips/bootloader.c | 164 +++++++++++++++++++++++++++++++++++
> hw/mips/meson.build | 2 +-
> 3 files changed, 214 insertions(+), 1 deletion(-)
> create mode 100644 include/hw/mips/bootloader.h
> create mode 100644 hw/mips/bootloader.c
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 1/4] hw/mips: Add a bootloader helper
2021-01-27 6:54 ` [PATCH v3 1/4] hw/mips: Add a bootloader helper Jiaxun Yang
2021-02-21 11:44 ` Philippe Mathieu-Daudé
@ 2021-02-21 13:16 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 11+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-21 13:16 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno, Paul Burton
On 1/27/21 7:54 AM, Jiaxun Yang wrote:
> Add a bootloader helper to generate simple bootloaders for kernel.
> It can help us reduce inline hex hack and also keep MIPS release 6
> compatibility easier.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> include/hw/mips/bootloader.h | 49 +++++++++++
> hw/mips/bootloader.c | 164 +++++++++++++++++++++++++++++++++++
> hw/mips/meson.build | 2 +-
> 3 files changed, 214 insertions(+), 1 deletion(-)
> create mode 100644 include/hw/mips/bootloader.h
> create mode 100644 hw/mips/bootloader.c
>
> diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
> new file mode 100644
> index 0000000000..2a0e1a11c9
> --- /dev/null
> +++ b/include/hw/mips/bootloader.h
> @@ -0,0 +1,49 @@
> +#ifndef HW_MIPS_BOOTLOADER_H
> +#define HW_MIPS_BOOTLOADER_H
> +
> +#include "exec/cpu-defs.h"
> +
> +void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr);
> +void bl_gen_jump_kernel(uint32_t **p, target_ulong sp, target_ulong a0,
> + target_ulong a1, target_ulong a2, target_ulong a3,
> + target_ulong kernel_addr);
> +void bl_gen_write_ulong(uint32_t **p, target_ulong val, target_ulong addr);
> +void bl_gen_write_u32(uint32_t **p, uint32_t val, target_ulong addr);
> +void bl_gen_write_u64(uint32_t **p, uint64_t val, target_ulong addr);
Again, if you don't mind, I inverted bl_gen_write() arguments:
void bl_gen_write_TYPE(uint32_t **p, target_ulong addr, TYPE val);
> +typedef enum bl_reg {
> + BL_REG_ZERO = 0,
> + BL_REG_AT = 1,
> + BL_REG_V0 = 2,
> + BL_REG_V1 = 3,
> + BL_REG_A0 = 4,
And moved the enum declaration to the source file.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 2/4] hw/mips: Use bl_gen_kernel_jump to generate bootloaders
2021-01-27 6:54 [PATCH v3 0/4] MIPS Bootloader helper Jiaxun Yang
2021-01-27 6:54 ` [PATCH v3 1/4] hw/mips: Add a bootloader helper Jiaxun Yang
@ 2021-01-27 6:54 ` Jiaxun Yang
2021-02-21 12:11 ` Philippe Mathieu-Daudé
2021-01-27 6:54 ` [PATCH v3 3/4] hw/mips/malta: Use bootloader helper to set BAR resgiters Jiaxun Yang
` (3 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Jiaxun Yang @ 2021-01-27 6:54 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Huacai Chen,
Philippe Mathieu-Daudé,
Aurelien Jarno
Replace embedded binary with generated code.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
hw/mips/boston.c | 17 ++---------------
hw/mips/fuloong2e.c | 28 ++++------------------------
hw/mips/malta.c | 41 ++++++++++-------------------------------
3 files changed, 16 insertions(+), 70 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 467fbc1c8b..b976c8199a 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -27,6 +27,7 @@
#include "hw/ide/ahci.h"
#include "hw/loader.h"
#include "hw/loader-fit.h"
+#include "hw/mips/bootloader.h"
#include "hw/mips/cps.h"
#include "hw/pci-host/xilinx-pcie.h"
#include "hw/qdev-clock.h"
@@ -324,21 +325,7 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr,
* a2/$6 = 0
* a3/$7 = 0
*/
- stl_p(p++, 0x2404fffe); /* li $4, -2 */
- /* lui $5, hi(fdt_addr) */
- stl_p(p++, 0x3c050000 | ((fdt_addr >> 16) & 0xffff));
- if (fdt_addr & 0xffff) { /* ori $5, lo(fdt_addr) */
- stl_p(p++, 0x34a50000 | (fdt_addr & 0xffff));
- }
- stl_p(p++, 0x34060000); /* li $6, 0 */
- stl_p(p++, 0x34070000); /* li $7, 0 */
-
- /* Load kernel entry address & jump to it */
- /* lui $25, hi(kernel_entry) */
- stl_p(p++, 0x3c190000 | ((kernel_entry >> 16) & 0xffff));
- /* ori $25, lo(kernel_entry) */
- stl_p(p++, 0x37390000 | (kernel_entry & 0xffff));
- stl_p(p++, 0x03200009); /* jr $25 */
+ bl_gen_jump_kernel(&p, 0, (int32_t)-2, fdt_addr, 0, 0, kernel_entry);
}
static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index bac2adbd5a..1ae84ecf92 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -33,6 +33,7 @@
#include "hw/i2c/smbus_eeprom.h"
#include "hw/block/flash.h"
#include "hw/mips/mips.h"
+#include "hw/mips/bootloader.h"
#include "hw/mips/cpudevs.h"
#include "hw/pci/pci.h"
#include "qemu/log.h"
@@ -185,30 +186,9 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base,
/* Second part of the bootloader */
p = (uint32_t *)(base + 0x040);
- /* lui a0, 0 */
- stl_p(p++, 0x3c040000);
- /* ori a0, a0, 2 */
- stl_p(p++, 0x34840002);
- /* lui a1, high(ENVP_VADDR) */
- stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff));
- /* ori a1, a0, low(ENVP_VADDR) */
- stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff));
- /* lui a2, high(ENVP_VADDR + 8) */
- stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff));
- /* ori a2, a2, low(ENVP_VADDR + 8) */
- stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff));
- /* lui a3, high(env->ram_size) */
- stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16));
- /* ori a3, a3, low(env->ram_size) */
- stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff));
- /* lui ra, high(kernel_addr) */
- stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff));
- /* ori ra, ra, low(kernel_addr) */
- stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff));
- /* jr ra */
- stl_p(p++, 0x03e00008);
- /* nop */
- stl_p(p++, 0x00000000);
+ bl_gen_jump_kernel(&p, ENVP_VADDR - 64, 2, ENVP_VADDR,
+ ENVP_VADDR + 8, loaderparams.ram_size,
+ kernel_addr);
}
static void main_cpu_reset(void *opaque)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 9afc0b427b..ffd67b8293 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -37,6 +37,7 @@
#include "hw/i2c/smbus_eeprom.h"
#include "hw/block/flash.h"
#include "hw/mips/mips.h"
+#include "hw/mips/bootloader.h"
#include "hw/mips/cpudevs.h"
#include "hw/pci/pci.h"
#include "sysemu/sysemu.h"
@@ -844,6 +845,7 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
static void write_bootloader(uint8_t *base, uint64_t run_addr,
uint64_t kernel_entry)
{
+ target_ulong a0;
uint32_t *p;
/* Small bootloader */
@@ -872,30 +874,6 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
/* Second part of the bootloader */
p = (uint32_t *) (base + 0x580);
- if (semihosting_get_argc()) {
- /* Preserve a0 content as arguments have been passed */
- stl_p(p++, 0x00000000); /* nop */
- } else {
- stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */
- }
-
- /* lui sp, high(ENVP_VADDR) */
- stl_p(p++, 0x3c1d0000 | (((ENVP_VADDR - 64) >> 16) & 0xffff));
- /* ori sp, sp, low(ENVP_VADDR) */
- stl_p(p++, 0x37bd0000 | ((ENVP_VADDR - 64) & 0xffff));
- /* lui a1, high(ENVP_VADDR) */
- stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff));
- /* ori a1, a1, low(ENVP_VADDR) */
- stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff));
- /* lui a2, high(ENVP_VADDR + 8) */
- stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff));
- /* ori a2, a2, low(ENVP_VADDR + 8) */
- stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff));
- /* lui a3, high(ram_low_size) */
- stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
- /* ori a3, a3, low(ram_low_size) */
- stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
-
/* Load BAR registers as done by YAMON */
stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
@@ -947,13 +925,14 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
#endif
stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */
- /* Jump to kernel code */
- stl_p(p++, 0x3c1f0000 |
- ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
- stl_p(p++, 0x37ff0000 |
- (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
- stl_p(p++, 0x03e00009); /* jalr ra */
- stl_p(p++, 0x00000000); /* nop */
+ if (semihosting_get_argc()) {
+ a0 = 0;
+ } else {
+ a0 = 2;
+ }
+ bl_gen_jump_kernel(&p, ENVP_VADDR - 64, a0, ENVP_VADDR,
+ ENVP_VADDR + 8, loaderparams.ram_low_size,
+ kernel_entry);
/* YAMON subroutines */
p = (uint32_t *) (base + 0x800);
--
2.30.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 2/4] hw/mips: Use bl_gen_kernel_jump to generate bootloaders
2021-01-27 6:54 ` [PATCH v3 2/4] hw/mips: Use bl_gen_kernel_jump to generate bootloaders Jiaxun Yang
@ 2021-02-21 12:11 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 11+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-21 12:11 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno, Paul Burton
On 1/27/21 7:54 AM, Jiaxun Yang wrote:
> Replace embedded binary with generated code.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> hw/mips/boston.c | 17 ++---------------
> hw/mips/fuloong2e.c | 28 ++++------------------------
> hw/mips/malta.c | 41 ++++++++++-------------------------------
> 3 files changed, 16 insertions(+), 70 deletions(-)
>
> diff --git a/hw/mips/boston.c b/hw/mips/boston.c
> index 467fbc1c8b..b976c8199a 100644
> --- a/hw/mips/boston.c
> +++ b/hw/mips/boston.c
> @@ -27,6 +27,7 @@
> #include "hw/ide/ahci.h"
> #include "hw/loader.h"
> #include "hw/loader-fit.h"
> +#include "hw/mips/bootloader.h"
> #include "hw/mips/cps.h"
> #include "hw/pci-host/xilinx-pcie.h"
> #include "hw/qdev-clock.h"
> @@ -324,21 +325,7 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr,
> * a2/$6 = 0
> * a3/$7 = 0
> */
> - stl_p(p++, 0x2404fffe); /* li $4, -2 */
> - /* lui $5, hi(fdt_addr) */
> - stl_p(p++, 0x3c050000 | ((fdt_addr >> 16) & 0xffff));
> - if (fdt_addr & 0xffff) { /* ori $5, lo(fdt_addr) */
> - stl_p(p++, 0x34a50000 | (fdt_addr & 0xffff));
> - }
> - stl_p(p++, 0x34060000); /* li $6, 0 */
> - stl_p(p++, 0x34070000); /* li $7, 0 */
> -
> - /* Load kernel entry address & jump to it */
> - /* lui $25, hi(kernel_entry) */
> - stl_p(p++, 0x3c190000 | ((kernel_entry >> 16) & 0xffff));
> - /* ori $25, lo(kernel_entry) */
> - stl_p(p++, 0x37390000 | (kernel_entry & 0xffff));
> - stl_p(p++, 0x03200009); /* jr $25 */
> + bl_gen_jump_kernel(&p, 0, (int32_t)-2, fdt_addr, 0, 0, kernel_entry);
OK.
> }
>
> static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
> diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
> index bac2adbd5a..1ae84ecf92 100644
> --- a/hw/mips/fuloong2e.c
> +++ b/hw/mips/fuloong2e.c
> @@ -33,6 +33,7 @@
> #include "hw/i2c/smbus_eeprom.h"
> #include "hw/block/flash.h"
> #include "hw/mips/mips.h"
> +#include "hw/mips/bootloader.h"
> #include "hw/mips/cpudevs.h"
> #include "hw/pci/pci.h"
> #include "qemu/log.h"
> @@ -185,30 +186,9 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base,
> /* Second part of the bootloader */
> p = (uint32_t *)(base + 0x040);
>
> - /* lui a0, 0 */
> - stl_p(p++, 0x3c040000);
> - /* ori a0, a0, 2 */
> - stl_p(p++, 0x34840002);
> - /* lui a1, high(ENVP_VADDR) */
> - stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff));
> - /* ori a1, a0, low(ENVP_VADDR) */
> - stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff));
> - /* lui a2, high(ENVP_VADDR + 8) */
> - stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff));
> - /* ori a2, a2, low(ENVP_VADDR + 8) */
> - stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff));
> - /* lui a3, high(env->ram_size) */
> - stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16));
> - /* ori a3, a3, low(env->ram_size) */
> - stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff));
> - /* lui ra, high(kernel_addr) */
> - stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff));
> - /* ori ra, ra, low(kernel_addr) */
> - stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff));
> - /* jr ra */
> - stl_p(p++, 0x03e00008);
> - /* nop */
> - stl_p(p++, 0x00000000);
> + bl_gen_jump_kernel(&p, ENVP_VADDR - 64, 2, ENVP_VADDR,
Where do you get $sp from?
> + ENVP_VADDR + 8, loaderparams.ram_size,
> + kernel_addr);
> }
>
> static void main_cpu_reset(void *opaque)
> diff --git a/hw/mips/malta.c b/hw/mips/malta.c
> index 9afc0b427b..ffd67b8293 100644
> --- a/hw/mips/malta.c
> +++ b/hw/mips/malta.c
> @@ -37,6 +37,7 @@
> #include "hw/i2c/smbus_eeprom.h"
> #include "hw/block/flash.h"
> #include "hw/mips/mips.h"
> +#include "hw/mips/bootloader.h"
> #include "hw/mips/cpudevs.h"
> #include "hw/pci/pci.h"
> #include "sysemu/sysemu.h"
> @@ -844,6 +845,7 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
> static void write_bootloader(uint8_t *base, uint64_t run_addr,
> uint64_t kernel_entry)
> {
> + target_ulong a0;
> uint32_t *p;
>
> /* Small bootloader */
> @@ -872,30 +874,6 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
> /* Second part of the bootloader */
> p = (uint32_t *) (base + 0x580);
>
> - if (semihosting_get_argc()) {
> - /* Preserve a0 content as arguments have been passed */
I'll keep that comment.
> - stl_p(p++, 0x00000000); /* nop */
> - } else {
> - stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */
> - }
> -
> - /* lui sp, high(ENVP_VADDR) */
> - stl_p(p++, 0x3c1d0000 | (((ENVP_VADDR - 64) >> 16) & 0xffff));
> - /* ori sp, sp, low(ENVP_VADDR) */
> - stl_p(p++, 0x37bd0000 | ((ENVP_VADDR - 64) & 0xffff));
> - /* lui a1, high(ENVP_VADDR) */
> - stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff));
> - /* ori a1, a1, low(ENVP_VADDR) */
> - stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff));
> - /* lui a2, high(ENVP_VADDR + 8) */
> - stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff));
> - /* ori a2, a2, low(ENVP_VADDR + 8) */
> - stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff));
> - /* lui a3, high(ram_low_size) */
> - stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
> - /* ori a3, a3, low(ram_low_size) */
> - stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
> -
> /* Load BAR registers as done by YAMON */
> stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
>
> @@ -947,13 +925,14 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
> #endif
> stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */
>
> - /* Jump to kernel code */
> - stl_p(p++, 0x3c1f0000 |
> - ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
> - stl_p(p++, 0x37ff0000 |
> - (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
> - stl_p(p++, 0x03e00009); /* jalr ra */
> - stl_p(p++, 0x00000000); /* nop */
> + if (semihosting_get_argc()) {
> + a0 = 0;
> + } else {
> + a0 = 2;
> + }
> + bl_gen_jump_kernel(&p, ENVP_VADDR - 64, a0, ENVP_VADDR,
> + ENVP_VADDR + 8, loaderparams.ram_low_size,
> + kernel_entry);
OK.
>
> /* YAMON subroutines */
> p = (uint32_t *) (base + 0x800);
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 3/4] hw/mips/malta: Use bootloader helper to set BAR resgiters
2021-01-27 6:54 [PATCH v3 0/4] MIPS Bootloader helper Jiaxun Yang
2021-01-27 6:54 ` [PATCH v3 1/4] hw/mips: Add a bootloader helper Jiaxun Yang
2021-01-27 6:54 ` [PATCH v3 2/4] hw/mips: Use bl_gen_kernel_jump to generate bootloaders Jiaxun Yang
@ 2021-01-27 6:54 ` Jiaxun Yang
2021-01-27 6:54 ` [PATCH v3 4/4] hw/mips/boston: Use bootloader helper to set GCRs Jiaxun Yang
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Jiaxun Yang @ 2021-01-27 6:54 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Huacai Chen,
Philippe Mathieu-Daudé,
Aurelien Jarno
Translate embedded assembly into IO writes which is more
readable.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
hw/mips/malta.c | 68 ++++++++++++++++---------------------------------
1 file changed, 22 insertions(+), 46 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index ffd67b8293..9466fd1058 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -875,55 +875,31 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
p = (uint32_t *) (base + 0x580);
/* Load BAR registers as done by YAMON */
- stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
-
-#ifdef TARGET_WORDS_BIGENDIAN
- stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */
-#else
- stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */
-#endif
- stl_p(p++, 0xad280068); /* sw t0, 0x0068(t1) */
-
- stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
-
-#ifdef TARGET_WORDS_BIGENDIAN
- stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */
-#else
- stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
-#endif
- stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
- stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */
-#else
- stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */
-#endif
- stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */
-
-#ifdef TARGET_WORDS_BIGENDIAN
- stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */
-#else
- stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */
-#endif
- stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
- stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */
-#else
- stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */
-#endif
- stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */
-
-#ifdef TARGET_WORDS_BIGENDIAN
- stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */
-#else
- stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
-#endif
- stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */
+ /* Bus endianess is always reversed */
#ifdef TARGET_WORDS_BIGENDIAN
- stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */
+#define cpu_to_gt32 cpu_to_le32
#else
- stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */
+#define cpu_to_gt32 cpu_to_be32
#endif
- stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */
+ /* move GT64120 registers from 0x14000000 to 0x1be00000 */
+ bl_gen_write_u32(&p, cpu_to_gt32(0xdf000000),
+ cpu_mips_phys_to_kseg1(NULL, 0x14000068));
+ /* setup MEM-to-PCI0 mapping */
+ /* setup PCI0 io window to 0x18000000-0x181fffff */
+ bl_gen_write_u32(&p, cpu_to_gt32(0xc0000000),
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00048));
+ bl_gen_write_u32(&p, cpu_to_gt32(0x40000000),
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00050));
+ /* setup PCI0 mem windows */
+ bl_gen_write_u32(&p, cpu_to_gt32(0x80000000),
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00058));
+ bl_gen_write_u32(&p, cpu_to_gt32(0x3f000000),
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00060));
+ bl_gen_write_u32(&p, cpu_to_gt32(0xc1000000),
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00080));
+ bl_gen_write_u32(&p, cpu_to_gt32(0x5e000000),
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00088));
+#undef cpu_to_gt32
if (semihosting_get_argc()) {
a0 = 0;
--
2.30.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 4/4] hw/mips/boston: Use bootloader helper to set GCRs
2021-01-27 6:54 [PATCH v3 0/4] MIPS Bootloader helper Jiaxun Yang
` (2 preceding siblings ...)
2021-01-27 6:54 ` [PATCH v3 3/4] hw/mips/malta: Use bootloader helper to set BAR resgiters Jiaxun Yang
@ 2021-01-27 6:54 ` Jiaxun Yang
2021-02-21 12:48 ` Philippe Mathieu-Daudé
2021-02-02 3:49 ` [PATCH v3 0/4] MIPS Bootloader helper Jiaxun Yang
2021-02-21 13:17 ` Philippe Mathieu-Daudé
5 siblings, 1 reply; 11+ messages in thread
From: Jiaxun Yang @ 2021-01-27 6:54 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Huacai Chen,
Philippe Mathieu-Daudé,
Aurelien Jarno
Translate embedded assembly into IO writes which is more
readable.
Also hardcode cm_base at boot time instead of reading from CP0.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
--
v3: Use bl_gen_write_ulong.
---
hw/mips/boston.c | 47 ++++++++---------------------------------------
1 file changed, 8 insertions(+), 39 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index b976c8199a..06e04ef8de 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -274,48 +274,18 @@ static void boston_register_types(void)
}
type_init(boston_register_types)
-static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr,
- bool is_64b)
+static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
{
const uint32_t cm_base = 0x16100000;
const uint32_t gic_base = 0x16120000;
const uint32_t cpc_base = 0x16200000;
- /* Move CM GCRs */
- if (is_64b) {
- stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */
- stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */
- } else {
- stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */
- stl_p(p++, 0x00084100); /* sll $8, $8, 4 */
- }
- stl_p(p++, 0x3c09a000); /* lui $9, 0xa000 */
- stl_p(p++, 0x01094025); /* or $8, $9 */
- stl_p(p++, 0x3c0a0000 | (cm_base >> 16)); /* lui $10, cm_base >> 16 */
- if (is_64b) {
- stl_p(p++, 0xfd0a0008); /* sd $10, 0x8($8) */
- } else {
- stl_p(p++, 0xad0a0008); /* sw $10, 0x8($8) */
- }
- stl_p(p++, 0x012a4025); /* or $8, $10 */
-
- /* Move & enable GIC GCRs */
- stl_p(p++, 0x3c090000 | (gic_base >> 16)); /* lui $9, gic_base >> 16 */
- stl_p(p++, 0x35290001); /* ori $9, 0x1 */
- if (is_64b) {
- stl_p(p++, 0xfd090080); /* sd $9, 0x80($8) */
- } else {
- stl_p(p++, 0xad090080); /* sw $9, 0x80($8) */
- }
-
- /* Move & enable CPC GCRs */
- stl_p(p++, 0x3c090000 | (cpc_base >> 16)); /* lui $9, cpc_base >> 16 */
- stl_p(p++, 0x35290001); /* ori $9, 0x1 */
- if (is_64b) {
- stl_p(p++, 0xfd090088); /* sd $9, 0x88($8) */
- } else {
- stl_p(p++, 0xad090088); /* sw $9, 0x88($8) */
- }
+ bl_gen_write_ulong(&p, cm_base,
+ cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS));
+ bl_gen_write_ulong(&p, gic_base | GCR_GIC_BASE_GICEN_MSK,
+ cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS));
+ bl_gen_write_ulong(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK,
+ cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS));
/*
* Setup argument registers to follow the UHI boot protocol:
@@ -529,8 +499,7 @@ static void boston_mach_init(MachineState *machine)
}
gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000,
- s->kernel_entry, s->fdt_base,
- cpu_type_is_64bit(machine->cpu_type));
+ s->kernel_entry, s->fdt_base);
} else if (!qtest_enabled()) {
error_report("Please provide either a -kernel or -bios argument");
exit(1);
--
2.30.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 4/4] hw/mips/boston: Use bootloader helper to set GCRs
2021-01-27 6:54 ` [PATCH v3 4/4] hw/mips/boston: Use bootloader helper to set GCRs Jiaxun Yang
@ 2021-02-21 12:48 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 11+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-21 12:48 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno, Paul Burton
On 1/27/21 7:54 AM, Jiaxun Yang wrote:
> Translate embedded assembly into IO writes which is more
> readable.
>
> Also hardcode cm_base at boot time instead of reading from CP0.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> --
> v3: Use bl_gen_write_ulong.
> ---
> hw/mips/boston.c | 47 ++++++++---------------------------------------
> 1 file changed, 8 insertions(+), 39 deletions(-)
>
> diff --git a/hw/mips/boston.c b/hw/mips/boston.c
> index b976c8199a..06e04ef8de 100644
> --- a/hw/mips/boston.c
> +++ b/hw/mips/boston.c
> @@ -274,48 +274,18 @@ static void boston_register_types(void)
> }
> type_init(boston_register_types)
>
> -static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr,
> - bool is_64b)
> +static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
> {
> const uint32_t cm_base = 0x16100000;
> const uint32_t gic_base = 0x16120000;
> const uint32_t cpc_base = 0x16200000;
>
> - /* Move CM GCRs */
> - if (is_64b) {
> - stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */
> - stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */
> - } else {
> - stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */
> - stl_p(p++, 0x00084100); /* sll $8, $8, 4 */
> - }
> - stl_p(p++, 0x3c09a000); /* lui $9, 0xa000 */
> - stl_p(p++, 0x01094025); /* or $8, $9 */
> - stl_p(p++, 0x3c0a0000 | (cm_base >> 16)); /* lui $10, cm_base >> 16 */
> - if (is_64b) {
> - stl_p(p++, 0xfd0a0008); /* sd $10, 0x8($8) */
> - } else {
> - stl_p(p++, 0xad0a0008); /* sw $10, 0x8($8) */
> - }
> - stl_p(p++, 0x012a4025); /* or $8, $10 */
> -
> - /* Move & enable GIC GCRs */
> - stl_p(p++, 0x3c090000 | (gic_base >> 16)); /* lui $9, gic_base >> 16 */
> - stl_p(p++, 0x35290001); /* ori $9, 0x1 */
> - if (is_64b) {
> - stl_p(p++, 0xfd090080); /* sd $9, 0x80($8) */
> - } else {
> - stl_p(p++, 0xad090080); /* sw $9, 0x80($8) */
> - }
> -
> - /* Move & enable CPC GCRs */
If you don't mind I'll keep the comments.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 0/4] MIPS Bootloader helper
2021-01-27 6:54 [PATCH v3 0/4] MIPS Bootloader helper Jiaxun Yang
` (3 preceding siblings ...)
2021-01-27 6:54 ` [PATCH v3 4/4] hw/mips/boston: Use bootloader helper to set GCRs Jiaxun Yang
@ 2021-02-02 3:49 ` Jiaxun Yang
2021-02-21 13:17 ` Philippe Mathieu-Daudé
5 siblings, 0 replies; 11+ messages in thread
From: Jiaxun Yang @ 2021-02-02 3:49 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Aleksandar Rikalo, Huacai Chen,
Philippe Mathieu-Daudé,
Paul Burton
在 2021/1/27 下午2:54, Jiaxun Yang 写道:
> v2:
> A big reconstruction. rewrite helpers with CPU feature and sepreate
> changesets.
> v3:
> respin
ping?
>
> Jiaxun Yang (4):
> hw/mips: Add a bootloader helper
> hw/mips: Use bl_gen_kernel_jump to generate bootloaders
> hw/mips/malta: Use bootloader helper to set BAR resgiters
> hw/mips/boston: Use bootloader helper to set GCRs
>
> include/hw/mips/bootloader.h | 49 +++++++++++
> hw/mips/bootloader.c | 164 +++++++++++++++++++++++++++++++++++
> hw/mips/boston.c | 64 +++-----------
> hw/mips/fuloong2e.c | 28 +-----
> hw/mips/malta.c | 109 +++++++----------------
> hw/mips/meson.build | 2 +-
> 6 files changed, 260 insertions(+), 156 deletions(-)
> create mode 100644 include/hw/mips/bootloader.h
> create mode 100644 hw/mips/bootloader.c
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v3 0/4] MIPS Bootloader helper
2021-01-27 6:54 [PATCH v3 0/4] MIPS Bootloader helper Jiaxun Yang
` (4 preceding siblings ...)
2021-02-02 3:49 ` [PATCH v3 0/4] MIPS Bootloader helper Jiaxun Yang
@ 2021-02-21 13:17 ` Philippe Mathieu-Daudé
5 siblings, 0 replies; 11+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-21 13:17 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno, Paul Burton
On 1/27/21 7:54 AM, Jiaxun Yang wrote:
> v2:
> A big reconstruction. rewrite helpers with CPU feature and sepreate
> changesets.
> v3:
> respin
>
> Jiaxun Yang (4):
> hw/mips: Add a bootloader helper
> hw/mips: Use bl_gen_kernel_jump to generate bootloaders
> hw/mips/malta: Use bootloader helper to set BAR resgiters
> hw/mips/boston: Use bootloader helper to set GCRs
>
> include/hw/mips/bootloader.h | 49 +++++++++++
> hw/mips/bootloader.c | 164 +++++++++++++++++++++++++++++++++++
> hw/mips/boston.c | 64 +++-----------
> hw/mips/fuloong2e.c | 28 +-----
> hw/mips/malta.c | 109 +++++++----------------
> hw/mips/meson.build | 2 +-
> 6 files changed, 260 insertions(+), 156 deletions(-)
> create mode 100644 include/hw/mips/bootloader.h
> create mode 100644 hw/mips/bootloader.c
>
Thanks, except the malta part, applied to mips-next.
^ permalink raw reply [flat|nested] 11+ messages in thread