From: Sean Anderson <seanga2@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH 11/14] spi: dw: Add registers necessary for DUAL/QUAD/OCTAL
Date: Sun, 31 Jan 2021 19:34:33 -0500 [thread overview]
Message-ID: <20210201003436.1180667-12-seanga2@gmail.com> (raw)
In-Reply-To: <20210201003436.1180667-1-seanga2@gmail.com>
This adds some registers needed for DUAL/QUAD/OCTAL modes. It also adds the
fields in (R)ISR so we can check for over-/under-flow.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
---
drivers/spi/designware_spi.c | 55 ++++++++++++++++++++++++++++++++++--
1 file changed, 52 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 1dd83e6ca6..169888a06d 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -56,6 +56,8 @@
#define DW_SPI_IDR 0x58
#define DW_SPI_VERSION 0x5c
#define DW_SPI_DR 0x60
+#define DW_SPI_RX_SAMPLE_DLY 0xf0
+#define DW_SPI_SPI_CTRL0 0xf4
/* Bit fields in CTRLR0 */
/*
@@ -80,8 +82,8 @@
#define CTRLR0_TMOD_RO 0x2 /* recv only */
#define CTRLR0_TMOD_EPROMREAD 0x3 /* eeprom read mode */
-#define CTRLR0_SLVOE_OFFSET 10
-#define CTRLR0_SRL_OFFSET 11
+#define CTRLR0_SLVOE_OFFSET BIT(10)
+#define CTRLR0_SRL BIT(11)
#define CTRLR0_CFS_MASK GENMASK(15, 12)
/* Only present when SSI_MAX_XFER_SIZE=32 */
@@ -92,13 +94,15 @@
#define CTRLR0_SPI_FRF_BYTE 0x0
#define CTRLR0_SPI_FRF_DUAL 0x1
#define CTRLR0_SPI_FRF_QUAD 0x2
+#define CTRLR0_SPI_FRF_OCTAL 0x3
/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
#define DWC_SSI_CTRLR0_DFS_MASK GENMASK(4, 0)
#define DWC_SSI_CTRLR0_FRF_MASK GENMASK(7, 6)
#define DWC_SSI_CTRLR0_MODE_MASK GENMASK(9, 8)
#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
-#define DWC_SSI_CTRLR0_SRL_OFFSET 13
+#define DWC_SSI_CTRLR0_SRL BIT(13)
+#define DWC_SSI_CTRLR0_SSTE BIT(14)
#define DWC_SSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22)
/* Bit fields in SR, 7 bits */
@@ -111,6 +115,51 @@
#define SR_TX_ERR BIT(5)
#define SR_DCOL BIT(6)
+/* Bit fields in (R)ISR */
+
+/* TX FIFO Empty */
+#define ISR_TXEI BIT(0)
+/* TX FIFO Overflow */
+#define ISR_TXOI BIT(1)
+/* RX FIFO Underflow */
+#define ISR_RXUI BIT(2)
+/* RX FIFO Overflow */
+#define ISR_RXOI BIT(3)
+/* RX FIFO Full */
+#define ISR_RXFI BIT(4)
+/* Multi-master contention */
+#define ISR_MSTI BIT(5)
+/* XIP Receive FIFO Overflow */
+#define ISR_XRXOI BIT(6)
+/* TX FIFO Underflow */
+#define ISR_TXUI BIT(7)
+/* AXI Error */
+#define ISR_AXIE BIT(8)
+/* SPI TX Error */
+#define ISR_SPITE BIT(10)
+/* SSI Done */
+#define ISR_DONE BIT(11)
+
+/* Bit fields in SPI_CTRLR0 */
+
+/*
+ * Whether the instruction or address use the value of SPI_FRF or use
+ * FRF_BYTE
+ */
+#define SPI_CTRLR0_TRANS_TYPE GENMASK(1, 0)
+#define SPI_CTRLR0_TRANS_TYPE_1_1_X 0x0
+#define SPI_CTRLR0_TRANS_TYPE_1_X_X 0x1
+#define SPI_CTRLR0_TRANS_TYPE_X_X_X 0x2
+/* Address width in 4-bit units */
+#define SPI_CTRLR0_ADDR_L_MASK GENMASK(5, 2)
+/* Enable mode bits after address in XIP mode */
+#define SPI_CTRLR0_XIP_MD_BIT_EN BIT(7)
+/* Instruction width in 4-bit units */
+#define SPI_CTRLR0_INST_L_MASK GENMASK(9, 8)
+/* Number of "dummy" cycles */
+#define SPI_CTRLR0_WAIT_CYCLES_MASK GENMASK(15, 11)
+#define SPI_CTRLR0_CLK_STRETCH_EN BIT(30)
+
#define RX_TIMEOUT 1000 /* timeout in ms */
struct dw_spi_plat {
--
2.29.2
next prev parent reply other threads:[~2021-02-01 0:34 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-01 0:34 [PATCH 00/14] spi: dw: Add support for DUAL/QUAD/OCTAL modes Sean Anderson
2021-02-01 0:34 ` [PATCH 01/14] cmd: sf: Display errno on erase failure Sean Anderson
2021-02-01 5:06 ` Bin Meng
2021-02-01 12:51 ` Pratyush Yadav
2021-02-01 0:34 ` [PATCH 02/14] cmd: sf: Print error on test failure Sean Anderson
2021-02-01 5:06 ` Bin Meng
2021-02-01 12:54 ` Pratyush Yadav
2021-02-01 0:34 ` [PATCH 03/14] mtd: spi-nor-core: Fix typo in documentation Sean Anderson
2021-02-01 5:06 ` Bin Meng
2021-02-01 12:23 ` Pratyush Yadav
2021-02-01 0:34 ` [PATCH 04/14] mtd: spi-mem: Export spi_mem_default_supports_op Sean Anderson
2021-02-01 5:06 ` Bin Meng
2021-02-01 12:07 ` Pratyush Yadav
2021-02-01 15:15 ` Sean Anderson
2021-02-01 0:34 ` [PATCH 05/14] spi: spi-mem: Add debug message for spi-mem ops Sean Anderson
2021-02-01 5:06 ` Bin Meng
2021-02-01 12:18 ` Pratyush Yadav
2021-02-01 15:33 ` Sean Anderson
2021-02-01 16:34 ` Pratyush Yadav
2021-02-01 0:34 ` [PATCH 06/14] spi: dw: Log status register on timeout Sean Anderson
2021-02-01 0:34 ` [PATCH 07/14] spi: dw: Mask all possible interrupts Sean Anderson
2021-02-04 4:51 ` Sean Anderson
2021-02-01 0:34 ` [PATCH 08/14] spi: dw: Switch to capabilities Sean Anderson
2021-02-01 0:34 ` [PATCH 09/14] spi: dw: Rewrite poll_transfer logic Sean Anderson
2021-02-01 0:34 ` [PATCH 10/14] spi: dw: Add DUAL/QUAD/OCTAL caps Sean Anderson
2021-02-01 18:00 ` Sean Anderson
2021-02-01 0:34 ` Sean Anderson [this message]
2021-02-01 0:34 ` [PATCH 12/14] spi: dw: Support DUAL/QUAD/OCTAL Sean Anderson
2021-02-01 0:34 ` [PATCH 13/14] spi: dw: Support clock stretching Sean Anderson
2021-02-01 0:34 ` [PATCH 14/14] riscv: k210: Enable QSPI for spi3 Sean Anderson
2021-02-01 5:16 ` Bin Meng
2021-02-04 2:32 ` Leo Liang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210201003436.1180667-12-seanga2@gmail.com \
--to=seanga2@gmail.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.