From: Zhen Lei <thunder.leizhen@huawei.com> To: Russell King <rmk+kernel@arm.linux.org.uk>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Will Deacon <will.deacon@arm.com>, "Haojian Zhuang" <haojian.zhuang@gmail.com>, Arnd Bergmann <arnd@arndb.de>, Rob Herring <robh+dt@kernel.org>, Wei Xu <xuwei5@hisilicon.com>, devicetree <devicetree@vger.kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, linux-kernel <linux-kernel@vger.kernel.org> Cc: Zhen Lei <thunder.leizhen@huawei.com> Subject: [PATCH v6 0/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller Date: Mon, 1 Feb 2021 11:35:57 +0800 [thread overview] Message-ID: <20210201033601.1642-1-thunder.leizhen@huawei.com> (raw) v5 --> v6: 1. Use raw_spin_lock_irqsave() instead of spin_lock_irqsave() 2. Move the macros defined in cache-kunpeng-l3.h into cache-kunpeng-l3.c, and delete that header file. 3. In some places, replace readl()/writel() with readl_relaxed()/writel_relaxed() to improve performance without affecting functions. 4. Returns 0 instead of an error code when Kunpeng L3 Cache matching failed. Thank you for Arnd's review comments and Russell's help. v4 --> v5: 1. Add SoC macro ARCH_KUNPENG50X, and the Kunpeng L3 cache controller only enabled on that platform. 2. Require the compatible string of the Kunpeng L3 cache controller must have a relevant name on a specific SoC. For example: compatible = "hisilicon,kunpeng509-l3cache", "hisilicon,kunpeng-l3cache"; v3 --> v4: Rename the compatible string from "hisilicon,l3cache" to "hisilicon,kunpeng-l3cache". Then adjust the file name, configuration option name, and description accordingly. v2 --> v3: Add Hisilicon L3 cache controller driver and its document. That's: patch 2-3. v1 --> v2: Discard the middle-tier functions and do silent narrowing cast in the outcache hook functions. For example: -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; v1: Do cast phys_addr_t to unsigned long by adding a middle-tier function. For example: -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void __l2c220_inv_range(unsigned long start, unsigned long end) { ... } +static void l2c220_inv_range(phys_addr_t start, phys_addr_t end) +{ + __l2c220_inv_range(start, end); +} Zhen Lei (4): ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks ARM: hisi: add support for Kunpeng50x SoC dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache controller ARM: Add support for Hisilicon Kunpeng L3 cache controller .../arm/hisilicon/kunpeng-l3cache.yaml | 40 ++++ arch/arm/include/asm/outercache.h | 6 +- arch/arm/mach-hisi/Kconfig | 6 + arch/arm/mm/Kconfig | 10 + arch/arm/mm/Makefile | 1 + arch/arm/mm/cache-feroceon-l2.c | 15 +- arch/arm/mm/cache-kunpeng-l3.c | 176 ++++++++++++++++++ arch/arm/mm/cache-l2x0.c | 50 +++-- arch/arm/mm/cache-tauros2.c | 15 +- arch/arm/mm/cache-uniphier.c | 6 +- arch/arm/mm/cache-xsc3l2.c | 12 +- 11 files changed, 308 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml create mode 100644 arch/arm/mm/cache-kunpeng-l3.c -- 2.26.0.106.g9fadedd
WARNING: multiple messages have this Message-ID (diff)
From: Zhen Lei <thunder.leizhen@huawei.com> To: Russell King <rmk+kernel@arm.linux.org.uk>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Will Deacon <will.deacon@arm.com>, "Haojian Zhuang" <haojian.zhuang@gmail.com>, Arnd Bergmann <arnd@arndb.de>, Rob Herring <robh+dt@kernel.org>, Wei Xu <xuwei5@hisilicon.com>, devicetree <devicetree@vger.kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, linux-kernel <linux-kernel@vger.kernel.org> Cc: Zhen Lei <thunder.leizhen@huawei.com> Subject: [PATCH v6 0/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller Date: Mon, 1 Feb 2021 11:35:57 +0800 [thread overview] Message-ID: <20210201033601.1642-1-thunder.leizhen@huawei.com> (raw) v5 --> v6: 1. Use raw_spin_lock_irqsave() instead of spin_lock_irqsave() 2. Move the macros defined in cache-kunpeng-l3.h into cache-kunpeng-l3.c, and delete that header file. 3. In some places, replace readl()/writel() with readl_relaxed()/writel_relaxed() to improve performance without affecting functions. 4. Returns 0 instead of an error code when Kunpeng L3 Cache matching failed. Thank you for Arnd's review comments and Russell's help. v4 --> v5: 1. Add SoC macro ARCH_KUNPENG50X, and the Kunpeng L3 cache controller only enabled on that platform. 2. Require the compatible string of the Kunpeng L3 cache controller must have a relevant name on a specific SoC. For example: compatible = "hisilicon,kunpeng509-l3cache", "hisilicon,kunpeng-l3cache"; v3 --> v4: Rename the compatible string from "hisilicon,l3cache" to "hisilicon,kunpeng-l3cache". Then adjust the file name, configuration option name, and description accordingly. v2 --> v3: Add Hisilicon L3 cache controller driver and its document. That's: patch 2-3. v1 --> v2: Discard the middle-tier functions and do silent narrowing cast in the outcache hook functions. For example: -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; v1: Do cast phys_addr_t to unsigned long by adding a middle-tier function. For example: -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void __l2c220_inv_range(unsigned long start, unsigned long end) { ... } +static void l2c220_inv_range(phys_addr_t start, phys_addr_t end) +{ + __l2c220_inv_range(start, end); +} Zhen Lei (4): ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks ARM: hisi: add support for Kunpeng50x SoC dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache controller ARM: Add support for Hisilicon Kunpeng L3 cache controller .../arm/hisilicon/kunpeng-l3cache.yaml | 40 ++++ arch/arm/include/asm/outercache.h | 6 +- arch/arm/mach-hisi/Kconfig | 6 + arch/arm/mm/Kconfig | 10 + arch/arm/mm/Makefile | 1 + arch/arm/mm/cache-feroceon-l2.c | 15 +- arch/arm/mm/cache-kunpeng-l3.c | 176 ++++++++++++++++++ arch/arm/mm/cache-l2x0.c | 50 +++-- arch/arm/mm/cache-tauros2.c | 15 +- arch/arm/mm/cache-uniphier.c | 6 +- arch/arm/mm/cache-xsc3l2.c | 12 +- 11 files changed, 308 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml create mode 100644 arch/arm/mm/cache-kunpeng-l3.c -- 2.26.0.106.g9fadedd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2021-02-01 3:38 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-01 3:35 Zhen Lei [this message] 2021-02-01 3:35 ` [PATCH v6 0/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller Zhen Lei 2021-02-01 3:35 ` [PATCH v6 1/4] ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks Zhen Lei 2021-02-01 3:35 ` Zhen Lei 2021-02-01 3:35 ` [PATCH v6 2/4] ARM: hisi: add support for Kunpeng50x SoC Zhen Lei 2021-02-01 3:35 ` Zhen Lei 2021-02-01 8:35 ` Arnd Bergmann 2021-02-01 8:35 ` Arnd Bergmann 2021-02-01 11:49 ` Leizhen (ThunderTown) 2021-02-01 11:49 ` Leizhen (ThunderTown) 2021-02-01 12:14 ` Arnd Bergmann 2021-02-01 12:14 ` Arnd Bergmann 2021-02-01 3:36 ` [PATCH v6 3/4] dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache controller Zhen Lei 2021-02-01 3:36 ` Zhen Lei 2021-02-01 3:36 ` [PATCH v6 4/4] ARM: Add support for Hisilicon " Zhen Lei 2021-02-01 3:36 ` Zhen Lei 2021-02-01 8:31 ` Arnd Bergmann 2021-02-01 8:31 ` Arnd Bergmann 2021-02-01 11:38 ` Leizhen (ThunderTown) 2021-02-01 11:38 ` Leizhen (ThunderTown)
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