From: Russell King - ARM Linux admin <linux@armlinux.org.uk>
To: Marc Zyngier <maz@kernel.org>
Cc: Ard Biesheuvel <ardb@kernel.org>,
Guillaume Tucker <guillaume.tucker@collabora.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Nicolas Pitre <nico@fluxnic.net>,
kernelci-results@groups.io
Subject: Re: next/master bisection: baseline.login on rk3288-rock2-square
Date: Thu, 4 Feb 2021 14:09:11 +0000 [thread overview]
Message-ID: <20210204140911.GX1463@shell.armlinux.org.uk> (raw)
In-Reply-To: <090003e6f825de1f8460c0e987e14577@kernel.org>
On Thu, Feb 04, 2021 at 12:26:44PM +0000, Marc Zyngier wrote:
> I agree. With set/way CMOs, there is no way to reach the PoC if
> it beyond the system cache, leading to an unbootable kernel.
> This is actually pretty well documented in the architecture,
> and it did bite us for the first time on XGene-1, 7 years ago.
That may be, however we still do set/way maintenance to invalidate
the L1 cache as that is required for ARMv7 to place the cache into
a known state, as stated by the architecture reference manual.
Arguably, that should be done by firmware, but when starting
secondary CPUs, there are platforms out there which do not bring
the L1 cache to a defined state. So we are pretty much stuck with
doing set/way operations during CPU initialisation in the main
kernel.
If ARMv8 decides that this is not supportable, then that's a matter
for ARMv8 to address without impacting the requirements of ARMv7.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
WARNING: multiple messages have this Message-ID (diff)
From: Russell King - ARM Linux admin <linux@armlinux.org.uk>
To: Marc Zyngier <maz@kernel.org>
Cc: kernelci-results@groups.io,
Geert Uytterhoeven <geert+renesas@glider.be>,
Nicolas Pitre <nico@fluxnic.net>,
Guillaume Tucker <guillaume.tucker@collabora.com>,
Linus Walleij <linus.walleij@linaro.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Ard Biesheuvel <ardb@kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: next/master bisection: baseline.login on rk3288-rock2-square
Date: Thu, 4 Feb 2021 14:09:11 +0000 [thread overview]
Message-ID: <20210204140911.GX1463@shell.armlinux.org.uk> (raw)
In-Reply-To: <090003e6f825de1f8460c0e987e14577@kernel.org>
On Thu, Feb 04, 2021 at 12:26:44PM +0000, Marc Zyngier wrote:
> I agree. With set/way CMOs, there is no way to reach the PoC if
> it beyond the system cache, leading to an unbootable kernel.
> This is actually pretty well documented in the architecture,
> and it did bite us for the first time on XGene-1, 7 years ago.
That may be, however we still do set/way maintenance to invalidate
the L1 cache as that is required for ARMv7 to place the cache into
a known state, as stated by the architecture reference manual.
Arguably, that should be done by firmware, but when starting
secondary CPUs, there are platforms out there which do not bring
the L1 cache to a defined state. So we are pretty much stuck with
doing set/way operations during CPU initialisation in the main
kernel.
If ARMv8 decides that this is not supportable, then that's a matter
for ARMv8 to address without impacting the requirements of ARMv7.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-02-04 14:12 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <601b773a.1c69fb81.9f381.a32a@mx.google.com>
2021-02-04 8:43 ` next/master bisection: baseline.login on rk3288-rock2-square Guillaume Tucker
2021-02-04 8:43 ` Guillaume Tucker
2021-02-04 9:07 ` Ard Biesheuvel
2021-02-04 9:07 ` Ard Biesheuvel
2021-02-04 10:06 ` Russell King - ARM Linux admin
2021-02-04 10:06 ` Russell King - ARM Linux admin
2021-02-04 10:27 ` Ard Biesheuvel
2021-02-04 10:27 ` Ard Biesheuvel
2021-02-04 10:33 ` Guillaume Tucker
2021-02-04 10:33 ` Guillaume Tucker
2021-02-04 11:32 ` Guillaume Tucker
2021-02-04 11:32 ` Guillaume Tucker
2021-02-04 11:44 ` Russell King - ARM Linux admin
2021-02-04 11:44 ` Russell King - ARM Linux admin
2021-02-04 12:09 ` Ard Biesheuvel
2021-02-04 12:09 ` Ard Biesheuvel
2021-02-04 15:42 ` Ard Biesheuvel
2021-02-04 15:42 ` Ard Biesheuvel
2021-02-04 15:53 ` Guillaume Tucker
2021-02-04 15:53 ` Guillaume Tucker
2021-02-04 16:01 ` Ard Biesheuvel
2021-02-04 16:01 ` Ard Biesheuvel
2021-02-04 18:06 ` Nick Desaulniers
2021-02-04 18:06 ` Nick Desaulniers
2021-02-04 18:12 ` Nathan Chancellor
2021-02-04 18:12 ` Nathan Chancellor
2021-02-04 18:23 ` Nick Desaulniers
2021-02-04 18:23 ` Nick Desaulniers
2021-02-04 21:31 ` Guillaume Tucker
2021-02-04 21:31 ` Guillaume Tucker
2021-02-04 21:50 ` Russell King - ARM Linux admin
2021-02-04 21:50 ` Russell King - ARM Linux admin
2021-02-05 8:21 ` Ard Biesheuvel
2021-02-05 8:21 ` Ard Biesheuvel
2021-02-05 12:05 ` Ard Biesheuvel
2021-02-05 12:05 ` Ard Biesheuvel
2021-02-06 13:10 ` Guillaume Tucker
2021-02-06 13:10 ` Guillaume Tucker
2021-02-06 13:12 ` Ard Biesheuvel
2021-02-06 13:12 ` Ard Biesheuvel
2021-02-04 21:09 ` Guillaume Tucker
2021-02-04 21:09 ` Guillaume Tucker
2021-02-04 10:47 ` Russell King - ARM Linux admin
2021-02-04 10:47 ` Russell King - ARM Linux admin
2021-02-04 10:55 ` Ard Biesheuvel
2021-02-04 10:55 ` Ard Biesheuvel
2021-02-04 12:26 ` Marc Zyngier
2021-02-04 12:26 ` Marc Zyngier
2021-02-04 14:09 ` Russell King - ARM Linux admin [this message]
2021-02-04 14:09 ` Russell King - ARM Linux admin
2021-02-04 14:25 ` Ard Biesheuvel
2021-02-04 14:25 ` Ard Biesheuvel
2021-02-04 14:36 ` Russell King - ARM Linux admin
2021-02-04 14:36 ` Russell King - ARM Linux admin
2021-02-04 15:52 ` Ard Biesheuvel
2021-02-04 15:52 ` Ard Biesheuvel
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