[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Marek Behún]

This syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.

There are some commits regarding DDR3 on top of version 14.0.0 in the
mv-ddr-marvell repository (from Chris Packham), but these changes
already are in U-Boot.

Marek

Marek Beh?n (18):
  ddr: marvell: a38x: fix write leveling suplementary algo
  ddr: marvell: a38x: import header change from upstream
  ddr: marvell: a38x: add ddr32 support
  ddr: marvell: a38x: add ddr 32bit ECC support
  ddr: marvell: a38x: import header change from upstream
  ddr: marvell: a38x: fix 32bit
  ddr: marvell: a38x: fix memory size calculation using 32bit bus width
  ddr: marvell: a38x: import header change from upstream
  ddr: marvell: a38x: allow board specific ODT configuration
  ddr: marvell: a38x: add 16Gbit memory devices support
  ddr: marvell: a38x: add support for twin-die combined memory device
  ddr: marvell: a38x: disable WL phase correction stage in case of
    bus_width=16bit
  ddr: marvell: a38x: import header change from upstream
  ddr: marvell: a38x: fix memory cs size function
  ddr: marvell: a38x: import code change from upstream
  ddr: marvell: a38x: enum mv_ddr_twin_die: change order
  ddr: marvell: a38x: bump version to 14.0.0
  ddr: marvell: a38x: fix comment in conditional macro

 board/CZ.NIC/turris_omnia/turris_omnia.c      |  2 ++
 board/Marvell/db-88f6820-amc/db-88f6820-amc.c |  1 +
 board/Marvell/db-88f6820-gp/db-88f6820-gp.c   |  1 +
 board/alliedtelesis/x530/x530.c               |  1 +
 board/gdsys/a38x/controlcenterdc.c            |  1 +
 board/kobol/helios4/helios4.c                 |  1 +
 board/solidrun/clearfog/clearfog.c            |  1 +
 drivers/ddr/marvell/a38x/ddr3_init.c          |  5 ++++
 drivers/ddr/marvell/a38x/ddr3_training.c      |  5 +++-
 drivers/ddr/marvell/a38x/ddr3_training_db.c   |  3 +++
 .../ddr/marvell/a38x/ddr3_training_ip_def.h   |  2 ++
 .../marvell/a38x/ddr3_training_ip_engine.c    |  5 +++-
 drivers/ddr/marvell/a38x/ddr_topology_def.h   | 23 ++++++++++++++++++-
 .../ddr/marvell/a38x/mv_ddr_build_message.c   |  2 +-
 drivers/ddr/marvell/a38x/mv_ddr_plat.c        |  9 ++++++--
 drivers/ddr/marvell/a38x/mv_ddr_topology.c    | 14 ++++++++---
 drivers/ddr/marvell/a38x/mv_ddr_topology.h    |  2 ++
 drivers/ddr/marvell/a38x/xor.c                |  6 ++---
 18 files changed, 72 insertions(+), 12 deletions(-)

-- 
2.26.2

[PATCH u-boot-marvell 01/18] ddr: marvell: a38x: fix write leveling suplementary algo

[Marek Behún]

commit ce62bef8fac559e27245259882e45f19cdc293ad upstream.

- fix JIRA A7K8K-5056
- remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage
- the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory
  then the algorithm will fail, since it think that there are no phase to correct

Signed-off-by: motib <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
index 979f3530b7..5fd9a052fa 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
@@ -864,8 +864,11 @@ int ddr3_tip_load_all_pattern_to_mem(u32 dev_num)
 			      DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3)));
 	}
 
-	for (pattern = 0; pattern < PATTERN_LAST; pattern++)
+	for (pattern = 0; pattern < PATTERN_LAST; pattern++) {
+		if (pattern == PATTERN_TEST)
+			continue;
 		ddr3_tip_load_pattern_to_mem(dev_num, pattern);
+	}
 
 	return MV_OK;
 }
-- 
2.26.2

[PATCH u-boot-marvell 02/18] ddr: marvell: a38x: import header change from upstream

[Marek Behún]

commit a165037ec26f301be75e1fabc263643683e85255 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 34196b1662..c55e3b57e4 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -148,7 +148,8 @@ enum mv_ddr_validation {
 	MV_DDR_VAL_DIS,
 	MV_DDR_VAL_RX,
 	MV_DDR_VAL_TX,
-	MV_DDR_VAL_RX_TX
+	MV_DDR_VAL_RX_TX,
+	MV_DDR_MEMORY_CHECK
 };
 
 struct mv_ddr_iface {
-- 
2.26.2

[PATCH u-boot-marvell 03/18] ddr: marvell: a38x: add ddr32 support

[Marek Behún]

commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream.

Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c

Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/mv_ddr_topology.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index 09840b1e70..f2cd7c0ef3 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -144,6 +144,9 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
 	unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
 
 	if (tm->cfg_src == MV_DDR_CFG_SPD) {
+		if (tm->bus_act_mask == BUS_MASK_32BIT)
+			tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32;
+
 		enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
 		enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
 
@@ -151,7 +154,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
 		case MV_DDR_PRI_BUS_WIDTH_16:
 			pri_and_ext_bus_width = BUS_MASK_16BIT;
 			break;
-		case MV_DDR_PRI_BUS_WIDTH_32:
+		case MV_DDR_PRI_BUS_WIDTH_32: /*each bit represents byte, so 0xf-is means 4 bytes-32 bit*/
 			pri_and_ext_bus_width = BUS_MASK_32BIT;
 			break;
 		case MV_DDR_PRI_BUS_WIDTH_64:
-- 
2.26.2

[PATCH u-boot-marvell 04/18] ddr: marvell: a38x: add ddr 32bit ECC support

[Marek Behún]

commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream.

Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c

Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/mv_ddr_spd.c      | 5 +++++
 drivers/ddr/marvell/a38x/mv_ddr_spd.h      | 1 +
 drivers/ddr/marvell/a38x/mv_ddr_topology.c | 6 +++++-
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.c b/drivers/ddr/marvell/a38x/mv_ddr_spd.c
index 04dbfe94d6..cb90d30a6a 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_spd.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.c
@@ -217,6 +217,11 @@ enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_
 	return ret_val;
 }
 
+void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity)
+{
+	spd_data->byte_fields.byte_4.bit_fields.die_capacity = capacity;
+}
+
 unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data)
 {
 	unsigned char mem_mirror = spd_data->byte_fields.byte_131.bit_fields.rank_1_mapping;
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.h b/drivers/ddr/marvell/a38x/mv_ddr_spd.h
index b4bfef3103..ee35377af5 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_spd.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.h
@@ -277,6 +277,7 @@ union mv_ddr_spd_data {
 int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_data[]);
 enum mv_ddr_dev_width mv_ddr_spd_dev_width_get(union mv_ddr_spd_data *spd_data);
 enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_data);
+void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity);
 unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data);
 unsigned char mv_ddr_spd_cs_bit_mask_get(union mv_ddr_spd_data *spd_data);
 unsigned char mv_ddr_spd_dev_type_get(union mv_ddr_spd_data *spd_data);
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index f2cd7c0ef3..0cbe8d3d1e 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -74,6 +74,10 @@ int mv_ddr_topology_map_update(void)
 		/* update device width in topology map */
 		iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data);
 
+		/* overwrite SPD configuration, with what the user set */
+		if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
+			mv_ddr_spd_die_capacity_user_get(&tm->spd_data, tm->interface_params[0].memory_size);
+
 		/* update die capacity in topology map */
 		iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data);
 
@@ -144,7 +148,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
 	unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
 
 	if (tm->cfg_src == MV_DDR_CFG_SPD) {
-		if (tm->bus_act_mask == BUS_MASK_32BIT)
+		if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
 			tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32;
 
 		enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
-- 
2.26.2

[PATCH u-boot-marvell 05/18] ddr: marvell: a38x: import header change from upstream

[Marek Behún]

commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header mv_ddr_topology.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/mv_ddr_topology.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.h b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
index 4fca47689f..1cb69ad085 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
@@ -179,7 +179,9 @@ enum mv_ddr_dic_evalue {
 
 /* phy electrical configuration values */
 enum mv_ddr_ohm_evalue {
+	MV_DDR_OHM_20 = 20,/*relevant for Synopsys C/A Drive strength only*/
 	MV_DDR_OHM_30 = 30,
+	MV_DDR_OHM_40 = 40,/*relevant for Synopsys C/A Drive strength only*/
 	MV_DDR_OHM_48 = 48,
 	MV_DDR_OHM_60 = 60,
 	MV_DDR_OHM_80 = 80,
-- 
2.26.2

[PATCH u-boot-marvell 06/18] ddr: marvell: a38x: fix 32bit

[Marek Behún]

commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream.

Signed-off-by: motib <motib@marvell.com>
Reviewed-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/mv_ddr_topology.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index 0cbe8d3d1e..3feb65ea46 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -149,7 +149,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
 
 	if (tm->cfg_src == MV_DDR_CFG_SPD) {
 		if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
-			tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32;
+			tm->spd_data.byte_fields.byte_13.bit_fields.primary_bus_width = MV_DDR_PRI_BUS_WIDTH_32;
 
 		enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
 		enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
-- 
2.26.2

[PATCH u-boot-marvell 07/18] ddr: marvell: a38x: fix memory size calculation using 32bit bus width

[Marek Behún]

commit ab9240402a70cc02496683971779e75eff410ab4 upstream.

- function mv_ddr_spd_die_capacity_user_get() has a bug,
  since it insert a user memory enum to it,
  instead of SPD memory enum (which are different)
- fix: remove mv_ddr_spd_die_capacity_user_get() function.
- memory size with 64 and 32 bit already calculated correctly
  at mv_ddr_mem_sz_per_cs_get() function

Signed-off-by: motib <motib@marvell.com>
Reviewed-by: Stefan Chulski <Stefan.Chulski@cavium.com>
Reviewed-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/mv_ddr_spd.c      | 5 -----
 drivers/ddr/marvell/a38x/mv_ddr_spd.h      | 1 -
 drivers/ddr/marvell/a38x/mv_ddr_topology.c | 4 ----
 3 files changed, 10 deletions(-)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.c b/drivers/ddr/marvell/a38x/mv_ddr_spd.c
index cb90d30a6a..04dbfe94d6 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_spd.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.c
@@ -217,11 +217,6 @@ enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_
 	return ret_val;
 }
 
-void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity)
-{
-	spd_data->byte_fields.byte_4.bit_fields.die_capacity = capacity;
-}
-
 unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data)
 {
 	unsigned char mem_mirror = spd_data->byte_fields.byte_131.bit_fields.rank_1_mapping;
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.h b/drivers/ddr/marvell/a38x/mv_ddr_spd.h
index ee35377af5..b4bfef3103 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_spd.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.h
@@ -277,7 +277,6 @@ union mv_ddr_spd_data {
 int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_data[]);
 enum mv_ddr_dev_width mv_ddr_spd_dev_width_get(union mv_ddr_spd_data *spd_data);
 enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_data);
-void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity);
 unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data);
 unsigned char mv_ddr_spd_cs_bit_mask_get(union mv_ddr_spd_data *spd_data);
 unsigned char mv_ddr_spd_dev_type_get(union mv_ddr_spd_data *spd_data);
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index 3feb65ea46..31711fdd49 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -74,10 +74,6 @@ int mv_ddr_topology_map_update(void)
 		/* update device width in topology map */
 		iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data);
 
-		/* overwrite SPD configuration, with what the user set */
-		if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
-			mv_ddr_spd_die_capacity_user_get(&tm->spd_data, tm->interface_params[0].memory_size);
-
 		/* update die capacity in topology map */
 		iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data);
 
-- 
2.26.2

[PATCH u-boot-marvell 08/18] ddr: marvell: a38x: import header change from upstream

[Marek Behún]

commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/ddr_topology_def.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index c55e3b57e4..342c2cf451 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -152,6 +152,11 @@ enum mv_ddr_validation {
 	MV_DDR_MEMORY_CHECK
 };
 
+enum mv_ddr_sscg {
+	SSCG_EN,
+	SSCG_DIS,
+};
+
 struct mv_ddr_iface {
 	/* base addr of ap ddr interface belongs to */
 	unsigned int ap_base;
@@ -180,6 +185,9 @@ struct mv_ddr_iface {
 	/* ddr interface validation mode */
 	enum mv_ddr_validation validation;
 
+	/* ddr interface validation mode */
+	enum mv_ddr_sscg sscg;
+
 	/* ddr interface topology map */
 	struct mv_ddr_topology_map tm;
 };
-- 
2.26.2

[PATCH u-boot-marvell 09/18] ddr: marvell: a38x: allow board specific ODT configuration

[Marek Behún]

commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream.

The ODT enable heuristic based on active chip-selects is not always
correct. Some board might use two chip-selects, but have only one ODT
line connected. Allow board specific mv_ddr_topology_map to directly set
the ODT configuration register value.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/ddr3_init.c        | 5 +++++
 drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 +++
 2 files changed, 8 insertions(+)

diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
index a971cc155a..7488770268 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -104,6 +104,7 @@ int ddr3_init(void)
 static int mv_ddr_training_params_set(u8 dev_num)
 {
 	struct tune_train_params params;
+	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 	int status;
 	u32 cs_num;
 	int ck_delay;
@@ -136,6 +137,10 @@ static int mv_ddr_training_params_set(u8 dev_num)
 	if (ck_delay > 0)
 		params.ck_delay = ck_delay;
 
+	/* Use platform specific override ODT value */
+	if (tm->odt_config)
+		params.g_odt_config = tm->odt_config;
+
 	status = ddr3_tip_tune_training_params(dev_num, &params);
 	if (MV_OK != status) {
 		printf("%s Training Sequence - FAILED\n", ddr_type);
diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 342c2cf451..3991fec272 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -125,6 +125,9 @@ struct mv_ddr_topology_map {
 	/* electrical parameters */
 	unsigned int electrical_data[MV_DDR_EDATA_LAST];
 
+	/* ODT configuration */
+	u32 odt_config;
+
 	/* Clock enable mask */
 	u32 clk_enable;
 
-- 
2.26.2

[PATCH u-boot-marvell 10/18] ddr: marvell: a38x: add 16Gbit memory devices support

[Marek Behún]

commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/ddr3_training_ip_def.h | 2 ++
 drivers/ddr/marvell/a38x/mv_ddr_topology.c      | 3 ++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
index 2a68669f36..8765df7cfb 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
@@ -80,6 +80,8 @@
 #define ADDR_SIZE_2GB			0x10000000
 #define ADDR_SIZE_4GB			0x20000000
 #define ADDR_SIZE_8GB			0x40000000
+#define ADDR_SIZE_16GB			0x80000000
+
 
 enum hws_edge_compare {
 	EDGE_PF,
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index 31711fdd49..c4c3ab72b2 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -248,7 +248,8 @@ static unsigned int mem_size[] = {
 	ADDR_SIZE_1GB,
 	ADDR_SIZE_2GB,
 	ADDR_SIZE_4GB,
-	ADDR_SIZE_8GB
+	ADDR_SIZE_8GB,
+	ADDR_SIZE_16GB
 	/* TODO: add capacity up to 256GB */
 };
 
-- 
2.26.2

[PATCH u-boot-marvell 11/18] ddr: marvell: a38x: add support for twin-die combined memory device

[Marek Behún]

commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream.

the twin-die combined memory device should be treatened as X8
device and not as X16 one

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

The default value for twin_die_combined is set to NOT_COMBINED for all
boards, as this was default behaviour prior this change.

Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 board/CZ.NIC/turris_omnia/turris_omnia.c      |  2 ++
 board/Marvell/db-88f6820-amc/db-88f6820-amc.c |  1 +
 board/Marvell/db-88f6820-gp/db-88f6820-gp.c   |  1 +
 board/alliedtelesis/x530/x530.c               |  1 +
 board/gdsys/a38x/controlcenterdc.c            |  1 +
 board/kobol/helios4/helios4.c                 |  1 +
 board/solidrun/clearfog/clearfog.c            |  1 +
 drivers/ddr/marvell/a38x/ddr_topology_def.h   | 12 ++++++++++++
 drivers/ddr/marvell/a38x/mv_ddr_topology.c    |  6 +++++-
 9 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 2da878d364..78b125edfe 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -285,6 +285,7 @@ static struct mv_ddr_topology_map board_topology_map_1g = {
 	    MV_DDR_TIM_2T} },		/* timing */
 	BUS_MASK_32BIT,			/* Busses mask */
 	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
 	{ {0} },			/* raw spd data */
 	{0}				/* timing parameters */
 };
@@ -307,6 +308,7 @@ static struct mv_ddr_topology_map board_topology_map_2g = {
 	    MV_DDR_TIM_2T} },		/* timing */
 	BUS_MASK_32BIT,			/* Busses mask */
 	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
 	{ {0} },			/* raw spd data */
 	{0}				/* timing parameters */
 };
diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
index 9cd9ea2c06..acc8a5ec6d 100644
--- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
+++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
@@ -72,6 +72,7 @@ static struct mv_ddr_topology_map board_topology_map = {
 	    MV_DDR_TIM_DEFAULT} },	/* timing */
 	BUS_MASK_32BIT,			/* Busses mask */
 	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
 	{ {0} },			/* raw spd data */
 	{0}				/* timing parameters */
 };
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index 2bdd55329d..a1d0104526 100644
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -93,6 +93,7 @@ static struct mv_ddr_topology_map board_topology_map = {
 	    MV_DDR_TIM_DEFAULT} },	/* timing */
 	BUS_MASK_32BIT,			/* Busses mask */
 	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
 	{ {0} },			/* raw spd data */
 	{0}				/* timing parameters */
 };
diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c
index c7438aeaf1..6caba24196 100644
--- a/board/alliedtelesis/x530/x530.c
+++ b/board/alliedtelesis/x530/x530.c
@@ -67,6 +67,7 @@ static struct mv_ddr_topology_map board_topology_map = {
 	    MV_DDR_TIM_2T} },		/* timing */
 	BUS_MASK_32BIT_ECC,		/* subphys mask */
 	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
 	{ {0} },			/* raw spd data */
 	{0},				/* timing parameters */
 	{ {0} },			/* electrical configuration */
diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
index a2287f9deb..66a0d769ce 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -70,6 +70,7 @@ static struct mv_ddr_topology_map ddr_topology_map = {
 	    MV_DDR_TIM_DEFAULT} },	/* timing */
 	BUS_MASK_32BIT,			/* Busses mask */
 	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
 	{ {0} },			/* raw spd data */
 	{0}				/* timing parameters */
 
diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c
index 17d2489415..5007194a52 100644
--- a/board/kobol/helios4/helios4.c
+++ b/board/kobol/helios4/helios4.c
@@ -70,6 +70,7 @@ static struct mv_ddr_topology_map board_topology_map = {
 	    MV_DDR_TIM_DEFAULT} },	/* timing */
 	BUS_MASK_32BIT_ECC,		/* Busses mask */
 	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
 	{ {0} },			/* raw spd data */
 	{0}				/* timing parameters */
 };
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index 92443d5177..3166f0abe0 100644
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -141,6 +141,7 @@ static struct mv_ddr_topology_map board_topology_map = {
 	    MV_DDR_TIM_DEFAULT} },	/* timing */
 	BUS_MASK_32BIT,			/* Busses mask */
 	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
 	{ {0} },			/* raw spd data */
 	{0},				/* timing parameters */
 	{ {0} },			/* electrical configuration */
diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 3991fec272..461f091472 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -14,6 +14,11 @@
 #define MV_DDR_MAX_BUS_NUM	9
 #define MV_DDR_MAX_IFACE_NUM	1
 
+enum mv_ddr_twin_die {
+	COMBINED,
+	NOT_COMBINED,
+};
+
 struct bus_params {
 	/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
 	u8 cs_bitmask;
@@ -47,6 +52,9 @@ struct if_params {
 	/* The DDR frequency for each interfaces */
 	enum mv_ddr_freq memory_freq;
 
+    /* ddr twin-die */
+	enum mv_ddr_twin_die twin_die_combined;
+
 	/*
 	 * delay CAS Write Latency
 	 * - 0 for using default value (jedec suggested)
@@ -113,6 +121,9 @@ struct mv_ddr_topology_map {
 	/* source of ddr configuration data */
 	enum mv_ddr_cfg_src cfg_src;
 
+	/* ddr twin-die */
+	enum mv_ddr_twin_die twin_die_combined;
+
 	/* raw spd data */
 	union mv_ddr_spd_data spd_data;
 
@@ -193,6 +204,7 @@ struct mv_ddr_iface {
 
 	/* ddr interface topology map */
 	struct mv_ddr_topology_map tm;
+
 };
 
 struct mv_ddr_iface *mv_ddr_iface_get(void);
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index c4c3ab72b2..2db6283c23 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -127,6 +127,11 @@ int mv_ddr_topology_map_update(void)
 		speed_bin_index = iface_params->speed_bin_index;
 		freq = iface_params->memory_freq;
 
+		if (tm->twin_die_combined == COMBINED) {
+			iface_params->bus_width = MV_DDR_DEV_WIDTH_8BIT;
+			iface_params->memory_size -= 1;
+		}
+
 		if (iface_params->cas_l == 0)
 			iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq);
 
@@ -281,7 +286,6 @@ unsigned long long mv_ddr_mem_sz_per_cs_get(void)
 	mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] *
 			(unsigned long long)sphys /
 			(unsigned long long)sphys_per_dunit;
-
 	return mem_sz_per_cs;
 }
 
-- 
2.26.2

[PATCH u-boot-marvell 12/18] ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bit

[Marek Behún]

commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream.

WL phase correcion stage is failing while using bus_width of 16bit, not
to be fix this stage is un-necessary when working with bus_width of 16
bit.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/ddr3_training_db.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c
index b2f11a8399..6aa7b6069e 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_db.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c
@@ -833,6 +833,9 @@ u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index)
 			pattern = pattern_table_get_isi_word16(index);
 			break;
 		default:
+			if (((int)type == 29) || ((int)type == 30))
+				break;
+
 			printf("error: %s: unsupported pattern type [%d] found\n",
 			       __func__, (int)type);
 			pattern = 0;
-- 
2.26.2

[PATCH u-boot-marvell 13/18] ddr: marvell: a38x: import header change from upstream

[Marek Behún]

commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 461f091472..2cca5676a0 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -52,9 +52,6 @@ struct if_params {
 	/* The DDR frequency for each interfaces */
 	enum mv_ddr_freq memory_freq;
 
-    /* ddr twin-die */
-	enum mv_ddr_twin_die twin_die_combined;
-
 	/*
 	 * delay CAS Write Latency
 	 * - 0 for using default value (jedec suggested)
-- 
2.26.2

[PATCH u-boot-marvell 14/18] ddr: marvell: a38x: fix memory cs size function

[Marek Behún]

commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream.

The funtion returnd cs size in byte instead of MB, that cause
calculation error since the caller was expected to get u32 and when he
got above 4G it refers it as 0.
The fix was to get the cs memory size from function as in MB and then
multiply it by 1MB.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/mv_ddr_plat.c | 9 +++++++--
 drivers/ddr/marvell/a38x/xor.c         | 6 +++---
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
index 72f0dfbbbb..0d1df189e8 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
@@ -4,6 +4,7 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_common.h"
 #include "mv_ddr_training_db.h"
 #include "mv_ddr_regs.h"
 #include "mv_ddr_sys_env_lib.h"
@@ -1016,7 +1017,7 @@ int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size)
 		return MV_BAD_VALUE;
 	}
 
-	*cs_size = cs_mem_size << 20; /* write cs size in bytes */
+	*cs_size = cs_mem_size;
 
 	return MV_OK;
 }
@@ -1025,9 +1026,11 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
 {
 	u32 reg, cs;
 	uint64_t mem_total_size = 0;
+	uint64_t cs_mem_size_mb = 0;
 	uint64_t cs_mem_size = 0;
 	uint64_t mem_total_size_c, cs_mem_size_c;
 
+
 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
 	u32 physical_mem_size;
 	u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
@@ -1038,8 +1041,9 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
 	for (cs = 0; cs < MAX_CS_NUM; cs++) {
 		if (cs_ena & (1 << cs)) {
 			/* get CS size */
-			if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK)
+			if (ddr3_calc_mem_cs_size(cs, &cs_mem_size_mb) != MV_OK)
 				return MV_FAIL;
+			cs_mem_size = cs_mem_size_mb * _1M;
 
 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
 			/*
@@ -1088,6 +1092,7 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
 			 */
 			mem_total_size_c = (mem_total_size >> 16) & 0xffffffffffff;
 			cs_mem_size_c = (cs_mem_size >> 16) & 0xffffffffffff;
+
 			/* if the sum less than 2 G - calculate the value */
 			if (mem_total_size_c + cs_mem_size_c < 0x10000)
 				mem_total_size += cs_mem_size;
diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c
index 5fb9e216d3..98fb39eaf0 100644
--- a/drivers/ddr/marvell/a38x/xor.c
+++ b/drivers/ddr/marvell/a38x/xor.c
@@ -340,7 +340,7 @@ void ddr3_new_tip_ecc_scrub(void)
 {
 	u32 cs_c, max_cs;
 	u32 cs_ena = 0;
-	uint64_t total_mem_size, cs_mem_size = 0;
+	uint64_t total_mem_size, cs_mem_size_mb = 0, cs_mem_size = 0;
 
 	printf("DDR Training Sequence - Start scrubbing\n");
 	max_cs = mv_ddr_cs_num_get();
@@ -349,9 +349,9 @@ void ddr3_new_tip_ecc_scrub(void)
 
 #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
 	/* all chip-selects are of same size */
-	ddr3_calc_mem_cs_size(0, &cs_mem_size);
+	ddr3_calc_mem_cs_size(0, &cs_mem_size_mb);
 #endif
-
+	cs_mem_size = cs_mem_size_mb * _1M;
 	mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0);
 	total_mem_size = max_cs * cs_mem_size;
 	mv_xor_mem_init(0, 0, total_mem_size, 0xdeadbeef, 0xdeadbeef);
-- 
2.26.2

[PATCH u-boot-marvell 15/18] ddr: marvell: a38x: import code change from upstream

[Marek Behún]

commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes code in ddr3_training.c.

Import this change to remain consistent with upstream.

Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/ddr3_training.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index 34cc170910..0358f6287a 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -143,6 +143,7 @@ static struct reg_data odpg_default_value[] = {
 	{0x15a4, 0x0, MASK_ALL_BITS},
 	{0x15a8, 0x0, MASK_ALL_BITS},
 	{0x15ac, 0x0, MASK_ALL_BITS},
+	{0x1600, 0x0, MASK_ALL_BITS},
 	{0x1604, 0x0, MASK_ALL_BITS},
 	{0x1608, 0x0, MASK_ALL_BITS},
 	{0x160c, 0x0, MASK_ALL_BITS},
@@ -1569,6 +1570,8 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
 		val = ((cl_mask_table[cl_value] & 0x1) << 2) |
 			((cl_mask_table[cl_value] & 0xe) << 3);
 
+		cs_mask[0] = 0xc;
+
 		CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0,
 			val, (0x7 << 4) | (0x1 << 2)));
 
-- 
2.26.2

[PATCH u-boot-marvell 16/18] ddr: marvell: a38x: enum mv_ddr_twin_die: change order

[Marek Behún]

commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream.

@pali suggested this change
In commit 6285efb ("mv_ddr: add support for twin-die combined memory
device") was added support for twin-die combined memory device and
default value for explicitly uninitialized structure members is zero, s
also twin_die_combined is initialized to zero. Which means COMBINED
value.
As prior this commit there was no support for twin-die combined memory
device, default value for twin_die_combined should be NOT_COMBINED. This
change change order of enum mv_ddr_twin_die to ensure that NOT_COMBINED
has value zero.

Signed-off-by: heaterC <airyguy@gmx.de>
Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/ddr_topology_def.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 2cca5676a0..7f2317edfa 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -15,8 +15,8 @@
 #define MV_DDR_MAX_IFACE_NUM	1
 
 enum mv_ddr_twin_die {
-	COMBINED,
 	NOT_COMBINED,
+	COMBINED,
 };
 
 struct bus_params {
-- 
2.26.2

[PATCH u-boot-marvell 17/18] ddr: marvell: a38x: bump version to 14.0.0

[Marek Behún]

Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the
version in the mv-ddr-devel branch of upstream repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.

There is a new version numbering system, where after 18.12.0 came
1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0.

Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/mv_ddr_build_message.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
index cc6234fd40..a2bb8a96a6 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
@@ -1,3 +1,3 @@
 // SPDX-License-Identifier: GPL-2.0
 const char mv_ddr_build_message[] = "";
-const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-18.09.2";
+const char mv_ddr_version_string[] = "mv_ddr: 14.0.0";
-- 
2.26.2

[PATCH u-boot-marvell 18/18] ddr: marvell: a38x: fix comment in conditional macro

[Marek Behún]

The code was processed with unifdef utility to omit portions not
relevant to A38x and DDR3. This removes usage of many macros, including
A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove
the macros from #else comment.

Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
 drivers/ddr/marvell/a38x/ddr3_training.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index 0358f6287a..2b3af23202 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -219,7 +219,7 @@ static int ddr3_tip_pad_inv(void)
 						       DDR_PHY_CONTROL,
 						       PHY_CTRL_PHY_REG,
 						       data, data);
-#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X && !A70X0 && !A80X0 && !A3900 */
+#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X */
 #pragma message "unknown platform to configure ddr clock swap"
 #endif
 		}
-- 
2.26.2

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Marek Behun]

btw tested on Turris Omnia

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Chris Packham]

Hi Marek,

On 9/02/21 7:34 am, Marek Beh?n wrote:
> This syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch
> of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
>
> There are some commits regarding DDR3 on top of version 14.0.0 in the
> mv-ddr-marvell repository (from Chris Packham), but these changes
> already are in U-Boot.
Do you have this in a repo I can pull from? I've got a couple of boards 
I can give this a spin on.
> Marek
>
> Marek Beh?n (18):
>    ddr: marvell: a38x: fix write leveling suplementary algo
>    ddr: marvell: a38x: import header change from upstream
>    ddr: marvell: a38x: add ddr32 support
>    ddr: marvell: a38x: add ddr 32bit ECC support
>    ddr: marvell: a38x: import header change from upstream
>    ddr: marvell: a38x: fix 32bit
>    ddr: marvell: a38x: fix memory size calculation using 32bit bus width
>    ddr: marvell: a38x: import header change from upstream
>    ddr: marvell: a38x: allow board specific ODT configuration
>    ddr: marvell: a38x: add 16Gbit memory devices support
>    ddr: marvell: a38x: add support for twin-die combined memory device
>    ddr: marvell: a38x: disable WL phase correction stage in case of
>      bus_width=16bit
>    ddr: marvell: a38x: import header change from upstream
>    ddr: marvell: a38x: fix memory cs size function
>    ddr: marvell: a38x: import code change from upstream
>    ddr: marvell: a38x: enum mv_ddr_twin_die: change order
>    ddr: marvell: a38x: bump version to 14.0.0
>    ddr: marvell: a38x: fix comment in conditional macro
>
>   board/CZ.NIC/turris_omnia/turris_omnia.c      |  2 ++
>   board/Marvell/db-88f6820-amc/db-88f6820-amc.c |  1 +
>   board/Marvell/db-88f6820-gp/db-88f6820-gp.c   |  1 +
>   board/alliedtelesis/x530/x530.c               |  1 +
>   board/gdsys/a38x/controlcenterdc.c            |  1 +
>   board/kobol/helios4/helios4.c                 |  1 +
>   board/solidrun/clearfog/clearfog.c            |  1 +
>   drivers/ddr/marvell/a38x/ddr3_init.c          |  5 ++++
>   drivers/ddr/marvell/a38x/ddr3_training.c      |  5 +++-
>   drivers/ddr/marvell/a38x/ddr3_training_db.c   |  3 +++
>   .../ddr/marvell/a38x/ddr3_training_ip_def.h   |  2 ++
>   .../marvell/a38x/ddr3_training_ip_engine.c    |  5 +++-
>   drivers/ddr/marvell/a38x/ddr_topology_def.h   | 23 ++++++++++++++++++-
>   .../ddr/marvell/a38x/mv_ddr_build_message.c   |  2 +-
>   drivers/ddr/marvell/a38x/mv_ddr_plat.c        |  9 ++++++--
>   drivers/ddr/marvell/a38x/mv_ddr_topology.c    | 14 ++++++++---
>   drivers/ddr/marvell/a38x/mv_ddr_topology.h    |  2 ++
>   drivers/ddr/marvell/a38x/xor.c                |  6 ++---
>   18 files changed, 72 insertions(+), 12 deletions(-)
>

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Marek Behun]

On Mon, 8 Feb 2021 20:11:06 +0000
Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:

> Hi Marek,
> 
> Do you have this in a repo I can pull from? I've got a couple of boards 
> I can give this a spin on.

https://gitlab.nic.cz/turris/turris-omnia-uboot/
branch v2021.04-rc-mv-ddr-14.0.0

also please test branch v2021.04-rc-mv-ddr-14.0.0-samsung-ddr-fix, that
one contains one more commit that is needed for Omnia with Samsung DDR
chips.

Marek

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Chris Packham]

On 9/02/21 9:18 am, Marek Behun wrote:
> On Mon, 8 Feb 2021 20:11:06 +0000
> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
>
>> Hi Marek,
>>
>> Do you have this in a repo I can pull from? I've got a couple of boards
>> I can give this a spin on.
> https://gitlab.nic.cz/turris/turris-omnia-uboot/
> branch v2021.04-rc-mv-ddr-14.0.0
>
> also please test branch v2021.04-rc-mv-ddr-14.0.0-samsung-ddr-fix, that
> one contains one more commit that is needed for Omnia with Samsung DDR
> chips.

I've tested the dm-88f6820-amc board. Training completed without issue, 
as does memtester running from Linux.

Hit a bit of a snag on the x530 because the changes pushed it over the 
SPL size (it was already pretty close). I'll look to see if there's 
anything I can drop out or maybe bump the SPL size (I never did get a 
clear answer from Marvell as to what the size limit actually is).

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Chris Packham]

On 9/02/21 1:16 pm, Chris Packham wrote:
> On 9/02/21 9:18 am, Marek Behun wrote:
>> On Mon, 8 Feb 2021 20:11:06 +0000
>> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
>>
>>> Hi Marek,
>>>
>>> Do you have this in a repo I can pull from? I've got a couple of boards
>>> I can give this a spin on.
>> https://gitlab.nic.cz/turris/turris-omnia-uboot/
>> branch v2021.04-rc-mv-ddr-14.0.0
>>
>> also please test branch v2021.04-rc-mv-ddr-14.0.0-samsung-ddr-fix, that
>> one contains one more commit that is needed for Omnia with Samsung DDR
>> chips.
>
> I've tested the dm-88f6820-amc board. Training completed without 
> issue, as does memtester running from Linux.
>
> Hit a bit of a snag on the x530 because the changes pushed it over the 
> SPL size (it was already pretty close). I'll look to see if there's 
> anything I can drop out or maybe bump the SPL size (I never did get a 
> clear answer from Marvell as to what the size limit actually is).

I can temporarily work around the size issue by disabling watchdog 
support in SPL (I really don't want that to be the long term solution).

But then I encounter an odd problem. When I "reset" the board gets 
through the DDR training but never makes it to u-boot proper, but if I 
power cycle it boots through to the u-boot prompt. This doesn't happen 
on the db-88f6820-amc board. One difference between the x530 and the amc 
board is that the x530 has ECC so maybe something is going into the 
weeds if ECC has already been enabled by a previous boot.

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Marek Behun]

On Tue, 9 Feb 2021 01:08:54 +0000
Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:

> On 9/02/21 1:16 pm, Chris Packham wrote:
> > On 9/02/21 9:18 am, Marek Behun wrote:  
> >> On Mon, 8 Feb 2021 20:11:06 +0000
> >> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
> >>  
> >>> Hi Marek,
> >>>
> >>> Do you have this in a repo I can pull from? I've got a couple of boards
> >>> I can give this a spin on.  
> >> https://gitlab.nic.cz/turris/turris-omnia-uboot/
> >> branch v2021.04-rc-mv-ddr-14.0.0
> >>
> >> also please test branch v2021.04-rc-mv-ddr-14.0.0-samsung-ddr-fix, that
> >> one contains one more commit that is needed for Omnia with Samsung DDR
> >> chips.  
> >
> > I've tested the dm-88f6820-amc board. Training completed without 
> > issue, as does memtester running from Linux.
> >
> > Hit a bit of a snag on the x530 because the changes pushed it over the 
> > SPL size (it was already pretty close). I'll look to see if there's 
> > anything I can drop out or maybe bump the SPL size (I never did get a 
> > clear answer from Marvell as to what the size limit actually is).  
> 
> I can temporarily work around the size issue by disabling watchdog 
> support in SPL (I really don't want that to be the long term solution).
> 
> But then I encounter an odd problem. When I "reset" the board gets 
> through the DDR training but never makes it to u-boot proper, but if I 
> power cycle it boots through to the u-boot prompt. This doesn't happen 
> on the db-88f6820-amc board. One difference between the x530 and the amc 
> board is that the x530 has ECC so maybe something is going into the 
> weeds if ECC has already been enabled by a previous boot.
> 

Could you bisect which commit causes this?

Marek

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Chris Packham]

On 9/02/21 3:07 pm, Marek Behun wrote:
> On Tue, 9 Feb 2021 01:08:54 +0000
> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
>
>> On 9/02/21 1:16 pm, Chris Packham wrote:
>>> On 9/02/21 9:18 am, Marek Behun wrote:
>>>> On Mon, 8 Feb 2021 20:11:06 +0000
>>>> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
>>>>   
>>>>> Hi Marek,
>>>>>
>>>>> Do you have this in a repo I can pull from? I've got a couple of boards
>>>>> I can give this a spin on.
>>>> https://gitlab.nic.cz/turris/turris-omnia-uboot/
>>>> branch v2021.04-rc-mv-ddr-14.0.0
>>>>
>>>> also please test branch v2021.04-rc-mv-ddr-14.0.0-samsung-ddr-fix, that
>>>> one contains one more commit that is needed for Omnia with Samsung DDR
>>>> chips.
>>> I've tested the dm-88f6820-amc board. Training completed without
>>> issue, as does memtester running from Linux.
>>>
>>> Hit a bit of a snag on the x530 because the changes pushed it over the
>>> SPL size (it was already pretty close). I'll look to see if there's
>>> anything I can drop out or maybe bump the SPL size (I never did get a
>>> clear answer from Marvell as to what the size limit actually is).
>> I can temporarily work around the size issue by disabling watchdog
>> support in SPL (I really don't want that to be the long term solution).
>>
>> But then I encounter an odd problem. When I "reset" the board gets
>> through the DDR training but never makes it to u-boot proper, but if I
>> power cycle it boots through to the u-boot prompt. This doesn't happen
>> on the db-88f6820-amc board. One difference between the x530 and the amc
>> board is that the x530 has ECC so maybe something is going into the
>> weeds if ECC has already been enabled by a previous boot.
>>
> Could you bisect which commit causes this?
I'll give it a try. I've kind of done my dash for u-boot stuff for today 
but I'll try and get to it later tonight.

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Chris Packham]

On 9/02/21 3:07 pm, Marek Behun wrote:
> On Tue, 9 Feb 2021 01:08:54 +0000
> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
>
>> On 9/02/21 1:16 pm, Chris Packham wrote:
>>> On 9/02/21 9:18 am, Marek Behun wrote:
>>>> On Mon, 8 Feb 2021 20:11:06 +0000
>>>> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
>>>>   
>>>>> Hi Marek,
>>>>>
>>>>> Do you have this in a repo I can pull from? I've got a couple of boards
>>>>> I can give this a spin on.
>>>> https://gitlab.nic.cz/turris/turris-omnia-uboot/
>>>> branch v2021.04-rc-mv-ddr-14.0.0
>>>>
>>>> also please test branch v2021.04-rc-mv-ddr-14.0.0-samsung-ddr-fix, that
>>>> one contains one more commit that is needed for Omnia with Samsung DDR
>>>> chips.
>>> I've tested the dm-88f6820-amc board. Training completed without
>>> issue, as does memtester running from Linux.
>>>
>>> Hit a bit of a snag on the x530 because the changes pushed it over the
>>> SPL size (it was already pretty close). I'll look to see if there's
>>> anything I can drop out or maybe bump the SPL size (I never did get a
>>> clear answer from Marvell as to what the size limit actually is).
>> I can temporarily work around the size issue by disabling watchdog
>> support in SPL (I really don't want that to be the long term solution).
>>
>> But then I encounter an odd problem. When I "reset" the board gets
>> through the DDR training but never makes it to u-boot proper, but if I
>> power cycle it boots through to the u-boot prompt. This doesn't happen
>> on the db-88f6820-amc board. One difference between the x530 and the amc
>> board is that the x530 has ECC so maybe something is going into the
>> weeds if ECC has already been enabled by a previous boot.
>>
> Could you bisect which commit causes this?
Seems to be the last one (ddr: marvell: a38x: fix SPLIT_OUT_MIX state 
decision) not entirely sure what the problem is. So I guess you can 
consider the upstream update good, the fix SPLIT_OUT_MIX not so much it 
happens to be the thing that causes the issue and the straw that tips 
the build size over the limit.

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Marek Behun]

On Tue, 9 Feb 2021 06:50:35 +0000
Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:

> On 9/02/21 3:07 pm, Marek Behun wrote:
> > On Tue, 9 Feb 2021 01:08:54 +0000
> > Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
> >  
> >> On 9/02/21 1:16 pm, Chris Packham wrote:  
> >>> On 9/02/21 9:18 am, Marek Behun wrote:  
> >>>> On Mon, 8 Feb 2021 20:11:06 +0000
> >>>> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
> >>>>     
> >>>>> Hi Marek,
> >>>>>
> >>>>> Do you have this in a repo I can pull from? I've got a couple of boards
> >>>>> I can give this a spin on.  
> >>>> https://gitlab.nic.cz/turris/turris-omnia-uboot/
> >>>> branch v2021.04-rc-mv-ddr-14.0.0
> >>>>
> >>>> also please test branch v2021.04-rc-mv-ddr-14.0.0-samsung-ddr-fix, that
> >>>> one contains one more commit that is needed for Omnia with Samsung DDR
> >>>> chips.  
> >>> I've tested the dm-88f6820-amc board. Training completed without
> >>> issue, as does memtester running from Linux.
> >>>
> >>> Hit a bit of a snag on the x530 because the changes pushed it over the
> >>> SPL size (it was already pretty close). I'll look to see if there's
> >>> anything I can drop out or maybe bump the SPL size (I never did get a
> >>> clear answer from Marvell as to what the size limit actually is).  
> >> I can temporarily work around the size issue by disabling watchdog
> >> support in SPL (I really don't want that to be the long term solution).
> >>
> >> But then I encounter an odd problem. When I "reset" the board gets
> >> through the DDR training but never makes it to u-boot proper, but if I
> >> power cycle it boots through to the u-boot prompt. This doesn't happen
> >> on the db-88f6820-amc board. One difference between the x530 and the amc
> >> board is that the x530 has ECC so maybe something is going into the
> >> weeds if ECC has already been enabled by a previous boot.
> >>  
> > Could you bisect which commit causes this?  
> Seems to be the last one (ddr: marvell: a38x: fix SPLIT_OUT_MIX state 
> decision) not entirely sure what the problem is. So I guess you can 
> consider the upstream update good, the fix SPLIT_OUT_MIX not so much it 
> happens to be the thing that causes the issue and the straw that tips 
> the build size over the limit.

That's bad, because that is the one commit that is needed for Omnias
with Samsung chips. Could you try to apply this last commit without the
previous 18 ones? It should apply.

If it does not work, could you please send me your board ddr topology
definition? I will try to update the patch.

Marek

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Chris Packham]

On 10/02/21 2:15 am, Marek Behun wrote:
> On Tue, 9 Feb 2021 06:50:35 +0000
> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
>
>> On 9/02/21 3:07 pm, Marek Behun wrote:
>>> On Tue, 9 Feb 2021 01:08:54 +0000
>>> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
>>>   
>>>> On 9/02/21 1:16 pm, Chris Packham wrote:
>>>>> On 9/02/21 9:18 am, Marek Behun wrote:
>>>>>> On Mon, 8 Feb 2021 20:11:06 +0000
>>>>>> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
>>>>>>      
>>>>>>> Hi Marek,
>>>>>>>
>>>>>>> Do you have this in a repo I can pull from? I've got a couple of boards
>>>>>>> I can give this a spin on.
>>>>>> https://gitlab.nic.cz/turris/turris-omnia-uboot/
>>>>>> branch v2021.04-rc-mv-ddr-14.0.0
>>>>>>
>>>>>> also please test branch v2021.04-rc-mv-ddr-14.0.0-samsung-ddr-fix, that
>>>>>> one contains one more commit that is needed for Omnia with Samsung DDR
>>>>>> chips.
>>>>> I've tested the dm-88f6820-amc board. Training completed without
>>>>> issue, as does memtester running from Linux.
>>>>>
>>>>> Hit a bit of a snag on the x530 because the changes pushed it over the
>>>>> SPL size (it was already pretty close). I'll look to see if there's
>>>>> anything I can drop out or maybe bump the SPL size (I never did get a
>>>>> clear answer from Marvell as to what the size limit actually is).
>>>> I can temporarily work around the size issue by disabling watchdog
>>>> support in SPL (I really don't want that to be the long term solution).
>>>>
>>>> But then I encounter an odd problem. When I "reset" the board gets
>>>> through the DDR training but never makes it to u-boot proper, but if I
>>>> power cycle it boots through to the u-boot prompt. This doesn't happen
>>>> on the db-88f6820-amc board. One difference between the x530 and the amc
>>>> board is that the x530 has ECC so maybe something is going into the
>>>> weeds if ECC has already been enabled by a previous boot.
>>>>   
>>> Could you bisect which commit causes this?
>> Seems to be the last one (ddr: marvell: a38x: fix SPLIT_OUT_MIX state
>> decision) not entirely sure what the problem is. So I guess you can
>> consider the upstream update good, the fix SPLIT_OUT_MIX not so much it
>> happens to be the thing that causes the issue and the straw that tips
>> the build size over the limit.
> That's bad, because that is the one commit that is needed for Omnias
> with Samsung chips. Could you try to apply this last commit without the
> previous 18 ones? It should apply.
>
> If it does not work, could you please send me your board ddr topology
> definition? I will try to update the patch.

With just the one patch I see the hang (and the size blow out). The 
board topology is all upstream (board/alliedtelesis/x530/x530.c).

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Marek Behun]

On Tue, 9 Feb 2021 06:50:35 +0000
Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:

> On 9/02/21 3:07 pm, Marek Behun wrote:
> > On Tue, 9 Feb 2021 01:08:54 +0000
> > Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
> >  
> >> On 9/02/21 1:16 pm, Chris Packham wrote:  
> >>> On 9/02/21 9:18 am, Marek Behun wrote:  
> >>>> On Mon, 8 Feb 2021 20:11:06 +0000
> >>>> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
> >>>>     
> >>>>> Hi Marek,
> >>>>>
> >>>>> Do you have this in a repo I can pull from? I've got a couple of boards
> >>>>> I can give this a spin on.  
> >>>> https://gitlab.nic.cz/turris/turris-omnia-uboot/
> >>>> branch v2021.04-rc-mv-ddr-14.0.0
> >>>>
> >>>> also please test branch v2021.04-rc-mv-ddr-14.0.0-samsung-ddr-fix, that
> >>>> one contains one more commit that is needed for Omnia with Samsung DDR
> >>>> chips.  
> >>> I've tested the dm-88f6820-amc board. Training completed without
> >>> issue, as does memtester running from Linux.
> >>>
> >>> Hit a bit of a snag on the x530 because the changes pushed it over the
> >>> SPL size (it was already pretty close). I'll look to see if there's
> >>> anything I can drop out or maybe bump the SPL size (I never did get a
> >>> clear answer from Marvell as to what the size limit actually is).  
> >> I can temporarily work around the size issue by disabling watchdog
> >> support in SPL (I really don't want that to be the long term solution).
> >>
> >> But then I encounter an odd problem. When I "reset" the board gets
> >> through the DDR training but never makes it to u-boot proper, but if I
> >> power cycle it boots through to the u-boot prompt. This doesn't happen
> >> on the db-88f6820-amc board. One difference between the x530 and the amc
> >> board is that the x530 has ECC so maybe something is going into the
> >> weeds if ECC has already been enabled by a previous boot.
> >>  
> > Could you bisect which commit causes this?  
> Seems to be the last one (ddr: marvell: a38x: fix SPLIT_OUT_MIX state 
> decision) not entirely sure what the problem is. So I guess you can 
> consider the upstream update good, the fix SPLIT_OUT_MIX not so much it 
> happens to be the thing that causes the issue and the straw that tips 
> the build size over the limit.

BTW Chris if the first 18 patches are working for your devices, could
you please give Tested-by? Thanks.

Marek

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Pali Rohár]

On Tuesday 09 February 2021 01:08:54 Chris Packham wrote:
> On 9/02/21 1:16 pm, Chris Packham wrote:
> > On 9/02/21 9:18 am, Marek Behun wrote:
> >> On Mon, 8 Feb 2021 20:11:06 +0000
> >> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
> >>
> >>> Hi Marek,
> >>>
> >>> Do you have this in a repo I can pull from? I've got a couple of boards
> >>> I can give this a spin on.
> >> https://gitlab.nic.cz/turris/turris-omnia-uboot/
> >> branch v2021.04-rc-mv-ddr-14.0.0
> >>
> >> also please test branch v2021.04-rc-mv-ddr-14.0.0-samsung-ddr-fix, that
> >> one contains one more commit that is needed for Omnia with Samsung DDR
> >> chips.
> >
> > I've tested the dm-88f6820-amc board. Training completed without 
> > issue, as does memtester running from Linux.
> >
> > Hit a bit of a snag on the x530 because the changes pushed it over the 
> > SPL size (it was already pretty close). I'll look to see if there's 
> > anything I can drop out or maybe bump the SPL size (I never did get a 
> > clear answer from Marvell as to what the size limit actually is).
> 
> I can temporarily work around the size issue by disabling watchdog 
> support in SPL (I really don't want that to be the long term solution).

If you need to decrease size of U-Boot binary, can you try enabling
following two options?

CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_OPTIMIZE_INLINING=y

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Chris Packham]

On 9/02/21 10:15 pm, Pali Roh?r wrote:
> On Tuesday 09 February 2021 01:08:54 Chris Packham wrote:
>> On 9/02/21 1:16 pm, Chris Packham wrote:
>>> On 9/02/21 9:18 am, Marek Behun wrote:
>>>> On Mon, 8 Feb 2021 20:11:06 +0000
>>>> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
>>>>
>>>>> Hi Marek,
>>>>>
>>>>> Do you have this in a repo I can pull from? I've got a couple of boards
>>>>> I can give this a spin on.
>>>> https://gitlab.nic.cz/turris/turris-omnia-uboot/
>>>> branch v2021.04-rc-mv-ddr-14.0.0
>>>>
>>>> also please test branch v2021.04-rc-mv-ddr-14.0.0-samsung-ddr-fix, that
>>>> one contains one more commit that is needed for Omnia with Samsung DDR
>>>> chips.
>>> I've tested the dm-88f6820-amc board. Training completed without
>>> issue, as does memtester running from Linux.
>>>
>>> Hit a bit of a snag on the x530 because the changes pushed it over the
>>> SPL size (it was already pretty close). I'll look to see if there's
>>> anything I can drop out or maybe bump the SPL size (I never did get a
>>> clear answer from Marvell as to what the size limit actually is).
>> I can temporarily work around the size issue by disabling watchdog
>> support in SPL (I really don't want that to be the long term solution).
> If you need to decrease size of U-Boot binary, can you try enabling
> following two options?
Technically it's the size of the spl not u-boot proper.
> CONFIG_CC_OPTIMIZE_FOR_SIZE=y
This is already set it's default y.
> CONFIG_OPTIMIZE_INLINING=y
Setting both CONFIG_OPTIMIZE_INLINING=y and 
CONFIG_SPL_OPTIMIZE_INLINING=y don't help (they actually make the SPL a 
tiny bit bigger).

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Marek Behun]

Stefan,

these patches should probably have a different From: - i.e. the
original authors should be preserved (from the first Signed-off-by
tags), for example:

  motib <motib@marvell.com>
  Baruch Siach <baruch@tkos.co.il>
  heaterC <airyguy@gmx.de>

But some of these are not full names, so I don't know whether I should
resend this or not.

What do you think?

Marek

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Chris Packham]

On 9/02/21 7:34 am, Marek Beh?n wrote:
> This syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch
> of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
>
> There are some commits regarding DDR3 on top of version 14.0.0 in the
> mv-ddr-marvell repository (from Chris Packham), but these changes
> already are in U-Boot.

For this series, on the db-88f6820-amc and x530

Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

(I normally post to the mailing list from judge.packham at gmail.com so I'm 
not sure if you want to use that in the Tested-by instead. I try to do 
work stuff under alliedtelesis and free-time stuff under gmail but this 
in particular blurs the line).

> Marek
>
> Marek Beh?n (18):
>    ddr: marvell: a38x: fix write leveling suplementary algo
>    ddr: marvell: a38x: import header change from upstream
>    ddr: marvell: a38x: add ddr32 support
>    ddr: marvell: a38x: add ddr 32bit ECC support
>    ddr: marvell: a38x: import header change from upstream
>    ddr: marvell: a38x: fix 32bit
>    ddr: marvell: a38x: fix memory size calculation using 32bit bus width
>    ddr: marvell: a38x: import header change from upstream
>    ddr: marvell: a38x: allow board specific ODT configuration
>    ddr: marvell: a38x: add 16Gbit memory devices support
>    ddr: marvell: a38x: add support for twin-die combined memory device
>    ddr: marvell: a38x: disable WL phase correction stage in case of
>      bus_width=16bit
>    ddr: marvell: a38x: import header change from upstream
>    ddr: marvell: a38x: fix memory cs size function
>    ddr: marvell: a38x: import code change from upstream
>    ddr: marvell: a38x: enum mv_ddr_twin_die: change order
>    ddr: marvell: a38x: bump version to 14.0.0
>    ddr: marvell: a38x: fix comment in conditional macro
>
>   board/CZ.NIC/turris_omnia/turris_omnia.c      |  2 ++
>   board/Marvell/db-88f6820-amc/db-88f6820-amc.c |  1 +
>   board/Marvell/db-88f6820-gp/db-88f6820-gp.c   |  1 +
>   board/alliedtelesis/x530/x530.c               |  1 +
>   board/gdsys/a38x/controlcenterdc.c            |  1 +
>   board/kobol/helios4/helios4.c                 |  1 +
>   board/solidrun/clearfog/clearfog.c            |  1 +
>   drivers/ddr/marvell/a38x/ddr3_init.c          |  5 ++++
>   drivers/ddr/marvell/a38x/ddr3_training.c      |  5 +++-
>   drivers/ddr/marvell/a38x/ddr3_training_db.c   |  3 +++
>   .../ddr/marvell/a38x/ddr3_training_ip_def.h   |  2 ++
>   .../marvell/a38x/ddr3_training_ip_engine.c    |  5 +++-
>   drivers/ddr/marvell/a38x/ddr_topology_def.h   | 23 ++++++++++++++++++-
>   .../ddr/marvell/a38x/mv_ddr_build_message.c   |  2 +-
>   drivers/ddr/marvell/a38x/mv_ddr_plat.c        |  9 ++++++--
>   drivers/ddr/marvell/a38x/mv_ddr_topology.c    | 14 ++++++++---
>   drivers/ddr/marvell/a38x/mv_ddr_topology.h    |  2 ++
>   drivers/ddr/marvell/a38x/xor.c                |  6 ++---
>   18 files changed, 72 insertions(+), 12 deletions(-)
>

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Marek Behun]

Hi Stefan,

Chris put his Tested-by on this series and noone else replyied to it.
What do you think about this?

The only thing that may be problematic is that this series does not
preserve original commit authors (the ones who authored these commitsin
mv-ddr) in the From header, only in the first Signed-off-by's.
It's because I forgot to add correct From: tags.

Shall I fix this and resend it?

Marek

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Stefan Roese]

Hi Marek,

On 18.02.21 20:56, Marek Behun wrote:
> Chris put his Tested-by on this series and noone else replyied to it.
> What do you think about this?

How about the issue of size increase in the SPL? IIRC, then one patch
resulted in a too big image for one of the MVEBU boards.

> The only thing that may be problematic is that this series does not
> preserve original commit authors (the ones who authored these commitsin
> mv-ddr) in the From header, only in the first Signed-off-by's.
> It's because I forgot to add correct From: tags.
> 
> Shall I fix this and resend it?

Yes, please do. This will help me a bit.

Thanks,
Stefan

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Marek Behún]

On Fri, 19 Feb 2021 08:38:48 +0100
Stefan Roese <sr@denx.de> wrote:

> Hi Marek,
> 
> On 18.02.21 20:56, Marek Behun wrote:
> > Chris put his Tested-by on this series and noone else replyied to
> > it. What do you think about this?  
> 
> How about the issue of size increase in the SPL? IIRC, then one patch
> resulted in a too big image for one of the MVEBU boards.
> 
> > The only thing that may be problematic is that this series does not
> > preserve original commit authors (the ones who authored these
> > commitsin mv-ddr) in the From header, only in the first
> > Signed-off-by's. It's because I forgot to add correct From: tags.
> > 
> > Shall I fix this and resend it?  
> 
> Yes, please do. This will help me a bit.
> 
> Thanks,
> Stefan

I have sent v2 with From headers now containing original authors.

As for SPL, I have just tested these for all A38x boards, the results
are in the cover letter. In short for those boards where SPL is too
big, it is too big even before this series.

Marek

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Stefan Roese]

Hi Marek,

On 19.02.21 17:13, Marek Beh?n wrote:
> On Fri, 19 Feb 2021 08:38:48 +0100
> Stefan Roese <sr@denx.de> wrote:
> 
>> Hi Marek,
>>
>> On 18.02.21 20:56, Marek Behun wrote:
>>> Chris put his Tested-by on this series and noone else replyied to
>>> it. What do you think about this?
>>
>> How about the issue of size increase in the SPL? IIRC, then one patch
>> resulted in a too big image for one of the MVEBU boards.
>>
>>> The only thing that may be problematic is that this series does not
>>> preserve original commit authors (the ones who authored these
>>> commitsin mv-ddr) in the From header, only in the first
>>> Signed-off-by's. It's because I forgot to add correct From: tags.
>>>
>>> Shall I fix this and resend it?
>>
>> Yes, please do. This will help me a bit.
>>
>> Thanks,
>> Stefan
> 
> I have sent v2 with From headers now containing original authors.

Thanks.

> As for SPL, I have just tested these for all A38x boards, the results
> are in the cover letter. In short for those boards where SPL is too
> big, it is too big even before this series.

Okay. I'll queue this patchset for the upcoming merge window, or will
commit into next soon.

Thanks,
Stefan

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Pavol Rohár]

On Friday 19 February 2021 17:37:00 Stefan Roese wrote:
> Hi Marek,
> 
> On 19.02.21 17:13, Marek Beh?n wrote:
> > On Fri, 19 Feb 2021 08:38:48 +0100
> > Stefan Roese <sr@denx.de> wrote:
> > 
> > > Hi Marek,
> > > 
> > > On 18.02.21 20:56, Marek Behun wrote:
> > > > Chris put his Tested-by on this series and noone else replyied to
> > > > it. What do you think about this?
> > > 
> > > How about the issue of size increase in the SPL? IIRC, then one patch
> > > resulted in a too big image for one of the MVEBU boards.
> > > 
> > > > The only thing that may be problematic is that this series does not
> > > > preserve original commit authors (the ones who authored these
> > > > commitsin mv-ddr) in the From header, only in the first
> > > > Signed-off-by's. It's because I forgot to add correct From: tags.
> > > > 
> > > > Shall I fix this and resend it?
> > > 
> > > Yes, please do. This will help me a bit.
> > > 
> > > Thanks,
> > > Stefan
> > 
> > I have sent v2 with From headers now containing original authors.
> 
> Thanks.
> 
> > As for SPL, I have just tested these for all A38x boards, the results
> > are in the cover letter. In short for those boards where SPL is too
> > big, it is too big even before this series.
> 
> Okay. I'll queue this patchset for the upcoming merge window, or will
> commit into next soon.
> 
> Thanks,
> Stefan

Hello Stefan! Please let me know when you queue this patchset. I will
check if Marvell mv-ddr codebase is after merge fully synced in U-Boot.

[PATCH u-boot-marvell 00/18] Upgrade A38x DDR3 training to version 14.0.0

[Stefan Roese]

Hi Pavol,

On 24.02.21 15:28, Pavol Roh?r wrote:
> On Friday 19 February 2021 17:37:00 Stefan Roese wrote:
>> Hi Marek,
>>
>> On 19.02.21 17:13, Marek Beh?n wrote:
>>> On Fri, 19 Feb 2021 08:38:48 +0100
>>> Stefan Roese <sr@denx.de> wrote:
>>>
>>>> Hi Marek,
>>>>
>>>> On 18.02.21 20:56, Marek Behun wrote:
>>>>> Chris put his Tested-by on this series and noone else replyied to
>>>>> it. What do you think about this?
>>>>
>>>> How about the issue of size increase in the SPL? IIRC, then one patch
>>>> resulted in a too big image for one of the MVEBU boards.
>>>>
>>>>> The only thing that may be problematic is that this series does not
>>>>> preserve original commit authors (the ones who authored these
>>>>> commitsin mv-ddr) in the From header, only in the first
>>>>> Signed-off-by's. It's because I forgot to add correct From: tags.
>>>>>
>>>>> Shall I fix this and resend it?
>>>>
>>>> Yes, please do. This will help me a bit.
>>>>
>>>> Thanks,
>>>> Stefan
>>>
>>> I have sent v2 with From headers now containing original authors.
>>
>> Thanks.
>>
>>> As for SPL, I have just tested these for all A38x boards, the results
>>> are in the cover letter. In short for those boards where SPL is too
>>> big, it is too big even before this series.
>>
>> Okay. I'll queue this patchset for the upcoming merge window, or will
>> commit into next soon.
>>
>> Thanks,
>> Stefan
> 
> Hello Stefan! Please let me know when you queue this patchset. I will
> check if Marvell mv-ddr codebase is after merge fully synced in U-Boot.

I'm a bit behind right now, sorry. I'll try to answer tomorrow or latest
over the weekend.

Thanks,
Stefan